201242018 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種金屬閘極結構(metal gate structure) 及其製作方法，尤指一種實施後閘極(gate last)製程之金屬閘 極結構及其製作方法。 【先前技術】 在習知半導體產業中，多晶矽係廣泛地應用於半導體元 件如金氧半導體(metal-oxide-semiconductor，MOS)電晶體 中，作為標準的閘極材料選擇。然而，隨著M〇S電晶體尺 寸持續地^縮，傳統多晶石夕閘極因删穿透(b〇r〇n penetrati〇n) 效應導致元件效能降低，及其難以避免的空乏效應(depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容 值下降，進而導致元件驅動能力的衰退等困境。因此，半導 體業界更嘗以新的閘極㈣，例如_具#功函數(w〇rk function)金的導體來取代傳統的多晶㈣極，用以作為匹 配南介電常數(high-K)閘極介電層的控制電極。 而金屬閘極結構之製作方法係可概分為前閘極(柳响 製程及後閘極(gate last)製程兩大類。其中前閘極製程會在形 成金屬閘極結構後始進行源細及極超淺接面活化回火以及 化成金屬梦化物等尚熱預算製程，因此使得材料的選擇與調 201242018 整面對較多的挑戰。為避免上述高熱預算環境並獲得較寬的 材料選擇，業界係提出以後閘極製程取代前閘極製程之方 法。 請參閱第1圖，第1圖為一習知採用後閘極製程之一 η 型金屬閘極結構製作方法之示意圖。如第1圖所示，習知後 閘極製程中’係於一基底100上先形成一虛置閘極(dummy gate)或取代閘極(repbcement gate)(圖未示），虛置閘極包含 一高介電常數(high dielectric constant，以下簡稱為 high-K) 閘極介電層102、一作為底部阻障層的氣化鈦(titanium nitride，TiN)層104以及一多晶石夕層（圖未示）。並在完成一 般η型與p型電晶體的其他元件如輕推雜沒極(lightly-doped drain，LDD)、侧壁子、源極/汲極、金屬石夕化物（silicide)等 以及内層介電（inter-layer dielectric，ILD)層之製作後，將虛 置/取代閘極的多晶矽層移除，而於基底100上形成一閘極溝 渠（gate trench) 110。接下來於基底100上及閘極溝渠11 〇中 的TiN層104表面依序形成一作為蝕刻阻擋層以及底部阻障 層之氮化组(tantalum nitride，TaN)層106，例如一利用原子 層沈積（atomic layer deposition，ALD)技術形成的 TaN 層 106,以及一 p型功函數金屬層108。如第1圖所示，閘極溝 渠110内的TaN層106係呈一 U字形形狀的剖面結構。然 而值得注意的是，在移除多晶矽層形成閘極溝渠110時，TiN 層104係用以保護high-K閘極介電層102，因此TiN層104 201242018 表面係直接接觸触刻液而受到損害。而ALD技術乃利用製 程氣體與材料表面進行化學吸附反應，因此TiN層104受損 的異質（heterogeneous)表面直接影響到了 TaN層1〇6的形成結 果，導致TaN層106厚度未能達到預定厚度，並使其在閘極 溝渠110底部的階梯覆蓋率（step coverage)不佳，TiN層104 受損的異質表面甚至導致閘極溝渠110底部的TaN層106的 階梯覆蓋率低至70%以下。 接下來’係移除p型功函數金屬層1〇8,以於閘極溝渠ι1〇 内形成符合η型電晶體依電性需求的η型功函數金屬層（圖 未示）。值得注意的是’在移除ρ型功函數金屬層時， TaN層106係作為蝕刻停止層’用以保護下方的TiN層1〇4 與high-K閘極介電層1〇2。但如前所述，由於TaN層1〇6 的厚度未達預定厚度，且其階梯覆蓋度亦不佳，因此無法提 供良好的保護作用。換句話說，由於TaN層106的成膜不佳， 因此在移除p型功函數金屬層108時，TaN層106無法有效 阻擔#刻液’致使其下方的TiN層104，甚至high-K閘極介 電層102因接觸触刻液而受損，造成嚴重的閘極漏電（gate leakage)等問題。 由此可知，後閘極製程雖可避免源極/汲極超淺接面活化 回火以及形成金屬矽化物等高熱預算製程，而具有較寬廣的 材料選擇，但仍面臨複雜製程的整合性以及閘極溝渠内各膜 6 201242018 層的可靠度(reliability)等要求 【發明内容】 結構内各膜層可靠度之金及屬閘極 根據本發明所提供之申請專利範圍，係提供-種金屬閘極 結構’該金制極結構包含有—high_K _介電層、一設置於該 hlgh-K閘極介電層上之—字形侧停止層、叹至少—設置於該一 字形蝕刻停止層上之第一功函數金屬層。 根據本發明所提供之巾料利，錢供—種金屬間 極結構之製作方法’域作方法首先提供—基底，該基底上 形成有一虛置閘極，且該虛置閘極由下而上依序包含有一 high-K閘極介電層、—底部阻障層、—第—㈣停止層以及 -犧牲層。接下來，移除該犧牲層而於該基底上形成一閘極 溝渠’且該第停止層絲露㈣閘極賴底部。待形 成閘極溝渠後’係於該閘極溝渠内形成一第一功函數金屬 層。 根據本發明所提供之金屬閘極結構及其製作方法，係提供 一具有一字形第一蝕刻停止層的金屬閘極結構。由於該一; 形第-鋪停止層係於侧製程之前即形成於該底部阻障 201242018 層或該high-K閘極介電層之上，即形成於未曾受損的膜層 之上’故該一字形第一蝕刻停止層係獲得預定之厚度且較佳 的階梯覆蓋度。因此，該一字形第一蝕刻停止層可在後續敍 刻製程中提供良好的保護能力，確保其下方膜層不受蝕刻製 程的影響，更可確保後續形成的金屬閘極結構具有較佳的可 靠度。 【實施方式】 請參閱第2圖至第6圖，第2圖至第6圖係為本發明所 提供之金屬閘極結構之製作方法之一第一較佳實施例之示 意圖。值得注意的是，本較佳實施例係採用後閘極(gate-last) 製程與前閘極介電層（high-K first)製程。如第2圖所示，本 較佳實施例首先提供一基底200，如一矽基底、含矽基底、 或石夕覆絕緣(silicon-on-insulator，SOI)基底等。基底200表 面定義有一第一主動區域202a與一第二主動區域202b，且 基底200内係形成有一用以電性隔離第一主動區域2〇2a與 第二主動區域202b之淺溝隔離（shallow trench isolation，以 下簡稱為STI) 2〇4。接下來於基底2〇〇上依序形成一介質層 (interfacial layer) 206、一 high-K 閘極介電層 2〇8、一 底部阻 障層210、與一蝕刻停止層222。在本較佳實施例中，_介質 層206可包含矽氧化合物，而high-K閘極介電層2〇8包含 high-κ材料，其可以是一金屬氧化物層，例如一3稀土金屬氧 化物層如氧化給(hafnium oxide，Hf〇2)、矽峻铪氧化合物 8 201242018 (hafnium silicon oxide，HfSi〇4)、石夕酸铪氣氧化合物（hafnium silicon oxynitride，HfSiON)、氧化！呂（aluminum oxide， Al2〇3)、氧化贫屬（lanthanum oxide，La203)、氧化^[(tantalum oxide’ Ta2〇5)、氧化纪（yttrium oxide’ Y203)、氧化酷（zirconium oxide，Zr〇2)、鈦酸錄（strontiumtitanateoxide，SrTi03)、石夕酸 锆氧化合物（zirconium silicon oxide，ZrSi04)、锆酸铪 (hafnium zirconium oxide，HfZr04)、锶鉍鈕氧化物(str〇ntium bismuth tantalate，SrBi2Ta209, SBT)、鍅鈦酸鉛(lead zirconate titanate， PbZrxTikC^，PZT)或鈦酸鋇錄(barium strontium titanate，BaxSrvxTi03, BST)等。底部阻障層210較佳為一 TiN層，但不限於此。蝕 刻停止層222較佳為一 TaN層，但亦不限於此，蝕刻停止層 222可包含任何蝕刻率迥異於多晶矽層與底部阻障層21〇之 蝕刻率的材料。 值得注意的是’在本較佳實施例中，蚀刻停止層222係 利用-原子層沈積（ALD)方法22()形成。如前所述，由於 ALD方法220乃彻製程氣體與材料表面進行化學吸附反 應’因此蚀刻停止層222之前層，即底部阻障層21〇之表面 ，性對於ALD方法22〇的成膜結果影響甚矩。而在本較佳 實施例中，#刻V止層222係於形成底部阻障層21〇之後直 接藉由ALD方法220形成底部阻_ 2H)之上，此時底部 阻障層21G尚未經歷其他製程，因此底部阻障層210的完整 表面未受影響。有㈣此，_停止層m係可穩定地形成 201242018 於底部阻障層210之上，而可達loo%的階梯覆蓋度；此外 蝕刻停止層222係可在ALD方法220中達到預定厚度。 請參閱第3圖。在完成蚀刻停止層222之製作後，係於 基底200上形成一犧牲層226與一圖案化硬遮罩228。隨後 係進行一圖案化製程，透過圖案化硬遮罩228蝕刻犧牲層 226、轴刻停止層222、底部阻障層210、high-K閘極介電層 208與介質層206，而於基底200上的第一主動區域202a與 第二主動區域202b内分別形成一虛置閘極230。如第3圖所 不’虛置閘極230由下而上依序包含有介質層206、high-K 閘極介電層208、底部阻障層210、蝕刻停止層222、犧牲層 226與圖案化硬遮罩228，且上述介質層206、high-K閘極 介電層208、底部阻障層210、蝕刻停止層222以及犧牲層 226皆包含--字形狀的剖面結構。另外，在本較佳實施例 中犧牲層226係為一多晶石夕層，但不限於此。 請仍然參閱第3圖。在完成虛置閘極230之製作後，接 下來係利用不同導電型之離子佈植製程於第一主動區域 202a與第二主動區域202b中虛置閘極230兩侧之基底200 内分別形成一第一輕摻雜汲極(LDD) 232a與一第二LDD 232b。另外，在形成第一 LDD 232a與第二LDD 232b之前 還可分別於虛置閘極230之側壁分別先形成一偏位側壁子 (offset spacer)(圖未示）。隨後係於虛置閘極230之側壁分別 201242018 形成一側壁子234。最後再利用不同導電型之離子佈植製程 於第一主動區域202a與第二主動區域202b中側壁子234兩 側之基底200内分別形成一第一源極/汲極236a與一第二源 極/汲極236b。而於第一主動區域202a與第二主動區域2〇2b 内分別形成一第一導電型半導體元件240a與一第二導電型 半導體元件240b。另外在本較佳實施例中，亦可結合選擇性 應力系統(selective strain scheme，SSS)等製程，例如利用選 擇性磊晶成長（selective epitaxial growth，SEG)方法來製作第 一源極/汲極236a與第二源極/汲極236b。例如，當第一導電 型半導體元件240a為一 p型半導體元件，而第二導電型半 導體元件240b為一 η型半導體元件時，係可利用包含有錯 化矽（SiGe)之磊晶層以及包含碳化矽（Sic)有之磊晶層分別 製作第一源極/汲極236a與第二源極/汲極236b，以利用磊晶 層與閘極通道矽之間的應力作用更改善電性表現。此外，第 一源極/汲極236a與第二源極/汲極236b表面係分別包含有 一金屬矽化物（圖未示）。而在形成第一導電型半導體元件 240a與第二導電型半導體元件240b之後，係於半導體基底 200上依序形成一接觸洞姓刻停止層（contact etch stop layer，CESL) 242 與一内層介電（ild)層 244。 請參閱第4圖。接下來利用一平坦化製程’如一 CMP製 程，用以平坦化ILD層244與CESL 242，並移除圖案化硬 遮罩228 ’直至暴露出犧牲層226。在平坦化製程後，係利 201242018 用一#刻製程移除犧牲層226,而於第一主動區域2〇2a與第 二主動區域202b内分別形成一閘極溝渠246。值得泛魚的 是’在本較佳實施例中，一字形蝕刻停止層222係於移除 牲層226時用以保護其下方的底部阻障層21〇、high_K間極 介電層208與介質層206。且在蝕刻製程後，一字形蝕刻停 止層222係暴露於閘極溝渠246的底部。而在完成閘極溝= 246之製作後，係如第4圖所示，於基底200與閘極溝渠246 内的一字形蝕刻停止層222上形成一第一功函數金屬層 25〇在本較佳實施例中，第一功函數金屬層250係為一滿 ^第一導電型半導體元件240a，即p型半導體元件24〇a功 函數要求之金屬層，因此第一功函數金屬層250具有一第一 功函數’且第一功函數係介於4.8電子伏特(eV)與5.2eV之間。 ，參閱第5圖。接下來，係移除第二主動區域搬b内的 —力函數金屬層250。值得注意的是，在本較佳實施例中， 形蝕刻停止層222又可係於移除部分第一功函數金屬層 50時用以保護其下方的底部阻障層21〇、high_K閘極介電 2 208與介f層施。因此在移除第二主動區域獅内的第 ^函數金屬層25〇後，-字形钱刻停止層M2再次暴露於 =主動區域鳩内的閘極溝渠Μ6的底部。在移除第二 =區域202b内的第-功函數金屬層25〇之後，係於間極 =246内與基底上依序形成—第二功函數金屬層说 、一填充金屬層254 ’且填充金屬層254係填滿閘極溝渠 12 201242018 246。如第5圖所示，在第—主動區域2()2a内，第二功函數 金屬層252與填充金屬I 2M係依序形成於間極溝渠施内 的第-功函數金屬層250上；在第二主動區域2眺内，第 ,功函數金屬層252與填充金屬層254則是依序形成在钱刻 停止層222上。在本較佳實施例中，第二功函數金屬層攻 係為一滿足第二導電型半導體元件24〇b，即n型半導體元件 240b功函數要求之金屬層，因此第二功函數金屬層252:有 -第二功函數’且第二功函數係介於396¥與43〜之間。而 填充金屬層254則包含—填充能力良好且具低電阻值之金屬 材料’例如IS ’但不限於此。 凊參閱第6圖。在完成第一功函數金屬層25〇、第二功函 數金屬層252與填充金屬層254等膜層之製作後，係進行一 CMP製程，移除多餘的第一功函數金屬層25〇、第二功函數 金屬層252與填充金屬層254，而於基底200上的第一主動 區域202a與第二主動區域202b之内分別形成第一導電型半 導體元件240a之一第一金屬閘極結構260a與第二導電型半 導體元件240b之第一金屬閘極結構260b。且如第6圖所 示，本較佳實施例中第一金屬閘極結構260a之介質層206、 high-K閘極介電層208、底部阻障層210與蝕刻停止層222 的剖面結構係具有一一字形狀；而第一功函數金屬層25〇與 第二功函數金屬層252的剖面結構則具有一 u字形狀。另 外，第二金屬閘極結構260b之介質層206、high-K閘極介 13 201242018 電層208、底部阻障層210與蝕刻停止層222的剖面处構仪 具有--字齡而第二功函數金屬層252的剖面結：: 有- U字形狀。此外，本實施例亦可再選擇性去除助居、 244與CESL 242等，然後重新形成CESL與介電層以 提升半導體元件240a/240b的電性表現。 效 根據本第-較佳實施例所提供之金屬閘極結構之製作方 法’係提供具有-字形姓刻停止層222的金屬閘極处構 260a/鳩。由於—字雜刻停止層⑵係於移除犧:層 與移除部分第-功函數金屬層25()的㈣製程之前即 底部阻障層21G之上，即形成於未曾受損的異_層表面^ 上，故藉由ALD方法220形成的一字形蝕刻停止層222 ^ 可達到預定之厚度，且達到1〇〇%的階梯覆蓋度。因此，j 字形钱刻停止層222可在後續_製程中提供良好的保護: 力，確保其下方的底部阻障層21G、high_K閘極介電層：" 與介質層206等膜層不受任何蝕刻製程的影響，更可確保 續形成的金屬閘極結構26〇a/26〇b具有較佳的可靠度。 接下來請參閱第2圖與第3圖以及第7圖至第1〇圖， 2圖與第3圖以及第7圖至第1G圖係為本發明所提供之金: 閘極結構之製作方法之—第二較佳實施狀示意圖。由於第 二較佳實施例中，提供基底2〇〇、於基底2〇〇上形成介質層 2〇6、形成high-K閘極介電層208、形成底部阻障層、曰 201242018 與利用ALD方法形成蝕刻停止層222等步驟係與第一較佳 實施例及第2圖所繪示者相同，因此該等步驟係可參閱第2 圖及上述說明，而與此不再贊述。另夕卜，第二車交佳實施例中， 於第一主動區域202a與第二主動區域2〇2b内分別形成一第 一導電型半導體元件24〇a與一第二導電型半導體元件 240b、該等半導體元件24〇a/24〇b之各元件、以及虛置閘極 230等步驟係與第一較佳實施例及第3圖所！會示者相同，因 此該等步驟係可參閱第3圖及上述說明，於此亦不再贅述。 此外’第二較佳實施例中與第一較佳實施實施例相同的元件 係沿用相同的符號說明，且其材料選擇亦可同於第一較佳實 施例所揭露者。 請參閱第7圖。第二較佳實施例與第一較佳實施例不同 之處，係在利用一 CMP製程暴露出犧牲層226,以及利用一 蝕刻製程移除犧牲層226,而於第一主動區域202a與第二主 動區域202b内分別形成一閘極溝渠246之後。如前所述’ 一字形蝕刻停止層222係於移除犧牲層226時用以保護其下 方的底部阻障層210、high-K閘極介電層208與介質層206° 且在姓刻製程後’ 一字形餘刻停止層222係暴露於閘極溝渠 246的底部。之後’再次利用一 ALD方法220 ’於閘極溝渠 246内的一字形蝕刻停止層222與基底200上形成一蚀刻停 止層224。蚀刻停止層224之厚度係小於蚀刻停止層222之 厚度，且蚀刻停止層224所包含之材料係與餘刻停止層222 15 201242018 _壞，，在形成造成表 224包含與㈣停止層222相同之材 ^停止層 可說是形成於一同質卜啊娜)表面上。止層224 触刻停止層224係形成於包含相同材料之同質_，二於 222上，因隸刻停止層224之階梯覆蓋度亦可達。 請參閱第8圖。在完成蝕刻停止層224之製作後仪於 基底200與閘極溝渠246内的蝕刻停止層224上形成一#第& 功函數金屬層250。在本較佳實施例中，第一功函數金屬層 250亦為滿足p型半導體元件240a功函數要求之金屬層，因 此第一功函數金屬層250具有一第一功函數，且第—功函數係 介於4.8 eV與5.2 eV之間。 請參閱第9圖。接下來’係移除第二主動區域2〇2b内的 第一功函數金屬層250。值得注意的是，在本較佳實施例中’ 蝕刻停止層224係於移除部分第一功函數金屬層250時用以 保護其下方的底部阻障層210、high-K閘極介電層208與介 質層206。因此在移除第二主動區域202b内的第一功函數金 屬層250後，蝕刻停止層224係暴露於第二主動區域2〇2b 内的閘極溝渠246的底部。而在移除第二主動區域202b内 的第一功函數金屬層250之後，係於基底200上依序形成一 201242018 第二功函數金屬層252與一填充金屬層254，且填充金屬層 254係填滿閘極溝渠246。如第9圖所示，在第一主動區域 202a内，第二功函數金屬層252與填充金屬層254係依序形 成於閘極溝渠246内的第一功函數金屬層250上；在第二主 動區域202b内，第二功函數金屬層252與填充金屬層254 則是依序形成在蝕刻停止層224上。在本較佳實施例中，第 二功函數金屬層252亦為一 η型半導體元件240b功函數要 求之金屬層，因此第二功函數金屬層252具有一第二功函數， 且第二功函數係介於3.9 eV與4.3 eV之間。而填充金屬層254 則包含一填充能力良好之金屬材料，例如銘，但不限於此。 請參閱第10圖。在完成第一功函數金屬層250、第二功 函數金屬層252與填充金屬層254等膜層之製作後，係進行 一 CMP製程，移除多餘的蝕刻停止層224、第一功函數金屬 層250、第二功函數金屬層252與填充金屬層254，而於基 底200上的第一主動區域202a與第二主動區域202b之内分 別形成第一導電型半導體元件240a之一第一金屬閘極結構 270a與第二導電型半導體元件240b之一第二金屬閘極結構 270b。且如第10圖所示，本較佳實施例中第一金屬閘極結 構270a之介質層206、high-K閘極介電層208、底部阻障層 210與蝕刻停止層222的剖面結構係具有——字形狀；而蝕 刻停止層224、第一功函數金屬層250與第二功函數金屬層 252的剖面結構則具有一 U字形狀。另外，第二金屬閘極結 17 201242018 構270b之介質層206、high-K閘極介電層208、底部阻障層 210與蝕刻停止層222的剖面結構係具有一 一字开h 狀，而触 刻停止層224與第二功函數金屬層252的剖面結構則具有一 u字形狀。此外，本實施例亦可再選擇性去除ILD層2料與 CESL242等，然後重新形成CESL與介電層，以有欵提升半 導體元件240a/240b的電性表現。 根據本第二較佳實施例所提供之金屬閘極結構之製作方 法，係提供一具有一字形蝕刻停止層222與U字形蝕刻俨止 層224的金屬閘極結構270a/270b。由於一字形蝕剡俨止^ 222係於用以移除犧牲層226的蝕刻製程之前即形成二底^ 阻障層210之上，即形成於未曾受損的異質膜層表面之上， 故一字形蝕刻停止層222係可達到預定之厚度，且達到⑺ 的階梯覆蓋度。因此，一字形蝕刻停止層222可在用以移除° 犧牲層226的蝕刻製程中提供良好的保護能力，確保其下= 的底部阻障層210、high-K閘極介電層208與介質層2〇6等 膜層不受蝕刻製程的影響。另外，u字形蝕刻停止^ 224係 形成於移除部分第一功函數金屬層25〇之前，且更是形成於 具有同質表面的一字形蝕刻停止層222上，因此11字形蝕刻 停止層224亦可達到預定之厚度，且達到1〇〇%的階梯覆蓋 度。故U字形蝕刻停止層224可在用以移除第一功函數金屬 層250的關製程中提供良好的保護能力，確保其下方的底 部阻障層210、high-K閘極介電層2〇8與介質層2〇6膜層不 18 201242018 受蝕刻製程的影響。因此，本第二較佳實施例係可確保後續 形成的金屬閘極結構270a/27〇b具有較佳的可靠度。 綜上所述’根據本發明所提供之金屬閘極結構及其製作方 法’係提供〆具有一字形蝕刻停止層及具有U字形蝕刻停止 層的金屬閘極結構。由於一字形蝕刻停止層係於蝕刻製程之 前即形成於該底部阻障層或該high-K閘極介電層之上，即 形成於未曾受損的膜層之上；而U字形蝕刻停止層則是形成 於具有同質表面的一字形姓刻停止層上，故一字形姓刻停止 層與U字形蝕刻停止層皆獲得預定之厚度且較佳的階梯覆 蓋度。也因此一字形蝕刻停止層與U字形蝕刻停止層可在後 續蝕刻製程中提供良好的保護能力，確保其下方膜層不受蝕 刻製程的影響，更可確保後續形成的金屬閘極結構具有較佳 的玎靠度。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範图 戶斤做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為-習知採用後閘極製程之金屬閘極結構製作 法之示意圖。 力 第2圖至第6圖係為本發明所提供之金屬閘極結構之 作方法之一第一較佳實施例之示意圖。 19 201242018 第2圖與第3圖以及第7圖至第10圖係為本發明所提供 之金屬閘極結構之製作方法之一第二較佳實施例之示意圖。 【主要元件符號說明】 100基底 104氮化鈦層 108 P型功函數金屬層 2〇〇基底 202b第二主動區域 206介質層 21〇 底部阻障層 222蝕刻停止層 226犧牲層 230虛置閘極 232b第二輕摻雜汲極 236a第一源極/汲極 篇第-導電料導體元件 242接觸洞钱刻停止層 246閘極溝渠 252第二功函數金屬層 26〇a第-金屬閘極結構 27〇a第―金屬閘極結構 102高介電常數閘極介電層 106 氮化纽層 110閘極溝渠 202a第一主動區域 204 淺溝絕緣 208高介電常數閘極介電層 220原子層沈積方法 224 蝕刻停止層 228圖案化硬遮罩 232a第一輕捧雜沒極 234 側壁子 236b第二源極/汲極 240b第二導電型半導體元件 244 内層介電層 250第一功函數金屬層 254填充金屬層 260b第二金屬閘極結構 270b第二金屬閘極結構201242018 VI. Description of the Invention: [Technical Field] The present invention relates to a metal gate structure and a method of fabricating the same, and more particularly to a metal gate structure for implementing a gate last process And its production method. [Prior Art] In the conventional semiconductor industry, polycrystalline germanium is widely used in semiconductor elements such as metal-oxide-semiconductor (MOS) transistors as a standard gate material selection. However, as the M〇S transistor size continues to shrink, the traditional polycrystalline slab gates have reduced component performance due to the b穿透r〇n penetrati〇n effect, and its inevitable depletion effect ( Problems such as depletion effect) increase the thickness of the equivalent gate dielectric layer and decrease the value of the gate capacitance, which leads to the dilemma of component drive capability degradation. Therefore, the semiconductor industry has adopted a new gate (4), such as a conductor with a #w〇rk function gold instead of the traditional poly (tetra) pole, used as a matching south dielectric constant (high-K). The control electrode of the gate dielectric layer. The manufacturing method of the metal gate structure can be roughly divided into two types: the front gate (the willow process and the gate last process). The front gate process will start after the metal gate structure is formed. The ultra-shallow junction activation tempering and the formation of metal dreams and other hot budget processes, so the choice of materials and adjustment 201242018 face more challenges. To avoid the above high thermal budget environment and obtain a wider material selection, the industry The method of replacing the front gate process by the gate process is proposed. Please refer to Fig. 1, which is a schematic diagram of a conventional method for fabricating an n-type metal gate structure using a post gate process. In the conventional gate process, a dummy gate or a repbcement gate (not shown) is formed on a substrate 100, and the dummy gate includes a high dielectric. A high dielectric constant (hereinafter referred to as high-K) gate dielectric layer 102, a titanium nitride (TiN) layer 104 as a bottom barrier layer, and a polycrystalline layer (not shown) And complete the general η-type and p-type transistors Other components such as light-doped drain (LDD), sidewalls, source/drain, silicide, etc., and inter-layer dielectric (ILD) layers After fabrication, the dummy/replacement gate polysilicon layer is removed, and a gate trench 110 is formed on the substrate 100. Next, the surface of the TiN layer 104 on the substrate 100 and in the gate trench 11 Forming a tantalum nitride (TaN) layer 106 as an etch stop layer and a bottom barrier layer, such as a TaN layer 106 formed by atomic layer deposition (ALD) technology, and a p-type Work function metal layer 108. As shown in Fig. 1, the TaN layer 106 in the gate trench 110 has a U-shaped cross-sectional structure. However, it is worth noting that when the polysilicon layer is removed to form the gate trench 110, The TiN layer 104 is used to protect the high-K gate dielectric layer 102, so the surface of the TiN layer 104 201242018 is directly damaged by the contact engraving liquid. The ALD technology utilizes the process gas to chemically react with the surface of the material, so TiN Layer 104 damaged The (heterogeneous) surface directly affects the formation of the TaN layer 1〇6, resulting in the thickness of the TaN layer 106 failing to reach a predetermined thickness, and the step coverage at the bottom of the gate trench 110 is poor, and the TiN layer 104 is poor. The damaged heterogeneous surface even causes the step coverage of the TaN layer 106 at the bottom of the gate trench 110 to be as low as 70% or less. Next, the p-type work function metal layer 1〇8 is removed to form an n-type work function metal layer (not shown) conforming to the electrical requirements of the n-type transistor in the gate trench ι1〇. It is worth noting that the TaN layer 106 acts as an etch stop layer to protect the underlying TiN layer 1〇4 and the high-K gate dielectric layer 1〇2 when the p-type work function metal layer is removed. However, as described above, since the thickness of the TaN layer 1〇6 is less than the predetermined thickness and the step coverage is also poor, it does not provide a good protection. In other words, since the film formation of the TaN layer 106 is not good, when the p-type work function metal layer 108 is removed, the TaN layer 106 cannot effectively resist the engraving of the TiN layer 104, even the high-K. The gate dielectric layer 102 is damaged by contact with the etchant, causing serious problems such as gate leakage. It can be seen that the post-gate process can avoid the high-heat budget process such as source/drain ultra-shallow junction activation and tempering, and has a wide material selection, but still faces the integration of complex processes. Requirements for the reliability of each layer 6 201242018 layer in the gate trenches [Summary of the invention] The gold and gates of the reliability of each layer in the structure are provided according to the patent application scope provided by the present invention. The pole structure 'the gold pole structure comprises a -high_K _ dielectric layer, a zigzag side stop layer disposed on the hlgh-K gate dielectric layer, at least - disposed on the inline etch stop layer The first work function metal layer. According to the invention, the method for fabricating a metal-to-metal structure is first provided as a substrate, a dummy gate is formed on the substrate, and the dummy gate is bottom-up. A high-K gate dielectric layer, a bottom barrier layer, a - (four) stop layer, and a - sacrificial layer are sequentially included. Next, the sacrificial layer is removed to form a gate trench on the substrate and the first stop layer is exposed to the bottom. After forming the gate trench, a first work function metal layer is formed in the gate trench. According to the metal gate structure and the method of fabricating the same provided by the present invention, a metal gate structure having a first etch stop layer in a shape is provided. Since the first-type stop-stop layer is formed on the bottom barrier 201242018 layer or the high-K gate dielectric layer before the side process, that is, formed on the undamaged film layer The inline first etch stop layer achieves a predetermined thickness and a preferred step coverage. Therefore, the in-line first etch stop layer can provide good protection in the subsequent etching process, ensuring that the underlying film layer is not affected by the etching process, and further ensuring that the subsequently formed metal gate structure is more reliable. degree. [Embodiment] Please refer to Figs. 2 to 6 and Fig. 2 to Fig. 6 are diagrams showing a first preferred embodiment of a method for fabricating a metal gate structure according to the present invention. It should be noted that the preferred embodiment employs a gate-last process and a high-k first process. As shown in Fig. 2, the preferred embodiment first provides a substrate 200, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate. A surface of the substrate 200 defines a first active region 202a and a second active region 202b, and a shallow trench is formed in the substrate 200 for electrically isolating the first active region 2〇2a from the second active region 202b. Isolation, hereinafter referred to as STI) 2〇4. Next, an interfacial layer 206, a high-K gate dielectric layer 2〇8, a bottom barrier layer 210, and an etch stop layer 222 are sequentially formed on the substrate 2A. In the preferred embodiment, the dielectric layer 206 may comprise a germanium oxide compound, and the high-K gate dielectric layer 2〇8 comprises a high-k material, which may be a metal oxide layer, such as a 3 rare earth metal. The oxide layer is oxidized (hafnium oxide, Hf〇2), hafnium silicon oxide (HfSi〇4), hafnium silicon oxynitride (HfSiON), oxidation! Aluminum oxide (Al2〇3), lanthanum oxide (La203), oxidation^[(tantalum oxide' Ta2〇5), yttrium oxide' Y203, zirconium oxide, Zr〇2 ), strontiumtitanateoxide (SrTi03), zirconium silicon oxide (ZrSi04), hafnium zirconium oxide (HfZr04), str〇ntium bismuth tantalate, SrBi2Ta209, SBT), lead zirconate titanate (PbZrxTikC^, PZT) or barium strontium titanate (BaxSrvxTi03, BST). The bottom barrier layer 210 is preferably a TiN layer, but is not limited thereto. The etch stop layer 222 is preferably a TaN layer, but is not limited thereto, and the etch stop layer 222 may comprise any material having an etch rate different from that of the polysilicon layer and the bottom barrier layer 21 。. It is noted that in the preferred embodiment, the etch stop layer 222 is formed using an atomic layer deposition (ALD) method 22(). As described above, since the ALD method 220 is a chemisorption reaction between the process gas and the surface of the material, the surface of the layer before the etch stop layer 222, that is, the surface of the bottom barrier layer 21, affects the film formation result of the ALD method 22〇. Very moment. In the preferred embodiment, the undercut layer 222 is formed directly on the bottom barrier _ 2H by the ALD method 220 after the bottom barrier layer 21 is formed. At this time, the bottom barrier layer 21G has not undergone other The process is such that the entire surface of the bottom barrier layer 210 is unaffected. (4) Thus, the _stop layer m can stably form the 201242018 over the bottom barrier layer 210 to reach a step coverage of loo%; in addition, the etch stop layer 222 can reach a predetermined thickness in the ALD method 220. Please refer to Figure 3. After the fabrication of the etch stop layer 222 is completed, a sacrificial layer 226 and a patterned hard mask 228 are formed on the substrate 200. Subsequently, a patterning process is performed to etch the sacrificial layer 226, the gate stop layer 222, the bottom barrier layer 210, the high-K gate dielectric layer 208 and the dielectric layer 206 through the patterned hard mask 228, and on the substrate 200. A dummy gate 230 is formed in each of the first active region 202a and the second active region 202b. As shown in FIG. 3, the dummy gate 230 includes a dielectric layer 206, a high-K gate dielectric layer 208, a bottom barrier layer 210, an etch stop layer 222, a sacrificial layer 226, and a pattern from bottom to top. The hard mask 228 is formed, and the dielectric layer 206, the high-K gate dielectric layer 208, the bottom barrier layer 210, the etch stop layer 222, and the sacrificial layer 226 all include a cross-sectional structure in the shape of a word. Further, in the preferred embodiment, the sacrificial layer 226 is a polycrystalline layer, but is not limited thereto. Please still refer to Figure 3. After the fabrication of the dummy gate 230 is completed, the ion implantation process of different conductivity types is respectively formed in the substrate 200 on both sides of the dummy gate 230 in the first active region 202a and the second active region 202b. A first lightly doped drain (LDD) 232a and a second LDD 232b. In addition, an offset spacer (not shown) may be formed on the sidewalls of the dummy gate 230 before forming the first LDD 232a and the second LDD 232b, respectively. Subsequently, a sidewall 234 is formed on the sidewall of the dummy gate 230, respectively, 201242018. Finally, a first source/drain 236a and a second source are respectively formed in the substrate 200 on both sides of the sidewall 234 of the first active region 202a and the second active region 202b by using different conductivity type ion implantation processes. / bungee 236b. A first conductive type semiconductor element 240a and a second conductive type semiconductor element 240b are formed in the first active region 202a and the second active region 2〇2b, respectively. In addition, in the preferred embodiment, a selective strain scheme (SSS) or the like may be combined, for example, a selective epitaxial growth (SEG) method is used to fabricate the first source/drain 236a and second source/drain 236b. For example, when the first conductive type semiconductor element 240a is a p-type semiconductor element and the second conductive type semiconductor element 240b is an n-type semiconductor element, an epitaxial layer containing a distorted germanium (SiGe) can be utilized and included The epitaxial layer of the bismuth carbide (Sic) respectively forms the first source/drain 236a and the second source/drain 236b to improve the electrical performance by utilizing the stress between the epitaxial layer and the gate channel . In addition, the surface of the first source/drain 236a and the second source/drain 236b respectively comprise a metal halide (not shown). After the first conductive type semiconductor element 240a and the second conductive type semiconductor element 240b are formed, a contact etch stop layer (CESL) 242 and an inner layer dielectric are sequentially formed on the semiconductor substrate 200. (ild) layer 244. Please refer to Figure 4. Next, a planarization process, such as a CMP process, is used to planarize the ILD layer 244 and the CESL 242 and remove the patterned hard mask 228' until the sacrificial layer 226 is exposed. After the planarization process, the 201242018 removes the sacrificial layer 226 by a etch process, and forms a gate trench 246 in the first active region 2〇2a and the second active region 202b, respectively. It is worthy of the squid that in the preferred embodiment, the inline etch stop layer 222 is used to protect the underlying barrier layer 21 high, the high_K interpolar dielectric layer 208 and the medium under the removal of the 203. Layer 206. And after the etching process, the inline etch stop layer 222 is exposed to the bottom of the gate trench 246. After the fabrication of the gate trench = 246 is completed, as shown in FIG. 4, a first work function metal layer 25 is formed on the in-line etch stop layer 222 in the substrate 200 and the gate trench 246. In a preferred embodiment, the first work function metal layer 250 is a first conductive type semiconductor element 240a, that is, a metal layer required for the p-type semiconductor element 24〇a work function, and thus the first work function metal layer 250 has a The first work function 'and the first work function is between 4.8 eV and 5.2 eV. See Figure 5. Next, the force function metal layer 250 in the second active area transfer b is removed. It should be noted that in the preferred embodiment, the etch stop layer 222 can be used to protect the bottom barrier layer 21 high and high_K gates under the portion of the first work function metal layer 50. Electricity 2 208 and layer f application. Therefore, after removing the functional metal layer 25 of the second active region lion, the -shaped stop layer M2 is again exposed to the bottom of the gate trench 6 in the active region. After removing the first work function metal layer 25〇 in the second=region 202b, it is sequentially formed on the substrate in the interpole=246—the second work function metal layer, a filled metal layer 254′, and filled. Metal layer 254 fills gate trench 12 201242018 246. As shown in FIG. 5, in the first active region 2 () 2a, the second work function metal layer 252 and the filler metal I 2M are sequentially formed on the first work function metal layer 250 in the interpole trench; In the second active region 2, the work function metal layer 252 and the fill metal layer 254 are sequentially formed on the stop layer 222. In the preferred embodiment, the second work function metal layer is a metal layer that satisfies the work function of the second conductive type semiconductor device 24b, that is, the n-type semiconductor device 240b, and thus the second work function metal layer 252 There is a -second work function' and the second work function is between 396¥ and 43~. The filler metal layer 254 contains a metal material having a good filling ability and a low resistance value, such as IS ' but not limited thereto.凊 See Figure 6. After the fabrication of the first work function metal layer 25, the second work function metal layer 252, and the filling metal layer 254, a CMP process is performed to remove the excess first work function metal layer 25, The two work function metal layer 252 and the fill metal layer 254 form a first metal gate structure 260a of the first conductive type semiconductor element 240a and the first active region 202a and the second active region 202b, respectively. The first metal gate structure 260b of the second conductive type semiconductor element 240b. As shown in FIG. 6, the cross-sectional structure of the dielectric layer 206, the high-K gate dielectric layer 208, the bottom barrier layer 210, and the etch stop layer 222 of the first metal gate structure 260a in the preferred embodiment. The shape has a one-word shape; and the cross-sectional structure of the first work function metal layer 25A and the second work function metal layer 252 has a U-shape. In addition, the dielectric layer 206 of the second metal gate structure 260b, the high-K gate dielectric 13, the 201242018 electrical layer 208, the bottom barrier layer 210, and the etch stop layer 222 have a cross-section at the cross-section of the second metal gate structure 260b. The cross-section of the functional metal layer 252 is: - has a U shape. In addition, the present embodiment can also selectively remove the guest, 244 and CESL 242, etc., and then reform the CESL and dielectric layers to enhance the electrical performance of the semiconductor device 240a/240b. The method of fabricating the metal gate structure provided in accordance with the first preferred embodiment provides a metal gate structure 260a/鸠 having a --shaped stop layer 222. Since the word etch stop layer (2) is attached to the bottom barrier layer 21G before the (4) process of removing the portion of the first work function metal layer 25 (), it is formed in the undamaged _ The surface of the layer is so that the in-line etch stop layer 222^ formed by the ALD method 220 can reach a predetermined thickness and achieve a step coverage of 1%. Therefore, the j-shaped engraving stop layer 222 can provide good protection in the subsequent process: force to ensure that the underlying barrier layer 21G, high_K gate dielectric layer: " and the dielectric layer 206 are not protected The effect of any etching process ensures that the continuation of the metal gate structure 26〇a/26〇b has better reliability. Next, please refer to FIGS. 2 and 3 and 7 to 1 , 2 and 3 and 7 to 1 G are the gold provided by the present invention: Method for manufacturing gate structure A schematic view of a second preferred embodiment. In the second preferred embodiment, the substrate 2 is provided, the dielectric layer 2〇6 is formed on the substrate 2〇〇, the high-K gate dielectric layer 208 is formed, the bottom barrier layer is formed, 曰201242018, and ALD is utilized. The steps of forming the etch stop layer 222 and the like are the same as those of the first preferred embodiment and the second embodiment. Therefore, the steps can be referred to the second drawing and the above description, and will not be further described. In addition, in the second embodiment, a first conductive type semiconductor element 24a and a second conductive type semiconductor element 240b are respectively formed in the first active area 202a and the second active area 2〇2b. The steps of the components of the semiconductor elements 24A/24〇b and the dummy gates 230 are the same as in the first preferred embodiment and the third embodiment! The same is true for the same, so the steps are as shown in Figure 3 and the above description, and will not be repeated here. In the second preferred embodiment, the same components as those in the first preferred embodiment are denoted by the same reference numerals, and the material selection thereof may be the same as that disclosed in the first preferred embodiment. Please refer to Figure 7. The second preferred embodiment differs from the first preferred embodiment in that the sacrificial layer 226 is exposed by a CMP process, and the sacrificial layer 226 is removed by an etching process, and in the first active region 202a and the second After the gate trench 246 is formed in the active region 202b. As described above, the in-line etch stop layer 222 is used to protect the underlying barrier layer 210, the high-K gate dielectric layer 208 and the dielectric layer 206° below the sacrificial layer 226. The back 'inline shape stop layer 222 is exposed to the bottom of the gate trench 246. Thereafter, an etch stop layer 224 is formed on the in-line etch stop layer 222 and the substrate 200 in the gate trench 246 by an ALD method 220'. The thickness of the etch stop layer 224 is less than the thickness of the etch stop layer 222, and the material included in the etch stop layer 224 and the residual stop layer 222 15 201242018 _ is bad, and the formation of the table 224 is the same as the (4) stop layer 222. The material ^ stop layer can be said to be formed on the surface of a homogenous Bu. Stop layer 224 The etch stop layer 224 is formed on a homogenous _, 222, containing the same material, as the step coverage of the stop layer 224 can also be reached. Please refer to Figure 8. After the fabrication of the etch stop layer 224 is completed, a #第& work function metal layer 250 is formed on the etch stop layer 224 in the substrate 200 and the gate trench 246. In the preferred embodiment, the first work function metal layer 250 is also a metal layer that satisfies the work function requirement of the p-type semiconductor device 240a, so the first work function metal layer 250 has a first work function and the first work function. The system is between 4.8 eV and 5.2 eV. Please refer to Figure 9. Next, the first work function metal layer 250 in the second active region 2〇2b is removed. It should be noted that in the preferred embodiment, the etch stop layer 224 is used to protect the bottom barrier layer 210 and the high-K gate dielectric layer below the portion of the first work function metal layer 250. 208 and dielectric layer 206. Thus, after removing the first work function metal layer 250 in the second active region 202b, the etch stop layer 224 is exposed to the bottom of the gate trench 246 in the second active region 2〇2b. After the first work function metal layer 250 in the second active region 202b is removed, a 201242018 second work function metal layer 252 and a fill metal layer 254 are sequentially formed on the substrate 200, and the fill metal layer 254 is formed. Fill the gate trench 246. As shown in FIG. 9, in the first active region 202a, the second work function metal layer 252 and the fill metal layer 254 are sequentially formed on the first work function metal layer 250 in the gate trench 246; In the active region 202b, the second work function metal layer 252 and the fill metal layer 254 are sequentially formed on the etch stop layer 224. In the preferred embodiment, the second work function metal layer 252 is also a metal layer required for the work function of the n-type semiconductor device 240b, so the second work function metal layer 252 has a second work function, and the second work function. The system is between 3.9 eV and 4.3 eV. The filling metal layer 254 contains a metal material having a good filling ability, such as, but not limited to. Please refer to Figure 10. After the fabrication of the first work function metal layer 250, the second work function metal layer 252, and the filling metal layer 254, a CMP process is performed to remove the excess etch stop layer 224 and the first work function metal layer. 250, the second work function metal layer 252 and the filling metal layer 254, and forming a first metal gate of the first conductive type semiconductor element 240a in the first active region 202a and the second active region 202b on the substrate 200, respectively. The structure 270a and the second metal gate structure 270b of one of the second conductive type semiconductor elements 240b. As shown in FIG. 10, the cross-sectional structure of the dielectric layer 206, the high-K gate dielectric layer 208, the bottom barrier layer 210, and the etch stop layer 222 of the first metal gate structure 270a in the preferred embodiment. The shape of the etch stop layer 224, the first work function metal layer 250 and the second work function metal layer 252 has a U-shape. In addition, the cross-sectional structure of the dielectric layer 206, the high-K gate dielectric layer 208, the bottom barrier layer 210, and the etch stop layer 222 of the second metal gate junction 17 201242018 270b has a one-word open h shape. The cross-sectional structure of the etch stop layer 224 and the second work function metal layer 252 has a U-shape. In addition, the present embodiment can also selectively remove the ILD layer 2 and the CESL 242, and then reform the CESL and dielectric layers to enhance the electrical performance of the semiconductor elements 240a/240b. According to the method of fabricating the metal gate structure of the second preferred embodiment, a metal gate structure 270a/270b having an in-line etch stop layer 222 and a U-shaped etch stop layer 224 is provided. Since the inscribed etch stop 222 is formed on the barrier layer 210 before the etching process for removing the sacrificial layer 226, that is, formed on the surface of the heterogeneous film layer which has not been damaged, The glyph etch stop layer 222 is capable of reaching a predetermined thickness and reaches a step coverage of (7). Therefore, the in-line etch stop layer 222 can provide good protection in the etching process for removing the sacrificial layer 226, ensuring the lower barrier layer 210, the high-K gate dielectric layer 208 and the dielectric. Layers such as layer 2〇6 are not affected by the etching process. In addition, the U-shaped etch stop is formed before the first work function metal layer 25 is removed, and is formed on the in-line etch stop layer 222 having a homogenous surface, so that the 11-shaped etch stop layer 224 can also be formed. The predetermined thickness is reached and a step coverage of 1% is achieved. Therefore, the U-shaped etch stop layer 224 can provide good protection in the process of removing the first work function metal layer 250, ensuring the bottom barrier layer 210 and the high-K gate dielectric layer 2 below. 8 and dielectric layer 2〇6 film layer is not 18 201242018 affected by the etching process. Therefore, the second preferred embodiment ensures that the subsequently formed metal gate structure 270a/27〇b has better reliability. In summary, the metal gate structure and method of fabricating the same according to the present invention provides a metal gate structure having an in-line etch stop layer and a U-shaped etch stop layer. Since the in-line etch stop layer is formed on the bottom barrier layer or the high-K gate dielectric layer before the etching process, that is, formed on the undamaged film layer; and the U-shaped etch stop layer Then, it is formed on the inscription stop layer having a homogenous surface, so that both the inscription stop layer and the U-shaped etch stop layer obtain a predetermined thickness and a good step coverage. Therefore, the in-line etch stop layer and the U-shaped etch stop layer can provide good protection in the subsequent etching process, ensure that the underlying film layer is not affected by the etching process, and ensure that the subsequently formed metal gate structure is better. Awkwardness. The above is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the patent application of the present invention are within the scope of the present invention. [Simple Description of the Drawings] Figure 1 is a schematic diagram of a conventional method for fabricating a metal gate structure using a post-gate process. Figs. 2 to 6 are schematic views showing a first preferred embodiment of the method of the metal gate structure provided by the present invention. 19 201242018 FIGS. 2 and 3 and 7 to 10 are schematic views showing a second preferred embodiment of a method of fabricating a metal gate structure according to the present invention. [Main component symbol description] 100 substrate 104 titanium nitride layer 108 P-type work function metal layer 2 〇〇 substrate 202b second active region 206 dielectric layer 21 〇 bottom barrier layer 222 etch stop layer 226 sacrificial layer 230 dummy gate 232b second lightly doped drain 236a first source/drainage first-conductive material conductor element 242 contact hole engraving stop layer 246 gate trench 252 second work function metal layer 26〇a first-metal gate structure 27〇a first-metal gate structure 102 high dielectric constant gate dielectric layer 106 nitride layer 110 gate trench 202a first active region 204 shallow trench insulation 208 high dielectric constant gate dielectric layer 220 atomic layer Deposition Method 224 Etch Stop Layer 228 Patterned Hard Mask 232a First Lightweight Heteropole 234 Sidewall Sub-236b Second Source/Drain 240b Second Conductive Semiconductor Element 244 Inner Dielectric Layer 250 First Work Function Metal Layer 254 filler metal layer 260b second metal gate structure 270b second metal gate structure