WO2014176806A1

WO2014176806A1 - Semiconductor device and manufacturing method therefor

Info

Publication number: WO2014176806A1
Application number: PCT/CN2013/076475
Authority: WO
Inventors: 杨红; 王文武; 闫江; 马雪丽
Original assignee: 中国科学院微电子研究所
Priority date: 2013-05-03
Filing date: 2013-05-30
Publication date: 2014-11-06
Also published as: CN104134691A; CN104134691B

Abstract

Disclosed are a semiconductor device and a manufacturing method therefor. An example device may comprise: a substrate; and a gate stack which is formed on the substrate. The gate stack comprises a high-k gate dielectric layer and a gate conductor layer, wherein the gate conductor layer comprises a first metallic material layer and a second metallic material layer as well as an aluminium (Al) layer or an overlapping layer of Al and other metal or metallic compound sandwiched therebetween.

Description

Semiconductor device and method of manufacturing same

Priority is claimed on Japanese Patent Application No. 20131016077, filed on Jan. 3,,,,,,,,,,,,,,,,,,,,,, Technical field

The present disclosure relates to the field of semiconductors, and more particularly to a semiconductor device and a method of fabricating the same. Background technique

As the transistor feature size of large-scale integrated circuits continues to shrink, high-k gate dielectric/metal gate structures are gradually replacing conventional silicon/polysilicon gate structures. In order to meet the multi-value requirements of the device, the design of the double metal gate structure is generally adopted. That is, the NMOSFET and the PMOSFET are made of a metallic material having different work functions, so that the effective work function of the metal gate electrode is close to the conduction band edge (~4.2 eV) and the valence band edge (~5.1 eV) of the silicon substrate, respectively.

It is desirable to be able to more effectively adjust the effective work function of the gate electrode. Summary of the invention

It is an object of the present disclosure to at least partially provide a semiconductor device and a method of fabricating the same to more effectively adjust an effective work function of a gate electrode of the semiconductor device.

According to an aspect of the present disclosure, there is provided a semiconductor device comprising: a substrate; and a gate stack formed on the substrate, the gate stack including a high-k gate dielectric layer and a gate conductor layer, wherein the gate conductor layer includes A first layer of metallic material and a second layer of metallic material and an aluminum A1 layer sandwiched therebetween or a laminate of A1 and other metals or metal compounds.

In accordance with another aspect of the present disclosure, a method of fabricating a semiconductor device is provided, comprising: sequentially forming a high-k gate dielectric layer and a gate conductor layer on a substrate, and patterning them to form a gate stack, wherein the gate conductor The layer comprises a first layer of metallic material and a second layer of metallic material and an aluminum A1 layer sandwiched between them or a laminate of A1 and other metals or metal compounds.

According to an exemplary embodiment of the present disclosure, an A1 layer is inserted in a gate stack, particularly a gate conductor layer or A laminate of Al and other metals or metal compounds. By the diffusion of A1, the effective work function of the gate stack can be adjusted, and thus the multi-value adjustment of the semiconductor device can be realized. DRAWINGS

The above and other objects, features and advantages of the present disclosure will become more apparent from

1-2 are schematic diagrams showing a flow of manufacturing a semiconductor device in accordance with an embodiment of the present disclosure. detailed description

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that the description is only illustrative, and is not intended to limit the scope of the disclosure. In addition, descriptions of well-known structures and techniques are omitted in the following description in order to avoid unnecessarily obscuring the concept of the present disclosure.

Various structural schematics in accordance with embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, and some details are exaggerated for clarity of presentation and some details may be omitted. The various regions, the shapes of the layers, and the relative sizes and positional relationships therebetween are merely exemplary, and may vary in practice due to manufacturing tolerances or technical limitations, and may be Areas/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if a layer/element is "on" another layer/element, the layer/element may be "under" the other layer/element when the orientation is reversed.

According to an embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device can include a gate stack formed on a substrate. The gate stack can be a configuration of a high K gate dielectric layer/metallic gate conductor layer. According to an advantageous example, an aluminum (Al) layer or a stack of A1 and other metals or metal compounds is interposed in the metallic gate conductor layer to effectively adjust the effective work function of the gate stack. Here, the "effective work function" refers to a work function exhibited by the gate stack (in particular, the gate conductor layer) as a whole in electrical performance. In the case of inserting such an A1 layer or a laminate of A1 and other metals or metal compounds, the gate conductor layer may include a first metallic material layer under the A1 layer or laminate (which may have a corresponding a work function and/or a material capable of preventing A1 from diffusing downward) and a second metallic material layer on the A1 layer or stack (may have a corresponding second work function and/or can prevent A1 from rising Diffused material). Here, the term "metallic material" means a material exhibiting the same or similar electrical properties as a metal (for example, a work function close to a metal material), such as a metal material, a nitride of some metals such as TiN, or the like. By using the diffusion of A1 to these metallic material layers, the effective work function of the gate stack can be effectively adjusted. The first metallic material layer and the second metallic material layer may comprise the same or different materials (and thus have the same or different work functions, and those skilled in the art may select their respective work function and/or work function combination to Expand the adjustment range of the work function).

The gate stack can also include other layers. For example, the gate stack can include a gate dielectric protection layer and/or an etch stop layer disposed between the high K gate dielectric layer and the gate conductor layer. This layer or layers are particularly advantageous in CMOS integrated processes.

In accordance with other embodiments of the present disclosure, a method of fabricating a semiconductor device is provided. The method can include sequentially forming a high K gate dielectric layer and a gate conductor layer on the substrate and patterning them to form a gate stack. The gate conductor layer is, for example, a structure in which the first metal material layer and the second metal material layer are laminated with an A1 layer or a layer of A1 and another metal or metal compound. The technology of the present disclosure can be applied to a gate-first process as well as a back gate process. In the gate-first process, the high-k gate dielectric layer and the gate conductor layer can be directly formed on the surface of the substrate by a process such as deposition, and their patterning can be realized, for example, by lithography. In the gate-last process, the high-k gate dielectric layer and the gate conductor layer may be formed on the substrate, for example, by a deposition process or the like to fill a space between the gate spacers due to the removal of the sacrificial gate stack, and their composition may pass, for example, A planarization process such as chemical mechanical polishing (CMP) is performed to remain in the space.

According to an embodiment of the present disclosure, the material and/or thickness of the first metallic material layer and/or the second metallic material layer, the thickness of the A1 layer or the laminate of A1 and other metal or metal compounds, and/or may be selected. Parameters such as material and/or thickness of the other metal or metal compound to achieve adjustment of the effective work function of the gate stack. Due to various combinations of these parameters, a variety of effective work functions can be realized, and thus multi-threshold adjustment of the semiconductor device is realized.

In order to effectively control the diffusion of A1, according to an advantageous example, the semiconductor device can be heat treated. The temperature and/or time of the heat treatment can be selected based on the desired effective work function. This heat treatment can be carried out at various suitable stages. For example, it may be performed after forming each layer in the gate conductor layer, or at other timings after patterning.

The present disclosure can be presented in various forms, some of which are described below.

As shown in Figure 1, a substrate 1000 is provided. The substrate 1000 may be a suitable substrate in various forms, such as a bulk semiconductor substrate such as Si, Ge, etc., a compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb Etc., a semiconductor-on-insulator (SOI), etc. Here, a bulk silicon substrate and a silicon-based material will be described as an example. However, it should be noted that the present disclosure is not limited thereto.

On the substrate 1000, for example, by deposition, a high-k gate dielectric layer 1004, a first metallic material layer 1010, an Al layer or a laminate 1012 of A1 and other metals or metal compounds, and a second metallic material layer may be sequentially formed. 1014. For example, the high-k gate dielectric layer 1004 may include Hf0 ₂ or the like having a thickness of about 10-40 A; the first metallic material layer 1010 may include TiN or the like having a thickness of about 0.5-20 nm; the A1 layer or the A1 and other metals or metal compounds. The thickness of the laminate 1012 may be about 0.5-20 nm, the other metal may include Ti or the like, the metal compound may include TiN, TaN, etc.; the second metallic material layer 1014 may include the first metallic material layer 1010 The same or different materials, such as TiN, have a thickness of about 0.5-20 nm.

It should be noted here that those skilled in the art are aware of a variety of suitable high K gate dielectric materials and metallic gate conductor materials. For example, the work function of the first metallic material and/or the second metallic material itself can be close to the desired effective work function, so that the required effective work function can be achieved with a small amount of adjustment.

Additionally, in accordance with an advantageous example of the present disclosure, other layers may also be formed to improve device performance. For example, the interface layer 1002 can be formed by deposition or thermal oxidation on the surface of the substrate 1000. Interfacial layer 1002 can include an oxide (e.g., silicon oxide) having a thickness of between about 5A and 2 nm. In addition, between the high-k gate dielectric layer 1004 and the gate conductor layer (including the first metal material layer 1010, the A1 layer or the layer 1012 of the other metal or metal compound and the second metal material layer 1014), A gate dielectric protection layer 1006 and/or an etch etch stop layer 1008 may also be formed. For example, the gate dielectric protection layer 1006 may include TiN having a thickness of about 0.5-5 nm; the etch stop layer 1008 may include TaN having a thickness of about 0.5-8 nm. Generally, the gate dielectric protective layer 1006 and the etch stop layer 1008 are integrated in a CMOS process. Especially useful. For example, the gate dielectric protective layer 1006 can prevent the above metal/metal material from diffusing into the gate dielectric layer 1004 and thus causing problems such as a change in dielectric constant and an increase in gate leakage. Additionally, the etch stop layer 1008 can be used to function in etching a layer of PFET material in the NFET region in a CMOS integrated process that forms NFETs and PFETs. Further, other layers such as polysilicon or the like (not shown) may be formed over the gate conductor layer. One or more of these layers can be set as desired, as desired.

Next, as shown in Fig. 2, the above layers are patterned into a pattern corresponding to the gate stack, for example, by photolithography, and thus a gate stack is formed.

After the gate stack is formed, there are a number of ways to fabricate the device. For example, the gate stack can be used as a mask for halo and extension implants. Then, side walls 1016 can be formed on both sides of the gate stack. For example, the spacers 1016 can be formed by conformally depositing a layer of nitride (e.g., silicon nitride) on the substrate and selectively etching the nitride layer, such as reactive ion etching (RIE). Subsequently, source/drain implantation can be performed using the gate stack and spacers 1016 as a mask. Annealing can also be performed to activate the implanted ions and form source/drain regions. According to an example, the semiconductor device is formed as an n-type device.

As shown in Fig. 2, A1 in the laminate 1012 of the A1 layer or A1 and other metals or metal compounds may diffuse toward the first metallic material layer 1010 and the second metallic material layer 1014. According to an advantageous example, the structure shown in Fig. 2 can also be heat treated. For example, heat treatment may be carried out at about 100 to 900 ° C for about 10 seconds to 60 minutes. By controlling the temperature and/or time of the heat treatment, the diffusion of A1 into the metallic material layer can be adjusted to effectively adjust its work function. The specific temperature and/or specific time of the heat treatment can be selected according to the desired effective work function.

In addition, the material and/or thickness of the first metallic material layer and the second metallic material layer, the thickness of the A1 layer or the laminate of A1 and other metals or metal compounds, and/or the other metal or metal compound may be selected. The material and / or thickness to control the diffusion of A1. For example, the first metallic material layer 1010 and the second metallic material layer 1014 of different materials may be selected according to different diffusion coefficients of A1 between different materials to control the diffusion direction and depth of A1.

In addition, the first metallic material layer 1010 and/or the second metallic material layer 1014 may also be selected. It should be noted here that although the above describes an example of the gate-first process, the present disclosure is not limited to This. The techniques of the present disclosure may also be applied to a back gate process.

Advantageously, the techniques of the present disclosure are compatible with conventional CMOS processes. Therefore, effective work function adjustment of semiconductor devices (especially NMOS) can be achieved without introducing new materials and processes. In particular, according to an example of the present disclosure, the work function can be adjusted simply by adjusting the material and/or thickness of each layer in the gate conductor, and/or the temperature and/or time of subsequent heat treatment. For example, the fabrication of a multi-threshold device can be achieved by the material and/or thickness of the first metallic material layer and the second metallic material layer. The technique according to the present disclosure is highly scalable. For example, a more flexible work function adjustment can be achieved by inserting another metal or metal compound layer between the A1 layer and the first metallic material layer and/or the A1 layer and the second metallic material layer.

In the above description, detailed descriptions of the technical details such as patterning and etching of the respective layers have not been made. However, it will be understood by those skilled in the art that layers, regions, and the like of a desired shape can be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. In addition, although the respective embodiments have been described above, this does not mean that the measures in the respective embodiments are not advantageously used in combination.

The embodiments of the present disclosure have been described above. However, the examples are for illustrative purposes only and are not intended to limit the scope of the disclosure. The scope of the disclosure is defined by the appended claims and their equivalents. Numerous alternatives and modifications may be made by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to fall within the scope of the present disclosure.

Claims

Claim

A semiconductor device comprising:

Substrate;

a gate stack formed on a substrate, the gate stack including a high-k gate dielectric layer and a gate conductor layer, wherein the gate conductor layer includes a first metallic material layer and a second metallic material layer and sandwiched therebetween Aluminum A1 layer or a laminate of A1 and other metals or metal compounds.

The semiconductor device according to claim 1, wherein the first metallic material layer and the second metallic material layer comprise the same metallic material.

3. The semiconductor device according to claim 2, wherein the metallic material comprises TiN.

The semiconductor device according to claim 1, wherein the semiconductor device is an n-type device.

5. The semiconductor device according to claim 1, further comprising:

An interfacial layer formed on the surface of the substrate.

6. The semiconductor device according to claim 1, further comprising:

A gate dielectric protective layer formed between the high-k gate dielectric layer and the gate conductor layer.

7. The semiconductor device of claim 6, further comprising:

An etch stop layer formed between the gate dielectric protective layer and the gate conductor layer.

8. The semiconductor device according to claim 7, wherein the gate dielectric protective layer comprises TiN, and the etch stop layer comprises TaN.

The semiconductor device according to claim 1, wherein the laminate of the A1 layer or Al and other metal or metal compound has a thickness of about 0.5 to 20 nm.

The semiconductor device according to claim 1, wherein the first metallic material layer and the second metallic material layer each have a thickness of about 0.5 to 20 nm.

11. A method of fabricating a semiconductor device, comprising:

Forming a high-k gate dielectric layer and a gate conductor layer sequentially on the substrate and patterning them to form a gate stack,

Wherein, the gate conductor layer comprises a first metallic material layer and a second metallic material layer and an aluminum A1 layer sandwiched therebetween or a laminate of A1 and other metals or metal compounds.

12. The method of claim 11 further comprising:

Selecting the material and/or thickness of the first metallic material layer and/or the second metallic material layer, the thickness of the A1 layer or the laminate of A1 and other metal or metal compounds, and according to the desired effective work function of the gate stack / or the material and / or thickness of the other metal or metal compound.

13. The method of claim 11 further comprising:

The semiconductor device is subjected to a heat treatment in which the temperature and/or time of the heat treatment is selected in accordance with the required effective work function of the gate stack.

14. The method according to claim 13, wherein the heat treatment is performed at about 100 to 900 ° C for about 10 seconds to 60 minutes.