WO2012003611A1

WO2012003611A1 - Semiconductor device and menufacturing method thereof

Info

Publication number: WO2012003611A1
Application number: PCT/CN2010/001428
Authority: WO
Inventors: 朱慧珑; 刘洪刚; 骆志炯; 梁擎擎
Original assignee: 中国科学院微电子研究所
Priority date: 2010-07-07
Filing date: 2010-09-17
Publication date: 2012-01-12
Also published as: CN102315126A; WO2012003611A8

Abstract

A semiconductor device and a manufacturing method thereof are provided. The method includes that: epitaxially growing a stack structure comprised of wide band-gap III-V group compound semiconductor layer (1002)/ narrow band-gap III-V group compound semiconductor layer (1003)/ wide band-gap III-V group compound semiconductor layer (1004) on a body semiconductor substrate (1001); forming a gate stack on the stack structure; forming embedded strain zones in the body semiconductor substrate; forming source/drain regions on both sides of the gate stack and in the stack structure.

Description

Semiconductor device and manufacturing method thereof

Technical field

The present invention relates to the field of semiconductors, and more particularly to a novel semiconductor device and a method of fabricating the same, and more particularly to a high performance III-V metal oxide semiconductor field effect transistor (MOSFET) and a method of fabricating the same. Background technique

It has been confirmed that the strain in the channel can significantly affect the metal oxide semiconductor field effect transistor

The mobility of carriers in (MOSFET). For example, compressive stress along the channel helps to improve the performance of pFETs (p-type field effect transistors), while tensile stress along the channel helps improve the performance of nFETs (n-type field effect transistors).

For pFETs, the formation of SiGe embedded in the source/drain regions has been shown to effectively introduce compressive stresses in the channel and thereby improve the performance of the pFET. Similarly, for nFETs, the formation of Si:C embedded in the source and drain has been shown to effectively introduce tensile stress in the channel and thereby improve the performance of the nFET.

It has been found that III-V compound semiconductors contribute to improved carrier mobility. Therefore, the application of III-V compound semiconductors in integrated circuit processes has been explored. However, to date, there is no effective means for applying stress in such devices made of III-V semiconductors.

In view of the above, there is a need to provide a novel semiconductor device and a method of fabricating the same, and more particularly to a III-V family.

A MOSFET and a method of fabricating the same, in which stress can be effectively applied to a channel region thereof to improve its performance. Summary of the invention

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of fabricating the same that overcome the above problems in the prior art.

According to an aspect of the invention, a method of fabricating a semiconductor device is provided, comprising: epitaxially growing a wide band gap III-V compound semiconductor layer/narrow band gap III-V compound semiconductor layer/wide band gap III on a bulk semiconductor substrate a stacked structure of a group V compound semiconductor layer; forming a gate stack on the stacked structure; forming an embedded strain region in the bulk semiconductor substrate; and on both sides of the gate stack, in the stack Source/drain regions are formed in the layer structure. Preferably, the wide band gap III-V compound semiconductor includes any one of InAlAs, InP, AlSb, AlGaSb, GaP, InGaP, AlGaAs, InAlSb; and the narrow band gap III-V compound semiconductor includes InAs, InGaAs Any one of GaAs, GaSb, InGaSb, and InSb.

Preferably, the wide band gap ΙΠ-V compound semiconductor layer has a thickness of 1 to 5 nm; and the narrow band gap III-V compound semiconductor layer has a thickness of 5 to 20 nm.

Preferably, the gate stack comprises a high k gate dielectric / metal gate stack or a high k gate dielectric / metal gate / polysilicon stack.

Preferably, the gate stack comprises a gate dielectric/polysilicon gate stack, and after forming the source/drain regions, the method further comprises: removing the gate stack; forming an alternate high k gate dielectric/metal gate stack.

Preferably, the step of forming the embedded strain region comprises: forming a sacrificial strain region on both sides of the gate stack and embedding the semiconductor substrate; removing the sacrificial strain region; forming an embedded strain region. Wherein the step of forming the sacrificial strain region comprises: implanting As or P into the semiconductor substrate on both sides of the gate stack to form a sacrificial strain region.

Preferably, the semiconductor substrate includes shallow trench isolation for isolating adjacent devices. Thus, the step of removing the sacrificial strain region to form an embedded strain region includes: etching from the upper portion of the shallow trench isolation to a portion of the shallow trench isolation; selectively etching the remaining shallow trench isolation and Sacrificial strain zone; by epitaxial growth, an embedded strain zone is formed. Further preferably, before selectively etching the remaining shallow trench isolation, the method further comprises: covering the gate stack with the dielectric layer and the top and outer sides of the remaining stacked structures on both sides.

Preferably, the narrow band gap III-V compound semiconductor layer comprises at least one layer.

Preferably, the bulk semiconductor substrate comprises Si, and the embedded strain region comprises Si:C or SiGe.

Preferably, the step of forming source/drain regions comprises: forming source/drain regions in a stacked structure on both sides of the gate stack by ion implantation; wherein for nMOSFET, implanted ions include Si or S; for pMOSFET, implanted The ions include Zn or Be.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a bulk semiconductor substrate; a stacked structure comprising a wide band gap III-V compound semiconductor layer/narrow band gap III-V compound semiconductor layer/wide band gap III a -V group compound semiconductor layer formed on the bulk semiconductor substrate; a gate stack formed on the stacked structure; an embedded strain region formed on both sides of the gate stack, embedded in the bulk semiconductor substrate And a source/drain region formed in a stacked structure on both sides of the gate stack.

Preferably, the wide band gap III-V compound semiconductor includes any one of InAlAs, InP, AlSb, AlGaSb, GaP, InGaP, AlGaAs, InAlSb; and the narrow band gap ΙΠ-V compound semiconductor package Any of InAs, InGaAs, GaAs, GaSb, InGaSb, and InSb.

Preferably, the wide band gap III-V compound semiconductor layer has a thickness of 1 to 5 nm; and the narrow band gap III-V compound semiconductor layer has a thickness of 5 to 20 nm.

Preferably, for the nMOSFET, the source/drain regions include Si or S ions; and for the pMOSFET, the source/drain regions include Zn or Be ions.

According to an embodiment of the present invention, stress is applied to source/drain regions formed in a III-V compound semiconductor stacked structure formed on a bulk semiconductor substrate by forming an embedded strain region in a bulk semiconductor substrate. Thereby, stress is effectively applied to the ι-type compound semiconductor device to improve its performance without adversely affecting its structure. DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent from

1 to 12 are schematic cross-sectional views showing stages of a semiconductor device according to a first embodiment of the present invention during fabrication;

13 to 26 are schematic cross-sectional views showing stages of a semiconductor device in accordance with a second embodiment of the present invention during fabrication. detailed description

Hereinafter, the present invention will be described by way of specific embodiments shown in the drawings. However, it is to be understood that the description is not intended to limit the scope of the invention. In addition, descriptions of well-known structures and techniques are omitted in the following description in order to avoid unnecessarily obscuring the inventive concept.

A schematic diagram of a layer structure in accordance with an embodiment of the present invention is shown in the accompanying drawings. The figures are not drawn to scale, and some details are exaggerated for clarity and some details may be omitted. The various regions, the shapes of the layers, and the relative sizes and positional relationships between the figures are merely exemplary, and may vary in practice due to manufacturing tolerances or technical limitations, and those skilled in the art will It is desirable to additionally design regions/layers having different shapes, sizes, relative positions. (First Embodiment) A first embodiment of the present invention will be described below with reference to Figs.

As shown in Fig. 1, the manufacturing process according to the present invention starts from a bulk wafer such as a bulk Si wafer. Specifically, a stacked structure of a wide band gap III-V compound semiconductor material and a narrow band gap III-V compound semiconductor material is epitaxially grown on a bulk wafer, i.e., a semiconductor substrate 1001. For example, the following structure can be grown: two layers of wide band gap semiconductor material such as InAlAs 1002 and 1004, and a layer of narrow band gap material sandwiched between them, such as InAs or InGaAs 1003. The narrow band gap material layer can include at least one layer. For example, the wide band gap material layers such as InAlAs 1002 and 1004 may have a thickness of about 1 to 5 nm, and the narrow band gap material layers such as InAs or InGaAs 1003 may have a thickness of about 5 to 20 nm. Such epitaxial growth can be carried out, for example, by techniques such as molecular beam epitaxy (MBE).

Of course, combinations of other wide/narrow band gap III-V compound semiconductor material layers may also be used herein. For example, the wide band gap III-V compound semiconductor may include InAlAs, InP, AlSb, AlGaSb, GaP, InGaP, AlGaAs, Any one of InAlSb; and the narrow band gap III-V compound semiconductor may include any one of InAs, InGaAs, GaAs, GaSb, InGaSb, InSb.

A preferred combination may include any one or combination of the following: a wide band gap III-V compound semiconductor may be InAlAs or InP, a narrow band gap III-V compound semiconductor may be InAs or InGaAs; or a wide band gap III-V compound The semiconductor may be AlGaAs or InGaP, the narrow band gap III-V compound semiconductor may be GaAs; or the wide band gap III-V compound semiconductor may be InAlSb, AlSb or AlGaSb, and the narrow band gap III-V compound semiconductor may be GaSb, AnAs or InSb.

As shown in FIG. 2, preferably, in the stacked structure in which the semiconductor substrate 1001 includes the above, the stacked structure and the semiconductor substrate 1001 are embedded to form a shallow trench isolation (STI) 1005 to isolate the individual devices. region. Such an STI structure can be formed, for example, from SiO ₂ .

Next, a gate stack is formed on the substrate subjected to the above processing. In the present invention, for example, a high-k gate dielectric/metal gate stack can be employed. Specifically, first, as shown in FIG. 3, a high-k gate dielectric layer 1006 and a metal layer 1007 are sequentially deposited on the structure shown in FIG. For example, the high-k gate dielectric layer 1006 can be ΗίΌ ₂ and the metal 1007 can be tungsten (W). Here, the high-k gate dielectric layer 1006 may have a thickness of about 2 to 4 nm, and the metal layer 1007 may have a thickness of about 50 to 150 nm. Then, as shown in FIG. 4, the metal layer 1007 is patterned to form a gate stack. Specifically, for example, a photoresist 1008 is coated on the metal layer 1007 and then exposed through a mask to pattern the photoresist 1008 into a desired gate stack shape. Subsequently, the metal layer 1007 is etched (eg, reactive ion etching RIE) to form a corresponding gate stack. After etching, the photoresist 1008 is removed. The structure of the gate stack may also be composed of a high-k dielectric material/metal/polysilicon stack or a gate dielectric layer/conductive material/polysilicon stack, or a combination of other combinations, which is not limited in the present invention. Here, it should be noted that in this step, the high-k gate dielectric 1006 is preferably not simultaneously etched to protect the underlying stacked structure. However, the present invention is not limited to this. The high-k gate dielectric layer 1006 can also be etched simultaneously such that it forms a final gate stack with the metal layer 1007.

Next, as shown in Fig. 5, side walls 1009 are formed on both sides of the formed gate stack. For example, the side wall 1009 can include a nitride. Specifically, the spacers 1009 are formed, for example, by depositing a layer of nitride and selectively etching the layer nitride (e.g., RIE) so that the nitride remains only on the side of the gate stack.

After the gate stack and the spacers are formed as described above, an embedded strain region may be formed in the semiconductor substrate 1001 to apply stress to the subsequently formed source/drain regions. In order to form such an embedded strain region, for example, a sacrificial strain region can be formed first in the semiconductor substrate, and then the sacrificial strain region can be replaced to form a final embedded strain region.

Specifically, as shown in Fig. 6, ion implantation is performed using, for example, As or P plasma. The energy of the ion implantation is controlled so that the implanted ions can enter the semiconductor substrate 1001 under the stacked structure on both sides of the gate stack. Then, as shown in Fig. 7, heat treatment may optionally be performed, for example, annealing at a temperature of about 800-900 ° C to activate the implanted As or P ions to form the sacrificial strain region 1010. This ion implantation is similar to the source/drain ion implantation process in conventional CMOS processes and will not be described here. Here, since the implanted group III or V element ions (such as As or P), the ion implantation has little effect on the laminated structure (e.g., InAlAs/InAs).

After the sacrificial strain zone is formed as described above, the sacrificial strain zone can be "replaced" to enable the stressed strain zone to be replaced by the embedded strain zone with stress to achieve the stress structure.

To do this, it is first necessary to expose the sacrificial strain zone portion and thereby remove it. Therefore, as shown in FIG. 8, the high-k gate dielectric layer 1006 can be sequentially applied (if the high-k gate dielectric 1006 has been etched together when the metal 1007 is etched, it is not required here) and the STI 1005 is performed. Selective etching (eg, RIE). Specifically, the high-k gate dielectric 1006 is selectively etched to remain only under the gate stack and the sidewall spacers; in addition, the STI 1005 is selectively etched such that a portion of the sidewall of the semiconductor substrate 1001 is exposed ( In the present embodiment, a portion of the sacrificial strain region 1010 is exposed.

Then, preferably, as shown in Fig. 9, an etch protection layer (e.g., nitride) 1011 is deposited and patterned to remove portions thereof above the STI 1005. Therefore, the etch protection layer 1011 covers the gate stack and the top and sidewalls of the stacked structure.

Next, as shown in FIG. 10, the STI 1005 is further selectively etched (eg, RIE) to substantially remove the STI 1005 to fully expose the sacrificial strain region 1010. Subsequently, the sacrificial strain region 1010 is selectively etched to substantially remove the sacrificial strain region 1010. Here, due to the sacrificial strain region 1010 and the semiconductor substrate 1001 This selective etching can be achieved by the difference in the impurity concentration, for example, by an etchant such as KOH, TMAH, EDP, Ν ₂ Η ₄ · Η ₂ 0 .

After the void is formed at the location of the sacrificial strain zone 1010 as described above, the formation of the embedded strain zone can be performed. Specifically, as shown in Fig. 11, in the cavity formed in the semiconductor substrate 1001 by removing the sacrificial strain region 1010, the embedded strain region 1012 is formed by selective epitaxial growth. The lattice structure of the embedded strain region 1012 is different from the lattice structure of the semiconductor substrate 1001 (for example, Si), thereby generating a certain stress, and the stress can be transmitted to the laminated structure, especially the narrow band gap material. In the layer 1003 (the source/drain and channel regions of the transistor structure of the present embodiment are formed in the narrow band gap material layer 1003), stress applied to the channel region is generated in the narrow band gap material layer 1003. For example, for an nFET (n-type field effect transistor), the embedded strain region 1012 can be Si:C to generate tensile stress; and for a pFET (p-type field effect transistor), the embedded strain region 1012 can be SiGe for Produces compressive stress.

Thus, the embedded strain zone is formed in the above manner. It should be noted that those skilled in the art can design other ways to form such an embedded strain zone without departing from the scope of the invention. An important feature of the present invention is to form an embedded strain region in a bulk semiconductor substrate to apply stress to source/drain regions formed in a III-V compound semiconductor stacked structure formed on a bulk semiconductor substrate, rather than embedding The specific formation of the strain zone.

After the embedded strain regions are formed as described above, the source may be formed on both sides of the gate stack, such as in the III-V compound semiconductor stacked structure (particularly in the narrow band gap material layer 1003), for example by ion implantation or the like. / Drain area (not shown). For example, for nFETs, Si or S can be used for ion implantation; for pFETs, Zn or Be can be used for ion implantation.

Thus, the basic structure of the semiconductor device according to the embodiment of the present invention is formed. As shown in FIG. 11, the semiconductor device includes: a bulk semiconductor substrate 1001; a stacked structure (1002, 1003, 1004) formed on the bulk semiconductor substrate 1001, including a wide band gap III-V compound semiconductor layer (1002) / narrow band gap III-V compound semiconductor layer (1003) / wide band gap III-V compound semiconductor layer (1004); gate stack formed on the stacked structure (1006, 1007); on both sides of the gate stack, in the semiconductor An embedded strain region (1012) embedded in the substrate 1001; and a source/drain region formed in the stacked structure (1002, 1003, 1004).

Finally, on the basis of the above basic structure, as shown in Fig. 12, a coating layer 1013 such as an oxide may be formed on the device structure formed as described above. The oxide is simultaneously deposited in the STI trench to form the STI again. In addition, a contact portion 1014 that is in contact with the source/drain regions may be formed. The contact portion 1014 is formed, for example, by etching a contact hole, then forming a liner in the contact hole, and finally filling the metal plug. Since the top has a coating 1013, and there is still a width The bandgap semiconductor material layer 1004, therefore the contact holes should penetrate deep into the narrow bandgap semiconductor material layer 1003 to form a good contact. The material of the liner may be formed of any one or more of the following: TaN, TiN, Ta, Ti, TiSiN, TaSiN, TiW, WN or Ru. The material of the metal plug may be: W, Al, Cu or TiAl.

The method of forming the source/drain regions is not limited to the above-described manner of ion implantation. Optionally, the cladding is removed over the stacked structures on both sides of the gate stack and a metal layer is formed. A preferred metal material is TaN. The source/drain regions can also be realized by the metal-semiconductor junction formed by the metal in contact with the underlying semiconductor, thus forming a Schottky barrier.

(Second embodiment)

The method of the present invention can also be compatible with replacement gate processes. Hereinafter, a second embodiment of the present invention will be described with reference to Figs. 13 to 26, in which a replacement gate process is incorporated. Hereinafter, differences between the second embodiment and the first embodiment will be mainly described; for steps not described in detail, reference may be made to the description of the corresponding steps in the above first embodiment. Like reference numerals in the drawings denote like parts.

First, as shown in Fig. 13, a stacked structure is formed on a semiconductor substrate 2001, for example, epitaxially grown InAlAs 2002, InAs/InGaAs 2003 > InAlAs2004. The composition of the laminated structure can be referred to the description of the previous embodiment.

For example, InAlAs 2002 and 2004 may have a thickness of about 1 to 5 nm, and InAs or InGaAs 2003 may have a thickness of about 5 to 20 nm.

Preferably, STI 2005 can be formed as shown in FIG.

Then, as described in FIGS. 15 and 16, a sacrificial gate stack is formed on the substrate subjected to the above processing. Specifically, as shown in FIG. 15, a sacrificial gate dielectric 2006 and a sacrificial gate body 2007 are sequentially deposited on the structure shown in FIG. For example, the sacrificial gate dielectric 2006 may be Si0 ₂ and the sacrificial gate body 2007 may be polysilicon. Here, the thickness of the sacrificial gate dielectric 2006 may be about 2 to 4 nm, and the thickness of the sacrificial gate body 2007 may be about 50 to 150 nm. Then, as shown in FIG. 16, the sacrificial gate body 2007 is patterned to form a sacrificial gate stack. Specifically, the photoresist 2008 is patterned, for example, on the sacrificial gate body 2007, and then exposed through a mask to form the desired gate stack shape. Subsequently, the sacrificial gate body 2007 is etched (eg, RIE) to form a corresponding gate stack. After the etching, the photoresist 2008 is removed.

Next, as shown in FIG. 17, sidewalls 2009 (e.g., nitride) are formed on both sides of the formed sacrificial gate stack. Subsequently, ion implantation of the sacrificial strain region is performed as shown in Fig. 18, and annealing treatment is performed to activate the implanted ions (e.g., As or P), thereby forming a sacrificial strain region 2010, as shown in Fig. 19.

Next, the sacrificial strain zone 2010 is subjected to a replacement process to form an embedded strain zone. To do this, first of all As shown in FIG. 20, the sacrificial gate dielectric 2006 is selectively etched (eg, RIE) to remain only under the gate stack and the sidewall spacers; in addition, the STI 2005 is selectively etched (eg, RIE) to expose A portion of the sidewall of the semiconductor substrate 2001 (in this embodiment, a portion of the sacrificial strain region 2010 is exposed). Then, as shown in FIG. 21, an etch protection layer 2011 is formed to cover the gate stack and the stacked structure.

Next, as shown in FIG. 22, the STI 2005 and the sacrificial strain region 2010 are removed by selective etching. Then, as shown in Fig. 23, in the cavity formed by the sacrificial strain region 2010 in the semiconductor substrate 2001, the embedded strain region 2012 is formed by selective epitaxial growth. For example, for an nFET (n-type field effect transistor), the embedded strain region 2012 can be Si:C to generate tensile stress; and for a pFET (p-type field effect transistor), the embedded strain region 2012 can be SiGe for Produces compressive stress.

Subsequently, as shown in FIG. 24, an interlayer dielectric layer 2013 (for example, SiO ₂ ) is deposited on the structure shown in FIG. 23 and planarized until reaching the etch protection layer 2011.

Next, as shown in FIG. 25, replacement gate processing is performed. Specifically, the etch protection layer 2011 on top of the sacrificial gate stack is removed by selective etching (eg, RIE). Then, the sacrificial gate body 2007 is further removed by selective etching (eg, RIE); the sacrificial gate dielectric 2006 may serve as an etch stop layer during the etching process. In the opening formed by removing the sacrificial gate body 2007, a high-k gate dielectric 2014 (for example, HfO ₂ ) and a metal layer 2015 (for example, W) are sequentially formed, thereby forming a replacement gate stack. Here, the gate stack may also include a high-k gate dielectric/metal gate/polysilicon stack. .

Here, the replacement gate treatment is preferably performed after the source/drain regions are formed in the stacked structure to avoid the process of forming the source/drain regions from affecting the gate performance.

Finally, as shown in Fig. 26, a coating 2016, such as a nitride, is formed on the device structure formed as described above. A contact portion 2017 that is in contact with the source/drain regions can be formed. The contact portion 2017 is formed, for example, by etching a contact hole and then filling a metal such as W.

In the above description, only one example of the replacement gate process has been described. It will be apparent to those skilled in the art that other forms of replacement gate processes can also be employed in the present invention.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. However, it should be understood by those skilled in the art that layers, regions, and the like of a desired shape can be formed by various means in the prior art. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above.

The invention has been described above with reference to the embodiments of the invention. However, these examples are for illustrative purposes only and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents Limited. Numerous alternatives and modifications may be made by those skilled in the art without departing from the scope of the invention.

Claims

Rights request

A method of fabricating a semiconductor device, comprising:

Epitaxial growth of a wide band gap III-V compound semiconductor layer on a bulk semiconductor substrate / narrow band gap III-V compound semiconductor layer / wide band gap πι-ν group compound semiconductor layer stack structure;

Forming a gate stack on the stacked structure;

Forming an embedded strain region in the bulk semiconductor substrate;

Source/drain regions are formed in the stacked structure on both sides of the gate stack.

2. The method according to claim 1, wherein

The wide band gap III-V compound semiconductor includes any one of InAlAs, InP, AlSb, AlGaSb, GaP, InGaP, AlGaAs, InAlSb;

The narrow band gap III-V compound semiconductor includes any one of InAs, InGaAs, GaAs, GaSb, InGaSb, and InSb.

The method according to claim 1, wherein the wide band gap III-V compound semiconductor layer has a thickness of 1 to 5 nm; and the narrow band gap III-V compound semiconductor layer has a thickness of 5 to 20 nm.

4. The method of claim 1, wherein the gate stack comprises a high k gate dielectric / metal gate stack or a high k gate dielectric / metal gate / polysilicon stack.

5. The method of claim 1, wherein the gate stack comprises a gate dielectric/polysilicon gate stack, and after forming the source/drain regions, the method further comprises:

Removing the gate stack;

An alternative high k gate dielectric/metal gate stack is formed.

6. The method according to claim 1, wherein the step of forming an embedded strain region comprises: forming a sacrificial strain region on both sides of the gate stack and embedding the semiconductor substrate;

Removing the sacrificial strain zone;

Form an embedded strain zone.

7. The method of claim 6, wherein the step of forming the sacrificial strain region comprises implanting As or P into the semiconductor substrate on both sides of the gate stack to form a sacrificial strain region.

8. The method of claim 7, wherein the semiconductor substrate comprises shallow trench isolation for isolating adjacent devices, Removing the sacrificial strain region, the step of forming the embedded strain region includes - etching from the upper portion of the shallow trench isolation to a portion of the shallow trench isolation;

Selectively etching the remaining shallow trench isolation and sacrificial strain regions;

By epitaxial growth, an embedded strain region is formed.

9. The method of claim 8 wherein, prior to selectively etching the remaining shallow trench isolation, the method further comprises:

The gate stack and the top and outer sides of the remaining laminate structures on both sides are covered with a dielectric layer.

10. The method according to claim 1, wherein the narrow band gap m-v compound semiconductor layer comprises at least one layer.

11. The method of claim 1, wherein the bulk semiconductor substrate comprises si, and the embedded strain region comprises Si:C or SiGe.

The method according to any one of claims 1 to 11, wherein the forming the source/drain regions comprises: forming source/drain regions in a stacked structure on both sides of the gate stack by ion implantation, wherein For an n-type semiconductor device, the implanted ions include Si or S; for a p-type semiconductor device, the implanted ions include Zn or Be.

13. A semiconductor device comprising:

Bulk semiconductor substrate;

a stacked structure comprising a wide band gap m-v compound semiconductor layer/narrow band gap m-v compound semiconductor layer/wide band gap III-V compound semiconductor layer formed on the bulk semiconductor substrate;

a gate stack formed on the stacked structure;

Embedded strain regions are formed on both sides of the gate stack, embedded in the bulk semiconductor substrate; and source/drain regions are formed in a stacked structure on both sides of the gate stack.

14. The semiconductor device according to claim 13, wherein

15. The method according to claim 13, wherein the thickness of the wide band gap III-V compound semiconductor layer is! 〜 5 nm; The narrow band gap III-V compound semiconductor layer has a thickness of 5 to 20 nm.

16. The method according to claim 13, wherein the narrow band gap mv group compound semiconductor layer comprises at least one layer.

17. The semiconductor device according to claim 13, wherein the bulk semiconductor substrate comprises Si, and the embedded strain region comprises Si:C or SiGe.

The semiconductor device according to any one of claims 13 to 17, wherein, for the n-type semiconductor device, Si or S ions are included in the source/drain regions; and for the p-type semiconductor device, the source/drain The zone includes Zn or Be ions.