WO2012003611A1 - Dispositif semi-conducteur et son procédé de fabrication - Google Patents

Dispositif semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2012003611A1
WO2012003611A1 PCT/CN2010/001428 CN2010001428W WO2012003611A1 WO 2012003611 A1 WO2012003611 A1 WO 2012003611A1 CN 2010001428 W CN2010001428 W CN 2010001428W WO 2012003611 A1 WO2012003611 A1 WO 2012003611A1
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Prior art keywords
band gap
gate stack
compound semiconductor
semiconductor substrate
semiconductor layer
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PCT/CN2010/001428
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English (en)
Chinese (zh)
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WO2012003611A8 (fr
Inventor
朱慧珑
刘洪刚
骆志炯
梁擎擎
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中国科学院微电子研究所
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Publication of WO2012003611A1 publication Critical patent/WO2012003611A1/fr
Publication of WO2012003611A8 publication Critical patent/WO2012003611A8/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Definitions

  • the present invention relates to the field of semiconductors, and more particularly to a novel semiconductor device and a method of fabricating the same, and more particularly to a high performance III-V metal oxide semiconductor field effect transistor (MOSFET) and a method of fabricating the same.
  • MOSFET metal oxide semiconductor field effect transistor
  • MOSFET Metal Organic field effect transistors
  • compressive stress along the channel helps to improve the performance of pFETs (p-type field effect transistors)
  • tensile stress along the channel helps improve the performance of nFETs (n-type field effect transistors).
  • the formation of SiGe embedded in the source/drain regions has been shown to effectively introduce compressive stresses in the channel and thereby improve the performance of the pFET.
  • the formation of Si:C embedded in the source and drain has been shown to effectively introduce tensile stress in the channel and thereby improve the performance of the nFET.
  • III-V compound semiconductors contribute to improved carrier mobility. Therefore, the application of III-V compound semiconductors in integrated circuit processes has been explored. However, to date, there is no effective means for applying stress in such devices made of III-V semiconductors.
  • An object of the present invention is to provide a semiconductor device and a method of fabricating the same that overcome the above problems in the prior art.
  • a method of fabricating a semiconductor device comprising: epitaxially growing a wide band gap III-V compound semiconductor layer/narrow band gap III-V compound semiconductor layer/wide band gap III on a bulk semiconductor substrate a stacked structure of a group V compound semiconductor layer; forming a gate stack on the stacked structure; forming an embedded strain region in the bulk semiconductor substrate; and on both sides of the gate stack, in the stack Source/drain regions are formed in the layer structure.
  • the wide band gap III-V compound semiconductor includes any one of InAlAs, InP, AlSb, AlGaSb, GaP, InGaP, AlGaAs, InAlSb; and the narrow band gap III-V compound semiconductor includes InAs, InGaAs Any one of GaAs, GaSb, InGaSb, and InSb.
  • the wide band gap ⁇ -V compound semiconductor layer has a thickness of 1 to 5 nm; and the narrow band gap III-V compound semiconductor layer has a thickness of 5 to 20 nm.
  • the gate stack comprises a high k gate dielectric / metal gate stack or a high k gate dielectric / metal gate / polysilicon stack.
  • the gate stack comprises a gate dielectric/polysilicon gate stack, and after forming the source/drain regions, the method further comprises: removing the gate stack; forming an alternate high k gate dielectric/metal gate stack.
  • the step of forming the embedded strain region comprises: forming a sacrificial strain region on both sides of the gate stack and embedding the semiconductor substrate; removing the sacrificial strain region; forming an embedded strain region.
  • the step of forming the sacrificial strain region comprises: implanting As or P into the semiconductor substrate on both sides of the gate stack to form a sacrificial strain region.
  • the semiconductor substrate includes shallow trench isolation for isolating adjacent devices.
  • the step of removing the sacrificial strain region to form an embedded strain region includes: etching from the upper portion of the shallow trench isolation to a portion of the shallow trench isolation; selectively etching the remaining shallow trench isolation and Sacrificial strain zone; by epitaxial growth, an embedded strain zone is formed.
  • the method further comprises: covering the gate stack with the dielectric layer and the top and outer sides of the remaining stacked structures on both sides.
  • the narrow band gap III-V compound semiconductor layer comprises at least one layer.
  • the bulk semiconductor substrate comprises Si
  • the embedded strain region comprises Si:C or SiGe.
  • the step of forming source/drain regions comprises: forming source/drain regions in a stacked structure on both sides of the gate stack by ion implantation; wherein for nMOSFET, implanted ions include Si or S; for pMOSFET, implanted The ions include Zn or Be.
  • a semiconductor device comprising: a bulk semiconductor substrate; a stacked structure comprising a wide band gap III-V compound semiconductor layer/narrow band gap III-V compound semiconductor layer/wide band gap III a -V group compound semiconductor layer formed on the bulk semiconductor substrate; a gate stack formed on the stacked structure; an embedded strain region formed on both sides of the gate stack, embedded in the bulk semiconductor substrate And a source/drain region formed in a stacked structure on both sides of the gate stack.
  • the wide band gap III-V compound semiconductor includes any one of InAlAs, InP, AlSb, AlGaSb, GaP, InGaP, AlGaAs, InAlSb; and the narrow band gap ⁇ -V compound semiconductor package Any of InAs, InGaAs, GaAs, GaSb, InGaSb, and InSb.
  • the wide band gap III-V compound semiconductor layer has a thickness of 1 to 5 nm; and the narrow band gap III-V compound semiconductor layer has a thickness of 5 to 20 nm.
  • the narrow band gap III-V compound semiconductor layer comprises at least one layer.
  • the bulk semiconductor substrate comprises Si
  • the embedded strain region comprises Si:C or SiGe.
  • the source/drain regions include Si or S ions; and for the pMOSFET, the source/drain regions include Zn or Be ions.
  • stress is applied to source/drain regions formed in a III-V compound semiconductor stacked structure formed on a bulk semiconductor substrate by forming an embedded strain region in a bulk semiconductor substrate.
  • stress is effectively applied to the ⁇ -type compound semiconductor device to improve its performance without adversely affecting its structure.
  • 1 to 12 are schematic cross-sectional views showing stages of a semiconductor device according to a first embodiment of the present invention during fabrication
  • 13 to 26 are schematic cross-sectional views showing stages of a semiconductor device in accordance with a second embodiment of the present invention during fabrication. detailed description
  • FIG. 1 A schematic diagram of a layer structure in accordance with an embodiment of the present invention is shown in the accompanying drawings.
  • the figures are not drawn to scale, and some details are exaggerated for clarity and some details may be omitted.
  • the various regions, the shapes of the layers, and the relative sizes and positional relationships between the figures are merely exemplary, and may vary in practice due to manufacturing tolerances or technical limitations, and those skilled in the art will It is desirable to additionally design regions/layers having different shapes, sizes, relative positions. (First Embodiment)
  • a first embodiment of the present invention will be described below with reference to Figs.
  • the manufacturing process according to the present invention starts from a bulk wafer such as a bulk Si wafer. Specifically, a stacked structure of a wide band gap III-V compound semiconductor material and a narrow band gap III-V compound semiconductor material is epitaxially grown on a bulk wafer, i.e., a semiconductor substrate 1001.
  • a bulk wafer i.e., a semiconductor substrate 1001.
  • the following structure can be grown: two layers of wide band gap semiconductor material such as InAlAs 1002 and 1004, and a layer of narrow band gap material sandwiched between them, such as InAs or InGaAs 1003.
  • the narrow band gap material layer can include at least one layer.
  • the wide band gap material layers such as InAlAs 1002 and 1004 may have a thickness of about 1 to 5 nm, and the narrow band gap material layers such as InAs or InGaAs 1003 may have a thickness of about 5 to 20 nm.
  • Such epitaxial growth can be carried out, for example, by techniques such as molecular beam epitaxy (MBE).
  • MBE molecular beam epitaxy
  • the wide band gap III-V compound semiconductor may include InAlAs, InP, AlSb, AlGaSb, GaP, InGaP, AlGaAs, Any one of InAlSb; and the narrow band gap III-V compound semiconductor may include any one of InAs, InGaAs, GaAs, GaSb, InGaSb, InSb.
  • a preferred combination may include any one or combination of the following: a wide band gap III-V compound semiconductor may be InAlAs or InP, a narrow band gap III-V compound semiconductor may be InAs or InGaAs; or a wide band gap III-V compound
  • the semiconductor may be AlGaAs or InGaP, the narrow band gap III-V compound semiconductor may be GaAs; or the wide band gap III-V compound semiconductor may be InAlSb, AlSb or AlGaSb, and the narrow band gap III-V compound semiconductor may be GaSb, AnAs or InSb.
  • the stacked structure and the semiconductor substrate 1001 are embedded to form a shallow trench isolation (STI) 1005 to isolate the individual devices. region.
  • STI shallow trench isolation
  • Such an STI structure can be formed, for example, from SiO 2 .
  • a gate stack is formed on the substrate subjected to the above processing.
  • a high-k gate dielectric/metal gate stack can be employed. Specifically, first, as shown in FIG. 3, a high-k gate dielectric layer 1006 and a metal layer 1007 are sequentially deposited on the structure shown in FIG.
  • the high-k gate dielectric layer 1006 can be ⁇ 2 and the metal 1007 can be tungsten (W).
  • the high-k gate dielectric layer 1006 may have a thickness of about 2 to 4 nm, and the metal layer 1007 may have a thickness of about 50 to 150 nm.
  • the metal layer 1007 is patterned to form a gate stack.
  • a photoresist 1008 is coated on the metal layer 1007 and then exposed through a mask to pattern the photoresist 1008 into a desired gate stack shape. Subsequently, the metal layer 1007 is etched (eg, reactive ion etching RIE) to form a corresponding gate stack. After etching, the photoresist 1008 is removed.
  • the structure of the gate stack may also be composed of a high-k dielectric material/metal/polysilicon stack or a gate dielectric layer/conductive material/polysilicon stack, or a combination of other combinations, which is not limited in the present invention.
  • the high-k gate dielectric 1006 is preferably not simultaneously etched to protect the underlying stacked structure.
  • the present invention is not limited to this.
  • the high-k gate dielectric layer 1006 can also be etched simultaneously such that it forms a final gate stack with the metal layer 1007.
  • side walls 1009 are formed on both sides of the formed gate stack.
  • the side wall 1009 can include a nitride.
  • the spacers 1009 are formed, for example, by depositing a layer of nitride and selectively etching the layer nitride (e.g., RIE) so that the nitride remains only on the side of the gate stack.
  • an embedded strain region may be formed in the semiconductor substrate 1001 to apply stress to the subsequently formed source/drain regions.
  • a sacrificial strain region can be formed first in the semiconductor substrate, and then the sacrificial strain region can be replaced to form a final embedded strain region.
  • ion implantation is performed using, for example, As or P plasma.
  • the energy of the ion implantation is controlled so that the implanted ions can enter the semiconductor substrate 1001 under the stacked structure on both sides of the gate stack.
  • heat treatment may optionally be performed, for example, annealing at a temperature of about 800-900 ° C to activate the implanted As or P ions to form the sacrificial strain region 1010.
  • This ion implantation is similar to the source/drain ion implantation process in conventional CMOS processes and will not be described here.
  • the implanted group III or V element ions such as As or P
  • the ion implantation has little effect on the laminated structure (e.g., InAlAs/InAs).
  • the sacrificial strain zone can be "replaced" to enable the stressed strain zone to be replaced by the embedded strain zone with stress to achieve the stress structure.
  • the high-k gate dielectric layer 1006 can be sequentially applied (if the high-k gate dielectric 1006 has been etched together when the metal 1007 is etched, it is not required here) and the STI 1005 is performed. Selective etching (eg, RIE). Specifically, the high-k gate dielectric 1006 is selectively etched to remain only under the gate stack and the sidewall spacers; in addition, the STI 1005 is selectively etched such that a portion of the sidewall of the semiconductor substrate 1001 is exposed ( In the present embodiment, a portion of the sacrificial strain region 1010 is exposed.
  • RIE reactive etching
  • an etch protection layer e.g., nitride
  • the etch protection layer 1011 covers the gate stack and the top and sidewalls of the stacked structure.
  • the STI 1005 is further selectively etched (eg, RIE) to substantially remove the STI 1005 to fully expose the sacrificial strain region 1010.
  • the sacrificial strain region 1010 is selectively etched to substantially remove the sacrificial strain region 1010.
  • This selective etching can be achieved by the difference in the impurity concentration, for example, by an etchant such as KOH, TMAH, EDP, ⁇ 2 ⁇ 4 ⁇ ⁇ 2 0 .
  • the formation of the embedded strain zone can be performed. Specifically, as shown in Fig. 11, in the cavity formed in the semiconductor substrate 1001 by removing the sacrificial strain region 1010, the embedded strain region 1012 is formed by selective epitaxial growth.
  • the lattice structure of the embedded strain region 1012 is different from the lattice structure of the semiconductor substrate 1001 (for example, Si), thereby generating a certain stress, and the stress can be transmitted to the laminated structure, especially the narrow band gap material.
  • the embedded strain region 1012 can be Si:C to generate tensile stress; and for a pFET (p-type field effect transistor), the embedded strain region 1012 can be SiGe for Produces compressive stress.
  • the embedded strain zone is formed in the above manner. It should be noted that those skilled in the art can design other ways to form such an embedded strain zone without departing from the scope of the invention.
  • An important feature of the present invention is to form an embedded strain region in a bulk semiconductor substrate to apply stress to source/drain regions formed in a III-V compound semiconductor stacked structure formed on a bulk semiconductor substrate, rather than embedding The specific formation of the strain zone.
  • the source may be formed on both sides of the gate stack, such as in the III-V compound semiconductor stacked structure (particularly in the narrow band gap material layer 1003), for example by ion implantation or the like. / Drain area (not shown).
  • Si or S can be used for ion implantation
  • pFETs Zn or Be can be used for ion implantation.
  • the semiconductor device includes: a bulk semiconductor substrate 1001; a stacked structure (1002, 1003, 1004) formed on the bulk semiconductor substrate 1001, including a wide band gap III-V compound semiconductor layer (1002) / narrow band gap III-V compound semiconductor layer (1003) / wide band gap III-V compound semiconductor layer (1004); gate stack formed on the stacked structure (1006, 1007); on both sides of the gate stack, in the semiconductor An embedded strain region (1012) embedded in the substrate 1001; and a source/drain region formed in the stacked structure (1002, 1003, 1004).
  • a coating layer 1013 such as an oxide may be formed on the device structure formed as described above.
  • the oxide is simultaneously deposited in the STI trench to form the STI again.
  • a contact portion 1014 that is in contact with the source/drain regions may be formed.
  • the contact portion 1014 is formed, for example, by etching a contact hole, then forming a liner in the contact hole, and finally filling the metal plug. Since the top has a coating 1013, and there is still a width The bandgap semiconductor material layer 1004, therefore the contact holes should penetrate deep into the narrow bandgap semiconductor material layer 1003 to form a good contact.
  • the material of the liner may be formed of any one or more of the following: TaN, TiN, Ta, Ti, TiSiN, TaSiN, TiW, WN or Ru.
  • the material of the metal plug may be: W, Al, Cu or TiAl.
  • the method of forming the source/drain regions is not limited to the above-described manner of ion implantation.
  • the cladding is removed over the stacked structures on both sides of the gate stack and a metal layer is formed.
  • a preferred metal material is TaN.
  • the source/drain regions can also be realized by the metal-semiconductor junction formed by the metal in contact with the underlying semiconductor, thus forming a Schottky barrier.
  • the method of the present invention can also be compatible with replacement gate processes.
  • a second embodiment of the present invention will be described with reference to Figs. 13 to 26, in which a replacement gate process is incorporated.
  • differences between the second embodiment and the first embodiment will be mainly described; for steps not described in detail, reference may be made to the description of the corresponding steps in the above first embodiment.
  • Like reference numerals in the drawings denote like parts.
  • a stacked structure is formed on a semiconductor substrate 2001, for example, epitaxially grown InAlAs 2002, InAs/InGaAs 2003 > InAlAs2004.
  • the composition of the laminated structure can be referred to the description of the previous embodiment.
  • InAlAs 2002 and 2004 may have a thickness of about 1 to 5 nm
  • InAs or InGaAs 2003 may have a thickness of about 5 to 20 nm.
  • STI 2005 can be formed as shown in FIG.
  • a sacrificial gate stack is formed on the substrate subjected to the above processing.
  • a sacrificial gate dielectric 2006 and a sacrificial gate body 2007 are sequentially deposited on the structure shown in FIG.
  • the sacrificial gate dielectric 2006 may be Si0 2 and the sacrificial gate body 2007 may be polysilicon.
  • the thickness of the sacrificial gate dielectric 2006 may be about 2 to 4 nm, and the thickness of the sacrificial gate body 2007 may be about 50 to 150 nm.
  • the sacrificial gate body 2007 is patterned to form a sacrificial gate stack.
  • the photoresist 2008 is patterned, for example, on the sacrificial gate body 2007, and then exposed through a mask to form the desired gate stack shape. Subsequently, the sacrificial gate body 2007 is etched (eg, RIE) to form a corresponding gate stack. After the etching, the photoresist 2008 is removed.
  • RIE etching
  • sidewalls 2009 e.g., nitride
  • ion implantation of the sacrificial strain region is performed as shown in Fig. 18, and annealing treatment is performed to activate the implanted ions (e.g., As or P), thereby forming a sacrificial strain region 2010, as shown in Fig. 19.
  • implanted ions e.g., As or P
  • the sacrificial strain zone 2010 is subjected to a replacement process to form an embedded strain zone.
  • the sacrificial gate dielectric 2006 is selectively etched (eg, RIE) to remain only under the gate stack and the sidewall spacers; in addition, the STI 2005 is selectively etched (eg, RIE) to expose A portion of the sidewall of the semiconductor substrate 2001 (in this embodiment, a portion of the sacrificial strain region 2010 is exposed).
  • an etch protection layer 2011 is formed to cover the gate stack and the stacked structure.
  • the embedded strain region 2012 is formed by selective epitaxial growth.
  • the embedded strain region 2012 can be Si:C to generate tensile stress; and for a pFET (p-type field effect transistor), the embedded strain region 2012 can be SiGe for Produces compressive stress.
  • an interlayer dielectric layer 2013 (for example, SiO 2 ) is deposited on the structure shown in FIG. 23 and planarized until reaching the etch protection layer 2011.
  • replacement gate processing is performed. Specifically, the etch protection layer 2011 on top of the sacrificial gate stack is removed by selective etching (eg, RIE). Then, the sacrificial gate body 2007 is further removed by selective etching (eg, RIE); the sacrificial gate dielectric 2006 may serve as an etch stop layer during the etching process.
  • a high-k gate dielectric 2014 for example, HfO 2
  • a metal layer 2015 for example, W
  • the gate stack may also include a high-k gate dielectric/metal gate/polysilicon stack. .
  • the replacement gate treatment is preferably performed after the source/drain regions are formed in the stacked structure to avoid the process of forming the source/drain regions from affecting the gate performance.
  • a coating 2016, such as a nitride is formed on the device structure formed as described above.
  • a contact portion 2017 that is in contact with the source/drain regions can be formed.
  • the contact portion 2017 is formed, for example, by etching a contact hole and then filling a metal such as W.

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Abstract

L'invention concerne un dispositif semi-conducteur et son procédé de fabrication. Ledit procédé consiste à faire croître par épitaxie une structure empilée composée d'une couche semi-conductrice de composés des groupes III-V à large bande interdite (1002), d'une couche semi-conductrice de composés des groupes III-V à bande interdite étroite (1003) et d'une couche semi-conductrice de composés des groupes III-V à large bande interdite (1004) sur un substrat semi-conducteur (1001); former un empilement de grille sur la structure empilée; former des zones de déformation intégrées dans le substrat semi-conducteur; et former des régions de source/drain des deux côtés de l'empilement de grille et dans la structure empilée.
PCT/CN2010/001428 2010-07-07 2010-09-17 Dispositif semi-conducteur et son procédé de fabrication WO2012003611A1 (fr)

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CN2010102272712A CN102315126A (zh) 2010-07-07 2010-07-07 半导体器件及其制作方法
CN201010227271.2 2010-07-07

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US10366892B2 (en) 2014-04-07 2019-07-30 International Business Machines Corporation Hybrid III-V technology to support multiple supply voltages and off state currents on same chip

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