WO2014169591A1 - 显示面板驱动方法、驱动装置及显示器件 - Google Patents
显示面板驱动方法、驱动装置及显示器件 Download PDFInfo
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- WO2014169591A1 WO2014169591A1 PCT/CN2013/084850 CN2013084850W WO2014169591A1 WO 2014169591 A1 WO2014169591 A1 WO 2014169591A1 CN 2013084850 W CN2013084850 W CN 2013084850W WO 2014169591 A1 WO2014169591 A1 WO 2014169591A1
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- display area
- signal
- starting time
- display
- synchronization signal
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 230000003111 delayed effect Effects 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 230000005540 biological transmission Effects 0.000 description 7
- 230000008054 signal transmission Effects 0.000 description 7
- 230000001360 synchronised effect Effects 0.000 description 6
- 238000005192 partition Methods 0.000 description 5
- 230000001934 delay Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
- 108010038447 Chromogranin A Proteins 0.000 description 1
- 102100031186 Chromogranin-A Human genes 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- CPTIBDHUFVHUJK-NZYDNVMFSA-N mitopodozide Chemical group C1([C@@H]2C3=CC=4OCOC=4C=C3[C@H](O)[C@@H](CO)[C@@H]2C(=O)NNCC)=CC(OC)=C(OC)C(OC)=C1 CPTIBDHUFVHUJK-NZYDNVMFSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
Definitions
- Embodiments of the present invention relate to a display panel driving method, a driving device, and a display device.
- the scan driving of the display module portion usually controls the gate driving circuit through a signal processing chip, thereby transmitting the gate driving signal to the display panel according to a preset timing, so there is no synchronization problem.
- a signal processing chip since the amount of signals that need to be processed at the same time becomes large, one chip usually cannot complete the scanning drive of the entire display panel, so multiple chips are usually used to simultaneously perform different display areas. Scanning drive, coordination between multiple chips is particularly important.
- a frame storage unit is usually added to each chip, and a serial peripheral interface (Serial Peripheral Int erface Bus, SP I) is usually used.
- SP I Serial Peripheral Int erface Bus
- the signal communicates between every two chips, allowing the two chips to work synchronously.
- the synchronization process specifically pre-stores one or more frames of the two chips, and the two chips simultaneously transmit data to the display areas controlled by the SP I signals.
- SP I Serial Peripheral Int erface Bus
- Embodiments of the present invention provide a display panel driving method, a driving device, and a display device, which can improve the delay in the gate driving signal of the sub-area control display panel and reduce the production cost.
- a display panel driving method is provided:
- the display panel includes at least two timing controllers and at least two display areas, each of which corresponds to one display area; the driving method includes: each timing controller obtains a synchronization signal according to the acquired display signal of the corresponding display area
- the synchronization signal includes a start time of the first line scan signal of the corresponding display area;
- the timing controller is configured according to at least one display area
- the sync signal of the domain adjusts the start timing of the first line scan signal of all display areas such that the start times of the first line scan signals of all display areas are the same.
- a display panel driving apparatus includes at least two timing controllers, each of which corresponds to a display area of a display panel, wherein each timing controller is acquired according to The display signal corresponding to the display area is synchronized, and the synchronization signal includes a start time of the first line scan signal of the corresponding display area; the timing controller adjusts the first line scan signal of all the display areas according to the synchronization signal of the at least one display area The starting time is such that the start times of the first line scan signals of all display areas are the same.
- a display device including the display panel driving device as described above is provided.
- FIG. 1 is a schematic flowchart of a display panel driving method according to an embodiment of the present invention
- FIG. 2 is a schematic flowchart of another display panel driving method according to an embodiment of the present invention
- FIG. 4 is a schematic diagram of a use of a display panel driving apparatus according to an embodiment of the present invention
- FIG. 5 is a timing structural diagram of a delay caused by a near-end signal processing process according to an embodiment of the present invention
- FIG. 6 is a timing structural diagram of delays caused by different transmission paths according to an embodiment of the present invention.
- the display panel provided by the embodiment of the present invention includes at least two timing controllers and at least two display areas, each of which corresponds to one display area.
- the driving method includes: each timing controller is configured according to the corresponding display area.
- the display signal obtains a synchronization signal, and the synchronization signal includes a start time of the first line scan signal of the corresponding display area; the timing controller adjusts the start time of the first line scan signal of all the display areas according to the synchronization signal of the at least one display area, The start times of the first line scan signals of all display areas are made the same.
- the timing controller realizes the difference calculation by synchronizing the synchronization signals at different positions, and realizes the position of the internal display screen by adjusting the starting position of the internal display screen. Synchronous adjustment of the timing signal effectively improves the delay of the gate drive signal.
- the display panel of such a structure does not need to be provided with a large number of display buffer units, thereby greatly reducing the production cost of the display product.
- the display panel includes two timing controllers, that is, a first timing controller and a second timing controller.
- the first timing controller corresponds to the first display area
- the second timing controller corresponds to the second display area.
- the display panel driving method provided by the embodiment of the present invention, as shown in FIG. 1, includes the following steps.
- the first timing controller obtains a first frame synchronization signal according to the acquired display signal of the first display area, where the first frame synchronization signal includes a start time of the first line of the first display area.
- the second timing controller obtains a second frame synchronization signal according to the acquired display signal of the second display area, where the second frame synchronization signal includes a start time of the first line of the second display area.
- the timing controller can acquire the display of the corresponding display area near the end The signal obtains a start timing of the first line scan signal of the display area by the time signal recorded in the display signal, thereby forming a frame synchronization signal.
- the timing controller adjusts the start timings of the first row scan signals of the first display region and the second display region according to the first frame synchronization signal and the second frame synchronization signal to make the first display region
- the start timing of the row scan signal is the same as the start timing of the first row scan signal of the second display region, and the two timing controllers include a first timing controller and a second timing controller.
- the display panel includes a plurality of display areas, and the display panel includes at least two timing controllers, each of which corresponds to one display area. For controlling the timing output of the gate drive signal in the display area.
- the first timing controller and the second timing controller described above are only used to distinguish any two different timing controllers, and are not intended to limit the number of timing controllers in the present invention. When multiple timing controllers are included, any of the two timing controllers can satisfy the above method steps.
- the display panel includes two timing controllers, that is, the first timing controller and the second timing controller are taken as an example, the first timing controller corresponds to the first display area, and the second timing control
- the display panel driving method provided by the embodiment of the present invention may include, for example, the following:
- the first timing controller obtains a first frame synchronization signal according to the acquired display signal of the first display area, where the first frame synchronization signal includes a start time of the first line scan signal of the first display area;
- the second timing controller obtains a second frame synchronization signal according to the acquired display signal of the second display area, where the second frame synchronization signal includes a start time of the first row scan signal of the second display area.
- the first timing controller receives the second frame synchronization signal sent by the second timing controller, and adjusts a start time of the first row scan signal of the first display area according to the first frame synchronization signal and the second frame synchronization signal ;
- the second timing controller receives the first frame synchronization signal sent by the first timing controller, and adjusts a start time of the first line scan signal of the second display area according to the first frame synchronization signal and the second frame synchronization signal.
- the respective frame synchronization signals can be sent to other timing controllers (ie, for the first timing controller, it sends the frame synchronization signal to the other than the first timing controller.
- the other timing controllers, for the second timing controller send the frame synchronization signal to other timing controllers than the second timing controller, so that the timing controller adjusts the start timing of the first line scan signal.
- adjusting the start timing of the first line scan signal according to the first frame synchronization signal and the second frame synchronization signal may include: according to the first frame synchronization signal and the The second frame synchronization signal obtains a first delay amount t1 between a start time of the first line scan signal of the first display area and a start time of the first line scan signal of the second display area;
- the display signal of the first display area and the second display area has a delay, for example, according to the delay amount displayed by the two areas is t1, it is only necessary to simultaneously display the signal timing to the front side.
- the signal timing is delayed by half of the delay amount by tl /2 , and the display of the signal timing is shifted by half of the delay amount by half of the delay amount of the signal timing.
- the start time of the first line scan signal in the display area corresponding to one of the timing controllers may be used as the standard time, and the remaining timing controllers respectively display the respective time points according to the standard time.
- the first row of scanning signal timing in the region is adjusted in advance or delayed to eliminate the delay amount of the start timing of the first row of scanning signals in different display regions, thereby realizing the synchronization of the partition control.
- a small number of row registers may be added to the internal timing controller, and the invalid data time (Vb l an ing time) is inserted or removed in the vertical direction in the display signal processing.
- Vb l an ing time the invalid data time
- the advance or delay of the scan signal timing Since several rows of registers are added to the timing controller, advancing or delaying several rows of signals does not affect the display.
- the display panel driving method may further include: Each timing controller obtains a synchronization signal according to the obtained display signal of the corresponding display area, and the synchronization signal further includes a start time of the last line scan signal corresponding to the display area; the timing controller starts and ends according to the start signal of the first line scan signal The start time of the line scan signal adjusts the start time of each line of the scan signal corresponding to the display area to eliminate the delay amount of the start time of each line of the scan signal in the corresponding display area.
- the display panel includes two timing controllers, that is, the first timing controller and the second timing controller are taken as an example, the first timing controller corresponds to the first display area, and the second timing controller Corresponding to the second display area, the display panel driving method provided by the embodiment of the present invention may further include:
- the first timing controller obtains a third frame synchronization signal according to the acquired display signal of the first display area, where the third frame synchronization signal includes a start time of the last line scan signal of the first display area.
- the first timing controller adjusts a start time of each line of the scan signal in the first display area according to the first frame synchronization signal and the third frame synchronization signal to eliminate a start time of each line of the scan signal in the first display area. The amount of delay.
- the line scan signal at the far end of the display area usually has a delay compared with the near-end line scan signal due to the production process or the external environment.
- the delay of the transmission path can be eliminated by collecting the frame sync signal of the far end.
- the processing by the first timing controller to adjust the start time of each line of the scan signal in the first display area according to the first frame synchronization signal and the third frame synchronization signal may include:
- the first timing controller obtains a second delay amount between a start time of the last line scan signal of the first display area and a start time of the first line scan signal according to the first frame sync signal and the third frame sync signal.
- the start time of each row of the scan signal in the first display area is adjusted in advance according to the second delay amount to eliminate the delay amount of the start time of each line of the scan signal in the first display area.
- the first timing controller obtains a second delay amount between a start time of the last line scan signal of the first display area and a start time of the first line scan signal according to the first frame synchronization signal and the third frame synchronization signal.
- t 2 the gate scan lines are equidistantly arranged in the vertical direction. According to the vertical resolution n of the display signal, the delay t 2/( nl ) generated by each line of the signal relative to the previous line during the transmission can be obtained.
- the inside of the controller can be adjusted
- the start signal position of the gate drive signal at different lines, that is, the start position of the mth row gate drive signal is advanced (m-1)* t 2/ ( n-1 ). This eliminates the effects of delays in the display area due to signal transmission paths.
- the process of timing adjustment of the gate driving signal by the first timing controller for the delay caused by the signal transmission path in the corresponding display area is also applicable to other timing controllers. That is to say, other timing controllers, such as the second timing controller, may also perform steps S205 and S206 to eliminate the delay amount of the start time of each line of the scanning signal in the second display area.
- steps S205 and S206 may also perform steps S205 and S206 to eliminate the delay amount of the start time of each line of the scanning signal in the second display area.
- the display panel is divided into left and right partial display areas, and the two display areas are respectively corresponding to the respective timing controllers, and the display panel driving method provided by the embodiment of the present invention is performed. Detailed description.
- the left and right timing controllers R respectively obtain the near-end display signals (S302), and form corresponding frame synchronization signals STV_L and STV_R (the suffixes L and R respectively indicate the left timing controller and Right timing controller) (S303), these frame sync signals will be output to the near end of the display panel to control the initialization of the gate driver.
- the left and right timing controllers R output gate drive signals 0E_L and 0E_R, respectively.
- STV, -L and STV, -R signals can be acquired at the far end after delay. (The far-end control signal is incremented, " to distinguish it from the near end).
- the respective frame synchronization signals STV are respectively transmitted to the other side between the two timing controllers for comparison (S304).
- a timing controller obtains the STV signal of the other party, first compare the STV_L and STV_R signals, and the delay difference tl (S305) of the two signals can be obtained.
- the left and right display areas are respectively adjusted at this time, wherein the timing of the STV_L is relatively advanced, the left display screen is delayed by tl/2 time, and the right display screen is advanced by tl/2 time (S306). ), so that the partition control can be synchronized.
- This method can be implemented by inserting or removing the vertical V-blanking time during the display signal processing. Since several rows of registers are added to the timing controller, several rows of signals are advanced or delayed without affecting the display. At this point, the delay caused by near-end signal processing can be eliminated.
- the remote STV signal needs to be collected (S 308 ). Since the reverse of the display screen is required in the conventional display panel, the remote STV signal is led to the external circuit, so the signal can be obtained by a related method in the prior art.
- the invention is not limited thereto.
- the timing controllers in the left and right regions respectively compare the STV and STV signals of the respective regions to obtain different delay amounts t 2 or 1 3 (S 309 ) caused by the signal transmission path in the vertical direction of the region, as shown in FIG. 6 .
- the timing controller internally obtains the delay t 2 / ( n-1 ) of each line of the signal relative to the previous line of the signal according to the vertical resolution n of the display signal.
- the timing controller internally adjusts the start signal position of the gate drive signal at different lines, that is, the mth line, and the start position of the gate drive signal is advanced (m_l) * t 2 / ( n-1 ) ( S 31 0 -S 31 1).
- the different delay effects caused by the respective signal transmission paths of the left and right display areas can be eliminated, thereby achieving the same display effect between the two display areas and within any display area.
- the timing controller realizes the difference calculation by synchronizing the synchronization signals at different positions, and realizes the position of the internal display screen by adjusting the starting position of the internal display screen. Synchronous adjustment of the timing signal effectively improves the delay of the gate drive signal.
- the display panel of such a structure does not need to be provided with a large number of display buffer units, thereby greatly reducing the production cost of the display product.
- the display panel driving device provided by the embodiment of the present invention includes at least two timing controllers, and each timing controller corresponds to one display area;
- Each timing controller obtains a synchronization signal according to the acquired display signals for the respective display areas, the synchronization signal includes a start time of the first line scan signal for the respective display area; and the timing controller is configured according to at least two timing controllers
- the sync signal of the display area adjusts the start timing of the first line scan signal such that the start timings of the first line scan signals of the different display areas are the same.
- the display panel driving device provided by the embodiment of the present invention includes at least two timing controllers, each of which corresponds to one display area.
- the embodiment is described by taking the display panel as two timing controllers, that is, including the first timing controller and the second timing controller.
- the first timing controller corresponds to the first display area
- the second timing controller corresponds to the second display area.
- a first timing controller 41 configured to obtain a first frame synchronization signal according to the acquired display signal of the first display area, where the first frame synchronization signal includes a first line scan of the first display area The starting moment of the signal.
- the second timing controller 42 is configured to obtain a second frame synchronization signal according to the acquired display signal of the second display area, where the second frame synchronization signal includes a start time of the first line scan signal of the second display area.
- the timing controller is further configured to adjust a start time of the first line scan signal according to the first frame synchronization signal and the second frame synchronization signal, so that a start time of the first line scan signal of the first display area is the first time of the second display area
- the start time of the line scan signal is the same.
- the timing controller realizes the difference calculation by synchronizing the synchronization signals at different positions, and realizes the position of the internal display screen by adjusting the starting position of the internal display screen. Synchronous adjustment of the timing signal effectively improves the delay of the gate drive signal.
- the display panel of such a structure does not need to be provided with a large number of display buffer units, thereby greatly reducing the production cost of the display product.
- the display panel includes a plurality of display areas
- the timing controller includes at least two timing controllers, each of which corresponds to one display area. For controlling the timing output of the gate drive signal in the display area.
- the first timing controller and the second timing controller described above are only used to distinguish any two different timing controllers, and are not intended to limit the number of timing controllers in the present invention. When multiple timing controllers are included, any of the two timing controllers can satisfy the above method steps.
- the first timing controller corresponds to the first display area
- the second timing controller corresponds to the second display area.
- the first timing controller can also be used to:
- the third frame synchronization signal includes a start time of the last line scan signal of the first display area.
- the line scan signal at the far end of the display area usually has a delay compared with the near-end line scan signal due to the production process or the external environment.
- the delay of the transmission path can be eliminated by collecting the frame sync signal of the far end.
- the first timing controller adjusts according to the first frame synchronization signal and the third frame synchronization signal
- the specific process of the start time of each row of scan signals in the first display area may include: the first timing controller obtaining the start time of the last line scan signal of the first display area according to the first frame synchronization signal and the third frame synchronization signal The second amount of delay between the start of the first line of the scan signal.
- the start time of each row of the scan signal in the first display area is adjusted in advance according to the second delay amount to eliminate the delay amount of the start time of each line of the scan signal in the first display area.
- the first timing controller obtains a second delay amount between a start time of the last line scan signal of the first display area and a start time of the first line scan signal according to the first frame synchronization signal and the third frame synchronization signal.
- t 2 the gate scan lines are equidistantly arranged in the vertical direction. According to the vertical resolution n of the display signal, the delay t 2/( nl ) generated by each line of the signal relative to the previous line during the transmission can be obtained.
- the controller can internally adjust (m-1) * t 2 / ( n-1 ) by adjusting the start signal position of the gate drive signal at different lines, that is, the start position of the m-th row gate drive signal. This eliminates the effects of delays in the display area due to signal transmission paths.
- the process of timing adjustment of the gate driving signal by the first timing controller for the delay caused by the signal transmission path in the corresponding display area is also applicable to other timing controllers.
- the embodiments of the invention are also to be considered as illustrative and not restrictive.
- a display device provided by an embodiment of the present invention includes the display panel driving device as described above.
- the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a camera, a video camera, a digital photo frame, a navigation device, and the like, or any display product or component.
- the display device provided by the embodiment of the invention includes a display panel driving device.
- the timing controller performs differential calculation between the synchronization signals at different positions, and adjusts the start of the internal display screen.
- the position realizes synchronous adjustment of the timing signal, thereby effectively improving the delay of the gate driving signal.
- the display panel of such a structure does not need to be provided with a large number of display buffer units, thereby greatly reducing the production cost of the display product. It will be understood by those skilled in the art that all or part of the steps of implementing the foregoing embodiments may be performed by hardware related to program instructions.
- the foregoing program may be stored in a computer readable storage medium, and when executed, the program includes The foregoing steps of the method embodiment; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.
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US14/236,204 US9607542B2 (en) | 2013-04-18 | 2013-10-08 | Display panel driving method, driving device and display device |
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CN201310136371.8A CN103236241B (zh) | 2013-04-18 | 2013-04-18 | 一种显示面板驱动方法、驱动装置及显示器件 |
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CN115083363A (zh) * | 2022-06-15 | 2022-09-20 | 海宁奕斯伟集成电路设计有限公司 | 时序信号产生装置、方法及屏幕逻辑板和液晶显示器装置 |
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---|---|---|---|---|
CN103236241B (zh) | 2013-04-18 | 2015-05-27 | 京东方科技集团股份有限公司 | 一种显示面板驱动方法、驱动装置及显示器件 |
CN103903548B (zh) * | 2014-03-07 | 2016-03-02 | 京东方科技集团股份有限公司 | 一种显示面板的驱动方法和驱动系统 |
KR20160076227A (ko) * | 2014-12-22 | 2016-06-30 | 삼성전자주식회사 | 디스플레이 장치, 이를 포함하는 디스플레이 시스템 및 디스플레이 방법 |
KR102431311B1 (ko) * | 2015-01-15 | 2022-08-12 | 티씨엘 차이나 스타 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 | 표시 장치 |
CN104900208B (zh) * | 2015-06-25 | 2018-07-06 | 京东方科技集团股份有限公司 | 时序控制器、时序控制方法及显示面板 |
CN105609078B (zh) * | 2016-02-01 | 2018-02-06 | 昆山龙腾光电有限公司 | 栅极驱动电路和液晶显示装置 |
US10354569B2 (en) * | 2017-02-08 | 2019-07-16 | Microsoft Technology Licensing, Llc | Multi-display system |
CN109754738A (zh) * | 2017-11-02 | 2019-05-14 | 瑞鼎科技股份有限公司 | 面板显示位置微调方法 |
KR102527852B1 (ko) * | 2018-05-02 | 2023-05-03 | 삼성디스플레이 주식회사 | 게이트 쉬프트량을 자동으로 설정하는 표시 장치 및 표시 장치의 구동 방법 |
CN112534493A (zh) * | 2018-07-25 | 2021-03-19 | 深圳市柔宇科技股份有限公司 | 显示装置、电子设备及显示驱动方法 |
CN114927110B (zh) * | 2022-06-27 | 2024-03-15 | 青岛信芯微电子科技股份有限公司 | 一种背光控制方法、显示设备、芯片系统及介质 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070052857A1 (en) * | 2005-09-08 | 2007-03-08 | Samsung Electronics Co., Ltd. | Display driver |
CN102592566A (zh) * | 2011-12-09 | 2012-07-18 | 友达光电股份有限公司 | 数据驱动装置、对应的操作方法与对应的显示器 |
CN202601137U (zh) * | 2012-05-04 | 2012-12-12 | 京东方科技集团股份有限公司 | 阵列驱动单元及显示装置 |
CN102968974A (zh) * | 2012-12-10 | 2013-03-13 | 深圳市华星光电技术有限公司 | 液晶显示器及其驱动显示方法 |
CN103236241A (zh) * | 2013-04-18 | 2013-08-07 | 京东方科技集团股份有限公司 | 一种显示面板驱动方法、驱动装置及显示器件 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1296753C (zh) * | 2003-07-11 | 2007-01-24 | 友达光电股份有限公司 | 多晶硅薄膜晶体管液晶显示器的电路布局方法 |
KR100983712B1 (ko) * | 2003-12-30 | 2010-09-24 | 엘지디스플레이 주식회사 | 액정표시장치의 구동부 |
KR100654775B1 (ko) * | 2004-12-08 | 2006-12-08 | 엘지.필립스 엘시디 주식회사 | 액정표시장치 및 이를 이용한 모바일단말기 |
CN101425272A (zh) * | 2007-10-31 | 2009-05-06 | 中华映管股份有限公司 | 用以降低扫描信号延迟的主动元件阵列及其平面显示器 |
CN101383913B (zh) * | 2008-08-28 | 2010-07-21 | 广东威创视讯科技股份有限公司 | 显示叠加控制系统及其控制方法 |
US8704732B2 (en) * | 2010-09-29 | 2014-04-22 | Qualcomm Incorporated | Image synchronization for multiple displays |
CN102592531B (zh) * | 2011-01-17 | 2015-01-14 | 奇景光电股份有限公司 | 显示装置及其时序控制模块 |
JP5488624B2 (ja) * | 2012-02-03 | 2014-05-14 | カシオ計算機株式会社 | 映像出力装置、及び映像出力方法 |
-
2013
- 2013-04-18 CN CN201310136371.8A patent/CN103236241B/zh not_active Expired - Fee Related
- 2013-10-08 US US14/236,204 patent/US9607542B2/en active Active
- 2013-10-08 WO PCT/CN2013/084850 patent/WO2014169591A1/zh active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070052857A1 (en) * | 2005-09-08 | 2007-03-08 | Samsung Electronics Co., Ltd. | Display driver |
CN102592566A (zh) * | 2011-12-09 | 2012-07-18 | 友达光电股份有限公司 | 数据驱动装置、对应的操作方法与对应的显示器 |
CN202601137U (zh) * | 2012-05-04 | 2012-12-12 | 京东方科技集团股份有限公司 | 阵列驱动单元及显示装置 |
CN102968974A (zh) * | 2012-12-10 | 2013-03-13 | 深圳市华星光电技术有限公司 | 液晶显示器及其驱动显示方法 |
CN103236241A (zh) * | 2013-04-18 | 2013-08-07 | 京东方科技集团股份有限公司 | 一种显示面板驱动方法、驱动装置及显示器件 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115083363A (zh) * | 2022-06-15 | 2022-09-20 | 海宁奕斯伟集成电路设计有限公司 | 时序信号产生装置、方法及屏幕逻辑板和液晶显示器装置 |
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US20150294614A1 (en) | 2015-10-15 |
US9607542B2 (en) | 2017-03-28 |
CN103236241A (zh) | 2013-08-07 |
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