WO2014169492A1 - 电致发光元件驱动电路 - Google Patents

电致发光元件驱动电路 Download PDF

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Publication number
WO2014169492A1
WO2014169492A1 PCT/CN2013/074553 CN2013074553W WO2014169492A1 WO 2014169492 A1 WO2014169492 A1 WO 2014169492A1 CN 2013074553 W CN2013074553 W CN 2013074553W WO 2014169492 A1 WO2014169492 A1 WO 2014169492A1
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Prior art keywords
thin film
film transistor
drain
electroluminescent element
source
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PCT/CN2013/074553
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English (en)
French (fr)
Inventor
郭平昇
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/992,718 priority Critical patent/US8896224B2/en
Publication of WO2014169492A1 publication Critical patent/WO2014169492A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an electroluminescent element driving circuit. ⁇ Background technique ⁇
  • electroluminescent displays have attracted more and more attention due to their wide viewing angle, fast response, high color saturation, etc., and their use is becoming more and more popular, especially in products such as mobile phones, media players and small entry-level TVs. Most notable.
  • FIG. 1 is a schematic structural view of a prior art electroluminescent element driving circuit.
  • a prior art electroluminescent element driving circuit includes: a switching thin film transistor ⁇ , a driving thin film transistor ⁇ 2', a storage capacitor C, and an electroluminescent element D'.
  • the function of the electroluminescent element driving circuit is: in the sampling phase, an electrical signal with a certain relationship of the brightness of the electroluminescent element D' is charged into the storage capacitor C; during the holding phase, the electrical signal stored in the storage capacitor C is guaranteed The electroluminescent element continues to emit light during the holding phase.
  • the prior art electroluminescent device D' will decay during the working process, and its resistance value will change, which causes its luminance to be greatly affected by its decay, which in turn leads to poor display performance of the electroluminescent display.
  • the technical problem to be solved by the present invention is to provide an electroluminescence element drive circuit capable of reducing the influence of the decay of the electroluminescence element on its brightness.
  • a technical solution adopted by the present invention is to provide an electroluminescent element driving circuit, wherein the electroluminescent element driving circuit comprises: a first thin film transistor, a second thin film transistor, a third thin film transistor, A fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a storage capacitor, and an electroluminescence element.
  • the cathode is connected to the source of the first thin film transistor
  • the source of the second thin film transistor is connected to the drain of the first thin film transistor
  • the source of the third thin film transistor is connected to the drain of the second thin film transistor
  • the drain of the third thin film transistor is The first end and the second end of the storage capacitor are respectively connected to the gate and the drain of the second thin film transistor
  • the source of the fourth thin film transistor is connected to the second working voltage
  • the source of the second thin film transistor is connected to the fourth thin film.
  • a drain of the transistor a source of the sixth thin film transistor is connected to a drain of the second thin film transistor, a drain of the sixth thin film transistor is connected to the data signal, and a source of the fifth thin film transistor is connected to a drain of the fourth thin film transistor, and the connection is
  • the gate of the second thin film transistor is connected to the drain of the fifth thin film transistor, and the duty cycle of the electroluminescent element driving circuit includes a sampling phase and a holding phase, and the first thin film transistor, the second thin film transistor, and the third thin film transistor are in the sustain phase source
  • the impedance formed by the drain and the overlap of the three is greater than the impedance of the electroluminescent element, the fourth thin film transistor
  • the fifth thin film transistor and the sixth thin film transistor are turned off in the sustain phase, and the second thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned on at the sampling stage, the source and the drain are turned on, A thin film transistor and a third thin film transistor are turned
  • the gates of the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are all connected to the first gate signal, and the gates of the first thin film transistor and the third thin film transistor are both connected to the first gate signal a second gate signal, the first gate signal and the second gate signal are used to control the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor to turn off the source and drain and control the first thin film transistor during the sustain phase, The second thin film transistor and the third thin film transistor are turned on in the sustain phase.
  • an electroluminescent element driving circuit comprising: a first thin film transistor, a second thin film transistor, a third thin film transistor, a storage capacitor, and an electro a light-emitting element, wherein an anode of the electroluminescent element is connected to a first working voltage, a cathode is connected to a source of the first thin film transistor, a source of the second thin film transistor is connected to a drain of the first thin film transistor, and a source of the third thin film transistor is connected The drain of the second thin film transistor, the third thin film The drain of the transistor is grounded, and the first end and the second end of the storage capacitor are respectively connected to the gate and the drain of the second thin film transistor.
  • the duty cycle of the electroluminescent element driving circuit includes a sampling phase and a holding phase, the first thin film transistor, The second thin film transistor and the third thin film transistor are turned on in the sustain phase, and the storage capacitor is used to store an electrical signal between the gate and the drain of the second thin film transistor in the sampling phase, and is used in the sustain phase.
  • the voltage between the gate and the drain of the second thin film transistor is kept varied with the electrical signal to control the brightness of the electroluminescent element.
  • the electroluminescent device driving circuit further includes: a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor, wherein a source of the fourth thin film transistor is connected to the second working voltage, and a source of the second thin film transistor is connected to the fourth a drain of the thin film transistor, a source of the sixth thin film transistor is connected to a drain of the second thin film transistor, a drain of the sixth thin film transistor is connected to the data signal, and a source of the fifth thin film transistor is connected to a drain of the fourth thin film transistor, and is connected
  • the gate of the second thin film transistor is connected to the drain of the fifth thin film transistor, and the second thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned on at the sampling stage, and the first thin film transistor is turned on.
  • the third thin film transistor is turned off at the source and drain during the sampling phase.
  • the gates of the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are all connected to the first gate signal, and the gates of the first thin film transistor and the third thin film transistor are both connected to the first gate signal a second gate signal, the first gate signal and the second gate signal are used to control the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor to turn off the source and drain and control the first thin film transistor during the sustain phase, The second thin film transistor and the third thin film transistor are turned on in the sustain phase.
  • the level of the first gate signal in the sampling phase is opposite to the level in the sustaining phase, and the first gate signal and the second gate signal are further used to control the source of the first thin film transistor and the third thin film transistor during the sampling phase And the drain is turned off and the second thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are controlled to be turned on at the sampling stage.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are N-channel thin film field effect transistors, first The gate signal is high during the sampling phase and low during the hold phase.
  • the electroluminescent element driving circuit is in the holding phase for a duration longer than the sampling phase in one duty cycle.
  • the electroluminescence element is an organic electroluminescence element.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are N-channel indium gallium oxide thin film transistors.
  • the sixth thin film transistor is equivalent to a current source during the sampling phase.
  • the current flowing through the current source is determined by the data signal and the first gate signal.
  • the present invention forms a path in which the electroluminescent element driving circuit operates in the holding phase by providing a plurality of stacked thin film transistors, which can reduce the decay of the electroluminescent element and its brightness.
  • the effect of setting the pixel built-in current source can compensate for the uniformity and reliability of the threshold voltage and electron mobility of the thin film transistor while ensuring low cost, and can compensate for the loss of the power supply voltage.
  • FIG. 1 is a schematic structural view of a prior art electroluminescent element driving circuit
  • Figure 2 is a schematic view showing the structure of a preferred embodiment of the electroluminescent device of the present invention.
  • Fig. 3 is an equivalent circuit diagram of the electroluminescent element driving circuit of the embodiment of the invention operating in the holding phase.
  • FIG. 2 is a schematic structural view of a preferred embodiment of the electroluminescent element driving circuit of the present invention.
  • the electroluminescent element driving circuit preferably includes: a first thin film transistor T1, a second thin film transistor T2 , a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor.
  • Electroluminescent element D and storage capacitor C In this embodiment, the first thin film transistor T1, the second thin film transistor ⁇ 2, the third thin film transistor ⁇ 3, the fourth thin film transistor ⁇ 4, The fifth thin film transistor T5 and the sixth thin film transistor T6 are germanium channel indium gallium oxide thin film transistors.
  • the transistor ⁇ 4, the fifth thin film transistor ⁇ 5, and the sixth thin film transistor ⁇ 6 may also be other thin film transistors.
  • the electroluminescent element D is preferably an OLED (Organic Light-Emitting Diode). In other embodiments, the electroluminescent element D may be other elements.
  • the anode of the electroluminescent element D is connected to the first working voltage VI, the cathode is connected to the source of the first thin film transistor T1, the source of the second thin film transistor T2 is connected to the drain of the first thin film transistor T1, and the source of the third thin film transistor T3
  • the drain is connected to the drain of the second thin film transistor T2, the drain of the third thin film transistor T3 is grounded, and the first end and the second end of the storage capacitor C are respectively connected to the gate and the drain of the second thin film transistor T2.
  • the source of the fourth thin film transistor T4 is connected to the second working voltage V2
  • the source of the second thin film transistor T2 is connected to the drain of the fourth thin film transistor T4
  • the source of the sixth thin film transistor T6 is connected to the drain of the second thin film transistor T2.
  • the drain of the sixth thin film transistor T6 is connected to the data signal Vdata
  • the source of the fifth thin film transistor T5 is connected to the drain of the fourth thin film transistor T4
  • the gate of the second thin film transistor T2 is connected to the drain of the fifth thin film transistor T5 .
  • the gates of the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are all connected to the first gate signal Vsel, and the gates of the first thin film transistor T1 and the third thin film transistor T3 are connected to the first gate.
  • the second gate signal Vsel' in which the signal Vsel is inverted.
  • the duty cycle of the electroluminescent element drive circuit includes a sampling phase and a holding phase.
  • the electroluminescent element drive circuit is in the hold phase for a period of time greater than the duration of the sampling phase during one duty cycle.
  • the storage capacitor C is used to store an electrical signal between the gate and the drain of the second thin film transistor T2 during the sampling phase, and is used to maintain a voltage-dependent electrical signal between the gate and the drain of the second thin film transistor T2 during the sustain phase. Change to control the brightness of the electroluminescent element D.
  • the level of the first gate signal Vsel in the sampling phase is opposite to the level in the sustain phase. In this embodiment, the first gate signal Vsel is at a high level during the sampling phase, and the hold phase is a low level. In other embodiments, the first gate signal Vsel may also be a low level during the sampling phase, correspondingly It can also be high in the hold phase.
  • the electroluminescent element driving circuit When the first gate signal Vsel is at a high level, the second gate signal Vser is at a low level. At this time, the source and drain of the first thin film transistor T1 and the third thin film transistor T3 are turned off, and the source and drain of the second thin film transistor T2, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are turned on. .
  • the electroluminescent element drive circuit operates in the sampling phase.
  • the second thin film transistor T2, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 form a via between the second operational voltage V2 and the data signal Vdata.
  • the storage capacitor C Since the storage capacitor C is connected in parallel between the gate and the drain of the second thin film transistor T2, the storage capacitor C records an electrical signal between the gate and the drain of the second thin film transistor T2, that is, the gate of the second thin film transistor T2. The change in voltage between the drain and the drain.
  • the first gate signal Vsel When the first gate signal Vsel is at a low level, the Vsel' second gate signal is at a high level.
  • the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 are turned off in the sustain phase, and the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are in the sustain phase.
  • the pole and the drain are turned on.
  • the electroluminescent element drive circuit operates in the hold phase.
  • the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 form a via between the first operating voltage VI and the ground GND.
  • the storage capacitor C is connected in parallel between the gate and the drain of the second thin film transistor T2, and the voltage between the gate and the drain of the second thin film transistor T2 is changed according to the electric signal, thereby achieving the purpose of controlling the brightness of the electroluminescent element D. .
  • FIG. 3 is a circuit diagram showing the operation of the electroluminescent device driving circuit in the embodiment of the present invention as shown in FIG. 2, wherein Rout characterizes the first thin film transistor T1 and the second thin film transistor ⁇ 2.
  • Rout characterizes the first thin film transistor T1 and the second thin film transistor ⁇ 2.
  • the equivalent impedance of the triple thin film transistor ⁇ 3 is overlapped, the current source Is is connected in parallel with the admittance Rout, the load port is connected to the electroluminescent element D, and the current source Is current magnitude I is the current when the load port is short-circuited.
  • R D is the electric resistance of the electroluminescent element D.
  • Rout characterizes the equivalent impedance after the first thin film transistor T1, the second thin film transistor ⁇ 2, and the third thin film transistor ⁇ 3 are overlapped, Rout >> R D . Decay in the electroluminescent element D, ie R D When the change occurs, it is known from the formula (1) that the current Id flowing through the electroluminescent element D hardly changes, and therefore the light emission is not unstable due to the decay of the electroluminescent element D.
  • the sixth thin film transistor T6 is equivalent to a current source during the sampling phase.
  • the current 16 flowing through the current source is determined by the data signal Vdata and the first gate signal Vsel.
  • the current source is a built-in current source of the pixel, that is, a current source is established in the pixel unit.
  • the current source is also a conventional driver chip, so the cost is lower.
  • the working principle of the built-in pixel current source is as follows: Since the sixth thin film transistor T6 is saturated in the sampling phase, the drain current formula operated by the FET in saturation state can be known:
  • ⁇ ⁇ is the mobility of electrons
  • Cox is the gate oxide capacitance per unit area
  • W/L is the width to length ratio of the sixth thin film transistor
  • Vth is the threshold voltage of the sixth thin film transistor.
  • the second thin film transistor T2 will be described as an example.
  • the second operating voltage V2 drops, causing the voltage drop between the source and the drain of the second thin film transistor T2 to be sampled.
  • the present invention forms a path in which the electroluminescent element driving circuit operates in the holding phase by providing a plurality of stacked thin film transistors, which can reduce the influence of the decay of the electroluminescent element on its brightness, by setting the built-in current of the pixel.
  • the source can compensate for the uniformity and reliability of the threshold voltage and electron mobility of the thin film transistor at the same time, and can compensate for the loss of the power supply voltage.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种电致发光元件驱动电路，该电路包括，第一、第二、第三薄膜晶体管（T1，T2，T3），存储电容（C）以及电致发光元件（D），电致发光元件（D）的阳极连接第一工作电压（V1），阴极连接第一薄膜晶体管（T1）的源极，第二薄膜晶体管（Τ2）的源极连接第一薄膜晶体管（T1）的漏极，第三薄膜晶体管（Τ3）的源极连接第二薄膜晶体管（Τ2）的漏极，第三薄膜晶体管（Τ3）的漏极接地。通过上述方式，能够降低电致发光元件（D）衰变对其亮度的影响。

Description

电致发光元件驱动电路
【技术领域】
本发明涉及显示技术领域， 特别是涉及一种电致发光元件驱动电路。 【背景技术】
目前， 电致发光显示器由于具有视角广、 反应快、 色彩饱和度高等优点而 越来越受人们关注， 使用也越来越普遍， 特别是在手机、 媒体播放器及小型入 门级电视等产品中最为显著。
电致发光显示器需要驱动电路来驱动电致发光元件发光。 请参阅图 1 , 图 1 是现有技术电致发光元件驱动电路的结构示意图。 如图 1 所示， 现有技术的电 致发光元件驱动电路包括： 开关薄膜晶体管 ΊΤ、 驱动薄膜晶体管 Τ2'、 存储电 容 C 以及电致发光元件 D'。 电致发光元件驱动电路实现的功能为： 在采样阶 段， 将电致发光元件 D' 亮度呈一定关系的电信号充到存储电容 C 中； 在保持 阶段， 存储在存储电容 C 中的电信号保证电致发光元件 在保持阶段持续发 光。 但是现有技术电致发光元件 D' 在工作过程中会产生衰变， 其阻值会发生 变化， 导致其发光亮度受其衰变的影响较大， 进而导致电致发光显示器的显示 效果不佳。
因此， 需要提供一种电致发光元件驱动电路， 以解决上述问题。 【发明内容】
本发明主要解决的技术问题是提供一种电致发光元件驱动电路， 能够降低 电致发光元件衰变对其亮度的影响。
为解决上述技术问题， 本发明采用的一个技术方案是： 提供一种电致发光 元件驱动电路， 其中， 电致发光元件驱动电路包括： 第一薄膜晶体管、 第二薄 膜晶体管、 第三薄膜晶体管、 第四薄膜晶体管、 第五薄膜晶体管、 第六薄膜晶 体管、 存储电容以及电致发光元件。 其中电致发光元件的阳极连接第一工作电 压， 阴极连接第一薄膜晶体管的源极， 第二薄膜晶体管的源极连接第一薄膜晶 体管的漏极， 第三薄膜晶体管的源极连接第二薄膜晶体管的漏极， 第三薄膜晶 体管的漏极接地， 存储电容的第一端和第二端分别连接第二薄膜晶体管的栅极 和漏极， 第四薄膜晶体管的源极连接第二工作电压， 第二薄膜晶体管的源极连 接第四薄膜晶体管的漏极， 第六薄膜晶体管的源极连接第二薄膜晶体管的漏极 , 第六薄膜晶体管的漏极连接数据信号， 第五薄膜晶体管的源极连接第四薄膜晶 体管的漏极， 连接第二薄膜晶体管的栅极连接第五薄膜晶体管的漏极， 电致发 光元件驱动电路的工作周期包括采样阶段和保持阶段， 第一薄膜晶体管、 第二 薄膜晶体管以及第三薄膜晶体管在保持阶段源极与漏极导通且三者叠接形成的 阻抗大于电致发光元件的阻抗， 第四薄膜晶体管、 第五薄膜晶体管、 第六薄膜 晶体管在保持阶段源极与漏极截止， 第二薄膜晶体管、 第四薄膜晶体管、 第五 薄膜晶体管、 第六薄膜晶体管在采样阶段源极与漏极导通， 第一薄膜晶体管和 第三薄膜晶体管在采样阶段源极与漏极截止， 存储电容用于在采样阶段存储第 二薄膜晶体管的栅极与漏极之间的电信号， 且用于在保持阶段保持第二薄膜晶 体管的栅极与漏极之间电压随电信号变化， 以控制电致发光元件的亮度。
其中， 第四薄膜晶体管、 第五薄膜晶体管以及第六薄膜晶体管的栅极均连 接第一栅极信号， 第一薄膜晶体管和第三薄膜晶体管的栅极均连接与第一栅极 信号反相的第二栅极信号， 第一栅极信号和第二栅极信号用于控制第四薄膜晶 体管、 第五薄膜晶体管以及第六薄膜晶体管在保持阶段源极与漏极截止以及控 制第一薄膜晶体管、 第二薄膜晶体管以及第三薄膜晶体管在保持阶段源极与漏 极导通。
为解决上述技术问题， 本发明采用的另一个技术方案是： 提供一种电致发 光元件驱动电路， 该电路包括： 第一薄膜晶体管、 第二薄膜晶体管、 第三薄膜 晶体管、 存储电容以及电致发光元件， 其中电致发光元件的阳极连接第一工作 电压， 阴极连接第一薄膜晶体管的源极， 第二薄膜晶体管的源极连接第一薄膜 晶体管的漏极， 第三薄膜晶体管的源极连接第二薄膜晶体管的漏极， 第三薄膜 晶体管的漏极接地， 存储电容的第一端和第二端分别连接第二薄膜晶体管的栅 极和漏极， 电致发光元件驱动电路的工作周期包括采样阶段和保持阶段， 第一 薄膜晶体管、 第二薄膜晶体管以及第三薄膜晶体管在保持阶段源极与漏极导通， 存储电容用于在采样阶段存储第二薄膜晶体管的栅极与漏极之间的电信号， 且 用于在保持阶段保持第二薄膜晶体管的栅极与漏极之间电压随电信号变化， 以 控制电致发光元件的亮度。
其中， 电致发光元件驱动电路还包括： 第四薄膜晶体管、 第五薄膜晶体管 以及第六薄膜晶体管， 其中第四薄膜晶体管的源极连接第二工作电压， 第二薄 膜晶体管的源极连接第四薄膜晶体管的漏极， 第六薄膜晶体管的源极连接第二 薄膜晶体管的漏极， 第六薄膜晶体管的漏极连接数据信号， 第五薄膜晶体管的 源极连接第四薄膜晶体管的漏极， 连接第二薄膜晶体管的栅极连接第五薄膜晶 体管的漏极， 第二薄膜晶体管、 第四薄膜晶体管、 第五薄膜晶体管、 第六薄膜 晶体管在采样阶段源极与漏极导通， 第一薄膜晶体管和第三薄膜晶体管在采样 阶段源极与漏极截止。
其中， 第四薄膜晶体管、 第五薄膜晶体管以及第六薄膜晶体管的栅极均连 接第一栅极信号， 第一薄膜晶体管和第三薄膜晶体管的栅极均连接与第一栅极 信号反相的第二栅极信号， 第一栅极信号和第二栅极信号用于控制第四薄膜晶 体管、 第五薄膜晶体管以及第六薄膜晶体管在保持阶段源极与漏极截止以及控 制第一薄膜晶体管、 第二薄膜晶体管以及第三薄膜晶体管在保持阶段源极与漏 极导通。
其中， 第一栅极信号在采样阶段的电平和在保持阶段的电平相反， 第一栅 极信号和第二栅极信号还用于控制第一薄膜晶体管和第三薄膜晶体管在采样阶 段源极与漏极截止以及控制第二薄膜晶体管、 第四薄膜晶体管、 第五薄膜晶体 管、 第六薄膜晶体管在采样阶段源极与漏极导通。
其中， 第一薄膜晶体管、 第二薄膜晶体管、 第三薄膜晶体管、 第四薄膜晶 体管、 第五薄膜晶体管以及第六薄膜晶体管为 N沟道薄膜场效应晶体管， 第一 栅极信号在采样阶段为高电平且在保持阶段为低电平。
其中， 电致发光元件驱动电路在一个工作周期内， 处于保持阶段的时长大 于处于采样阶段的时长。
其中， 电致发光元件为有机电致发光元件。
其中， 第一薄膜晶体管、 第二薄膜晶体管、 第三薄膜晶体管、 第四薄膜晶 体管、第五薄膜晶体管以及第六薄膜晶体管为 N沟道铟镓辞氧化物薄膜晶体管。
其中， 第六薄膜晶体管在采样阶段等效为一电流源。
其中， 流过电流源的电流由数据信号和第一栅极信号共同确定。
本发明的有益效果是： 区别于现有技术的情况， 本发明通过设置多个叠接 的薄膜晶体管形成电致发光元件驱动电路工作在保持阶段的通路， 能够降低电 致发光元件衰变对其亮度的影响， 通过设置像素内建电流源， 在保证成本较低 的情况下能够同时补偿薄膜晶体管的阈值电压和电子迁移率的均勾性和可靠 性， 还能够补偿电源电压的损耗。
【附图说明】
图 1是现有技术电致发光元件驱动电路的结构示意图；
图 2是本发明电致发光元件优选实施例的结构示意图；
图 3本发明实施例电致发光元件驱动电路工作在保持阶段时的等效电路图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细描述。
请参阅图 2,图 2是本发明电致发光元件驱动电路优选实施例的结构示意图。 在本实施例中， 电致发光元件驱动电路优选地包括： 第一薄膜晶体管 Tl、 第二 薄膜晶体管 Τ2、 第三薄膜晶体管 Τ3、 第四薄膜晶体管 Τ4、 第五薄膜晶体管 Τ5、 第六薄膜晶体管 Τ6、 电致发光元件 D以及存储电容 C。 在本实施例中， 第一薄 膜晶体管 Tl、 第二薄膜晶体管 Τ2、 第三薄膜晶体管 Τ3、 第四薄膜晶体管 Τ4、 第五薄膜晶体管 T5以及第六薄膜晶体管 Τ6为 Ν沟道铟镓辞氧化物薄膜晶体管， 在其他实施例中， 第一薄膜晶体管 Tl、 第二薄膜晶体管 Τ2、 第三薄膜晶体管 Τ3、 第四薄膜晶体管 Τ4、 第五薄膜晶体管 Τ5以及第六薄膜晶体管 Τ6也可以是 其他薄膜晶体管。 在本实施例中， 电致发光元件 D 优选为 OLED(Organic Light-Emitting Diode, 有机发光二极管）， 在其他实施例中， 电致发光元件 D也 可以是其他元件。
电致发光元件 D 的阳极连接第一工作电压 VI , 阴极连接第一薄膜晶体管 T1的源极， 第二薄膜晶体管 T2的源极连接第一薄膜晶体管 T1的漏极， 第三薄 膜晶体管 T3的源极连接第二薄膜晶体管 T2的漏极，第三薄膜晶体管 T3的漏极 接地，存储电容 C的第一端和第二端分别连接第二薄膜晶体管 T2的栅极和漏极。 第四薄膜晶体管 T4的源极连接第二工作电压 V2,第二薄膜晶体管 T2的源极连 接第四薄膜晶体管 T4的漏极， 第六薄膜晶体管 T6的源极连接第二薄膜晶体管 T2 的漏极， 第六薄膜晶体管 T6 的漏极连接数据信号 Vdata, 第五薄膜晶体管 T5的源极连接第四薄膜晶体管 T4的漏极， 连接第二薄膜晶体管 T2的栅极连接 第五薄膜晶体管 T5的漏极。 第四薄膜晶体管 Τ4、 第五薄膜晶体管 Τ5以及第六 薄膜晶体管 Τ6的栅极均连接第一栅极信号 Vsel, 第一薄膜晶体管 T1和第三薄 膜晶体管 T3的栅极均连接与第一栅极信号 Vsel反相的第二栅极信号 Vsel'。
电致发光元件驱动电路的工作周期包括采样阶段和保持阶段。 电致发光元 件驱动电路在一个工作周期内， 处于保持阶段的时长大于处于采样阶段的时长。 存储电容 C用于在采样阶段存储第二薄膜晶体管 T2的栅极与漏极之间的电信 号，且用于在保持阶段保持第二薄膜晶体管 T2的栅极与漏极之间电压随电信号 变化， 以控制电致发光元件 D的亮度。 第一栅极信号 Vsel在采样阶段的电平和 在保持阶段的电平相反。 在本实施例中， 第一栅极信号 Vsel在采样阶段为高电 平， 保持阶段为低电平， 在其他实施例中， 第一栅极信号 Vsel在采样阶段也可 以是低电平， 相应的在保持阶段也可以是高电平。
下面结合附图和实施例描述电致发光元件驱动电路的工作原理。 当第一栅极信号 Vsel为高电平时， 第二栅极信号 Vser 为低电平。 此时第 一薄膜晶体管 T1和第三薄膜晶体管 T3源极与漏极截止， 第二薄膜晶体管 T2、 第四薄膜晶体管 Τ4、第五薄膜晶体管 Τ5、第六薄膜晶体管 Τ6源极与漏极导通。 电致发光元件驱动电路工作在采样阶段。 第二薄膜晶体管 Τ2、 第四薄膜晶体管 Τ4、 第五薄膜晶体管 Τ5以及第六薄膜晶体管 Τ6在第二工作电压 V2和数据信 号 Vdata之间形成通路。 由于存储电容 C并联在第二薄膜晶体管 T2的栅极与漏 极之间， 因此存储电容 C记录的是第二薄膜晶体管 T2栅极与漏极之间电信号， 即第二薄膜晶体管 T2栅极与漏极之间电压的变化。 当第一栅极信号 Vsel为低 电平时， Vsel' 第二栅极信号为高电平。 此时第四薄膜晶体管 T4、 第五薄膜晶 体管 Τ5以及第六薄膜晶体管 Τ6在保持阶段源极与漏极截止， 第一薄膜晶体管 Tl、 第二薄膜晶体管 Τ2以及第三薄膜晶体管 Τ3在保持阶段源极与漏极导通。 电致发光元件驱动电路工作在保持阶段。 第一薄膜晶体管 Tl、 第二薄膜晶体管 Τ2以及第三薄膜晶体管 Τ3在第一工作电压 VI和地 GND之间形成通路。 存储 电容 C并联在第二薄膜晶体管 Τ2的栅极与漏极之间， 保持第二薄膜晶体管 Τ2 的栅极与漏极之间电压随电信号变化， 从而达到控制电致发光元件 D亮度的目 的。
请进一步参阅图 3,图 3是本发明实施例电致发光元件驱动电路工作在保持 理等效为如图 2所示的电路图， 其中 Rout表征第一薄膜晶体管 Tl、第二薄膜晶 体管 Τ2、 第三薄膜晶体管 Τ3叠接后的等效阻抗， 电流源 Is与导纳 Rout并联， 负载端口接电致发光元件 D, 电流源 Is电流大小 I为负载端口短路时的电流。 由电
Figure imgf000008_0001
其中， RD为电致发光元件 D的电阻。
由于 Rout表征第一薄膜晶体管 Tl、 第二薄膜晶体管 Τ2、 第三薄膜晶体管 Τ3叠接后的等效阻抗， 因此 Rout > > RD。 在电致发光元件 D发生衰变， 即 RD 发生变化时， 由公式（ 1 )可知流过电致发光元件 D的电流 Id几乎不发生变化， 因此不会因为电致发光元件 D的衰变而导致其发光不稳定。
进一步， 请再参阅图 2, 第六薄膜晶体管 T6在采样阶段等效为一电流源。 流过该电流源的电流 16由数据信号 Vdata和第一栅极信号 Vsel共同确定。 具体 地， 该电流源为像素内建电流源， 即在像素单元内建立一个电流源。 该电流源 采用的还是传统的驱动芯片， 因此成本较低。 像素内建电流源工作原理为： 由 于第六薄膜晶体管 T6在采样阶段处于饱和状态， 由场效应管工作在饱和状态的 漏极电流公式可知：
16 =→ nCox— (Vsel-Vdata-Vth)2
2 L、 ) ( 2 )
其中， μ η为电子的迁移率， Cox为单位面积栅氧化层电容， W/L为第六薄 膜晶体管的宽长比， Vth为第六薄膜晶体管的阈值电压。
承前所述， 由于 μ η、 Cox, W/L, Vth在整个电致发光元件驱动电路工作周 期内保持不变， 因此由公式（2 )可知流过像素内建电流源的电流 16由数据信号 Vdata和第一栅极信号 Vsel共同确定。
下面结合实施例说明本发明的像素内建电流源的作用。
第一， 由于保持阶段的时长远远大于采样阶段的时长， 因此需要考虑到第 一薄膜晶体管 Tl、 第二薄膜晶体管 Τ2、 第三薄膜晶体管 Τ3的衰减问题， 以第 二薄膜晶体管 Τ2为例进行说明。 当第二薄膜晶体管 Τ2发生衰减时， 其阈值电 压上升和 /或电子迁移率下降，在采样阶段时第二薄膜晶体管 Τ2的栅极电位会自 动上升以维持 12不变（因为 16由 Vdata和 Vsel决定， 而流过第二薄膜晶体管 T2的电流 12=16, 所以 12不会随第二薄膜晶体管 T2的衰减而改变 ), 此电压储 存在存储电容 C, 当在保持阶段时， 电致发光元件上的电流 Id ( Id=I2 ) 不变。 因此，像素内建电流源能够同时补偿第二薄膜晶体管 T2的阈值电压和电子迁移 率的均勾性和可靠性。
第二， 同样以第二薄膜晶体管 T2为例进行说明。 当电源电压损耗时， 第二 工作电压 V2下降， 导致第二薄膜晶体管 T2源极与漏极之间电压下降， 在采样 阶段时第二薄膜晶体管 T2的栅极电位会自动上升， 以保持流过第二薄膜晶体管 T2的电流 12=16, 从而 12维持固定， 此电压储存在存储电容 C, 使得在保持阶 段时， Id ( Id=I2 ) 不变。 因此， 像素内建电流源能够补偿因电源电压损耗造成 的第二薄膜晶体管 T2源极漏极之间电压下降。
区别于现有技术， 本发明通过设置多个叠接的薄膜晶体管形成电致发光元 件驱动电路工作在保持阶段的通路， 能够降低电致发光元件衰变对其亮度的影 响， 通过设置像素内建电流源， 在保证成本较低的情况下能够同时补偿薄膜晶 体管的阈值电压和电子迁移率的均勾性和可靠性， 还能够补偿电源电压的损耗。
以上所述仅为本发明的实施方式， 并非因此限制本发明的专利范围， 凡是 利用本发明说明书及附图内容所作的等效结构或等效流程变换， 或直接或间接 运用在其他相关的技术领域， 均同理包括在本发明的专利保护范围内。

Claims

权利要求
1. 一种电致发光元件驱动电路， 其中， 所述电致发光元件驱动电路包括： 第一薄膜晶体管、 第二薄膜晶体管、 第三薄膜晶体管、 第四薄膜晶体管、 第五 薄膜晶体管、 第六薄膜晶体管、 存储电容以及电致发光元件， 其中所述电致发 光元件的阳极连接第一工作电压， 阴极连接所述第一薄膜晶体管的源极， 所述 第二薄膜晶体管的源极连接所述第一薄膜晶体管的漏极， 所述第三薄膜晶体管 的源极连接所述第二薄膜晶体管的漏极， 所述第三薄膜晶体管的漏极接地， 所 述存储电容的第一端和第二端分别连接所述第二薄膜晶体管的栅极和漏极， 所 述第四薄膜晶体管的源极连接第二工作电压， 所述第二薄膜晶体管的源极连接 所述第四薄膜晶体管的漏极， 所述第六薄膜晶体管的源极连接所述第二薄膜晶 体管的漏极， 所述第六薄膜晶体管的漏极连接数据信号， 所述第五薄膜晶体管 的源极连接所述第四薄膜晶体管的漏极， 连接所述第二薄膜晶体管的栅极连接 所述第五薄膜晶体管的漏极， 所述电致发光元件驱动电路的工作周期包括采样 阶段和保持阶段， 所述第一薄膜晶体管、 所述第二薄膜晶体管以及所述第三薄 膜晶体管在所述保持阶段源极与漏极导通且三者叠接形成的阻抗大于所述电致 发光元件的阻抗， 所述第四薄膜晶体管、 所述第五薄膜晶体管、 第六薄膜晶体 管在所述保持阶段源极与漏极截止， 所述第二薄膜晶体管、 所述第四薄膜晶体 管、 所述第五薄膜晶体管、 所述第六薄膜晶体管在所述采样阶段源极与漏极导 通， 所述第一薄膜晶体管和所述第三薄膜晶体管在所述采样阶段源极与漏极截 止， 所述存储电容用于在所述采样阶段存储所述第二薄膜晶体管的栅极与漏极 之间的电信号， 且用于在所述保持阶段保持所述第二薄膜晶体管的栅极与漏极 之间电压随所述电信号变化， 以控制所述电致发光元件的亮度。
2. 根据权利要求 1所述的电致发光元件驱动电路， 其中， 所述第四薄膜晶 体管、 所述第五薄膜晶体管以及所述第六薄膜晶体管的栅极均连接第一栅极信 号， 所述第一薄膜晶体管和第三薄膜晶体管的栅极均连接与所述第一栅极信号 反相的第二栅极信号， 所述第一栅极信号和所述第二栅极信号用于控制所述第 四薄膜晶体管、 所述第五薄膜晶体管以及所述第六薄膜晶体管在所述保持阶段 源极与漏极截止以及控制所述第一薄膜晶体管、 所述第二薄膜晶体管以及所述 第三薄膜晶体管在所述保持阶段源极与漏极导通。
3. 一种电致发光元件驱动电路， 其中， 所述电致发光元件驱动电路包括： 第一薄膜晶体管、 第二薄膜晶体管、 第三薄膜晶体管、 存储电容以及电致发光 元件， 其中所述电致发光元件的阳极连接第一工作电压， 阴极连接所述第一薄 膜晶体管的源极， 所述第二薄膜晶体管的源极连接所述第一薄膜晶体管的漏极， 所述第三薄膜晶体管的源极连接所述第二薄膜晶体管的漏极， 所述第三薄膜晶 体管的漏极接地， 所述存储电容的第一端和第二端分别连接所述第二薄膜晶体 管的栅极和漏极， 所述电致发光元件驱动电路的工作周期包括采样阶段和保持 阶段， 所述第一薄膜晶体管、 所述第二薄膜晶体管以及所述第三薄膜晶体管在 所述保持阶段源极与漏极导通， 所述存储电容用于在所述采样阶段存储所述第 二薄膜晶体管的栅极与漏极之间的电信号， 且用于在所述保持阶段保持所述第 二薄膜晶体管的栅极与漏极之间电压随所述电信号变化， 以控制所述电致发光 元件的亮度。
4. 根据权利要求 3所述的电致发光元件驱动电路， 其中， 所述电致发光元 件驱动电路还包括： 第四薄膜晶体管、 第五薄膜晶体管以及第六薄膜晶体管， 其中所述第四薄膜晶体管的源极连接第二工作电压， 所述第二薄膜晶体管的源 极连接所述第四薄膜晶体管的漏极， 所述第六薄膜晶体管的源极连接所述第二 薄膜晶体管的漏极， 所述第六薄膜晶体管的漏极连接数据信号， 所述第五薄膜 晶体管的源极连接所述第四薄膜晶体管的漏极， 连接所述第二薄膜晶体管的栅 极连接所述第五薄膜晶体管的漏极， 所述第二薄膜晶体管、 所述第四薄膜晶体 管、 所述第五薄膜晶体管、 所述第六薄膜晶体管在所述采样阶段源极与漏极导 通， 所述第一薄膜晶体管和所述第三薄膜晶体管在所述采样阶段源极与漏极截 止。
5 根据权利要求 4所述的电致发光元件驱动电路， 其中， 所述第四薄膜晶 体管、 所述第五薄膜晶体管以及所述第六薄膜晶体管的栅极均连接第一栅极信 号， 所述第一薄膜晶体管和第三薄膜晶体管的栅极均连接与所述第一栅极信号 反相的第二栅极信号， 所述第一栅极信号和所述第二栅极信号用于控制所述第 四薄膜晶体管、 所述第五薄膜晶体管以及所述第六薄膜晶体管在所述保持阶段 源极与漏极截止以及控制所述第一薄膜晶体管、 所述第二薄膜晶体管以及所述 第三薄膜晶体管在所述保持阶段源极与漏极导通。
6. 根据权利要求 5所述的电致发光元件驱动电路， 其中， 所述第一栅极信 号在所述采样阶段的电平和在所述保持阶段的电平相反， 所述第一栅极信号和 所述第二栅极信号还用于控制所述第一薄膜晶体管和所述第三薄膜晶体管在所 述采样阶段源极与漏极截止以及控制所述第二薄膜晶体管、 所述第四薄膜晶体 管、 所述第五薄膜晶体管、 所述第六薄膜晶体管在所述采样阶段源极与漏极导 通。
7. 根据权利要求 6所述的电致发光元件驱动电路， 其中， 所述第一薄膜晶 体管、 所述第二薄膜晶体管、 所述第三薄膜晶体管、 所述第四薄膜晶体管、 所 述第五薄膜晶体管以及所述第六薄膜晶体管为 N沟道薄膜场效应晶体管， 所述 第一栅极信号在所述采样阶段为高电平且在所述保持阶段为低电平。
8. 根据权利要求 7所述的电致发光元件驱动电路， 其中， 所述电致发光元 件驱动电路在一个所述工作周期内， 处于所述保持阶段的时长大于处于所述采 样阶段的时长。
9. 根据权利要求 8所述的电致发光元件驱动电路， 其中， 所述电致发光元 件为有机电致发光元件。
10. 根据权利要求 9所述的电致发光元件驱动电路， 其中， 所述第一薄膜晶 体管、 所述第二薄膜晶体管、 所述第三薄膜晶体管、 所述第四薄膜晶体管、 所 述第五薄膜晶体管以及所述第六薄膜晶体管为 N 沟道铟镓辞氧化物薄膜晶体 管。
11. 根据权利要求 10所述的电致发光元件驱动电路， 其中， 所述第六薄膜 晶体管在所述采样阶段等效为一电流源。
12. 根据权利要求 11所述的电致发光元件驱动电路， 其中， 流过所述电流 源的电流由所述数据信号和所述第一栅极信号共同确定。
PCT/CN2013/074553 2013-04-19 2013-04-23 电致发光元件驱动电路 Ceased WO2014169492A1 (zh)

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