WO2014157086A1 - Dispositif d'imagerie - Google Patents

Dispositif d'imagerie Download PDF

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Publication number
WO2014157086A1
WO2014157086A1 PCT/JP2014/058086 JP2014058086W WO2014157086A1 WO 2014157086 A1 WO2014157086 A1 WO 2014157086A1 JP 2014058086 W JP2014058086 W JP 2014058086W WO 2014157086 A1 WO2014157086 A1 WO 2014157086A1
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Prior art keywords
charge
pixel
circuits
amplifier
signal
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PCT/JP2014/058086
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English (en)
Japanese (ja)
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香川　景一郎
川人　祥二
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国立大学法人静岡大学
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Priority to JP2015508483A priority Critical patent/JP6324372B2/ja
Publication of WO2014157086A1 publication Critical patent/WO2014157086A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/62—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light
    • G01N21/63—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light optically excited
    • G01N21/64—Fluorescence; Phosphorescence
    • G01N21/645—Specially adapted constructive features of fluorimeters
    • G01N21/6456—Spatial resolved fluorescence measurements; Imaging
    • G01N21/6458—Fluorescence microscopy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
    • G01N21/62—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light
    • G01N21/63—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light optically excited
    • G01N21/64—Fluorescence; Phosphorescence
    • G01N2021/6417—Spectrofluorimetric devices

Definitions

  • the present invention relates to an imaging apparatus for imaging an observation object.
  • FCS Fluorescence Correlation Spectroscopy
  • the present invention has been made in view of such a problem, and an object thereof is to provide an imaging apparatus that realizes multi-point observation of an observation object at high speed and with low noise.
  • an imaging device includes a plurality of pixel circuits that convert light into electric charge, a plurality of signal processing circuits connected to each of the plurality of pixel circuits, and a pixel circuit. And a control circuit that controls the operation of the signal processing circuit.
  • the pixel circuit includes a light receiving unit that converts light into electric charge, a longitudinal charge discharging unit that is formed from the center to the end of the light receiving unit, and a charge discharging unit.
  • Temporary storage unit provided on the end side of the storage unit, a plurality of transfer gates arranged so as to surround the temporary storage unit, and a plurality of charge detections provided across the plurality of transfer gates in the temporary storage unit
  • Each of the plurality of signal processing circuits has a plurality of readout circuits provided corresponding to each of the plurality of charge detection units, and each of the readout circuits receives a voltage signal from the charge detection unit.
  • the impedance change And a source follower amplifier that reads out and amplifies by removing reset noise from the voltage signal, and a plurality of sample and hold circuits that receive the voltage signal output from the gain amplifier in parallel.
  • the reset operation, charge accumulation operation, and charge read operation are controlled to be executed by pipeline processing corresponding to a plurality of charge detection units, and at the same time, the amplification operation, the sample hold operation, and the external in the plurality of read circuits of the signal processing circuit Control is performed so that the signal read operation to the is executed by pipeline processing.
  • the charges generated by the light receiving unit in the pixel circuit are transferred at high speed to the plurality of charge detection units via the charge discharging unit, the temporary storage unit, and the plurality of transfer gates. Further, the charges transferred to the plurality of charge detection units are converted into voltage signals by a readout circuit provided corresponding to the plurality of charge detection units, and then subjected to sample hold processing and signal readout processing. At this time, reset, charge accumulation, and charge readout in the plurality of charge transfer paths of the pixel circuit are executed by pipeline processing by the control circuit, and amplification, sample hold, and signal readout in the plurality of readout circuits for each pixel are also piped. It is executed by line processing.
  • multi-point observation of an observation object can be realized at high speed and with low noise.
  • FIG. 1 is a schematic configuration diagram of a fluorescence correlation spectroscopic microscope system 100 including an imaging device 1 according to a preferred embodiment of the present invention. It is a block diagram which shows schematic structure of the imaging device 1 of FIG.
  • FIG. 3 is a plan view showing a structure of a pixel circuit 3 in FIG. 2.
  • 4 is a graph showing a potential distribution along a longitudinal direction of a charge discharging unit 15 of the pixel circuit 3 of FIG. 3.
  • 4 is a graph showing a simulation result of the number of remaining charges in the light receiving unit 13 and the charge discharging unit 15 when the charge is transferred to the lower charge detection unit 19 in FIG. 3.
  • FIG. 3 is a circuit diagram showing a configuration of one pixel including a pixel circuit 3 and a pixel amplifier 5 in FIG. 2.
  • 3 is a timing chart of a clock signal generated by the control circuit 7 of FIG. It is a top view which shows the structure of 3 A of pixel circuits which concern on the modification of this invention.
  • 7 is a timing chart showing temporal changes in the intensity of excitation light controlled by the control circuit 7 and temporal changes in the clock signal given from the control circuit 7 to a transfer gate 14A.
  • FIG. 1 is a schematic configuration diagram of a fluorescence correlation spectroscopic microscope system 100 including an imaging device 1 according to a preferred embodiment of the present invention.
  • the fluorescence correlation spectroscopic microscope system 100 is a measurement system that performs an analysis by FCS at a two-dimensional multipoint on the observation object S.
  • the fluorescence correlation spectroscopic microscope system 100 includes an excitation light source 101 such as a laser light source that generates excitation light to be irradiated on the observation target S, and spot-like excitation in which the excitation light irradiated from the excitation light source 101 is two-dimensionally arranged.
  • the excitation light is condensed and incident on the optical element 103 made of a diffraction grating or a microlens array that converts light into light and the observation object S, and the fluorescence generated from the observation object S is concomitantly connected to the imaging apparatus 1.
  • a microscope 105 for imaging, a signal processing unit 107 that is connected to the imaging device 1 and processes an analog signal output from the imaging device 1, and a data processing unit 109 that processes digital data output from the signal processing unit 107 Consists of including.
  • the microscope 105 included in the fluorescence correlation spectroscopy microscope system 100 reflects the excitation light from the optical element 103 toward the observation object S and transmits the fluorescence from the observation object S toward the imaging device 1.
  • the signal processing unit 107 also converts a plurality of AD converters 115 that convert analog voltage signals output in parallel from the plurality of output terminals of the imaging device 1 into digital signals, and the digital signals output from the AD converter 115.
  • An FPGA (Field Programmable Gate Array) 117 that performs various operations is provided.
  • the data processing unit 109 uses the calculation data output from the FPGA 117 to calculate autocorrelation or cross-correlation, and generates and outputs an analysis value such as a power spectrum.
  • FIG. 2 is a block diagram illustrating a schematic configuration of the imaging apparatus 1.
  • the imaging device 1 is two-dimensionally arranged, and includes a plurality of pixel circuits 3 that convert fluorescence into electric charges, and a plurality of pixel amplifiers (signals) connected to each of the plurality of pixel circuits 3.
  • These pixel circuits 3 are arranged in a total of 100, for example, 10 rows and 10 columns, but the number can be set to various numbers.
  • the plurality of pixel amplifiers 5 are provided in the same number as the pixel circuits 3 corresponding to the pixel circuits 3, and a plurality of (for example, five) pixel amplifiers are grouped to form a plurality of pixel amplifier units 9.
  • Each pixel amplifier unit 9 is provided with an analog output terminal for outputting a voltage signal generated by the pixel circuit 3 to the outside. From the analog output terminal, the outputs of the plurality of pixel circuits 3 are bundled from the pixel amplifier unit 9 and read out serially.
  • the image pickup apparatus 1 is configured such that signal readout operations can be simultaneously performed from all the pixel circuits 3 by controlling the pixel amplifier 5.
  • the control circuit 7 controls the operation timing of each circuit by supplying various clock signals to the pixel circuit 3, the pixel amplifier 5, and the pixel amplifier unit 9.
  • FIG. 3 is a plan view showing the structure of the pixel circuit 3.
  • the pixel circuit 3 is integrated and formed on a semiconductor substrate 11 such as a silicon substrate, and has a substantially circular light receiving portion 13, a longitudinal charge discharging portion 15, and three transfer gates 17. And three charge detectors 19.
  • the light receiving unit 13 is a region that converts incident fluorescence into electric charges (photoelectrons), and is, for example, a buried photodiode formed on the semiconductor substrate 11.
  • the size of the light receiving unit 13 can be set to various sizes according to the pixel size, but is set to a diameter of about 10 ⁇ m, for example.
  • the charge discharging portion 15 is formed so as to increase in width from the center portion to the end portion from the center portion to the end portion of the light receiving portion 13.
  • the accumulation part 15a is integrally formed.
  • the charge discharging unit 15 and the temporary storage unit 15a are doped with n-type impurities, and the impurity concentration is set higher than that of the light receiving unit 13, so that the potential is set higher than that of the light receiving unit. Has been. As a result, a potential gradient is formed such that the potential increases from the entire light receiving unit 13 toward the charge discharging unit 15.
  • the charge discharging unit 15 is formed so as to become narrower from the end of the light receiving unit 13 toward the center, the charge discharging unit 15 is temporarily extended from the center of the light receiving unit 13 in the longitudinal direction inside the charge discharging unit 15. A potential gradient in which the potential gradually increases toward the accumulation unit 15a is also formed.
  • the three transfer gates 17 are gate electrodes stacked on the semiconductor substrate 11 with an insulating layer interposed therebetween.
  • the clock signal TX is given from the external control circuit 7, the charge discharge unit 15 to the charge detection unit 19 are provided. Control charge transfer.
  • These transfer gates 17 are arranged at a distance from each other so as to be in contact with the temporary storage unit 15 a provided on the outer side (end side) of the light receiving unit 13 of the charge discharging unit 15.
  • the three transfer gates 17 have the same distance from the center of the temporary storage unit 15a, the distance from the center of the light receiving unit 13 is substantially equal to each other, and the distance from each other is also equal. It is arranged on three sides of the outer edge so as to surround the temporary storage unit 15a.
  • the three charge detection units 19 are formed outside the light receiving unit 13 and adjacent to the temporary storage unit 15a with the transfer gates 17 interposed therebetween, and are transferred from the temporary storage unit 15a by the control of the respective transfer gates 17. It is a floating diffusion layer that accumulates the accumulated charge.
  • the number of transfer gates 17 and charge detection units 19 is not limited to three as long as it is two or more, but is set to three in terms of both miniaturization of pixel circuit 3 and high speed of charge transfer. It is preferred that
  • FIG. 4 shows a potential distribution along the longitudinal direction of the charge discharging unit 15 of the pixel circuit 3.
  • FIG. 4A shows an overall potential distribution of the pixel circuit 3
  • FIG. 4B shows a clock signal TX. 2 shows potential distribution around the transfer gate 17 when V is set to various voltages.
  • the potential of the charge discharging unit 15 is set higher than the potential of the light receiving unit 13, and the potential along the longitudinal direction of the charge discharging unit 15 is changed from the light receiving unit 13 side to the temporary storage unit.
  • a potential gradient that gradually increases toward the side 15a is formed. Therefore, it can be seen that charges generated in the entire light receiving unit 13 are quickly transported to the temporary storage unit 15a via the charge discharging unit 15. Further, as shown in FIG.
  • FIGS. 5 to 7 show the simulation results of the time change of the number of transferred charges when it is assumed that photoelectrons are generated at the edge of the light receiving unit 13, and FIG. FIG. 6 is a simulation result of the number of remaining charges in the light receiving unit 13 and the charge discharging unit 15 when transferred to the detecting unit 19, and FIG. 6 shows the light receiving unit 13 and the charge discharging when transferred to the left charge detecting unit 19 in FIG.
  • FIG. 7 shows the simulation results of the number of charges returned to the light receiving unit 13 and the charge discharging unit 15 when transferred to the lower charge detection unit 19 in FIG. Yes. From these results, it was found that charge transfer could be completed in about 20 ns regardless of the position of the charge detection unit 19 as a transfer destination, and it was confirmed that there was almost no influence of return charge.
  • FIG. 8 is a circuit diagram illustrating a configuration of one pixel of the imaging device 1 including the pixel circuit 3 and the pixel amplifier 5.
  • the pixel circuit 3 includes one light receiving unit 13, three transfer gates 17, and three charge detection units 19. Each charge detection unit 19 further includes a charge detection unit.
  • the reset gate 21 for resetting the charge of 19 is connected to an amplifier 23 which is a source follower amplifier circuit that reads out the voltage signal output from the charge detection unit 19 by impedance conversion.
  • the reset gate 21 is supplied with a clock signal RST from the control circuit 7 to control the charge reset timing.
  • the pixel amplifier 5 is provided corresponding to the three charge detectors 19 of the pixel circuit 3, and receives in parallel the three gain amplifiers 25 that amplify the output from the amplifier 23 and the voltage signals of the respective gain amplifiers 25.
  • Three sample and hold circuits 27 are included.
  • the gain amplifier 25 includes two-stage CDS (Correlated Double Sampling) amplifiers (first and second amplifiers) 29a and 29b having different gains. Specifically, the CDS amplifier 29a is set to a relatively large gain such as 32 times, and the CDS amplifier 29b is set to a relatively small gain such as 8 times.
  • a CDS amplifier 29b is connected to the subsequent stage of the CDS amplifier 29a, and the input of the CDS amplifier 29a is grounded via the capacitor 33 and is connected to the output of the amplifier 23 via the switch 31.
  • the CDS amplifier 29a includes a switch 35a, capacitors 37a and 39a, and an operational amplifier 41a
  • the CDS amplifier 29b includes a switch 35b, capacitors 37b and 39b, and an operational amplifier 41b.
  • One input of the operational amplifier 41a receives an output voltage from the amplifier 23 via the switch 31 and the capacitor 37a connected in series, and the other input of the operational amplifier 41a receives a common reference signal.
  • a switch 35a and a capacitor 39a are connected in parallel between one input of the operational amplifier 41a and the output of the operational amplifier 41a.
  • one input of the operational amplifier 41b receives an output voltage from the operational amplifier 41a via the capacitor 37b
  • the other input of the operational amplifier 41b receives a common reference signal.
  • a switch 35b and a capacitor 39b are connected in parallel between one input of the operational amplifier 41b and the output of the operational amplifier 41b. The output of the operational amplifier 41b is connected to the sample hold circuit 27 in the subsequent stage.
  • the clock signals ⁇ R1 and ⁇ R2 are supplied from the control circuit 7 to the switches 35a and 35b, respectively, so that the timing of the amplification operation is controlled. That is, at the timing when the reset potential is output from the amplifier 23, the switches 31, 35a and 35b are closed, and the reset levels are taken into the capacitors 37a, 39a, 37b and 39b. Next, after the accumulation is completed, the switch 35a is opened while the switch 31 is closed, and then the switch 35b is opened. Then, the transfer gate 17 is turned on to transfer the charge of the temporary storage unit 15 a to the charge detection unit 19, and the voltage level of the charge detection unit 19 is taken into the capacitors 37 a, 39 a, 37 b and 39 b via the amplifier 23. At this time, since the switches 35a and 35b are opened, a difference between the reset level and the voltage level, that is, an analog CDS result is generated at the outputs of the operational amplifiers 41a and 41b.
  • capacitors 43a and 43b which are two storage elements, are connected in parallel to the output of the gain amplifier 25. Specifically, one end of each of the capacitors 43a and 43b is grounded, and the other end is connected to the output of the operational amplifier 41b via the switches 45a and 45b. Furthermore, the other ends of the capacitors 43a and 43b are connected to analog output terminals of the imaging device 1 via switches 47a and 47b, respectively.
  • the sample hold circuit 27 is supplied with clock signals SH0, SEL0, SH1, and SEL1 from the control circuit 7 in each of the switches 45a, 47a, 45b, and 47b.
  • the timing of reading is controlled. That is, the clock signal SH0 is turned on, the switch 45a is closed, and the sample hold operation of the output voltage level of the gain amplifier 25 to the capacitor 43a is executed. Next, the clock signal SH0 is turned off, the clock signal SEL0 is turned on, the switch 45a is opened, the switch 47a is closed, and the signal reading operation to the outside of the output voltage level held by the capacitor 43a is executed.
  • the timing of the sample hold operation and signal read operation in the capacitor 43b is similarly controlled by the clock signals SH1 and SEL1.
  • the sample and hold circuit 27 including the two capacitors 43a and 43b can perform a double buffering operation. By alternately operating the two capacitors 43a and 43b, the output voltage level can be stored and read out to the outside. The reading speed can be improved by performing in parallel.
  • FIG. 9 is a timing chart of the clock signal generated by the control circuit 7.
  • a part of the change of the clock signal in the operation from the charge reset to the signal output in the two signal readout paths corresponding to the two charge detectors 19 of the pixel circuit 3 is shown.
  • the reference numerals of the clock signals are numbered in parentheses to identify each signal readout path.
  • the clock signal RST (1) when the clock signal RST (1) is turned on, the charge of the charge detection unit 19 in the first signal readout path is reset, and immediately thereafter, the clock signals ⁇ R1 (1) and ⁇ R2 (1) are turned on. Incorporation of the reset level into the gain amplifier 25 is started. Thereafter, the clock signals ⁇ R1 (1) and ⁇ R2 (1) are turned off after a predetermined time has elapsed, and the clock signal TX (1) is turned on immediately thereafter. Thereby, the charge transfer operation in the charge detection unit 19 in the first signal readout path, the signal readout operation from the charge detection unit 19 to the gain amplifier 25, and the CDS operation (amplification operation) are sequentially performed.
  • the clock signal SEL0 (1) is turned on after the clock signal SH0 (1) is turned on for a predetermined time, whereby the sample / hold operation in the sample / hold circuit 27 and the signal reading operation to the outside are sequentially performed. Thereafter, the clock signal changing in the same manner is repeated, whereby the signal reading using the first signal reading path is repeated. At that time, in the sample hold operation and the external signal read operation in the sample hold circuit 27, the clock signals SH0, SEL0, SH1, and SEL1 are generated so that the two capacitors 43a and 43b are sequentially used.
  • the clock signal RST (2), TX is executed by the control circuit 7 so that charge reset, charge accumulation, and charge read in the second signal read path are executed with a shift from the timing in the first signal read path. (2) is generated. Thereby, each operation corresponding to the plurality of charge detection units 19 is executed by pipeline processing. Furthermore, the amplification operation, the sample hold operation, and the signal read operation in the gain amplifier 25 and the sample hold circuit 27 corresponding to the second signal read path are also executed while being shifted from the timing in the first signal read path. In addition, clock signals ⁇ R1 (2), ⁇ R2 (2), SH0 (2), SEL0 (2), SH1 (2), and SEL1 (2) are generated. Thereby, each operation corresponding to the plurality of gain amplifiers 25 and the plurality of sample and hold circuits 27 is also executed by the pipeline processing.
  • the charges generated by the light receiving unit 13 in the pixel circuit 3 are transferred in parallel to the plurality of charge detection units 19 via the charge discharging unit 15 and the plurality of transfer gates 17 at high speed.
  • the charges transferred to the plurality of charge detection units 19 are converted into voltage signals by a gain amplifier 25 provided corresponding to the plurality of charge detection units 19, and then sample-hold processing and signal reading by the sample-hold circuit 27. Processing is performed.
  • reset, charge accumulation, and charge readout in a plurality of signal readout paths of the pixel circuit 3 are executed by pipeline processing by the control circuit 7, and a plurality of gain amplifiers 25 and a plurality of sample hold units provided for each pixel are executed.
  • Amplification, sample hold, and signal readout in the circuit 27 are also executed by pipeline processing. This speeds up the signal readout operation for one pixel and also ensures the length of time from signal accumulation to signal readout for each pixel signal readout path, so that noise in the readout signal can also be reduced. Specifically, if there are M signal readout paths, the sampling rate for each pixel can be theoretically increased to M times, and a sampling rate of 1 MS / sec can be realized. As a result, multi-point observation can be realized at high speed and with low noise.
  • the gain amplifier 25 is composed of two stages of CDS amplifiers 29a and 29b having different gains. As a result, the input conversion noise can be reduced by limiting the band with the first stage CDS amplifier 29a, and the reset noise remaining in the first stage can be reduced with the second stage CDS amplifier 29b.
  • sample hold circuit 27 is controlled so as to sequentially execute the two capacitors 43a and 43b connected in parallel in the sample hold operation and the signal read operation. As a result, signal readout from the gain amplifier 25 to the outside can be further accelerated.
  • FIG. 10 is a plan view showing the structure of a pixel circuit 3A which is a modification of the present invention.
  • the pixel circuit 3A is formed on the semiconductor substrate 11 to be integrated, and has a substantially rectangular light receiving part 13A, four charge temporary storage parts 15A formed at the four corners of the light receiving part 13, A transfer gate 14A for controlling charge transfer from the light receiving unit 13 to each of the temporary charge storage units 15A, four transfer gates 17A arranged adjacent to the outside of each of the temporary charge storage units 15A, and a transfer gate 17A
  • the four charge detectors 19A are formed outside the temporary charge storage unit 15A.
  • the charge generated by the light receiving unit 13A passes through the four temporary charge storage units 15A. It can be transported at high speed in parallel to the four charge detectors 19A and taken out as signals.
  • the number of transfer gates 14A and 17A, the temporary charge storage unit 15A, and the charge detection unit 19A in the pixel circuit 3A is not limited to four, and an arbitrary number can be set.
  • the fluorescence correlation spectroscopic microscope system 100 including such a pixel circuit 3A modulates a clock signal applied to the transfer gate 14A corresponding to the plurality of charge transfer paths, thereby generating a plurality of power spectra equivalent to the autocorrelation function.
  • the frequency component can be obtained discretely. That is, using the structure in which one pixel includes K transfer gates 14A and K charge temporary storage units 15A, the control circuit 7 controls the result of inner products for several basis functions.
  • the pixel value is stored in the temporary charge storage unit 15A, and after a sufficient storage time, the pixel value is read out to the data processing unit 109. Then, the data processing unit 109 reads K pixel values for one pixel.
  • the data processing unit 109 can calculate a discrete power spectrum from K ⁇ L pixel values read from one pixel by repeating L times by changing the basis function and reading the pixel value.
  • the control circuit 7 controls the driving of the pixel circuit 3A and the modulation of the excitation light in the excitation light source 101. That is, to realize complete charge transfer, only one transfer gate 14A is simultaneously turned on, so that a plurality of transfer gates 14A are not turned on at the same time and an intermediate potential is not applied to the transfer gates 14A. Controlled. Under such conditions, the control circuit 7 performs high-speed on / off binary control for the plurality of transfer gates 14A, and a clock applied to each transfer gate 14A so as to express an arbitrary basis function. Modulate the signal.
  • FIG. 11 shows the time change of the intensity of the excitation light controlled by the control circuit 7 and the time change of the clock signal given from the control circuit 7 to the transfer gate 14A when the pixel circuit 3A has three charge transfer paths.
  • the sine wave is approximated by a rectangular shape, and at the same time, the clock signals TX1 (1), TX1 (2), TX1 (3 ) Is intermittently turned on so that it is not turned on.
  • the control signal CTL for modulating the intensity of the excitation light is generated so as to increase or decrease in accordance with the sum of the weights of the basis functions h 1 (t), h 2 (t), and h 3 (t).
  • the calculation of the power spectrum in the data processing unit 109 is executed as follows.
  • the data processing unit 109 The power spectrum at frequencies 0 and ⁇ can be calculated by the following equation.
  • ( g 1 + g 3) 2/2,
  • (g 1 2 +2 g 2 2 + g 3 2 -2 g 1 g 2 -2 g 2 g 3 ) / 2
  • a matrix in which basis functions for obtaining a discrete power spectrum are arranged as a row vector is A
  • a temporal change in fluorescence intensity is a column vector f
  • a measured inner product value is a column vector g.
  • Af Af Represented by
  • A (1 + cos ⁇ 1 t, 1 + sin ⁇ 1 t, 1-cos ⁇ 1 t,..., 1 + cos ⁇ K t, 1 + sin ⁇ K t).
  • the data processing unit 109 can convert the measured g into a power spectrum using the above-described relational expression.
  • the data processing unit 109 performs an operation as shown in the following equation from a column vector g ′ of inner product values measured using an arbitrary matrix B and a matrix B having an inverse matrix B ⁇ 1 . It can be converted into a column vector g that can be converted into a power spectrum.
  • g ′ Bf
  • 3L basis functions are required to obtain L power spectra.
  • the same number of power spectrum components can be obtained by 2L + 1 basis functions.
  • the size of the molecule is obtained. And the number can be measured at a low frame rate. For example, by reading two frames, the size of the molecule can be identified.
  • the conventional method of calculating the correlation function after measuring the temporal change of the fluorescence intensity continuous measurement of about 1 to 10 seconds is required at a frame rate of 1 Mbps or more. According to this embodiment, it is more useful for molecular screening than conventional methods.
  • fluorescence correlation spectroscopy can be realized with almost the same architecture and frame rate as a normal image sensor, it is advantageous in terms of reduction in area, resolution, and cost.
  • the charge discharging portion is formed so as to increase in width from the center portion to the end portion of the light receiving portion.
  • a potential gradient can be formed in the longitudinal direction of the charge discharging unit, so that charges can be transported from the light receiving unit to the charge detecting unit at a high speed, and as a result, charge reading from the pixel circuit can be performed at higher speed.
  • the pixel circuit preferably has three transfer gates and three charge detection units. In this case, both downsizing of the pixel circuit and high speed of charge reading from the pixel circuit can be achieved.
  • the gain amplifier has a first amplifier having a larger gain and a second amplifier having a smaller gain. In this case, input conversion noise and reset noise in the voltage signal of the readout circuit can be reduced.
  • control circuit performs control so that a plurality of sample hold circuits are sequentially used in the sample hold operation and the signal read operation in each of the read circuits.
  • control circuit controls the plurality of signal processing circuits to simultaneously execute the signal reading operation from all of the plurality of pixel circuits.
  • the present invention uses an imaging apparatus for imaging an observation object, and realizes multi-point observation of the observation object at high speed and with low noise.

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  • Pathology (AREA)
  • Investigating, Analyzing Materials By Fluorescence Or Luminescence (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

Cette invention porte sur un dispositif d'imagerie (1) qui est équipé de multiples circuits de pixel (3), d'amplificateurs de pixel (5) et d'un circuit de commande (7). Chaque circuit de pixel (3) comprend une section de réception de lumière (13), une section de drainage de charges (15), une section d'accumulation temporaire (15a) qui est placée sur un côté d'extrémité de la section de drainage de charges (15), de multiples portes de transfert (17) qui sont agencées de manière à entourer la section d'accumulation temporaire (15a), et de multiples sections de détection de charges (19) qui sont agencées sur la section d'accumulation temporaire (15a) en travers des portes de transfert (17). Chaque amplificateur de pixel (5) comprend un amplificateur de gain (25) et un échantillonneur bloqueur (27) pour chacune des multiples sections de détection de charges (19). Le circuit de commande (7) effectue une commande de manière que des opérations de réinitialisation, des opérations d'accumulation de charges et des opérations de lecture de charges soient exécutées en pipeline pour des circuits de pixel (3), et que des opérations d'amplification, des opérations d'échantillonneur bloqueur maintien et des opérations de lecture de signal pour délivrer des signaux à l'extérieur soient exécutées en pipeline pour des amplificateurs de gain (25) et des échantillonneurs bloqueurs (27).
PCT/JP2014/058086 2013-03-25 2014-03-24 Dispositif d'imagerie WO2014157086A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015508483A JP6324372B2 (ja) 2013-03-25 2014-03-24 撮像装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-062917 2013-03-25
JP2013062917 2013-03-25

Publications (1)

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WO2014157086A1 true WO2014157086A1 (fr) 2014-10-02

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Country Link
JP (1) JP6324372B2 (fr)
WO (1) WO2014157086A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11917313B2 (en) 2021-09-21 2024-02-27 Kabushiki Kaisha Toshiba Solid-state imaging device

Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2003052048A (ja) * 2001-08-07 2003-02-21 Olympus Optical Co Ltd 撮像素子、撮像装置および撮像方法
JP2003234496A (ja) * 2002-02-12 2003-08-22 Sony Corp 固体撮像装置およびその製造方法
JP2007194488A (ja) * 2006-01-20 2007-08-02 Sony Corp 固体撮像装置
JP2011243862A (ja) * 2010-05-20 2011-12-01 Sony Corp 撮像デバイス及び撮像装置

Family Cites Families (3)

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Publication number Priority date Publication date Assignee Title
JP2004194488A (ja) * 2002-12-13 2004-07-08 Toyota Motor Corp ハイブリッドモータ
JP2004266597A (ja) * 2003-03-03 2004-09-24 Shoji Kawahito 全画素同時電子シャッタ機能つきイメージセンサ
JP4644825B2 (ja) * 2007-03-30 2011-03-09 国立大学法人静岡大学 固体撮像装置及びその駆動方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003052048A (ja) * 2001-08-07 2003-02-21 Olympus Optical Co Ltd 撮像素子、撮像装置および撮像方法
JP2003234496A (ja) * 2002-02-12 2003-08-22 Sony Corp 固体撮像装置およびその製造方法
JP2007194488A (ja) * 2006-01-20 2007-08-02 Sony Corp 固体撮像装置
JP2011243862A (ja) * 2010-05-20 2011-12-01 Sony Corp 撮像デバイス及び撮像装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11917313B2 (en) 2021-09-21 2024-02-27 Kabushiki Kaisha Toshiba Solid-state imaging device

Also Published As

Publication number Publication date
JP6324372B2 (ja) 2018-05-16
JPWO2014157086A1 (ja) 2017-02-16

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