WO2014155624A1 - Procédé de fabrication de tranche de semi-conducteur et tranche de semi-conducteur - Google Patents

Procédé de fabrication de tranche de semi-conducteur et tranche de semi-conducteur Download PDF

Info

Publication number
WO2014155624A1
WO2014155624A1 PCT/JP2013/059364 JP2013059364W WO2014155624A1 WO 2014155624 A1 WO2014155624 A1 WO 2014155624A1 JP 2013059364 W JP2013059364 W JP 2013059364W WO 2014155624 A1 WO2014155624 A1 WO 2014155624A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor wafer
abrasive
acid
manufacturing
abrasive grains
Prior art date
Application number
PCT/JP2013/059364
Other languages
English (en)
Japanese (ja)
Inventor
山根　昭彦
Original Assignee
Ｐｖクリスタロックスソーラー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ｐｖクリスタロックスソーラー株式会社 filed Critical Ｐｖクリスタロックスソーラー株式会社
Priority to PCT/JP2013/059364 priority Critical patent/WO2014155624A1/fr
Publication of WO2014155624A1 publication Critical patent/WO2014155624A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method of manufacturing a semiconductor wafer that is etched with an acid for texture formation, and the semiconductor wafer.
  • Semiconductor wafers for solar cells are shipped through a slicing process for cutting a semiconductor wafer from a polycrystalline silicon ingot, a peeling process for peeling the semiconductor wafer from the support plate, and a final cleaning process for removing dirt and dust from the semiconductor wafer. Etched by battery manufacturer.
  • the free abrasive grain method is a method of cutting a semiconductor wafer by rubbing a slurry, which is a mixture of liquid and abrasive grains, onto a polycrystalline silicon ingot using a wire saw.
  • the semiconductor wafer is cut out while the abrasive grains contained in the slurry break the polycrystalline silicon ingot.
  • the fixed abrasive method is a method of cutting a semiconductor wafer by pressing a wire saw formed by dispersing and fixing abrasive grains on a core wire against a polycrystalline silicon ingot.
  • the slicing process by the fixed abrasive method is to cut a semiconductor wafer while chopping a polycrystalline silicon ingot. Therefore, in the fixed abrasive method, there are few layers that become chips compared to the free abrasive method, and many semiconductor wafers can be cut out from one polycrystalline silicon ingot, and cracks and the like are generated. There is an advantage that the semiconductor wafer can be cut out thinly.
  • Etching is a process of forming uneven texture on the surface of the semiconductor wafer. If the surface of the semiconductor wafer is flat, part of the incident light is reflected and cannot be converted into current. For this reason, solar cell manufacturers have provided irregularities called textures on the surface, giving them the opportunity to re-enter part of the reflected light on the semiconductor wafer multiple times, reducing the surface reflectance, and thus the performance of the solar cell. Has improved.
  • etching treatment examples thereof include an alkali etching treatment and an acid etching treatment.
  • alkali is to add isopropyl alcohol into an alkaline solution of KOH or NAOH and immerse one or both sides of a semiconductor wafer in the alkaline solution for several minutes.
  • a typical example of the etching process using an acid is one in which one or both sides of a semiconductor wafer are immersed in an acid solution containing hydrofluoric acid or nitric acid as a main component for about 1 to 2 minutes.
  • the fixed abrasive method is more advantageous than the free abrasive method in terms of production cost, and the practical use of the fixed abrasive method is expected.
  • an acid etching process is performed, a uniform texture cannot be formed on a semiconductor wafer sliced by a fixed abrasive method.
  • the present invention has been proposed in order to solve the above-described problems of the prior art, and while the semiconductor wafer is cut out by a fixed abrasive method, the entire surface of the semiconductor wafer is textured even in an etching process using an acid. It is an object of the present invention to provide a manufacturing method capable of forming a semiconductor wafer and a semiconductor wafer by the manufacturing method.
  • the present inventors have thought that the texture formed by the etching treatment with acid is greatly influenced by the damaged layer existing on the semiconductor wafer before the etching treatment.
  • Etching with acid is considered to be a method for removing only the damaged layer, and the shape of the damaged layer formed in as-slice (no processing after slicing) is similar to that of the texture. Because it is.
  • the damaged layer is a concavo-convex layer formed on the surface of the semiconductor wafer and is generated in the slicing process.
  • the entire surface of the semiconductor wafer is formed with unevenness in advance before the etching process.
  • the surface of the semiconductor wafer becomes a smooth surface cut with a knife, so that the uneven layer is incompletely formed.
  • Slicing step of fixed abrasive method that cuts out the semiconductor wafer by cutting a crystalline ingot with a core wire in which abrasive particles are dispersed and fixed on the surface.
  • the semiconductor A wet blast type damage layer forming step for forming a damaged layer on the semiconductor wafer by spraying a slurry of liquid and abrasive grains onto at least one surface of the wafer.
  • washing with water A drying step of drying the semiconductor wafer through cleaning.
  • a finish cleaning process using a solvent for the semiconductor wafer may be omitted between the damaged layer forming process and the drying process. This is because the cleaning effect by the wet blasting process appears by combining the slicing process by the fixed abrasive method and the damaged layer forming process by the wet blasting process.
  • the texture unevenness density and the damage layer depth can be controlled by the grain size of the abrasive grains used in the wet blasting process. It was. That is, in this damage layer forming step, the particle size of the abrasive grains contained in the slurry can be changed according to the target uneven density of the texture. In the damage layer forming step, the grain size of the abrasive grains contained in the slurry can be changed according to the depth of the damage layer to be formed.
  • a second aspect according to the present invention is a semiconductor wafer before being etched with an acid to form irregularities on the surface, which is a fixed abrasive that cuts a crystalline ingot with a core wire having abrasive grains fixed on the surface. It is characterized in that a damage layer is formed on the surface by being cut out by a grain method, and after being cut out, a slurry of liquid and abrasive grains is sprayed on at least one surface by a wet blast method.
  • a damaged layer can be formed on the entire surface even when a semiconductor wafer is cut out by a fixed abrasive method, and a texture can be formed even if an etching process with an acid is performed. Therefore, many semiconductor wafers can be cut out from one crystalline ingot as compared with the free abrasive grain method, and the manufacturing cost of the semiconductor wafer for solar cells can be reduced.
  • FIG. 2 is a photograph showing observation results after wet blasting treatment under conditions 1 and 2 of Example 1.
  • FIG. It is a photograph which shows the observation result of the case where wet blasting is performed under Condition 1 and Comparative Example 1.
  • FIG. 1 is a flowchart showing a semiconductor wafer manufacturing process.
  • the semiconductor wafer is for solar cells, and is manufactured by cutting out a crystalline ingot.
  • the crystalline ingot is, for example, a polycrystalline silicon ingot.
  • the manufacturing process is as follows. That is, as shown in FIG. 1, a semiconductor wafer is sliced from a crystalline ingot (step S01), a peeling step (step S02) for peeling the cut semiconductor wafer, and a damage layer on the surface of the semiconductor wafer.
  • the damaged layer forming step (step S03) for forming the semiconductor wafer and the drying step (step S04) for drying the semiconductor wafer through washing with water are sequentially manufactured.
  • the semiconductor wafer that has undergone this process is shipped to a solar cell manufacturer through an inspection process that separates good and defective products.
  • a solar cell manufacturer In the solar cell manufacturer, an uneven texture is formed on the surface, and further processing for the solar cell is performed.
  • the formation of the texture is intended to reduce the surface reflectance.
  • the formation of the texture is generally performed by various etching processes. However, in the present manufacturing method of a semiconductor wafer, it is assumed that the etching process with an acid is performed.
  • a plurality of semiconductor wafers are cut out from the crystalline ingot by a fixed abrasive method.
  • the fixed abrasive method the crystalline ingot is cut with a wire saw made of a core wire in which abrasive particles are dispersed and fixed on the surface.
  • FIG. 2 is a schematic diagram showing a fixed abrasive grain slicing process.
  • symbol 100 has shown the crystalline ingot.
  • a plurality of wire saws 10 are arranged in parallel and can travel between the rotating rollers 11 a and 11 b.
  • one side of the crystalline ingot is bonded to the support plate 12.
  • a plurality of semiconductor wafers are cut out from the crystalline ingot by moving relative to the traveling wire saw 10 while pressing the crystalline ingot supported by the support plate 12. The crystalline ingot is sliced until the support plate 12 is reached.
  • the core wire of the wire saw 10 is desirably a high carbon steel including a metal wire such as iron, nickel, cobalt, chromium, tungsten, molybdenum, copper, titanium, aluminum, and an alloy selected from these, or a piano wire.
  • a metal wire such as iron, nickel, cobalt, chromium, tungsten, molybdenum, copper, titanium, aluminum, and an alloy selected from these, or a piano wire.
  • abrasive grains can be applied as long as the abrasive grains dispersed and fixed to the core wire can cut silicon.
  • the abrasive grains are dispersed and fixed to the core wire using various methods such as a resin bond method, an electrodeposition method, or a brazing method.
  • the adhesive that bonds the crystalline ingot and the support plate 12 is not particularly limited, but it is desirable that the adhesive be bonded with an epoxy adhesive.
  • FIG. 3 is a schematic diagram showing a peeling process.
  • reference numeral 200 indicates a semiconductor wafer.
  • the support plate 12 and the semiconductor wafer are immersed in a basket 13 filled with a stripping solution 14 for dissolving the adhesive.
  • the stripping solution 14 an aqueous solution in which lactic acid is diluted with water can be used.
  • a uniform damaged layer is formed on the entire surface of the semiconductor wafer sliced by the fixed abrasive method after the fixed abrasive method slicing step and before the texture formation by etching using acid. Further, a rough cleaning step may be included between the slicing step and the damaged layer forming step.
  • the damage layer is a layer formed by irregularities on the surface of the semiconductor wafer. Forming a uniform damaged layer on the entire surface of the semiconductor wafer means that a damaged layer is formed on one or both sides of the semiconductor wafer, there is no smooth area on the surface, and the unevenness is formed evenly as a whole. is there.
  • the surface of the semiconductor wafer is wet blasted.
  • the wet blasting process is a process of grinding the surface of the semiconductor wafer by spraying a slurry of liquid and abrasive grains onto the surface of the semiconductor wafer.
  • FIG. 4 is a schematic diagram showing the wet blasting process.
  • a slurry in which a liquid and abrasive grains are mixed is sprayed from a nozzle 15 with compressed air.
  • the width of the nozzle 15 is sufficiently wider than the width of the semiconductor wafer, and the slurry ejected from the nozzle 15 is directed to the surface of the semiconductor wafer.
  • the nozzle 15 and the semiconductor wafer can be moved relatively, and the entire surface of the semiconductor wafer is wet-blasted. In this wet blasting process, scanning on the semiconductor wafer by the nozzle 15 may be repeated once or a plurality of times.
  • the abrasive used in the wet blasting process is any one of alumina, diamond, CBN, SiC, or a mixture thereof.
  • a liquid mixed with abrasive grains water is mainly used, but a surfactant may be contained.
  • the mixing ratio of abrasive grains in the slurry is preferably 10 to 30 vol%. In this range, in addition to the damage layer forming effect, the cleaning effect of the semiconductor wafer appears and the finishing cleaning process is not necessary.
  • the grain size of the abrasive grains can be changed according to the depth of the target damage layer and the target uneven density of the texture formed by etching.
  • the particle size of the abrasive used in this wet blasting process is large, the damage layer becomes deep, in other words, the height difference of the unevenness tends to increase. It was.
  • the particle size of the abrasive used in the wet blasting process is large, the uneven density of the texture tends to be improved. There is a tendency for the area of the two irregularities to become smaller and closer.
  • drying process In the drying process, the semiconductor wafer is placed in a drying chamber to remove moisture. This drying step is performed after washing with water following the damaged layer forming step. Washing with water is a process of washing away dirt and dust. That is, when wet blasting is performed, a finish cleaning step using ultrasonic waves in a solvent such as an alkali can be omitted.
  • the etching process In the etching process, the surface of the semiconductor wafer is exposed to an etching solution. Specifically, while rotating the semiconductor wafer, an etching solution is dropped on the surface, and the etching solution is spread over the entire surface of the semiconductor wafer. A semiconductor wafer may be immersed in an etching solution.
  • the etching process is not limited to this, and various methods can be adopted.
  • the etchant is an acid and is preferably a hydrofluoric acid solution that is a mixed acid of hydrofluoric acid and nitric acid. For example, phosphoric acid, acetic acid, carboxylic acid, or a surfactant may be added.
  • the semiconductor wafer is manufactured as follows and subjected to an etching process with an acid and observed. Went.
  • the present invention is not limited to these examples.
  • Example 1 A polycrystalline silicon wafer with a wafer thickness of 180 ⁇ m is cut out from the polycrystalline silicon ingot by a fixed abrasive method, and after peeling, the polycrystalline silicon wafer is wet-blasted only on one side under the conditions shown in FIG. did.
  • alumina A # 2000 (Mako Co., Ltd., Macorundum, particle size: 6.7 ⁇ m) is mixed with water to produce a slurry having an abrasive concentration of 20 vol%.
  • This slurry was sprayed onto the polycrystalline silicon wafer at a compressed air pressure of 0.2 MPa using a wet blasting device (manufactured by Macau Corporation, Sigma, nozzle width: 600 mm).
  • the projection distance between the nozzle tip from which the slurry is ejected and the polycrystalline silicon wafer was 20 mm, and the projection angle of the polycrystalline silicon wafer with respect to the slurry injection axis was 90 °.
  • the polycrystalline silicon wafer and the nozzle were moved relative to each other at 30 mm / sec, and the slurry was projected onto the entire surface of the polycrystalline silicon wafer.
  • the number of scans of the nozzle is one.
  • Condition 2 of the wet blasting process is a wet blasting apparatus in which alumina A # 800 (manufactured by Macau Corporation, Macorundum, particle size: 14.0 ⁇ m) and water are mixed to produce a slurry having an abrasive concentration of 20 vol%. (Mako Co., Ltd., Zeta, Nozzle width: 320 mm)
  • the surface state of the polycrystalline silicon wafer was observed with a laser microscope (Keyence Corporation, VL-9700) before and after the wet blast treatment and after the etching treatment with acid.
  • Comparative Example 1 A polycrystalline silicon wafer having a wafer thickness of 180 ⁇ m is cut out from the polycrystalline silicon ingot by a fixed abrasive grain method, and after performing a peeling process, an etching process using acid under the same conditions as in Example 1 without performing a wet blasting process. Went.
  • the depth of the damaged layer was about Ra: 0.387 ⁇ m and Rz: about 5.120 ⁇ m.
  • the depth of the damaged layer was about Ra: 0.459 ⁇ m and Rz: 5.934 ⁇ m. Note that the depth of the damaged layer is determined by masking a part of the polycrystalline silicon wafer so that the wet blast process does not reach the area, and measuring the step between the wet blast process and the masked area. It was obtained by doing.
  • FIG. 7 and 8 show the observation results after etching with acid for Example 1 and Comparative Example 1.
  • FIG. 7 shows the observation results of the case of wet blasting under condition 1 (wet blasting abrasive grain size 6.7 ⁇ m) and Comparative Example 1.
  • FIG. 8 shows the condition 2 (wet blasting abrasive grain of It is an observation result of the case of wet blasting with a diameter of 14.0 ⁇ m) and Comparative Example 1.
  • Example 7 and 8 it can be seen that the texture is uniformly formed in Example 1 as compared with Comparative Example 1 in which the wet blast treatment was not performed.
  • the surface roughness when etching with acid is Ra: 0.423 ⁇ m, Rz: 6.573 ⁇ m.
  • the surface roughness is Ra: 0.738 ⁇ m, Rz: 10.173 ⁇ m, and it can be seen that the surface roughness after etching can be controlled by changing the grain size of the abrasive grains used in the wet blast treatment.
  • Example 2 After a polycrystalline silicon wafer having a wafer thickness of 180 ⁇ m is cut out from the polycrystalline silicon ingot by a fixed abrasive method and subjected to a peeling process, the polycrystalline silicon wafer is wet-blasted only on one side under conditions 1 and 2 in FIG. Processing was carried out. Then, after washing with water and drying, the surface state of the polycrystalline silicon wafer was visually observed. That is, in order to confirm the cleaning effect by the wet blasting process, the finishing cleaning process was omitted.
  • preliminary cleaning, rinsing, alkaline solution cleaning, and rinsing were performed in this order, followed by drying with warm air.
  • preliminary cleaning and alkaline solution cleaning a polycrystalline silicon wafer was immersed in an alkaline solution and ultrasonic waves were emitted.
  • the alkaline solution used is 0.5-5% by weight NaOH.
  • the used ultrasonic waves are 10 to 100 kHz and 100 to 500 W.
  • rinsing a polycrystalline silicon wafer was immersed in pure water purified using an RO membrane and irradiated with ultrasonic waves.
  • the rinse time is 2-5 minutes.
  • drying with warm air the polycrystalline silicon wafer was exposed to 100 ° hot air.
  • the drying time with warm air is 2 to 5 minutes.
  • Example 2 Comparative Example 2
  • Comparative Example 3 Comparative Example 3
  • FIG. 9 Even when Example 2 was compared with Comparative Example 2, no difference was found in the surface cleanability.
  • a polycrystalline silicon wafer is cut out by the fixed abrasive method, dust adheres to the manufacturing method in which the finishing cleaning process is omitted only for the wet blasting process and the manufacturing method in which the finishing cleaning process is added after the wet blasting process. There was no difference in the degree.
  • silicon cutting waste generated in the slicing process, organic coolant residue used in the slicing process, and residue of the stripping liquid used in the detaching process It dried and adhered to the surface of the polycrystalline silicon wafer. That is, the cleaning effect cannot be expected in the drive blast process compared to the wet blast process.
  • the method for manufacturing a semiconductor wafer according to the present embodiment is a method for manufacturing a semiconductor wafer before etching with acid for texture formation, and includes the following steps.
  • the unevenness density of the texture can be freely designed by changing the particle size of the abrasive grains contained in the slurry, It is possible to freely design the depth of the damaged layer by changing the grain size of the abrasive grains contained in the slurry.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

L'invention concerne : un procédé de fabrication dans lequel une tranche de semi-conducteur est découpée à l'aide d'une technique à abrasif fixe et une texture peut être formée sur la totalité de la surface de ladite tranche de semi-conducteur, même avec l'utilisation d'un processus de gravure utilisant un acide ; et une tranche de semi-conducteur obtenue par l'intermédiaire dudit procédé de fabrication. Ladite tranche de semi-conducteur est fabriquée par l'intermédiaire d'une étape de découpage par abrasif fixe, une étape de formation de couche d'endommagement par sablage humide, et une étape de séchage et est soumise à un processus de gravure utilisant un acide. Dans l'étape de découpe, un lingot cristallin est découpé par un fil de noyau qui possède des grains abrasifs fixés sur la surface de celui-ci de manière dispersée. Dans l'étape de formation de couche d'endommagement, après l'étape de découpe, la surface de la tranche de semi-conducteur est pulvérisée avec une bouillie comprenant un liquide et des grains abrasifs. Dans l'étape de séchage, après l'étape de formation de couche d'endommagement, la tranche de semi-conducteur est séchée.
PCT/JP2013/059364 2013-03-28 2013-03-28 Procédé de fabrication de tranche de semi-conducteur et tranche de semi-conducteur WO2014155624A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2013/059364 WO2014155624A1 (fr) 2013-03-28 2013-03-28 Procédé de fabrication de tranche de semi-conducteur et tranche de semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2013/059364 WO2014155624A1 (fr) 2013-03-28 2013-03-28 Procédé de fabrication de tranche de semi-conducteur et tranche de semi-conducteur

Publications (1)

Publication Number Publication Date
WO2014155624A1 true WO2014155624A1 (fr) 2014-10-02

Family

ID=51622697

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/059364 WO2014155624A1 (fr) 2013-03-28 2013-03-28 Procédé de fabrication de tranche de semi-conducteur et tranche de semi-conducteur

Country Status (1)

Country Link
WO (1) WO2014155624A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016215142A (ja) * 2015-05-21 2016-12-22 株式会社ケーブイケー 水栓
WO2018162546A1 (fr) * 2017-03-10 2018-09-13 Gebr. Schmid Gmbh Procédé pour la production de plaquettes texturées et dispositif de traitement d'abrasion par pulvérisation
CN114558863A (zh) * 2022-04-29 2022-05-31 深圳市赛元微电子有限公司 一种用于芯片表面处理装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146432A (ja) * 2010-01-12 2011-07-28 Noritake Co Ltd 太陽電池用シリコン基板の製造方法
JP2011222608A (ja) * 2010-04-06 2011-11-04 Okamoto Machine Tool Works Ltd 半導体基板の薄肉研削方法およびそれに用いる半導体基板の薄肉研削加工装置
JP2011243926A (ja) * 2010-05-21 2011-12-01 Shin Etsu Chem Co Ltd 太陽電池の製造方法及び太陽電池
JP2012227304A (ja) * 2011-04-19 2012-11-15 Hayashi Junyaku Kogyo Kk エッチング液組成物およびエッチング方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146432A (ja) * 2010-01-12 2011-07-28 Noritake Co Ltd 太陽電池用シリコン基板の製造方法
JP2011222608A (ja) * 2010-04-06 2011-11-04 Okamoto Machine Tool Works Ltd 半導体基板の薄肉研削方法およびそれに用いる半導体基板の薄肉研削加工装置
JP2011243926A (ja) * 2010-05-21 2011-12-01 Shin Etsu Chem Co Ltd 太陽電池の製造方法及び太陽電池
JP2012227304A (ja) * 2011-04-19 2012-11-15 Hayashi Junyaku Kogyo Kk エッチング液組成物およびエッチング方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016215142A (ja) * 2015-05-21 2016-12-22 株式会社ケーブイケー 水栓
WO2018162546A1 (fr) * 2017-03-10 2018-09-13 Gebr. Schmid Gmbh Procédé pour la production de plaquettes texturées et dispositif de traitement d'abrasion par pulvérisation
CN114558863A (zh) * 2022-04-29 2022-05-31 深圳市赛元微电子有限公司 一种用于芯片表面处理装置

Similar Documents

Publication Publication Date Title
KR101103415B1 (ko) 반도체 웨이퍼 양면 연마 방법
JP4667263B2 (ja) シリコンウエハの製造方法
KR101292884B1 (ko) 탄화 규소 단결정 기판
WO2006129485A1 (fr) Procede de fabrication de tranche liee et appareil destine a rectifier la circonference exterieure de la tranche liee
WO2002001616A1 (fr) Procede de traitement d'une plaquette de semi-conducteur et plaquette de semi-conducteur
JP6327329B1 (ja) シリコンウェーハの研磨方法およびシリコンウェーハの製造方法
WO2006028017A1 (fr) Procédé servant à produire une plaque de silicium
JP2007300127A (ja) 研磨した半導体ウェーハの製造方法
JP2007204286A (ja) エピタキシャルウェーハの製造方法
JP2007317988A (ja) 貼り合わせウエーハの製造方法
CN110010458B (zh) 控制半导体晶圆片表面形貌的方法和半导体晶片
KR20110016822A (ko) 연마 반도체 웨이퍼 제조 방법
CN110314896A (zh) 一种半导体衬底材料抛光方法
WO2014155624A1 (fr) Procédé de fabrication de tranche de semi-conducteur et tranche de semi-conducteur
JP2001358107A (ja) 再生ウェーハから半導体ウェーハへの変換法
CN105074870A (zh) 操作基板、半导体用复合基板、半导体电路基板及其制造方法
CN104097270A (zh) 线锯及线锯的制造方法
JP3943869B2 (ja) 半導体ウエーハの加工方法および半導体ウエーハ
TWI537098B (zh) Chemical mechanical polishing pads and chemical mechanical grinding methods
JP5510935B2 (ja) 半導体ウェハの製造方法
KR20100135649A (ko) 반도체 웨이퍼의 양면을 화학적으로 그라인딩하는 방법
JP2006278701A (ja) 半導体ウェハの製造方法
JP2013129023A (ja) サファイア基板の製造方法及びサファイア基板
JP4366928B2 (ja) 片面鏡面ウェーハの製造方法
KR20200135296A (ko) 실리콘 웨이퍼의 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13880157

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 04/01/2016)

NENP Non-entry into the national phase

Ref country code: JP

NENP Non-entry into the national phase

Ref country code: JP

122 Ep: pct application non-entry in european phase

Ref document number: 13880157

Country of ref document: EP

Kind code of ref document: A1