WO2014132858A1 - Module de mémoire - Google Patents

Module de mémoire Download PDF

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Publication number
WO2014132858A1
WO2014132858A1 PCT/JP2014/053896 JP2014053896W WO2014132858A1 WO 2014132858 A1 WO2014132858 A1 WO 2014132858A1 JP 2014053896 W JP2014053896 W JP 2014053896W WO 2014132858 A1 WO2014132858 A1 WO 2014132858A1
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WO
WIPO (PCT)
Prior art keywords
memory module
transmission line
wiring
terminal
dram
Prior art date
Application number
PCT/JP2014/053896
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English (en)
Japanese (ja)
Inventor
匡顕 吉村
大野　隆夫
Original Assignee
ピーエスフォー ルクスコ エスエイアールエル
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by ピーエスフォー ルクスコ エスエイアールエル filed Critical ピーエスフォー ルクスコ エスエイアールエル
Publication of WO2014132858A1 publication Critical patent/WO2014132858A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Definitions

  • the present invention relates to a memory module on which a plurality of memory chips are mounted.
  • a termination resistor element is installed at one end of the transmission line in order to reduce the fact that a signal transmitted at high speed is reflected on the transmission line and disturbs the signal waveform.
  • a technique for connecting and reducing a reflected signal is considered (for example, see Patent Document 1).
  • DDR4 DRAM Double Data Rate 4 Dynamic Access Memory
  • CRC Cyclic Redundancy Check
  • parity check error to the outside of the DRAM as an alert signal.
  • Such a DDR4 DRAM is provided with an alert pin as an output terminal for outputting an alert signal.
  • FIG. 1 is a diagram showing an example of connections on a memory module substrate on which a plurality of DRAMs having an alert signal output function are mounted.
  • the transmission line of the CA (Column Address) signal and the CTRL (Control) signal input from the outside of the memory module 1000 is one stroke.
  • the writing is connected to an input terminal and an input terminal 1002 provided in each of the DRAMs 2000-1 to 2000-9.
  • the transmission line is connected to the terminating resistor 3000 at the end of the DRAM 2000-9 which is the farthest end from the input terminal 1002.
  • the alert signal transmission line for each of the DRAMs 2000-1 to 2000-9 to notify the occurrence of an error is connected to the alert terminal and the output terminal 1001 provided in each of the DRAMs 2000-1 to 2000-9 in a single stroke. Yes.
  • the alert signal output from the DRAMs 2000-1 to 2000-9 is output from the output terminal 1001 provided in the memory module 1000 to the memory controller.
  • the alert signal is reflected on the transmission line.
  • the alert signal when an alert signal is output from the alert terminal of the DRAM 2000-9, the alert signal propagates in the direction of the output terminal 1001 and also in the direction of the DRAM 2000-8. Then, the alert signal propagated in the direction of the DRAM 2000-8 is reflected by the DRAM 2000-1 and propagates in the direction of the output terminal 1001. Due to this reflection, the alert signal output from the output terminal 1001 is disturbed and the alert signal is delayed.
  • the memory module of the present invention includes A loop-shaped transmission line having a plurality of memory chips mounted therein and connected in common with an alert terminal provided in each of the plurality of memory chips to notify that the plurality of memory chips have detected a predetermined error
  • a first connection point on the transmission line and an output terminal are connected via a first resistance element, and the second connection point is the farthest end on the transmission line from the first connection point.
  • a substrate A plurality of first terminals mounted on the substrate, each having a first terminal for outputting a passive signal based on a command signal from the outside, and a second terminal for outputting an active signal not based on the command signal
  • a memory chip Among a plurality of terminals provided in the plurality of memory chips, a transmission line that connects the second terminals in common, A resistance element connected between the transmission line and a wiring for supplying a predetermined potential formed on the substrate;
  • a memory module comprising: the transmission line; and a wiring formed on the substrate and connected to an output terminal that can be connected to the outside.
  • the alert terminals provided in each of the plurality of memory chips mounted on the memory module are connected by the loop-shaped transmission line, and the first connection point on the transmission line and the memory module are connected.
  • the output terminal is connected via a resistance element, and the second connection point that is the farthest end on the transmission line from the first connection point and the power source are connected via the resistance element. Disturbance of the waveform of the alert signal output from can be improved, and the delay of the alert signal can be improved.
  • FIG. 3 is a diagram illustrating an example of an internal configuration of a memory module illustrated in FIG. 2.
  • FIG. 3 is a diagram illustrating an example of wiring in the memory module illustrated in FIG. 2. It is a figure which shows the wiring length of each wiring used for observation. It is a figure which shows the observation result of the signal waveform in a memory controller when an alert signal is output from DRAM. It is a figure which shows the observation result of the signal waveform in a memory controller when an alert signal is output from DRAM. It is a figure which shows the observation result of the signal waveform in a memory controller when an alert signal is output from DRAM. It is a figure which shows the observation result of the signal waveform in a memory controller when an alert signal is output from DRAM. It is a figure which shows the example of application of the memory module of this invention.
  • the point of the present invention lies in the alert signal output from each DRAM, the data input / output wiring connected to the corresponding DQ terminal of each DRAM, and the command / address commonly connected to each DRAM by fly-by.
  • the CA system wiring for transmitting the system signals and the CTL system wiring for transmitting the control system signals are not shown in the drawing.
  • the data input / output wiring transmits data bidirectionally, and the CA system wiring and the control system wiring transmit data in one direction from the memory controller to the memory, as shown in FIG. It shall be present as well.
  • the data input / output wiring is a bidirectional wiring that transmits a data signal for reading or writing in accordance with a Read / Write command.
  • the CA wiring is a wiring for transmitting a command / address signal from the memory controller to each DRAM in one direction, and its termination is the same as that shown in FIG. 1 for preventing reflection of the command / address signal. Further, it is assumed that a termination resistor is provided.
  • the memory module 100 of the present invention and the memory controller 300 that controls the memory module 100 are connected via an output terminal 101 provided in the memory module 100. From the output terminal 101, an alert signal (Alert_n) output from a DRAM mounted (mounted) in the memory module 100 is output.
  • Alert_n an alert signal
  • DRAMs 200-1 to 200-9 which are a plurality of memory chips, are mounted. Each of the DRAMs 200-1 to 200-9 has alert terminals 201-1 to 201-9 for outputting an alert signal.
  • a loop-shaped transmission line formed on the memory module 100 is connected to each of the alert terminals 201-1 to 201-9.
  • connection point 104 on the transmission line and the output terminal 101 are connected via a resistance element 102 (first resistance element).
  • connection point 105 which is the farthest end from the connection point 104 on the transmission line is connected to the power source (VDD) via the resistance element 103 (second resistance element).
  • the memory controller is used to fix the transmission line to the power supply voltage (VDD) and when the alert signal is output. It plays a role of ensuring a sufficient voltage drop for judgment on the side.
  • the resistance element 103 is usually configured by an open drain transistor. This alert signal is a signal notifying that the DRAMs 200-1 to 200-9 have detected a predetermined error.
  • FIG. 4 is a diagram showing an example of wiring in the memory module 100 shown in FIG.
  • the DRAMs 200-1 to 200-9 are each composed of DRAMs 200-1F to 200-9F mounted on the front side of the substrate and DRAMs 200-1B to 200-9B mounted on the rear side of the substrate. Will be described as an example.
  • an alert terminal 201-1 for outputting an alert signal from the DRAM 200-1F and the DRAM 200-1B and an alert terminal 201-2 for outputting an alert signal from the DRAM 200-2F and the DRAM 200-2B are provided. They are connected by wiring TL10.
  • An alert terminal 201-2 that outputs an alert signal from the DRAM 200-2F and the DRAM 200-2B and an alert terminal 201-3 that outputs an alert signal from the DRAM 200-3F and the DRAM 200-3B are connected by a wiring TL9. ing.
  • An alert terminal 201-3 that outputs an alert signal from the DRAM 200-3F and the DRAM 200-3B and an alert terminal 201-4 that outputs an alert signal from the DRAM 200-4F and the DRAM 200-4B are connected by a wiring TL8.
  • An alert terminal 201-4 that outputs an alert signal from the DRAM 200-4F and the DRAM 200-4B and an alert terminal 201-5 that outputs an alert signal from the DRAM 200-5F and the DRAM 200-5B are connected by a wiring TL7.
  • An alert terminal 201-5 that outputs an alert signal from the DRAM 200-5F and the DRAM 200-5B and an alert terminal 201-6 that outputs an alert signal from the DRAM 200-6F and the DRAM 200-6B are connected by a wiring TL6.
  • An alert terminal 201-6 that outputs an alert signal from the DRAM 200-6F and DRAM 200-6B and an alert terminal 201-7 that outputs an alert signal from the DRAM 200-7F and DRAM 200-7B are connected by a wiring TL5.
  • an alert terminal 201-7 that outputs an alert signal from the DRAM 200-7F and DRAM 200-7B and an alert terminal 201-8 that outputs an alert signal from the DRAM 200-8F and DRAM 200-8B are connected by a wiring TL4.
  • an alert terminal 201-8 that outputs an alert signal from the DRAM 200-8F and DRAM 200-8B and an alert terminal 201-9 that outputs an alert signal from the DRAM 200-9F and DRAM 200-9B are connected by a wiring TL3.
  • the alert terminal 201-9 that outputs an alert signal from the DRAM 200-9F and the DRAM 200-9B and the connection point 104 are connected by a wiring TL2. Further, the connection point 104 and the resistance element 102 are connected by a wiring TL1. Further, the connection point 104 and the alert terminal 201-1 that outputs an alert signal from the DRAM 200-1F and the DRAM 200-1B are connected by a wiring TL_RTT. Further, the wirings TL2 to TL10 and the wiring TL_RTT form a loop-shaped transmission line.
  • the following shows the signal waveform observation results in the memory controller 300 when an alert signal is output from the DRAM.
  • the resistance values of the resistance elements 102 and 103 were set to 25 ohms.
  • the wiring length of the wiring TL12 from the alert terminal to each of the alert terminals 201-1 to 201-9 is set to the value shown in FIG.
  • FIG. 5 is a diagram showing the wiring length of each wiring used for observation.
  • the wiring length of the wiring TL1 was 15.2 mm. Further, the wiring length of the wiring TL2 was set to 13.7 mm. Further, the wiring length of the wiring TL3 was set to 29.9 mm. Further, the wiring length of the wiring TL4 was set to 20.0 mm. Further, the wiring length of the wiring TL5 was set to 27.2 mm. Further, the wiring length of the wiring TL6 was set to 12.8 mm. Further, the wiring length of the wiring TL7 was set to 12.8 mm. Further, the wiring length of the wiring TL8 was set to 21.4 mm. Further, the wiring length of the wiring TL9 was set to 11.7 mm.
  • the wiring length of the wiring TL10 was set to 24.6 mm. Further, the wiring length of the wiring TL11 was set to 4.1 mm. Further, the wiring length of the wiring TL12 was set to 6.5 mm. The wiring length of the wiring TL_RTT is 10 mm.
  • FIG. 6 is a diagram showing signal waveform observation results in the memory controller 300 when an alert signal is output from the DRAM 200-1F.
  • FIG. 7 is a diagram showing a signal waveform observation result in the memory controller 300 when an alert signal is output from the DRAM 200-3F.
  • FIG. 8 is a diagram showing a signal waveform observation result in the memory controller 300 when an alert signal is output from the DRAM 200-5F.
  • the disturbance of the alert signal waveform output from the memory module 100 can be improved.
  • FIG. 9 is a diagram showing an application example of the memory module of the present invention.
  • each of a plurality of electronic components 400 corresponding to the memory module of the present invention is branched from a transmission line between a receiver-side device 500 corresponding to a memory controller and a resistance element 600 that is a termination resistor. Connected in form.
  • the number of electronic components 400 is not defined. Further, the number of branches from one branch point on the transmission line is not specified.
  • the alert signal issued from the DRAM has been described as an object.
  • any signal can be applied as long as the signal is actively issued from the DRAM to the memory controller.
  • the data signal output from the DRAM to the memory controller is a signal based on the command signal from the memory controller and is a passive signal, and thus does not correspond to the signal issued actively.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

La présente invention concerne des bornes d'alarme ((201-1) à (201-9)) situées sur chaque DRAM ((200-1) à (200-9)) montée sur ce module de mémoire (100), qui sont connectées avec une ligne de transmission en forme de boucle. Un point de connexion (104) sur la ligne de transmission et une borne de sortie (101) sont connectés par l'intermédiaire d'un élément à résistance (102) et une source d'alimentation et un point de connexion (105), qui est la borne la plus éloignée du point de connexion (104) sur la ligne de transmission, sont connectés par l'intermédiaire d'un élément à résistance (103).
PCT/JP2014/053896 2013-02-26 2014-02-19 Module de mémoire WO2014132858A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013035656 2013-02-26
JP2013-035656 2013-02-26

Publications (1)

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WO2014132858A1 true WO2014132858A1 (fr) 2014-09-04

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10105306A (ja) * 1996-10-02 1998-04-24 Fujitsu Ltd 信号伝送システム及び半導体装置
JP2004062530A (ja) * 2002-07-29 2004-02-26 Elpida Memory Inc メモリモジュール及びメモリシステム

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10105306A (ja) * 1996-10-02 1998-04-24 Fujitsu Ltd 信号伝送システム及び半導体装置
JP2004062530A (ja) * 2002-07-29 2004-02-26 Elpida Memory Inc メモリモジュール及びメモリシステム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"JEDEC STANDARD DDR 4 SDRAM JESD79-4", JEDEC, September 2012 (2012-09-01), pages 6, Retrieved from the Internet <URL:http://www.jedec.org/standards-documents/docs/jesd79-4> [retrieved on 20140411] *

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