WO2014132815A1 - Dispositif de détection d'image à semi-conducteur, procédé de fabrication, et dispositif électronique - Google Patents

Dispositif de détection d'image à semi-conducteur, procédé de fabrication, et dispositif électronique Download PDF

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Publication number
WO2014132815A1
WO2014132815A1 PCT/JP2014/053480 JP2014053480W WO2014132815A1 WO 2014132815 A1 WO2014132815 A1 WO 2014132815A1 JP 2014053480 W JP2014053480 W JP 2014053480W WO 2014132815 A1 WO2014132815 A1 WO 2014132815A1
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Prior art keywords
unit
transfer
floating diffusion
pixel
photoelectric conversion
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PCT/JP2014/053480
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English (en)
Japanese (ja)
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典弘 久保
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ソニー株式会社
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Publication of WO2014132815A1 publication Critical patent/WO2014132815A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

Definitions

  • the present disclosure relates to a solid-state imaging device, a manufacturing method, and an electronic device, and in particular, a solid-state imaging device and a manufacturing method capable of suppressing deterioration in image quality due to white spots with a simpler structure, Further, it relates to an electronic device.
  • a solid-state imaging device such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor) image sensor is used.
  • CCD Charge Coupled Device
  • CMOS Complementary Metal Oxide Semiconductor
  • a solid-state imaging device for a pixel array unit in which a plurality of pixels are arranged in an array, a control process for driving each pixel in the pixel array unit, and a signal output from each pixel in the pixel array unit.
  • a peripheral circuit that performs signal processing is provided.
  • the pixel is a PD (Photodiode) that generates a charge corresponding to the amount of light received by photoelectric conversion, and an FD (Floating Diffusion) that is used to convert the charge generated by the photodiode into a pixel signal.
  • a transfer transistor for transferring charges generated in the photodiode to the FD portion is disposed between the PD and the FD portion. For example, a voltage of ⁇ 1 V or less is applied to the gate electrode of the transfer transistor during the period in which the charge is accumulated in the PD, and thereby, the charge is designed not to flow freely from the PD to the FD portion. .
  • the voltage almost the same as that of the pixel power supply is always applied to the FD portion, by applying a voltage of ⁇ 1 V or less to the gate electrode of the transfer transistor, the voltage between the gate electrode of the transfer transistor and the FD portion is reduced.
  • the voltage gap becomes large and a strong electric field is generated.
  • Such a strong electric field affects the pixel signal output from the pixel.
  • the image quality may be deteriorated by appearing as a white spot in an image constructed from the pixel signal.
  • a side wall is formed on the side surface thereof, so that the end portion of the gate electrode of the transfer transistor and the FD portion are formed.
  • An offset according to the sidewall is provided.
  • the power supply voltage to a high voltage (for example, 2.7 V or more)
  • a high voltage for example, 2.7 V or more
  • the voltage gap becomes too high between the gate electrode of the transfer transistor and the FD portion when the transfer transistor is off. Is done. Therefore, even if the sidewall is formed, a strong electric field is generated at the end of the gate electrode of the transfer transistor, and it is difficult to suppress the generation of white spots.
  • the gate electrode of the transfer transistor has a tapered shape at the lower portion at the boundary between the transfer transistor and the FD portion, so that the gate electrode of the transfer transistor and the FD portion A technique for relaxing the electric field between them is disclosed.
  • the gate electrode of the transfer transistor in order to form the tapered portion, the gate electrode of the transfer transistor needs to dig a few tens of nm or more below. Therefore, it becomes weak against process variations, the dark current may deteriorate, and the lower interface state of the gate electrode of the transfer transistor may increase. Due to these factors, not only is there a concern about characteristic deterioration such as deterioration of white spots, but the cost increases due to an increase in the number of steps.
  • the present disclosure has been made in view of such a situation, and is capable of suppressing deterioration in image quality due to generation of white spots with a simpler structure.
  • a solid-state imaging device includes a photoelectric conversion unit that performs photoelectric conversion to generate charges, a floating diffusion unit that converts charges generated in the photoelectric conversion units into signals, and the floating conversion unit from the photoelectric conversion unit to the floating A transfer unit that transfers charge to the diffusion unit; and a sidewall that is formed on a side surface of the electrode that constitutes the transfer unit on the side of the floating diffusion unit, from the electrode that constitutes the transfer unit to the floating diffusion unit In the meantime, a gap region having a predetermined interval not less than the width of the sidewall is formed.
  • a manufacturing method includes a photoelectric conversion unit that generates a charge by performing photoelectric conversion, a floating diffusion unit that converts the charge generated in the photoelectric conversion unit into a signal, and the floating diffusion from the photoelectric conversion unit.
  • a solid-state imaging device manufacturing method comprising: a transfer unit that transfers charges to a unit; and a sidewall that is formed on a side surface of the electrode that constitutes the transfer unit on the side of the floating diffusion unit.
  • a step of forming the floating diffusion portion so as to provide a gap region having a predetermined interval between the electrode to be configured and the floating diffusion portion;
  • An electronic apparatus includes a photoelectric conversion unit that generates a charge by performing photoelectric conversion, a floating diffusion unit that converts the charge generated in the photoelectric conversion unit into a signal, and the floating diffusion from the photoelectric conversion unit.
  • a transfer unit that transfers charges to the unit, and a sidewall that is formed on a side surface of the electrode that constitutes the transfer unit on the side of the floating diffusion unit, from the electrode that constitutes the transfer unit to the floating diffusion unit.
  • a solid-state imaging device in which a gap region having a predetermined interval equal to or larger than the width of the sidewall is formed is provided.
  • a gap region having a predetermined interval is formed between the gate electrode constituting the transfer transistor and the floating diffusion portion.
  • FIG. 1A shows a planar configuration example of the pixel
  • FIG. 1B shows a circuit diagram equivalent to the pixel shown in FIG. 1A
  • FIG. Shows the cross-sectional structure of the pixel.
  • the pixel 11 includes a PD 12, a transfer transistor 13, an FD unit 14, an amplification transistor 15, a selection transistor 16, and a reset transistor 17.
  • the charge generated in the PD 12 by photoelectric conversion is transferred to the FD unit 14 via the transfer transistor 13, converted into a pixel signal by the amplification transistor 15, and then the vertical signal line VSL via the selection transistor 16. Is output.
  • the pixel 11 is formed with respect to the silicon substrate 21, and the gate electrode 22 of the transfer transistor 13 is formed on the surface of the silicon substrate 21 via an insulating film (not shown).
  • a sidewall 23 is formed on the side surface of the gate electrode 22 on the FD portion 14 side.
  • the FD portion 14 is constituted by a dense N-type region 24 formed by injecting an N-type impurity into the silicon substrate 21.
  • a voltage of ⁇ 1 V or less is applied to the gate electrode 22 of the transfer transistor 13 during the period in which the charge is accumulated in the PD 12, so that the charge is free from the PD 12 to the FD unit 14. It is designed not to flow out. Since the FD portion 14 is always applied with a voltage substantially the same as that of the pixel power supply VDD, by applying a voltage of ⁇ 1 V or less to the gate electrode 22 of the transfer transistor 13, A voltage gap becomes large with the part 14, and a strong electric field is generated.
  • the PD 12 and the gate electrode 22 of the transfer transistor 13 are formed. Thereafter, a sidewall 23 is manufactured on the side surface of the gate electrode 22 on the opposite side where the PD 12 is formed. Then, the sidewall 23 is self-aligned, and an N-type impurity is implanted to form a dense N-type region 24, whereby the FD portion 14 is formed. By doing so, the end portion of the gate electrode 22 of the transfer transistor 13 and the FD portion 14 are offset according to the region where the sidewall 23 is formed, and the electric field generated at the end portion of the gate electrode 22 of the transfer transistor 13. Will drop.
  • the power supply voltage is designed to be a high voltage (for example, 2.7 V or more)
  • a strong electric field is generated even in the configuration in which the sidewall 23 is formed and the offset is provided.
  • a white spot occurred.
  • the number of white spots (hereinafter appropriately referred to as FD white spots) generated due to such a strong electric field has a characteristic that depends on the voltage of the pixel power supply.
  • FIG. 3 shows the relationship between the pixel power supply voltage and the number of FD white spots.
  • the horizontal axis indicates the voltage of the pixel power supply
  • the vertical axis indicates the value obtained by normalizing the number of FD white spots by the number when the pixel power supply is 2.5V.
  • FIG. 3 shows that the number of FD white spots increases as the voltage of the pixel power supply is increased.
  • Patent Document 1 has a structure in which the gate electrode of the transfer transistor has a tapered portion at the bottom, so that it is difficult to adjust process conditions.
  • FIG. 4 is a diagram illustrating a configuration example of the first embodiment of a pixel to which the present technology is applied.
  • FIG. 4A shows an example of a planar configuration of a pixel
  • FIG. 4B shows a cross-sectional structure of the pixel.
  • the pixel 31 includes a PD 32, a transfer transistor 33, an FD unit 34, an amplification transistor 35, a selection transistor 36, and a reset transistor 37.
  • a gap region 38 is provided between the transfer transistor 33 and the FD portion 34.
  • the PD 32 receives light and performs photoelectric conversion, and generates and accumulates charges corresponding to the light quantity.
  • the transfer transistor 33 transfers the charge generated in the PD 32 to the FD unit 34, and the FD unit 34 temporarily accumulates the charge and converts the charge into a signal.
  • the amplification transistor 35 amplifies the charge accumulated in the FD unit 34 and outputs a signal having a level corresponding to the charge to the vertical signal line via the selection transistor 36.
  • the reset transistor 37 discharges the charge accumulated in the FD unit 34 to the pixel power supply VDD and resets it.
  • the pixel 31 is formed with respect to the silicon substrate 41, and the gate electrode 42 of the transfer transistor 33 is formed on the surface of the silicon substrate 41 via an insulating film (not shown).
  • the A sidewall 43 is formed on the side surface of the transfer transistor 33 on the side of the FD portion 34 of the gate electrode 42.
  • the FD portion 34 is constituted by a dense N-type region 44 formed by ion-implanting N-type impurities into the silicon substrate 41, and an N-type region 45 is formed at a location deeper than the dense N-type region 44.
  • the N-type region 45 is used for transferring charges from the PD 32 to the transfer transistor 33.
  • the gap region 38 is provided by forming the dark N-type region 44 constituting the FD portion 34 at a distance D from the end of the gate electrode 42 of the transfer transistor 33.
  • the distance D in the gap region 38 is set to a predetermined interval at least equal to or larger than the width of the sidewall 43, for example, 100 nm.
  • the gate electrode 42, formation of the side wall 43, and formation of the FD part 34 it does not limit about the order which forms them, You may form in any order.
  • a strong electric field is generated between the gate electrode 42 of the transfer transistor 33 and the FD portion 34 by providing the gap region 38 having the distance D so as to have a gap wider than the width of the sidewall 43. Can be prevented from occurring.
  • the distance D in the gap region 38 to 100 nm or more, it is possible to prevent the generation of FD white spots caused by a strong electric field.
  • the selection range of the pixel power supply can be expanded.
  • FIG. 5 shows the relationship between the electric field intensity generated at the end of the gate electrode 42 of the transfer transistor 33, the potential barrier between the PD 32 and the FD portion 34, and the distance D of the gap region 38. .
  • the horizontal axis of FIG. 5 indicates the distance D of the gap region 38
  • the left vertical axis indicates the electric field intensity generated at the end of the gate electrode 42 of the transfer transistor 33
  • the right vertical axis indicates The potential barrier between PD32 and FD part 34 is shown.
  • the distance D of the gap region 38 that is, the distance D from the end of the gate electrode 42 of the transfer transistor 33 to the FD portion 14 is 100 nm or more, the end of the gate electrode 42 of the transfer transistor 33.
  • the electric field strength at the end of the gate electrode 42 of the transfer transistor 33 gradually converges.
  • FIG. 6 is a diagram illustrating a configuration example of the pixel 31 according to the second embodiment.
  • the same reference numerals are given to the same components as those of the pixel 31 in FIG. 4, and detailed description thereof will be omitted. That is, the pixel 31 ⁇ / b> A is different from the pixel 31 in that an additional N-type region 51 is formed near the surface of the silicon substrate 41 from the gap region 38 to the FD portion 34.
  • the additional N-type region 51 has an N-type impurity concentration in the region of a depth of about 0.1 ⁇ m from the surface of the silicon substrate 41 at a concentration that is two orders of magnitude lower than the N-type impurity concentration injected into the FD portion 34. It is formed by injection.
  • the additional N-type region 51 functions as a transfer auxiliary unit that assists transfer of charges from the transfer transistor 33 toward the FD unit 34.
  • the step of implanting N-type impurities to form the additional N-type region 51 is performed after the sidewall 43 is formed, so that the end of the sidewall 43 and the end of the additional N-type region 51 are Formed to match.
  • FIG. 6B shows the shape of the potential with respect to the X direction (direction along the cross section of FIG. 6A) of the pixel 31A.
  • 6C shows the distribution of N-type impurities in the FD portion 34 and the additional N-type region 51.
  • the horizontal axis indicates the depth from the surface of the silicon substrate 41
  • the vertical axis indicates the concentration of the N-type impurity.
  • the concentration of the N-type impurity injected into the additional N-type region 51 is two orders of magnitude lower than the concentration of the N-type impurity injected into the FD portion 34.
  • the n-type impurity concentration is highest.
  • charge transfer via the additional N-type region 51 is performed.
  • the transfer gradient from the transfer transistor 33 to the FD portion 34 is enhanced by the additional N-type region 51, and then further enhanced by the dark N-type region 44 in the FD portion 34.
  • charges can be efficiently transferred to the FD portion 34.
  • the pixel 31A can suppress the generation of FD white spots even when the pixel voltage is set to a high voltage of 2.7 V or more, and in addition, the charge from the transfer transistor 33 to the FD unit 34 can be suppressed. Transfer can be performed well. Further, the process conditions for manufacturing the pixel 31A can be designed so as to achieve both suppression of the FD white spot and improvement of charge transfer. Thereby, the pixel 31A can avoid the generation of the FD white spot and the black spot, and can further improve the image quality.
  • FIG. 7 is a diagram illustrating a configuration example of the third to fifth embodiments of the pixel 31.
  • the same reference numerals are given to the same components as those of the pixel 31A of FIG. 6, and detailed description thereof is omitted.
  • the pixel 31B is configured differently from the pixel 31A of FIG. 6 in that the end of the additional N-type region 51a is formed to coincide with the end of the gate electrode 42 of the transfer transistor 33.
  • N-type impurities are implanted by self-alignment of the gate electrode 42, whereby the additional N-type region 51a is formed. It is formed.
  • the pixel 31B can further improve the charge transfer efficiency than the pixel 31A.
  • FIG. 7B shows a pixel 31C of the fourth embodiment.
  • the end of the additional N-type region 51b protrudes more toward the gate electrode 42 of the transfer transistor 33 than the end of the sidewall 43, and more than the end of the gate electrode 42 of the transfer transistor 33.
  • 6 is different from the pixel 31 ⁇ / b> A in FIG. 6 in that it is formed so as to be on the FD portion 34 side. That is, in the pixel 31C, after forming the gate electrode 42 of the transfer transistor 33 and before forming the sidewall 43, a gap is provided between the end of the gate electrode 42 of the transfer transistor 33 and a mask is used. By implanting N-type impurities, an additional N-type region 51b is formed.
  • the balance between the electric field strength and the transfer efficiency can be adjusted. The interval is adjusted to obtain optimum characteristics.
  • the pixel 31D is different from the pixel 31A in FIG. 6 in that an N-type region 45a used for charge transfer from the PD 32 to the FD unit 34 is formed to the periphery of the transfer transistor 33. That is, in the pixel 31D, the N-type region 45a is not connected to the FD portion 34.
  • the additional N-type region 51 is formed as in the pixel 31A. However, the additional N-type region 51a such as the pixel 31B or the additional N-type region 51b such as the pixel 31C is formed. The additional N-type region 51 such as the pixel 31 may not be formed.
  • the first manufacturing method of the pixel 31 will be described with reference to FIG.
  • the sidewall material 61 to be the sidewall 43 is formed over the distance D from the side surface of the gate electrode 42.
  • the distance D is, for example, 100 nm or more as described above.
  • the sidewall material 61 is self-aligned to inject a dense N-type impurity to form a dense N-type region 44, thereby forming the FD portion 34.
  • the side wall material 61 is etched to form the side wall 43, whereby the gap region 38 of the distance D is provided.
  • the pixel 31 in which the gap region 38 with the distance D is provided between the end of the gate electrode 42 of the transfer transistor 33 and the FD portion 34 can be manufactured.
  • the sidewall material 61 is shared with other masks and N-type impurities are implanted, so that the process can be reduced and the manufacturing cost of the pixel 31 can be reduced.
  • a gate electrode material 62 to be the gate electrode 42 of the transfer transistor 33 is formed on the surface of the silicon substrate 41.
  • the gate electrode material 62 is formed so as to extend according to the distance D from the position serving as the end of the gate electrode 42 toward the side where the FD portion 34 is formed.
  • the distance D is, for example, 100 nm or more as described above.
  • the gate electrode material 62 is self-aligned to inject a dense N-type impurity to form a dense N-type region 44, thereby forming the FD portion 34.
  • the gate electrode material 62 is etched to form the gate electrode 42 so that the end of the gate electrode 42 is formed at a position away from the FD portion 34 according to the distance D. A gap region 38 of distance D is provided. Thereafter, the sidewall 43 is formed.
  • the pixel 31 in which the gap region 38 with the distance D is provided between the end of the gate electrode 42 of the transfer transistor 33 and the FD portion 34 can be manufactured. Further, in this manufacturing method, the gate electrode material 62 is shared with other masks and N-type impurities are implanted, so that the process can be reduced and the manufacturing cost of the pixel 31 can be reduced.
  • an FD is provided so that the gap region 38 of the distance D is provided.
  • the portion 34 may be formed.
  • the silicon substrate 41 is inclined with respect to the implantation direction. .
  • the FD portion 34 can be formed so as to be separated from the gate electrode 42 according to the distance D by using the shadow of the gate electrode 42.
  • the sidewall 43 is formed.
  • the FD portion 34 can be formed so as to be separated from the gate electrode 42 according to the distance D by using the shadow of the gate electrode 42.
  • the solid-state imaging device 101 includes a pixel array unit 102, a vertical drive unit 103, a column processing unit 104, a horizontal drive unit 105, an output unit 106, and a drive control unit 107.
  • the pixels 31 of the various configuration examples described above are arranged in an array, and are connected to the vertical driving unit 103 via a plurality of horizontal signal lines corresponding to the number of rows of the pixels 31.
  • the vertical drive unit 103 sequentially supplies a drive signal for driving (transferring, selecting, resetting, etc.) each pixel 31 for each row of the plurality of pixels 31 included in the pixel array unit 102 via the horizontal signal line. Supply.
  • the column processing unit 104 extracts the signal level of the pixel signal by performing CDS (Correlated Double Sampling) processing on the pixel signal output from each pixel 32 via the vertical signal line. Pixel data corresponding to the amount of light received by the pixel 31 is acquired.
  • the horizontal driving unit 105 outputs, to the column processing unit 104, a driving signal for causing the column processing unit 104 to output pixel data acquired from each pixel 31 for each column of the plurality of pixels 31 included in the pixel array unit 102. Supply sequentially.
  • the pixel data is supplied from the column processing unit 104 to the output unit 106 at a timing according to the drive signal of the horizontal driving unit 105, and the output unit 106 amplifies the pixel data, for example, to the image processing circuit in the subsequent stage. Output.
  • the drive control unit 107 controls driving of each block inside the solid-state image sensor 101. For example, the drive control unit 107 generates a clock signal according to the drive cycle of each block and supplies the clock signal to each block.
  • the solid-state imaging device 101 configured as described above includes various imaging devices such as an imaging system such as a digital still camera or a digital video camera, a mobile phone having an imaging function, or other devices having an imaging function. It can be applied to electronic equipment.
  • an imaging system such as a digital still camera or a digital video camera
  • a mobile phone having an imaging function or other devices having an imaging function. It can be applied to electronic equipment.
  • FIG. 12 is a block diagram illustrating a configuration example of an imaging device mounted on an electronic device.
  • the imaging apparatus 201 includes an optical system 202, an imaging element 203, a signal processing circuit 204, a monitor 205, and a memory 206, and can capture still images and moving images.
  • the optical system 202 includes one or more lenses, guides image light (incident light) from a subject to the image sensor 203, and forms an image on a light receiving surface (sensor unit) of the image sensor 203.
  • the solid-state image sensor 101 having the pixels 31 of the various configuration examples described above is applied.
  • electrons are accumulated for a certain period according to the image formed on the light receiving surface via the optical system 202. Then, a signal corresponding to the electrons accumulated in the image sensor 203 is supplied to the signal processing circuit 204.
  • the signal processing circuit 204 performs various signal processing on the pixel signal output from the image sensor 203.
  • An image (image data) obtained by performing signal processing by the signal processing circuit 204 is supplied to the monitor 205 and displayed, or supplied to the memory 206 and stored (recorded).
  • the imaging apparatus 201 configured as described above, by applying the solid-state imaging device 101 having the pixel 31 configured as described above, generation of white spots is suppressed even when the pixel power supply is set to a high voltage. Therefore, it is possible to obtain an image with better image quality.
  • the silicon substrate constituting the solid-state imaging device 101 may be either an Nsub substrate or a Psub substrate. Further, as the solid-state imaging device 101, any of a front side CMOS sensor, a backside illumination type CMOS sensor, and a CCD can be employed.
  • this technique can also take the following structures.
  • a photoelectric conversion unit that generates electric charges by performing photoelectric conversion;
  • a floating diffusion unit that converts the charge generated in the photoelectric conversion unit into a signal;
  • a transfer unit that transfers charges from the photoelectric conversion unit to the floating diffusion unit;
  • a sidewall formed on a side surface of the electrode constituting the transfer portion on the floating diffusion portion side, and
  • a gap region having a predetermined interval equal to or larger than the width of the sidewall is formed between the electrode constituting the transfer portion and the floating diffusion portion.
  • the transfer auxiliary portion is formed such that an end portion on the transfer portion side coincides with an end portion of a sidewall formed on a side surface of the electrode constituting the transfer portion on the floating diffusion portion side.
  • the transfer auxiliary unit has an end on the transfer unit side that protrudes closer to the transfer unit than an end of a sidewall formed on a side surface of the electrode constituting the transfer unit on the floating diffusion side, and

Abstract

L'invention concerne un dispositif de détection d'image à semi-conducteur, un procédé de fabrication et un dispositif électronique, la dégradation de la qualité de l'image provoquée par l'occurrence de points blancs pouvant être supprimée par l'utilisation d'une structure plus simple. Un pixel comprend : une partie de conversion photoélectrique mettant en œuvre une conversion photoélectrique pour produire une charge ; une partie de diffusion flottante convertissant la charge produite par la partie de conversion photoélectrique en signal ; un transistor de transfert transférant la charge de la partie de conversion photoélectrique à la partie de diffusion flottante ; et une paroi latérale formée sur une surface latérale d'une électrode de grille constituant le transistor de transfert, ladite surface latérale étant tournée vers la partie de diffusion flottante. Une zone d'espace, laquelle est un intervalle prédéterminé, supérieur ou égal à la largeur de la paroi latérale, entre l'électrode de grille constituant le transistor de transfert et la partie de diffusion flottante, est formée. Cette technique peut être appliquée, par exemple, à un capteur CMOS à rétro-éclairage.
PCT/JP2014/053480 2013-02-27 2014-02-14 Dispositif de détection d'image à semi-conducteur, procédé de fabrication, et dispositif électronique WO2014132815A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05218070A (ja) * 1992-01-30 1993-08-27 Sanyo Electric Co Ltd Ｍｏｓ電界効果半導体装置
JPH0964353A (ja) * 1995-08-25 1997-03-07 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2003273349A (ja) * 2002-03-15 2003-09-26 Seiko Epson Corp 半導体装置の製造方法
JP2009135349A (ja) * 2007-12-03 2009-06-18 Panasonic Corp Ｍｏｓ型固体撮像装置およびその製造方法
JP2009212111A (ja) * 2008-02-29 2009-09-17 Renesas Technology Corp トランジスタ

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05218070A (ja) * 1992-01-30 1993-08-27 Sanyo Electric Co Ltd Ｍｏｓ電界効果半導体装置
JPH0964353A (ja) * 1995-08-25 1997-03-07 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2003273349A (ja) * 2002-03-15 2003-09-26 Seiko Epson Corp 半導体装置の製造方法
JP2009135349A (ja) * 2007-12-03 2009-06-18 Panasonic Corp Ｍｏｓ型固体撮像装置およびその製造方法
JP2009212111A (ja) * 2008-02-29 2009-09-17 Renesas Technology Corp トランジスタ

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