WO2014128996A1 - Chip-type positive temperature coefficient thermistor element - Google Patents

Chip-type positive temperature coefficient thermistor element Download PDF

Info

Publication number
WO2014128996A1
WO2014128996A1 PCT/JP2013/072706 JP2013072706W WO2014128996A1 WO 2014128996 A1 WO2014128996 A1 WO 2014128996A1 JP 2013072706 W JP2013072706 W JP 2013072706W WO 2014128996 A1 WO2014128996 A1 WO 2014128996A1
Authority
WO
WIPO (PCT)
Prior art keywords
thermistor element
external electrode
tmax
chip
face
Prior art date
Application number
PCT/JP2013/072706
Other languages
French (fr)
Japanese (ja)
Inventor
有民 西郷
洋 井原木
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Publication of WO2014128996A1 publication Critical patent/WO2014128996A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/02—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material having positive temperature coefficient
    • H01C7/022—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material having positive temperature coefficient mainly consisting of non-metallic substances
    • H01C7/023—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material having positive temperature coefficient mainly consisting of non-metallic substances containing oxides or oxidic compounds, e.g. ferrites
    • H01C7/025—Perovskites, e.g. titanates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/1406—Terminals or electrodes formed on resistive elements having positive temperature coefficient
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/148—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals embracing or surrounding the resistive element

Definitions

  • the present invention relates to a chip type positive temperature coefficient thermistor element having a volume of 0.12 mm 3 or less.
  • a thermistor element As an example of a conventional chip-type positive temperature coefficient thermistor element (hereinafter simply referred to as a thermistor element), for example, there is one described in Patent Document 1 below.
  • This thermistor element includes a ceramic base having a substantially rectangular parallelepiped shape, and external electrodes provided on both end faces of the thermistor element.
  • Each external electrode has a structure in which a conductive metal layer, a conductive resin layer, and a metal plating layer are laminated.
  • the conductive metal layer is formed immediately above both end faces of the ceramic substrate, and the metal plating layer is the outermost layer.
  • a glass layer is formed on the four side surfaces of the ceramic substrate on which no external electrode is provided in order to improve mechanical strength and the like.
  • the conventional thermistor element is not limited to the one described in Patent Document 1, and is typically used for overheating detection of a heat source. Specifically, the thermistor element is mounted in the vicinity of the heat source. When the temperature of the heat source (that is, the ambient temperature) increases, the temperature of the ceramic substrate increases and the resistance value increases. A power supply voltage is supplied to the thermistor element. Then, a voltage representing the ambient temperature is output between the output terminals of the thermistor element and supplied to the IC. The IC determines whether the heat source is in an overheated state based on the input voltage.
  • miniaturization for example, a volume of 0.12 mm 3 or less
  • miniaturization for example, a volume of 0.12 mm 3 or less
  • Even such a small thermistor element is required to respond at high speed (for example, within 1 second) after the heat source is overheated.
  • a general technique for that purpose is to thermally couple the thermistor element and the heat source with a resin or the like.
  • the cost becomes high.
  • an object of the present invention is to provide a chip-type positive temperature coefficient thermistor element having an element volume of 0.12 [mm 3 ] or less and excellent in responsiveness at low cost.
  • one aspect of the present invention is a chip-type positive temperature coefficient thermistor element having a volume of 0.12 [mm 3 ] or less, and faces in parallel with each other and faces in a predetermined direction.
  • a ceramic substrate having a second end face and a side face connecting the first end face and the second end face, wherein the internal resistance varies with temperature change, the first end face and the second end face.
  • a first external electrode and a second external electrode provided on the end face, the first external electrode and the second external electrode containing metal.
  • a distance d [ ⁇ m] in a predetermined direction between the first end surface and the second end surface is 300 ⁇ d ⁇ 700, and the first external electrode and / or the second external electrode are arranged in a predetermined direction.
  • the thickness tmax [ ⁇ m] at the maximum thickness is tmax ⁇ 0.015 ⁇ d ⁇ 1.5.
  • the first external electrode and / or the second external electrode containing metal has a sufficient thickness tmax ⁇ 0.015 ⁇ d ⁇ 1.5 [ ⁇ m]. Therefore, when the thermistor element is mounted in the vicinity of the heat source, the distance between the first external electrode and / or the second external electrode and the heat source is relatively short, so that heat from the heat source is transmitted to the ceramic base at high speed. As a result, it is possible to provide a thermistor element having excellent responsiveness. Further, since it is not necessary to cover the thermistor element and the heat source with resin or the like, it is possible to detect overheating at a low cost.
  • thermistor element chip type positive temperature coefficient thermistor element (hereinafter simply referred to as a thermistor element) according to an embodiment of the present invention will be described with reference to the drawings.
  • the X axis, the Y axis, and the Z axis shown in FIG. 1 are defined.
  • the X axis, Y axis, and Z axis indicate the left-right direction, the front-rear direction, and the vertical direction of the thermistor element 1.
  • the thermistor element 1 includes a ceramic base 2 and a pair of external electrodes 3a and 3b.
  • the ceramic substrate 2 is made of, for example, a ceramic material in which a predetermined additive is added to BaTiO 3 (barium titanate).
  • the additive is a rare earth, typically Sm (samarium).
  • Sm samarium
  • Nd neodymium
  • La lanthanum
  • the ceramic substrate 2 may have a single plate structure or a laminated structure.
  • FIG. 1 illustrates a single plate structure.
  • the ceramic base 2 has, for example, a substantially rectangular parallelepiped shape that is long in the left-right direction, and at least one connecting the first end surface Sa and the second end surface Sb and the first end surface Sa and the second end surface Sb. And two side surfaces Sc.
  • the end surfaces Sa and Sb are parallel to each other and face each other in the X-axis direction.
  • both end surfaces Sa and Sb have a substantially rectangular shape.
  • the side surface Sc includes the first side surface Sc1 to the fourth side surface Sc4 each having a substantially rectangular shape.
  • the length of the ceramic substrate 2 in the X-axis direction (hereinafter referred to as L dimension) is defined as a distance d [ ⁇ m] between the two end surfaces Sa and Sb. d is selected such that 300 ⁇ d ⁇ 700.
  • the width W in the Y-axis direction and the thickness T in the Z-axis direction are not particularly limited, but the size of the ceramic base 2 is determined so that the entire thermistor element 1 has a volume V of 0.12 [mm 3 ] or less. It is done.
  • the ceramic substrate 2 has a substantially rectangular parallelepiped shape.
  • the actual edge portion of the ceramic substrate 2 is not completely right but rounded.
  • the distance d is not the distance between the rounded portions of the two end surfaces Sa and Sb, but the distance between the planar portions occupying most of the two end surfaces Sa and Sb.
  • External electrodes 3a and 3b are formed on end surfaces Sa and Sb, and have base electrodes 4a and 4b, first plating films 5a and 5b, and second plating films 6a and 6b.
  • the base electrodes 4a and 4b are made of, for example, an Ag—Zn (silver / zinc) alloy and Ag (silver). Specifically, an Ag—Zn alloy layer is ohmic-bonded to each of the end faces Sa and Sb, and an Ag (silver) layer is formed on the Ag—Zn alloy layer.
  • the first plating films 5a and 5b are made of, for example, Ni and are formed on the base electrodes 4a and 4b.
  • the second plating films 6a and 6b are made of, for example, Sn (tin) and are formed on the first plating films 5a and 5b.
  • the maximum thickness tmax is basically the thickness of the portion of the target external electrodes 3a and 3b where the thickness in the X-axis direction (in other words, the normal direction of the end surfaces Sa and Sb) is maximum. .
  • the edge portion of the ceramic substrate 2 is not perfectly right but rounded.
  • the external electrodes 3a and 3b are also formed on the rounded portions of the end surfaces Sa and Sb. The thickness of this portion in the X-axis direction is determined with reference to the extended surface (virtual surface) Sv of the planar portion of the end surfaces Sa and Sb, as indicated by arrows in FIG.
  • the maximum thickness tmax As for the maximum thickness tmax defined as described above, at least a lower limit value is determined. Specifically, when the distance d [ ⁇ m] is 300 ⁇ d ⁇ 700, the maximum thickness tmax is determined as tmax ⁇ 0.015 ⁇ d ⁇ 1.5, as will be described in detail later. Further, the upper limit value of the maximum thickness tmax is set to 120 [ ⁇ m] in order to prevent the occurrence of the tombstone phenomenon when the thermistor element 1 is mounted.
  • An example of the manufacturing process of the thermistor element 1 generally includes the following processes.
  • a BaTiO 3 ceramic powder capable of obtaining desired characteristics is press-molded to a size of 150 [mm] ⁇ 150 [mm]. Thereafter, a predetermined degreasing / firing process is performed on the press-molded ceramic powder. Thereby, a mother substrate is obtained. The mother substrate is lapped until its thickness (corresponding to thickness T) reaches a predetermined value. Thereafter, a strip-shaped substrate having a predetermined width (corresponding to the width W in the front-rear direction) is obtained by dicing cut.
  • the strip-shaped substrate is diced again so that the L dimension is 300 [ ⁇ m] or more and 700 [ ⁇ m] or less (for example, 500 [ ⁇ m]).
  • an Ag—Zn paste that provides an ohmic junction with the ceramic is applied to each of the end surfaces Sa and Sb of the ceramic substrate 2. Thereafter, the ceramic substrate 2 coated with the Ag—Zn-based paste is baked. Then, after a thermosetting Ag paste is applied on the Ag—Zn alloy layer, the Ag paste is heated and cured. Thereby, the base electrodes 4a and 4b are formed. At this time, the maximum thickness tmax [ ⁇ m] of the external electrodes 3a and 3b is set to 0.015 ⁇ d ⁇ 1.5 ⁇ tmax ⁇ 120 (for example, about 80 [ ⁇ m]). The electrodes 4a and 4b are applied on the end surfaces Sa and Sb.
  • the ceramic substrate 2 is moved in the vertical direction, and the end surfaces Sa and Sb are immersed in the electrode paste.
  • the thickness of the base electrodes 4a and 4b is adjusted by controlling the speed of this vertical movement.
  • the thickness of the base electrodes 4a and 4b can be adjusted by adjusting the viscosity of the electrode paste or by scraping the electrode paste once applied to the end surfaces Sa and Sb.
  • first plating films 5a and 5b of Ni are formed on the surfaces of the base electrodes 4a and 4b by electroplating, and then the second plating film 6a of Sn is formed on the first plating films 5a and 5b. , 6b are formed.
  • the thermistor element 1 is completed through the above steps.
  • samples 1 to 9, 14, and 15 are 0.12 [mm 3 ]
  • samples 10 to 13 are 0.18 [mm 3 ].
  • Samples 1 to 3 and 14 are 700 [ ⁇ m]
  • Samples 4 to 6, 12, 13, and 15 are 500 [ ⁇ m]
  • Samples 7 to 9 are 300 [ ⁇ m].
  • Samples 10 and 11 are 1000 [ ⁇ m].
  • Samples 1, 10, and 12 are 9 [ ⁇ m]
  • Samples 2, 5, and 8 are 15 [ ⁇ m]
  • Samples 3, 6, 9, 11, and 13 are 120 [ ⁇ m].
  • sample 4 is 6 [ ⁇ m]
  • samples 7, 14, and 15 are 3 [ ⁇ m].
  • samples 1 to 9 have the element volume V, L dimension d, and maximum thickness tmax of the thermistor element 1. Samples 10-15 are listed in Table 1 for comparison with Samples 1-9.
  • the measurement system M includes any one of samples 1 to 15 and an oscilloscope 10.
  • Each sample 1 to 15 is supplied with a predetermined constant current I. Accordingly, the temperature of the ceramic substrate of each sample 1 to 15 increases, and the resistance value increases.
  • the oscilloscope 10 measures the voltage Vout between both terminals of each sample 1-15.
  • the applicant of the present application measures the initial voltage Vout when the current I is supplied to each of the samples 1 to 15 using the measurement system M as described above. Then, after the current I is supplied, the time until the measurement voltage Vout becomes, for example, 100 times the initial voltage Vout is measured as the response time Tres. According to the measurement results of the present inventors, it has been found that Samples 1 to 9 have an excellent response time of 1 second or less. That is, when the L dimension d [ ⁇ m] is 300 ⁇ d ⁇ 700 and 0.015 ⁇ d ⁇ 1.5 ⁇ tmax, the chip-type positive temperature coefficient thermistor element 1 having excellent responsiveness can be provided. it can.
  • the thermistor element 1 has an excellent response time of 1 second or less as a single element, so that it is not necessary to thermally couple the thermistor element 1 and the heat source with a resin or the like during actual use. As a result, it is possible to detect overheating at a low cost.
  • the chip-type positive temperature coefficient thermistor element according to the present invention has excellent responsiveness and is useful for overheating detection and overcurrent protection of a heat source.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Thermistors And Varistors (AREA)

Abstract

A chip-type positive temperature coefficient thermistor element (1) has an element volume of no more than 0.12 [mm3]. In order to improve responsiveness, the following are provided: a ceramic base material (2) which has end surfaces (Sa, Sb) that face one another in parallel in the X axis direction and side surfaces (Sc) that connect the end surfaces (Sa, Sb), and the inner resistance value of which changes according to a temperature change; and a metal-containing first external electrode (4a) and second external electrode (4b) that are provided on the end surfaces (Sa, Sb). The distance (d [μm]) in the X axis direction between the end surfaces (Sa, Sb) is 300 ≤ d ≤ 700, and the maximum point thickness (tmax [μm]) of the thickness in the X axis direction of the first external electrode (4a) and the second external electrode (4b) is tmax ≥ 0.015 x d - 1.5.

Description

チップ型正特性サーミスタ素子Chip-type positive temperature coefficient thermistor element
　本発明は、０．１２ｍｍ3以下の体積を有するチップ型正特性サーミスタ素子に関する。 The present invention relates to a chip type positive temperature coefficient thermistor element having a volume of 0.12 mm 3 or less.
　従来のチップ型正特性サーミスタ素子（以下、単にサーミスタ素子という）の一例としては、例えば下記特許文献１に記載のものがある。このサーミスタ素子は、略直方体形状を有するセラミック基体と、該サーミスタ素子の両端面に設けられた外部電極と、を備えている。各外部電極は、導電性金属層、導電性樹脂層および金属めっき層を積層した構造を有する。ここで、導電性金属層がセラミック基体の両端面直上に形成され、金属めっき層が最も外側の層となっている。また、セラミック基体において、外部電極が設けられていない四側面には、機械的強度等を向上させるためにガラス層が形成されている。 As an example of a conventional chip-type positive temperature coefficient thermistor element (hereinafter simply referred to as a thermistor element), for example, there is one described in Patent Document 1 below. This thermistor element includes a ceramic base having a substantially rectangular parallelepiped shape, and external electrodes provided on both end faces of the thermistor element. Each external electrode has a structure in which a conductive metal layer, a conductive resin layer, and a metal plating layer are laminated. Here, the conductive metal layer is formed immediately above both end faces of the ceramic substrate, and the metal plating layer is the outermost layer. In addition, a glass layer is formed on the four side surfaces of the ceramic substrate on which no external electrode is provided in order to improve mechanical strength and the like.
　特許文献１に記載のものに限らず、従来のサーミスタ素子は、典型的には、熱源の過熱検知に用いられる。具体的には、サーミスタ素子は熱源の近傍に実装される。この熱源の温度（つまり周囲温度）が増加すると、セラミック基体の温度が上昇すると共に抵抗値が上昇する。また、このサーミスタ素子には、電源電圧が供給されている。すると、サーミスタ素子の出力端子間には、周囲温度を表す電圧が出力され、ＩＣに供給される。ＩＣは、入力電圧に基づき、熱源が過熱状態か否かを判断する。 The conventional thermistor element is not limited to the one described in Patent Document 1, and is typically used for overheating detection of a heat source. Specifically, the thermistor element is mounted in the vicinity of the heat source. When the temperature of the heat source (that is, the ambient temperature) increases, the temperature of the ceramic substrate increases and the resistance value increases. A power supply voltage is supplied to the thermistor element. Then, a voltage representing the ambient temperature is output between the output terminals of the thermistor element and supplied to the IC. The IC determines whether the heat source is in an overheated state based on the input voltage.
特開平１０－０９２６０６号公報Japanese Patent Laid-Open No. 10-092606
　過熱検知用のサーミスタ素子に関しては、近年、小型化（例えば、０．１２ｍｍ3以下の体積）が進んでいる。このような小型のサーミスタ素子に対しても、熱源が過熱状態になってから高速に（例えば１秒以内に）応答することが要求される。そのための一般的手法は、サーミスタ素子と熱源とを樹脂等で熱結合させることであった。しかし、この手法では、樹脂等でサーミスタ素子と熱源とを覆う必要があるので、高コストになる。 In recent years, miniaturization (for example, a volume of 0.12 mm 3 or less) has been advanced with respect to a thermistor element for detecting overheat. Even such a small thermistor element is required to respond at high speed (for example, within 1 second) after the heat source is overheated. A general technique for that purpose is to thermally couple the thermistor element and the heat source with a resin or the like. However, in this method, since it is necessary to cover the thermistor element and the heat source with resin or the like, the cost becomes high.
　それゆえに、本発明の目的は、素子の体積が０．１２［ｍｍ3］以下で、低コストで応答性に優れたチップ型正特性サーミスタ素子を提供することである。 Therefore, an object of the present invention is to provide a chip-type positive temperature coefficient thermistor element having an element volume of 0.12 [mm 3 ] or less and excellent in responsiveness at low cost.
　上記目的を達成するために、本発明の一局面は、０．１２［ｍｍ3］以下の体積を有するチップ型正特性サーミスタ素子であって、互いに平行に向かい合いかつ所定方向に対向する第一端面および第二端面と、該第一端面および該第二端面の間を接続する側面を有するセラミック基体であって、温度変化により内部抵抗値が変化するセラミック基体と、前記第一端面および前記第二端面に設けられた第一外部電極および第二外部電極であって、金属を含有する第一外部電極および第二外部電極と、を備えている。前記第一端面および前記第二端面の間の所定方向への距離ｄ［μｍ］は、３００≦ｄ≦７００であり、前記第一外部電極および／または前記第二外部電極において、所定方向への厚みが最大の箇所の厚さｔmax［μｍ］は、ｔmax≧０．０１５×ｄ－１．５である。 In order to achieve the above object, one aspect of the present invention is a chip-type positive temperature coefficient thermistor element having a volume of 0.12 [mm 3 ] or less, and faces in parallel with each other and faces in a predetermined direction. A ceramic substrate having a second end face and a side face connecting the first end face and the second end face, wherein the internal resistance varies with temperature change, the first end face and the second end face. A first external electrode and a second external electrode provided on the end face, the first external electrode and the second external electrode containing metal. A distance d [μm] in a predetermined direction between the first end surface and the second end surface is 300 ≦ d ≦ 700, and the first external electrode and / or the second external electrode are arranged in a predetermined direction. The thickness tmax [μm] at the maximum thickness is tmax ≧ 0.015 × d−1.5.
　上記局面によれば、金属を含有する第一外部電極および／または第二外部電極は、ｔmax≧０．０１５×ｄ－１．５［μｍ］という十分な厚みを有する。したがって、熱源付近に本サーミスタ素子を実装した時、第一外部電極および／または第二外部電極と熱源との距離が相対的に近くなるため、熱源からの熱はセラミック基体に高速に伝わる。これによって、応答性に優れたサーミスタ素子を提供することが可能となる。また、樹脂等でサーミスタ素子および熱源を覆う必要もなくなるため、低コストで過熱検知を行うことが可能となる。 According to the above aspect, the first external electrode and / or the second external electrode containing metal has a sufficient thickness tmax ≧ 0.015 × d−1.5 [μm]. Therefore, when the thermistor element is mounted in the vicinity of the heat source, the distance between the first external electrode and / or the second external electrode and the heat source is relatively short, so that heat from the heat source is transmitted to the ceramic base at high speed. As a result, it is possible to provide a thermistor element having excellent responsiveness. Further, since it is not necessary to cover the thermistor element and the heat source with resin or the like, it is possible to detect overheating at a low cost.
本発明の一実施形態に係るチップ側正特性サーミスタ素子を示す縦断面図である。It is a longitudinal section showing a chip side positive characteristic thermistor element concerning one embodiment of the present invention. 図１のセラミック基体のエッジ部分における外部電極のＸ軸方向厚みを示す模式図である。It is a schematic diagram which shows the X-axis direction thickness of the external electrode in the edge part of the ceramic base | substrate of FIG. チップ型正特性サーミスタ素子の各試料の特性を測定するための回路構成を例示する図である。It is a figure which illustrates the circuit structure for measuring the characteristic of each sample of a chip | tip type | mold positive characteristic thermistor element.
　以下、図面を参照して、本発明の一実施形態に係るチップ型正特性サーミスタ素子（以下、単にサーミスタ素子という）について説明する。 Hereinafter, a chip type positive temperature coefficient thermistor element (hereinafter simply referred to as a thermistor element) according to an embodiment of the present invention will be described with reference to the drawings.
　（はじめに）
　まず、以下の説明の便宜のため、図１に示すＸ軸、Ｙ軸およびＺ軸を定義する。Ｘ軸、Ｙ軸およびＺ軸は、サーミスタ素子１の左右方向、前後方向および上下方向を示す。 (Introduction)
First, for the convenience of the following description, the X axis, the Y axis, and the Z axis shown in FIG. 1 are defined. The X axis, Y axis, and Z axis indicate the left-right direction, the front-rear direction, and the vertical direction of the thermistor element 1.
（サーミスタ素子の構成）
　図１において、サーミスタ素子１は、セラミック基体２と、二個一対の外部電極３ａ，３ｂと、を備えている。 (Configuration of thermistor element)
In FIG. 1, the thermistor element 1 includes a ceramic base 2 and a pair of external electrodes 3a and 3b.
　セラミック基体２は、例えばＢａＴｉＯ3（チタン酸バリウム）に所定の添加物が加えられたセラミック材料からなる。ここで、添加物は、希土類であり、典型的にはＳｍ（サマリウム）である。これ以外にも、Ｎｄ（ネオジム）またはＬａ（ランタン）等を添加物として用いることが可能である。 The ceramic substrate 2 is made of, for example, a ceramic material in which a predetermined additive is added to BaTiO 3 (barium titanate). Here, the additive is a rare earth, typically Sm (samarium). In addition to this, Nd (neodymium), La (lanthanum), or the like can be used as an additive.
　セラミック基体２は、単板構造および積層構造いずれの構造を有していても構わない。図１では、単板構造のものが例示されている。また、このセラミック基体２は、例えば、左右方向に長い略直方体形状を有しており、第一端面Ｓａおよび第二端面Ｓｂと、該第一端面Ｓａおよび該第二端面Ｓｂとを繋ぐ少なくとも一つの側面Ｓｃと、を有する。端面Ｓａ，Ｓｂは、互いに平行であって、Ｘ軸方向に相対向している。ここで、本実施形態では、両端面Ｓａ，Ｓｂ共に実質的に矩形形状を有する。この場合、側面Ｓｃは、それぞれが略長方形状の第一側面Ｓｃ１～第四側面Ｓｃ４を含むことになる。 The ceramic substrate 2 may have a single plate structure or a laminated structure. FIG. 1 illustrates a single plate structure. The ceramic base 2 has, for example, a substantially rectangular parallelepiped shape that is long in the left-right direction, and at least one connecting the first end surface Sa and the second end surface Sb and the first end surface Sa and the second end surface Sb. And two side surfaces Sc. The end surfaces Sa and Sb are parallel to each other and face each other in the X-axis direction. Here, in this embodiment, both end surfaces Sa and Sb have a substantially rectangular shape. In this case, the side surface Sc includes the first side surface Sc1 to the fourth side surface Sc4 each having a substantially rectangular shape.
　次に、セラミック基体２のサイズの一例を説明する。セラミック基体２のＸ軸方向の長さ（以下、Ｌ寸法という）を、二端面Ｓａ，Ｓｂの間の距離ｄ［μｍ］とする。ｄは、３００≦ｄ≦７００に選ばれる。Ｙ軸方向の幅ＷやＺ軸方向の厚さＴに関しては、特に限定されないが、サーミスタ素子１全体の体積Ｖが０．１２［ｍｍ3］以下になるように、セラミック基体２のサイズは定められる。 Next, an example of the size of the ceramic substrate 2 will be described. The length of the ceramic substrate 2 in the X-axis direction (hereinafter referred to as L dimension) is defined as a distance d [μm] between the two end surfaces Sa and Sb. d is selected such that 300 ≦ d ≦ 700. The width W in the Y-axis direction and the thickness T in the Z-axis direction are not particularly limited, but the size of the ceramic base 2 is determined so that the entire thermistor element 1 has a volume V of 0.12 [mm 3 ] or less. It is done.
　ここで、上記の通り、セラミック基体２は略直方体形状を有する。しかし、実際のセラミック基体２のエッジ部分は完全な直角では無く、丸みを持っている。上記距離ｄは、二端面Ｓａ，Ｓｂにおける丸み持った部分の間の距離では無く、二端面Ｓａ，Ｓｂの大部分を占める平面的な部分の間の距離である。 Here, as described above, the ceramic substrate 2 has a substantially rectangular parallelepiped shape. However, the actual edge portion of the ceramic substrate 2 is not completely right but rounded. The distance d is not the distance between the rounded portions of the two end surfaces Sa and Sb, but the distance between the planar portions occupying most of the two end surfaces Sa and Sb.
　外部電極３ａ，３ｂは、端面Ｓａ，Ｓｂに形成され、下地電極４ａ，４ｂと、第一メッキ膜５ａ，５ｂと、第二メッキ膜６ａ，６ｂと、を有する。 External electrodes 3a and 3b are formed on end surfaces Sa and Sb, and have base electrodes 4a and 4b, first plating films 5a and 5b, and second plating films 6a and 6b.
　下地電極４ａ，４ｂは、例えば、Ａｇ－Ｚｎ（銀・亜鉛）合金およびＡｇ（銀）からなる。具体的には、各端面Ｓａ，ＳｂにＡｇ－Ｚｎ合金層がオーミック接合しており、該Ａｇ－Ｚｎ合金層上にＡｇ（銀）層が形成されている。 The base electrodes 4a and 4b are made of, for example, an Ag—Zn (silver / zinc) alloy and Ag (silver). Specifically, an Ag—Zn alloy layer is ohmic-bonded to each of the end faces Sa and Sb, and an Ag (silver) layer is formed on the Ag—Zn alloy layer.
　また、第一メッキ膜５ａ，５ｂは、例えばＮｉからなり、下地電極４ａ，４ｂ上に形成される。第二メッキ膜６ａ，６ｂは、例えばＳｎ（スズ）からなり、第一メッキ膜５ａ，５ｂ上に形成される。 The first plating films 5a and 5b are made of, for example, Ni and are formed on the base electrodes 4a and 4b. The second plating films 6a and 6b are made of, for example, Sn (tin) and are formed on the first plating films 5a and 5b.
　上記のような外部電極３ａ，３ｂの一方または両方は、以下のような最大厚さｔmaxを有する。最大厚さｔmaxとは、基本的には、対象となる外部電極３ａ，３ｂにおいて、Ｘ軸方向への厚み（換言すると、端面Ｓａ，Ｓｂの法線方向）が最大の箇所の厚さである。上記の通り、セラミック基体２のエッジ部分は完全な直角ではなく、丸みを有する。また、周知の通り、外部電極３ａ，３ｂは、端面Ｓａ，Ｓｂの丸みを帯びた部分上も形成される。この部分のＸ軸方向への厚みは、図２に矢印で示すように、端面Ｓａ，Ｓｂの平面部分の延長面（仮想面）Ｓｖを基準として定められる。 One or both of the external electrodes 3a and 3b as described above have the following maximum thickness tmax. The maximum thickness tmax is basically the thickness of the portion of the target external electrodes 3a and 3b where the thickness in the X-axis direction (in other words, the normal direction of the end surfaces Sa and Sb) is maximum. . As described above, the edge portion of the ceramic substrate 2 is not perfectly right but rounded. As is well known, the external electrodes 3a and 3b are also formed on the rounded portions of the end surfaces Sa and Sb. The thickness of this portion in the X-axis direction is determined with reference to the extended surface (virtual surface) Sv of the planar portion of the end surfaces Sa and Sb, as indicated by arrows in FIG.
　以上の通り定義される最大厚さｔmaxに関しては、少なくとも下限値が定められる。具体的には、上記距離ｄ［μｍ］が３００≦ｄ≦７００の場合、最大厚さｔmaxは、詳細は後述するが、ｔmax≧０．０１５×ｄ－１．５と定められる。また、最大厚さｔmaxの上限値は、本サーミスタ素子１の実装時にツームストン現象の発生を防止するため、１２０［μｍ］と定められる。 As for the maximum thickness tmax defined as described above, at least a lower limit value is determined. Specifically, when the distance d [μm] is 300 ≦ d ≦ 700, the maximum thickness tmax is determined as tmax ≧ 0.015 × d−1.5, as will be described in detail later. Further, the upper limit value of the maximum thickness tmax is set to 120 [μm] in order to prevent the occurrence of the tombstone phenomenon when the thermistor element 1 is mounted.
（サーミスタ素子の製法の一例）
　上記サーミスタ素子１の製造工程の一例は、大略的には、下記の工程からなる。 (Example of thermistor element manufacturing method)
An example of the manufacturing process of the thermistor element 1 generally includes the following processes.
　まず、所望特性を得ることが可能なＢａＴｉＯ3系セラミック粉末が、１５０［ｍｍ］×１５０［ｍｍ］のサイズにプレス成形される。その後、プレス成形されたセラミック粉末に対して、所定の脱脂・焼成処理が行われる。これにより、マザー基板が得られる。マザー基板は、その厚さ（厚さＴに相当）が所定値となるまでラップ研磨が行われる。その後、ダイシングカットにより、所定幅（前後方向の幅Ｗに相当）を有する短冊状基板が得られる。 First, a BaTiO 3 ceramic powder capable of obtaining desired characteristics is press-molded to a size of 150 [mm] × 150 [mm]. Thereafter, a predetermined degreasing / firing process is performed on the press-molded ceramic powder. Thereby, a mother substrate is obtained. The mother substrate is lapped until its thickness (corresponding to thickness T) reaches a predetermined value. Thereafter, a strip-shaped substrate having a predetermined width (corresponding to the width W in the front-rear direction) is obtained by dicing cut.
　その後、短冊状基板は、そのＬ寸法が３００［μｍ］以上７００［μｍ］以下となるように（例えば、５００［μｍ］となるように）、再度ダイシングカットされる。 Thereafter, the strip-shaped substrate is diced again so that the L dimension is 300 [μm] or more and 700 [μm] or less (for example, 500 [μm]).
　以上の工程により、セラミック基体２が大量に作製される。 Through the above steps, a large amount of the ceramic substrate 2 is produced.
　次に、セラミック基体２の端面Ｓａ，Ｓｂのそれぞれには、セラミックとの間でオーミック接合が得られるＡｇ－Ｚｎ系ペーストが塗布される。その後、Ａｇ－Ｚｎ系ペーストが塗布されたセラミック基体２に対し焼き付け処理がなされる。その後、Ａｇ－Ｚｎ合金層上に、熱硬化性のＡｇペーストが塗布された後、Ａｇペーストを加熱して硬化させる。それによって、下地電極４ａ，４ｂが形成される。この時、外部電極３ａ，３ｂの最大厚さｔmax［μｍ］が、０．０１５×ｄ－１．５≦ｔmax≦１２０となるように（例えば、８０［μｍ］程度となるように）、下地電極４ａ，４ｂは端面Ｓａ，Ｓｂ上に塗布される。より具体的には、セラミック基体２を上下方向に移動させて、各端面Ｓａ，Ｓｂ部分が電極ペーストに浸される。例えば、この上下動の速度を制御することで、下地電極４ａ，４ｂの厚さが調整される。他にも、電極ペーストの粘性を調整したり、端面Ｓａ，Ｓｂに一旦塗布された電極ペーストを掻き取ったりすることで、下地電極４ａ，４ｂの厚さを調整することもできる。 Next, an Ag—Zn paste that provides an ohmic junction with the ceramic is applied to each of the end surfaces Sa and Sb of the ceramic substrate 2. Thereafter, the ceramic substrate 2 coated with the Ag—Zn-based paste is baked. Then, after a thermosetting Ag paste is applied on the Ag—Zn alloy layer, the Ag paste is heated and cured. Thereby, the base electrodes 4a and 4b are formed. At this time, the maximum thickness tmax [μm] of the external electrodes 3a and 3b is set to 0.015 × d−1.5 ≦ tmax ≦ 120 (for example, about 80 [μm]). The electrodes 4a and 4b are applied on the end surfaces Sa and Sb. More specifically, the ceramic substrate 2 is moved in the vertical direction, and the end surfaces Sa and Sb are immersed in the electrode paste. For example, the thickness of the base electrodes 4a and 4b is adjusted by controlling the speed of this vertical movement. In addition, the thickness of the base electrodes 4a and 4b can be adjusted by adjusting the viscosity of the electrode paste or by scraping the electrode paste once applied to the end surfaces Sa and Sb.
　最後に、下地電極４ａ，４ｂの表面に、電界メッキにより、まず、Ｎｉの第一メッキ膜５ａ，５ｂが形成され、その後、第一メッキ膜５ａ，５ｂ上にはＳｎの第二メッキ膜６ａ，６ｂが形成される。以上の工程により、サーミスタ素子１が完成する。 Finally, first plating films 5a and 5b of Ni are formed on the surfaces of the base electrodes 4a and 4b by electroplating, and then the second plating film 6a of Sn is formed on the first plating films 5a and 5b. , 6b are formed. The thermistor element 1 is completed through the above steps.
（素子体積Ｖ、Ｌ寸法ｄ、最大厚さｔmaxと、応答時間との関係）
　本件発明者は、素子体積Ｖ、Ｌ寸法ｄ、最大厚さｔmaxを変更して、以下の表１に示す試料番号１～１５のサーミスタ素子（以下、単に試料１～１５という）を作製し、図３に示すような測定系Ｍにて応答時間を確認した。 (Relationship between element volume V, L dimension d, maximum thickness tmax, and response time)
The present inventors changed the element volume V, L dimension d, and maximum thickness tmax to produce thermistor elements of sample numbers 1 to 15 (hereinafter simply referred to as samples 1 to 15) shown in Table 1 below. The response time was confirmed by the measurement system M as shown in FIG.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　表１に示すように、素子体積Ｖに関しては、試料１～９、１４、１５は０．１２［ｍｍ3］であり、試料１０～１３は０．１８［ｍｍ3］である。 As shown in Table 1, regarding the element volume V, samples 1 to 9, 14, and 15 are 0.12 [mm 3 ], and samples 10 to 13 are 0.18 [mm 3 ].
　また、Ｌ寸法ｄに関しては、試料１～３、１４は７００［μｍ］であり、試料４～６、１２，１３，１５は５００［μｍ］であり、試料７～９は３００［μｍ］であり、試料１０、１１は１０００［μｍ］である。 Regarding the L dimension d, Samples 1 to 3 and 14 are 700 [μm], Samples 4 to 6, 12, 13, and 15 are 500 [μm], and Samples 7 to 9 are 300 [μm]. Yes, Samples 10 and 11 are 1000 [μm].
　また、最大厚さｔmaxに関しては、試料１、１０、１２は９［μｍ］であり、試料２，５，８が１５［μｍ］であり、試料３、６、９、１１、１３は１２０［μｍ］であり、試料４は６［μｍ］であり、試料７、１４、１５は３［μｍ］である。 Regarding the maximum thickness tmax, Samples 1, 10, and 12 are 9 [μm], Samples 2, 5, and 8 are 15 [μm], and Samples 3, 6, 9, 11, and 13 are 120 [μm]. μm], sample 4 is 6 [μm], and samples 7, 14, and 15 are 3 [μm].
　試料１～１５のうち、上記サーミスタ素子１の素子体積Ｖ、Ｌ寸法ｄ、最大厚さｔmaxを有するのは、試料１～９である。試料１０～１５は、試料１～９との比較のために表１に挙げられている。 Among samples 1 to 15, samples 1 to 9 have the element volume V, L dimension d, and maximum thickness tmax of the thermistor element 1. Samples 10-15 are listed in Table 1 for comparison with Samples 1-9.
　ここで、図３に示す測定系Ｍを説明する。測定系Ｍは、試料１～１５のいずれかと、オシロスコープ１０と、を備えている。 Here, the measurement system M shown in FIG. 3 will be described. The measurement system M includes any one of samples 1 to 15 and an oscilloscope 10.
　各試料１～１５には、予め定められた一定値の電流Ｉが供給されている。これに応じて、各試料１～１５のセラミック基体の温度が上昇し、抵抗値が上昇する。オシロスコープ１０は、各試料１～１５の両端子間電圧Ｖoutを測定している。 Each sample 1 to 15 is supplied with a predetermined constant current I. Accordingly, the temperature of the ceramic substrate of each sample 1 to 15 increases, and the resistance value increases. The oscilloscope 10 measures the voltage Vout between both terminals of each sample 1-15.
　本件出願人は、上記のような測定系Ｍにて、各試料１～１５に電流Ｉを供給時の初期電圧Ｖoutを測定しておく。そして、電流Ｉの供給後、測定電圧Ｖoutが初期電圧Ｖoutの例えば１００倍になるまでの時間を応答時間Ｔresとして測定する。本件発明者の測定結果によれば、試料１～９が１秒以下という優れた応答時間であることが判明した。つまり、Ｌ寸法ｄ［μｍ］が３００≦ｄ≦７００であって、０．０１５×ｄ－１．５≦ｔmaxであれば、応答性に優れたチップ型正特性サーミスタ素子１を提供することができる。このように、サーミスタ素子１に関しては、素子単体で１秒以下という優れた応答時間を有するため、実際の使用時にサーミスタ素子１と熱源とを樹脂などにより熱結合する必要が無くなる。その結果、低コストで過熱検知を行うことが可能となる。 The applicant of the present application measures the initial voltage Vout when the current I is supplied to each of the samples 1 to 15 using the measurement system M as described above. Then, after the current I is supplied, the time until the measurement voltage Vout becomes, for example, 100 times the initial voltage Vout is measured as the response time Tres. According to the measurement results of the present inventors, it has been found that Samples 1 to 9 have an excellent response time of 1 second or less. That is, when the L dimension d [μm] is 300 ≦ d ≦ 700 and 0.015 × d−1.5 ≦ tmax, the chip-type positive temperature coefficient thermistor element 1 having excellent responsiveness can be provided. it can. As described above, the thermistor element 1 has an excellent response time of 1 second or less as a single element, so that it is not necessary to thermally couple the thermistor element 1 and the heat source with a resin or the like during actual use. As a result, it is possible to detect overheating at a low cost.
　本発明に係るチップ型正特性サーミスタ素子は、応答性に優れ、熱源の過熱検知や過電流保護等に有用である。 The chip-type positive temperature coefficient thermistor element according to the present invention has excellent responsiveness and is useful for overheating detection and overcurrent protection of a heat source.
　１　サーミスタ素子
　２　セラミック基体
　３ａ，３ｂ　外部電極 1 Thermistor element 2 Ceramic substrate 3a, 3b External electrode

Claims (2)

  1. 　０．１２［ｍｍ3］以下の体積を有するチップ型正特性サーミスタ素子であって、
    　互いに平行に向かい合いかつ所定方向に対向する第一端面および第二端面と、該第一端面および該第二端面の間を接続する側面と、を有するセラミック基体であって、温度変化により内部抵抗値が変化するセラミック基体と、
    　前記第一端面および前記第二端面に設けられた第一外部電極および第二外部電極であって、金属を含有する第一外部電極および第二外部電極と、を備え、
    　前記第一端面および前記第二端面の間の所定方向への距離ｄ［μｍ］は、３００≦ｄ≦７００であり、
    　前記第一外部電極および／または前記第二外部電極において、所定方向への厚みが最大の箇所の厚さｔmax［μｍ］は、ｔmax≧０．０１５×ｄ－１．５である、チップ型正特性サーミスタ素子。     A chip-type positive temperature coefficient thermistor element having a volume of 0.12 [mm 3 ] or less,
    A ceramic substrate having a first end face and a second end face that face each other in parallel and face each other in a predetermined direction, and a side face that connects between the first end face and the second end face. A ceramic substrate that changes,
    A first external electrode and a second external electrode provided on the first end surface and the second end surface, comprising a first external electrode and a second external electrode containing metal,
    A distance d [μm] in a predetermined direction between the first end surface and the second end surface is 300 ≦ d ≦ 700,
    In the first external electrode and / or the second external electrode, the thickness tmax [μm] of the portion having the maximum thickness in a predetermined direction is tmax ≧ 0.015 × d−1.5. Characteristic thermistor element.
  2. 　前記ｔmax［μｍ］は、ｔmax≦１２０である、請求項１に記載のチップ型正特性サーミスタ素子。 2. The chip-type positive temperature coefficient thermistor element according to claim 1, wherein tmax [μm] is tmax ≦ 120.
PCT/JP2013/072706 2013-02-21 2013-08-26 Chip-type positive temperature coefficient thermistor element WO2014128996A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-031771 2013-02-21
JP2013031771 2013-02-21

Publications (1)

Publication Number Publication Date
WO2014128996A1 true WO2014128996A1 (en) 2014-08-28

Family

ID=51390814

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/072706 WO2014128996A1 (en) 2013-02-21 2013-08-26 Chip-type positive temperature coefficient thermistor element

Country Status (2)

Country Link
TW (1) TWI497536B (en)
WO (1) WO2014128996A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1092606A (en) * 1996-09-13 1998-04-10 Mitsubishi Materials Corp Chip thermistor and its manufacture
JPH1183641A (en) * 1997-09-08 1999-03-26 Kurabe Ind Co Ltd Glass sealed thermistor
JP2006108221A (en) * 2004-10-01 2006-04-20 Shibaura Electronics Co Ltd High-temperature heat-resistant thermistor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4492737B2 (en) * 2008-06-16 2010-06-30 株式会社村田製作所 Electronic components
WO2011024724A1 (en) * 2009-08-28 2011-03-03 株式会社村田製作所 Thermistor and method for producing same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1092606A (en) * 1996-09-13 1998-04-10 Mitsubishi Materials Corp Chip thermistor and its manufacture
JPH1183641A (en) * 1997-09-08 1999-03-26 Kurabe Ind Co Ltd Glass sealed thermistor
JP2006108221A (en) * 2004-10-01 2006-04-20 Shibaura Electronics Co Ltd High-temperature heat-resistant thermistor

Also Published As

Publication number Publication date
TW201434056A (en) 2014-09-01
TWI497536B (en) 2015-08-21

Similar Documents

Publication Publication Date Title
JP6011574B2 (en) Multilayer ceramic capacitor
EP2131374A1 (en) Ceramic electronic component with diffusion bonding between external electrode and metal terminal, and method for manufacturing the same
US9959975B2 (en) Ceramic electronic component
CN107968149B (en) Piezoelectric element unit
JP6904383B2 (en) Laminated electronic components and their mounting structure
JP5668837B2 (en) Electronic component mounting structure
JP5522533B2 (en) Surface-mount type electronic component and manufacturing method
JP2014222812A (en) Oscillation device
JP2010114167A (en) Low-resistive chip resistor, and method for manufacturing the same
JP6107062B2 (en) Chip thermistor
WO2014128996A1 (en) Chip-type positive temperature coefficient thermistor element
JP5915567B2 (en) Chip-type positive temperature coefficient thermistor element
JPH10116706A (en) Chip type thermistor and its manufacturing method
US10074465B2 (en) Method of manufacturing electronic component, and electronic component
WO2015019643A1 (en) Thermistor element
JP6828256B2 (en) NTC thermistor element
JP2018026521A (en) Thick film type thermistor
JP7300589B2 (en) Laminated varistor manufacturing method and laminated varistor
JP7361250B2 (en) Manufacturing method for laminated electronic components
JP2010245488A (en) Resistor and manufacturing method of the same
JP5929998B2 (en) Chip thermistor
JP6551346B2 (en) Electronic component and method of manufacturing electronic component
JP2001143905A (en) Method of manufacturing chip type thermistor
WO2015022784A1 (en) Electronic component and method of manufacturing same
JP2010153441A (en) Ceramic element and manufacturing method for the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13875612

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13875612

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP