WO2014127589A1 - 信号线的制作方法、阵列基板的制作方法、阵列基板以及显示装置 - Google Patents

信号线的制作方法、阵列基板的制作方法、阵列基板以及显示装置 Download PDF

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WO2014127589A1
WO2014127589A1 PCT/CN2013/075909 CN2013075909W WO2014127589A1 WO 2014127589 A1 WO2014127589 A1 WO 2014127589A1 CN 2013075909 W CN2013075909 W CN 2013075909W WO 2014127589 A1 WO2014127589 A1 WO 2014127589A1
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Prior art keywords
barrier layer
gate
array substrate
layer
signal line
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English (en)
French (fr)
Inventor
阎长江
谢海征
陈磊
徐少颖
谢振宇
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/387,519 priority Critical patent/US9484253B2/en
Publication of WO2014127589A1 publication Critical patent/WO2014127589A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/054—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • Embodiments of the present invention relate to a method of fabricating a signal line, a method of fabricating an array, an array substrate, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • display of a picture is achieved by controlling a gray scale voltage applied to a pixel electrode of each sub-pixel, that is, when a turn-on voltage is applied to a gate line of a certain row, a thin film transistor (Thin Film Transistor, TFT) is turned on, and a given gray scale voltage on the data line can be transmitted to the pixel electrode of the sub-pixel, and the voltage difference between the pixel electrode and the common electrode of the sub-pixel determines the deflection state of the liquid crystal molecule, thereby adjusting the liquid crystal
  • TFT Thin Film Transistor
  • a TFT-LCD includes an array substrate, a counter substrate, and a liquid crystal layer filled between the array substrate and the opposite substrate.
  • Figure 1 is a schematic diagram of a conventional array.
  • the array substrate includes, in order from bottom to top, a glass substrate 11, a gate electrode 12, and a gate line (not shown) disposed in the same layer as the gate electrode 12, a gate insulating layer 13, and an active layer.
  • the gate 12 and the source 15 and the drain 16 overlap, and this coincidence causes the gate 12 to generate a coupling capacitance with the source 15 and the drain 16, thereby affecting the transmission speed of the active layer 14. Summary of the invention
  • a method of fabricating a signal line includes: sequentially forming a material layer for fabricating a signal line, a material layer for forming a first barrier layer, and a material layer for forming a second barrier layer; and preparing the first layer by a patterning process a barrier layer and the second barrier layer; and the signal line is formed by a patterning process.
  • a method of fabricating an array substrate includes the steps of fabricating a signal line, and the signal line is fabricated by the method of fabricating the signal line as described above.
  • an array substrate is provided.
  • the array includes a signal line, a first barrier layer on the signal line, and a second barrier layer on the first barrier layer.
  • a display device includes the above array substrate.
  • the signal line on the array substrate (the signal line may be a gate, a gate line or a data line of the thin film transistor) is thinned, so that the aperture ratio of the array substrate can be increased, and the backlight can be enhanced. Over rate, and improve the brightness of the picture.
  • the signal line is the gate of the thin film transistor
  • the gate since the gate is thinned, the overlapping area of the gate and the source and the drain can be reduced, and the coupling capacitance between the gate and the source and the drain can be By decreasing, the response time of the thin film transistor can be shortened.
  • the thin film transistor may have a plurality of insulating layer structures, thereby increasing the capacitance of the gate electrode. Improve the transmission speed of thin film transistors and improve the channel characteristics of thin film transistors.
  • 1 is a schematic structural view of a conventional array substrate
  • FIG. 4 is a schematic view showing a source, a drain, and an active layer formed on the insulating layer according to the present invention
  • Figure 5 is a schematic view showing the formation of a passivation layer on the source and drain according to the present invention.
  • FIG. 6 is a schematic structural diagram of an array reverse according to an embodiment of the invention. detailed description
  • Embodiments of the present invention provide a method of fabricating a signal line.
  • the method for manufacturing the signal line includes: sequentially forming a material layer for forming a signal line, a material layer for forming a first barrier layer, and a material layer for forming a second barrier layer, wherein under the same etching condition, The lateral etch rate of the material layer forming the first barrier layer is greater than the lateral etch rate of the material layer used to form the second barrier layer;
  • the signal line is formed by etching a material layer for forming a signal line by an etching process.
  • the signal line may be any wiring for transmitting a signal, such as a gate of a thin film transistor, a data line, a gate line, a common electrode line, or the like.
  • a deposition method may be employed to sequentially form a material layer for forming a signal line, a material layer for forming a first barrier layer, and a material layer for forming a second barrier layer.
  • Dry etching may be employed to etch the material layer used to form the first barrier layer and the material layer used to form the second barrier layer.
  • the material layer used to make the signal lines can be etched using wet etching.
  • Embodiments of the present invention also provide an array fabrication method.
  • the method of fabricating the array includes the steps of fabricating the signal lines described above.
  • the array substrate includes a thin film transistor, a gate line, and a data line, and the thin film transistor is located at a crossing position of the gate line and the data line.
  • the signal line may be a gate, a gate line or a data line of a thin film transistor.
  • the signal line may also be a common electrode line on the array substrate.
  • the gate electrode 22 is formed on the glass substrate 21.
  • the detailed fabrication process of the gate electrode 22 is as shown in FIG. 2, and the specific steps include: 1) first deposited on a glass substrate 21, molybdenum (Mo) or chrome (Cr) metal layers a, followed by depositing a silicon oxide (SiO x) layer (b) and silicon nitride (SiN x) layer c.
  • the SiO x layer b there is an opposite stress between the SiO x layer b and the SiN x layer c, and the SiO x layer b generates tensile stress on the glass substrate, and the 81 layer (which generates compressive stress on the glass substrate).
  • the tensile stress and the compressive stress cancel each other, thereby reducing the probability of deformation of the glass substrate caused by deposition.
  • the SiO lateral etch rate for fabricating the first barrier layer is greater than the lateral etch rate of the SiN x used to form the second barrier layer, the SiO x is employed.
  • a barrier layer is recessed to form a drill etch effect of the dry etch, which exposes more of the surface of the metal layer a for forming the gate electrode, thereby making it easier to refine the gate in the process.
  • the dry etching method since the dry etching method has high precision, the dry etching method can better control the line width of the gate.
  • the lateral etching rate of the material used to form the first barrier layer must be greater than the lateral etching rate of the material used to fabricate the second barrier layer, because only such a film layer
  • the structure can form a drilling effect, further exposing more of the surface of the metal layer a for forming the gate.
  • the SiO x material deposited on the metal layer a for forming the gate electrode has a good adhesion of 4 ⁇ , even if the subsequent process occurs, the gate electrode can be effectively prevented from being broken.
  • the drilling effect cannot be formed, and a recessed structure is not formed at the first barrier layer, so that more of the grid is not exposed.
  • the surface of the metal layer a of the pole cannot be thinned by the gate.
  • first barrier layer and the second barrier layer are made of the same material, the same drilling effect cannot be formed, and the surface of the metal layer a for forming the gate electrode cannot be exposed, and the gate cannot be thinned.
  • the gate 22 is thinned, the overlap between the gate 22 and the source 27 and the drain 28 can be eliminated or reduced, the coupling capacitance between the gate and the source and the drain is reduced, and the response time of the thin film transistor is shortened.
  • the gate electrode 22 is thinned, the aperture ratio of the array substrate can be increased, the transmittance of the backlight can be enhanced, and the image quality can be improved.
  • a gate insulating layer 25 is formed on the second barrier layer 24, as shown in FIG.
  • a resin is applied over the second barrier layer by a spin coating process to form a planarized gate insulating layer.
  • the gate insulating layer may also be silicon nitride or silicon oxide. However, it is not easy to form a planarized gate insulating layer using silicon nitride and silicon oxide as compared with a resin material.
  • the size of the gate capacitance can be adjusted by selecting the thickness of the gate insulating layer 25 and the material forming the gate insulating layer 25. The larger the gate capacitance, the easier it is to drive the thin film crystal switch and form a low on-state voltage and a high on-state current.
  • the SiO ⁇ S has a dielectric constant of 3 to 4
  • the SiN ⁇ S has a dielectric constant of 3 to 5
  • the resin material used for the gate insulating layer has a relative dielectric constant of 10 or more. Since the size of the capacitor is proportional to the relative dielectric constant, the use of a resin material can effectively increase the gate capacitance, overcoming the drawback of simply reducing the capacitance of the gate insulating layer, and avoiding the gate insulating layer being too thin. The resulting insulation layer is broken down and other problems.
  • a semiconductor film, a doped semiconductor film, and a source/drain metal film are deposited on the gate insulating layer 25, and an active layer is formed on the gate insulating layer 25 by a patterning process using a halftone mask or a gray tone mask. 26.
  • a passivation layer 29 is formed over the active layer 26, the source 27 and the drain 28, and via holes are formed on the passivation layer 29;
  • a silicon nitride film is deposited on the active layer 26, the source 27 and the drain 28 by plasma enhanced chemical vapor deposition (PECVD), and the nitride is patterned by a conventional mask. Silicon film to obtain via holes, as shown in Figure 5;
  • PECVD plasma enhanced chemical vapor deposition
  • the pixel electrode 210 is formed over the passivation layer 29;
  • a transparent conductive film such as indium tin oxide (ITO) is deposited on the passivation layer 29 by magnetron sputtering, and the transparent conductive film is patterned by a normal mask to form the pixel electrode 210.
  • the pixel electrode 210 is directly connected to the drain 28 through a via located in the passivation layer.
  • An embodiment of the present invention further provides an array substrate, wherein the array substrate includes a signal line, a first barrier layer on the signal line, and a second barrier layer on the first barrier layer. The signal line and the first barrier layer are recessed inward relative to the second barrier layer when viewed from a plane in which the array substrate is located.
  • the array substrate further includes a thin film transistor, a gate line, and a data line, and the thin film transistor is located at a crossing position of the gate line and the data line.
  • the signal line may be a gate, a gate line or a data line of a thin film transistor.
  • the signal line may also be a common electrode line on the array substrate.
  • the lateral etching speed of the material layer for forming the first barrier layer is greater than the lateral etching speed of the material layer for fabricating the second barrier layer, so that the first barrier layer can be opposite
  • the second barrier layer is recessed inward.
  • the first barrier layer Preferably, there is an opposite stress between the first barrier layer and the second barrier layer.
  • the material of the first barrier layer may be SiO x
  • the material of the second barrier layer may be SiN x .
  • the signal line has a width of 2 to 2.5 m, and within the width range, the signal line is ensured to be continuous.
  • an array includes a substrate 21, a gate electrode 22, a first barrier layer 23, a second barrier layer 24, a gate insulating layer 25, an active layer 26, and a source 27, from bottom to top.
  • the gate electrode 22, the first barrier layer 23, the second barrier layer 24, the gate insulating layer 25, the active layer 26, the source electrode 27, and the drain electrode 28 constitute a thin film transistor.
  • the gate lines are disposed in the same layer as the gate electrodes 22.
  • the data lines are placed in the same layer as source 27 and drain 28.
  • the gate 22 is located above the substrate 21 and has a width of 2 to 2.5 m.
  • the gate is made of metal molybdenum Mo or chromium Cr.
  • the first barrier layer 23 is located above the gate electrode 22 and is made of silicon oxide SiO x .
  • the second barrier layer 24 is located above the first barrier layer 23 and below the gate insulating layer 25, and is made of silicon nitride SiN x .
  • the lateral etch rate of the SiO x used to form the first barrier layer 23 is greater than the lateral etch rate of the SiN x used to form the second barrier layer 24. Due to the SiO x The lateral etching speed is large, so that the layer and the two layers adjacent thereto can form a concave structure together, that is, a drilling effect is generated to further expose more surfaces of the gate 22. At the same time, since 8 ⁇ has a good adhesion of 4 ,, even if the subsequent process occurs, the gate can be effectively protected from disconnection.
  • the gate insulating layer 25 is over the second barrier layer 24 for insulating the gate 22 from other layers.
  • the active layer 26 is located above the gate insulating layer 25 and corresponds to the position of the second barrier layer 24.
  • the source 27 is disposed above the active layer 26 and on one side of the active layer 26.
  • the drain 28 is disposed in the same layer as the source 27 and on the other side of the active layer 26.
  • the source 27 and the drain 28 are made of a conductive metal, for example, a single Mo, Cr, or a double-layered aluminum-bismuth alloy/molybdenum (AlNd/Mo).
  • the passivation layer 29 is located above the source 27 and the drain 28, and is made of silicon nitride, for example.
  • a via hole is formed in the passivation layer, and the drain electrode 28 is directly connected to the pixel electrode 210 through the via hole.
  • the pixel electrode 210 is located above the passivation layer 29 and is made of a transparent conductive material such as ITO.
  • the embodiment of the invention further provides a display device, which comprises the above array substrate.
  • the signal line on the array substrate (the signal line may be a gate, a gate line or a data line of the thin film transistor) is thinned, so that the aperture ratio of the array substrate can be increased, and the backlight can be enhanced. Over rate, and improve the brightness of the picture.
  • the signal line is the gate of the thin film transistor
  • the gate since the gate is thinned, the overlapping area of the gate and the source and the drain can be reduced, and the coupling capacitance between the gate and the source and the drain can be By decreasing, the response time of the thin film transistor can be shortened.
  • the thin film transistor may have a plurality of insulating layer structures, thereby increasing the capacitance of the gate electrode. Improve the transmission speed of thin film transistors and improve the channel characteristics of thin film transistors.

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Abstract

一种信号线的制作方法、阵列基板的制作方法、阵列基板以及显示装置。该信号线的制作方法包括：依次形成用于制作信号线的材料层、用于制作第一阻挡层的材料层和用于制作第二阻挡层的材料层；通过构图工艺制得所述第一阻挡层和所述第二阻挡层；以及通过构图工艺制得所述信号线。

Description

信号线的制作方法、 阵列基板的制作方法、 阵列基板以及显示装置 技术领域
本发明的实施例涉及信号线的制作方法、 阵列 反的制作方法、 阵列基 板以及显示装置。 背景技术
薄膜晶体管液晶显示器（ Thin Film Transistor Liquid Crystal Display, 缩 写为 TFT-LCD ) 占据着当前显示器市场的主导地位。 在 TFT-LCD中， 通过 控制施加在每个亚像素的像素电极上的灰阶电压来实现画面的显示， 即当某 一行的栅极线上施加开启电压的时候， 薄膜晶体管 （Thin Film Transistor, TFT )打开， 数据线上的给定的灰阶电压就可以传输到亚像素的像素电极上， 亚像素的像素电极和公共电极之间的电压差决定了液晶分子的偏转状况， 从 而达到调节液晶显示器的亮度和显示效果的目的。
通常， TFT-LCD包括阵列基板、对向基板以及填充在阵列基板和对向基 板之间的液晶层。
图 1为传统的阵列 ^反的结构示意图。 从图 1中可以看出， 所述阵列基 板从下至上依次包括： 玻璃基板 11、 栅极 12和与栅极 12同层设置的栅极线 (未示出 )、 栅绝缘层 13、 有源层 14、 源极 15、 漏极 16、 与源极 15和漏极 16同层设置的数据线 (未示出 )、钝化层 17和像素电极 18。 栅极 12和源极 15、 漏极 16存在重合， 而这种重合使得栅极 12与源极 15、 漏极 16产生了 耦合电容， 从而影响了有源层 14的传输速度。 发明内容
根据本发明的一个实施例， 提供一种信号线的制作方法。 该信号线的制 作方法包括： 依次形成用于制作信号线的材料层、 用于制作第一阻挡层的材 料层和用于制作第二阻挡层的材料层； 通过构图工艺制得所述第一阻挡层和 所述第二阻挡层； 以及通过构图工艺制得所述信号线。
根据本发明的另一个实施例， 提供一种阵列基板的制作方法。 该阵列基 板的制作方法包括制作信号线的步骤， 并且所述信号线由如上所述的信号线 的制作方法来制作。
根据本发明的另一个实施例， 提供一种阵列基板。 该阵列 反包括信号 线、位于所述信号线上的第一阻挡层和位于所述第一阻挡层上的第二阻挡层。
根据本发明的再一个实施例， 提供一种显示装置。 所述显示装置包括上 述阵列基板。
根据本发明的实施例， 阵列基板上的信号线（该信号线可以是薄膜晶体 管的栅极、 栅极线或数据线）被细线化， 从而可以增加阵列基板的开口率， 增强背光的透过率， 并提升画质亮度。
当信号线为薄膜晶体管的栅极时， 由于栅极被细线化，所以栅极和源极、 漏极的重合区域可以被缩小，栅极和源极、漏极之间的耦合电容可以被减小， 薄膜晶体管的响应时间可以被缩短。
此外， 当信号线为薄膜晶体管的栅极时， 由于第一阻挡层和第二阻挡层 的制作材料均为绝缘材料， 所以薄膜晶体管可具有多层绝缘层结构， 从而能 够增大栅极的电容， 提高薄膜晶体管传输速度， 改善薄膜晶体管沟道特性。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为传统的阵列基板的结构示意图；
图 2 ^ ^^Ji^ ^ L基底基板上制作 栅极的示意图
图 3
绝缘层的示意图
图 4为在根据本发 3 绝缘层上制 作源极、 漏极和有源层的示意图；
图 5为在根据本发^ -源极和漏极上制 作钝化层的示意图； 以及
图 6为根据本发明实施例的阵列 反的结构示意图 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例提供一种信号线的制作方法。该信号线的制作方法包括： 依次形成用于制作信号线的材料层、 用于制作第一阻挡层的材料层和用 于制作第二阻挡层的材料层， 其中在同一刻蚀条件下， 用于制作第一阻挡层 的材料层的横向刻蚀速度大于用于制作第二阻挡层的材料层的横向刻蚀速 度；
通过刻蚀工艺 , 对用于制作第一阻挡层的材料层和用于制作第二阻挡层 的材料层进行刻蚀， 制得所述第一阻挡层和所述第二阻挡层；
通过刻蚀工艺，对用于制作信号线的材料层进行刻蚀，制得所述信号线。 所述信号线可以是用于传输信号的任意配线， 例如薄膜晶体管的栅极、 数据线、 栅极线、 公共电极线等。
可以采用沉积方法来依次形成用于制作信号线的材料层、 用于制作第一 阻挡层的材料层和用于制作第二阻挡层的材料层。
可以采用干法刻蚀来对用于制作第一阻挡层的材料层和用于制作第二阻 挡层的材料层进行刻蚀。
可以采用湿法刻蚀来对用于制作信号线的材料层进行刻蚀。
本发明的实施例还提供一种阵列 ^反的制作方法。 该阵列 ^反的制作方 法包括上述制作信号线的步骤。
所述阵列基板包括薄膜晶体管、 栅极线和数据线， 所述薄膜晶体管位于 栅极线与数据线的交叉位置处。 所述信号线可以为薄膜晶体管的栅极、 栅极 线或数据线。 另外， 所述信号线也可以是位于阵列基板上的公共电极线。
下面， 以信号线为薄膜晶体管的栅极为例， 详细说明根据本发明实施例 的阵列 ^反的制作方法。 该方法可以包括如下步骤。
第一步， 在玻璃基板 21上制作栅极 22, 栅极 22的详细制作过程如图 2 所示， 具体步骤包括： 1 )先在玻璃基板 21上沉积钼 （ Mo )或铬（ Cr ) 的金属层 a, 然后依次 沉积氧化硅 ( SiOx )层 b和氮化硅 ( SiNx )层 c。
优选地， SiOx层 b和 SiNx层 c之间存在相反的应力， SiOx层 b对玻璃基 板会产生拉应力， 而 81 层（；会对玻璃基板产生压应力。 由此， 可使产生的 拉应力和压应力相互抵消， 从而减小了沉积时造成的玻璃基板变形概率。
2 )在 ^层 c上涂覆光刻胶， 使用传统的栅极掩模板进行曝光、 显影； 然后进行干法刻蚀工艺， 形成第一阻挡层 23和第二阻挡层 24;
在同一干法刻蚀条件下，由于所述用于制作第一阻挡层的 SiO 横向刻 蚀速率大于所述用于制作第二阻挡层的 SiNx的横向刻蚀速率，因此采用 SiOx 的第一阻挡层会凹进去， 形成干法刻蚀的钻刻效应， 使得更多的用于形成栅 极的金属层 a的表面暴露出来， 从而在工艺上更容易做到将栅极细小化。 同 时， 由于干法刻蚀法具有较高的精准度， 因此使用干法刻蚀法能够更好的控 制所述栅极的线宽。
需指出的是， 同一干法刻蚀条件下， 用于制作第一阻挡层的材料的横向 刻蚀速率必须大于用于制作第二阻挡层的材料的横向刻蚀速率， 因为只有这 样的膜层结构， 才可以形成钻刻效应， 进一步暴露更多的用于形成栅极的金 属层 a的表面。 同时， 由于用于形成栅极的金属层 a上面沉积的 SiOx材料具 有 4艮好的粘附性， 所以即使后续工序发生过刻， 也能够有效保护栅极不出现 断线。
若是相互更换第一阻挡层和第二阻挡层的材料， 则不能形成所述的钻刻 效应， 不会在第一阻挡层处形成凹进去的结构， 从而不能暴露出更多的用于 形成栅极的金属层 a的表面， 做不到栅极的细线化。
若第一阻挡层和第二阻挡层采用同样的制作材料， 同样不能形成钻刻效 应， 不能暴露出更多的用于形成栅极的金属层 a的表面， 不能将栅极细线化。
3 )进行湿刻工艺， 刻蚀掉暴露出来金属层 a, 得到细化后的栅极 22。 由于栅极 22被细线化，所以可以消除或缩小栅极 22与源极 27、漏极 28 间的重合， 减小栅极与源极、 漏极的耦合电容， 缩短薄膜晶体管的响应时间。 另外， 由于栅极 22被细线化， 所以可增加阵列基板的开口率， 增强背光的透 过率， 并提升画质亮度。
此外， 由于在形成栅极 22时仍采用传统的栅极掩模板， 因此不会增加工 艺成本。
第二步， 在第二阻挡层 24上制作栅极绝缘层 25 , 如图 3所示。
在制作栅极绝缘层 25的过程中，采用旋涂工艺，在第二阻挡层上方涂覆 树脂，形成平坦化的栅极绝缘层。栅极绝缘层也可以采用氮化硅或者氧化硅。 但是， 与树脂材料相比， 使用氮化硅和氧化硅不容易形成平坦化的栅极绝缘 层。 可通过选择栅极绝缘层 25的厚度和形成栅极绝缘层 25的材料， 来调节 栅极电容的大小。 栅极电容越大， 越容易驱动薄膜晶体开关， 并形成低的开 态电压和高的开态电流。
SiO^S对介电常数为 3〜4, SiN^S对介电常数为 3〜5 , 而用于制作栅极 绝缘层的树脂材料的相对介电常数则为 10以上。由于电容大小和相对介电常 数成正比， 因此使用树脂材料能够有效的增大栅极电容， 克服单纯依靠减薄 栅极绝缘层增大电容的方式的缺陷， 避免因栅极绝缘层过薄而造成的绝缘层 被击穿等问题的产生。
第三步，在栅绝缘层 25上沉积半导体薄膜、掺杂半导体薄膜和源漏金属 薄膜， 通过采用半色调掩模板或灰色调掩模板的构图工艺， 在栅极绝缘层 25 上形成有源层 26、 源极 27和漏极 28 , 如图 4所示；
第四步， 在有源层 26、 源极 27和漏极 28上方形成钝化层 29, 并在该钝 化层 29上形成过孔；
例如， 采用等离子体增强化学气相沉积技术（ Plasma Enhanced Chemical Vapor Deposition, PECVD )在有源层 26、 源极 27和漏极 28上沉积氮化硅 薄膜， 采用普通掩才莫板图案化该氮化硅薄膜以得到过孔， 如图 5所示；
第五步， 在钝化层 29上方制作像素电极 210;
例如， 使用磁控溅射法在钝化层 29上沉积诸如氧化铟锡（ITO )的透明 导电薄膜， 采用普通掩模图案化该透明导电薄膜以形成像素电极 210。 所述 像素电极 210通过位于钝化层的过孔直接与漏极 28连接。
至此， 完成了根据本发明实施例的阵列 反的制作方法。
尽管在上述描述中， 以栅极为例描述了信号线的制作过程。 但是， 显然 上述信号线的制作过程也适用于在阵列基板上形成栅极线、数据线和 /或公共 电极线以使它们细线化。 由此， 可以增加阵列基板的开口率， 增强背光的透 过率， 并提升画质亮度。 本发明实施例还提供一种阵列基板， 所述阵列基板包括信号线、 位于所 述信号线上的第一阻挡层和位于所述第一阻挡层上的第二阻挡层。 当从阵列 基板所在的平面观察时 , 所述信号线和所述第一阻挡层相对于所述第二阻挡 层向里凹进。
所述阵列基板还包括薄膜晶体管、 栅极线、 数据线， 所述薄膜晶体管位 于栅极线与数据线的交叉位置处。 所述信号线可以为薄膜晶体管的栅极、 栅 极线或数据线。 另外， 所述信号线也可以是位于阵列基板上的公共电极线。
优选地， 在同一刻蚀条件下， 用于制作第一阻挡层的材料层的横向刻蚀 速度大于用于制作第二阻挡层的材料层的横向刻蚀速度， 从而使得第一阻挡 层可相对于第二阻挡层向里凹进。
优选地， 所述第一阻挡层和所述第二阻挡层之间存在相反的应力。
优选地， 所述第一阻挡层的制作材料可以为 SiOx, 所述第二阻挡层的制 作材料可以为 SiNx。
优选地， 所述信号线的宽度为 2〜2.5 m, 且在此宽度范围内， 能够保证 信号线不断线。
下面， 以信号线为薄膜晶体管的栅极为例， 详细说明根据本发明实施例 的阵列 ^反。
参阅图 6,根据本发明实施例的阵列 反从下至上包括基板 21、栅极 22、 第一阻挡层 23、 第二阻挡层 24、 栅极绝缘层 25、 有源层 26、 源极 27、 漏极 28、 钝化层 29和像素电极 210。
栅极 22、 第一阻挡层 23、 第二阻挡层 24、 栅极绝缘层 25、 有源层 26、 源极 27和漏极 28构成薄膜晶体管。栅极线与栅极 22同层设置。数据线与源 极 27和漏极 28同层设置。
所述栅极 22位于基板 21的上方， 其宽度为 2〜2.5 m; 所述栅极的制作 材料为金属钼 Mo或铬 Cr。
所述第一阻挡层 23位于栅极 22上方， 其制作材料为氧化硅 SiOx。
所述第二阻挡层 24位于第一阻挡层 23上方、栅极绝缘层 25的下方，其 制作材料为氮化硅 SiNx。
同样的刻蚀条件下， 所述用于制作第一阻挡层 23的 SiOx的横向刻蚀速 度大于所述用于制作第二阻挡层 24的 SiNx的横向刻蚀速度。 由于所述 SiOx 的横向刻蚀速度较大， 因此该层和与其相邻的两层能够一起形成凹形结构， 即产生了钻刻效应而进一步暴露了更多的栅极 22表面。 同时， 由于 8^ 具 有 4艮好的粘附性，即使后续工序发生过刻，也能够有效保护栅极不出现断线。
所述栅极绝缘层 25位于第二阻挡层 24上方，用于使栅极 22与其它层电 极绝缘。
所述有源层 26位于栅极绝缘层 25上方，并与第二阻挡层 24的位置相对 应。
所述源极 27设置在有源层 26上方， 且位于有源层 26的一侧。
所述漏极 28与源极 27同层设置， 且位于有源层 26的另一侧。
所述源极 27和漏极 28的制作材料为导电金属， 例如， 单一的 Mo、 Cr、 或者双层的铝铌合金 /钼 （AlNd/Mo )等。
所述钝化层 29位于源极 27和漏极 28上方， 其制作材料例如为氮化硅
SiNx。 所述钝化层上形成有过孔， 漏极 28通过该过孔直接与像素电极 210连 接。
所述像素电极 210位于钝化层 29的上方， 其制作材料为诸如 ITO的透 明导电材料。
本发明实施例还提供一种显示装置， 该显示装置包括上述的阵列基板。 根据本发明的实施例， 阵列基板上的信号线（该信号线可以是薄膜晶体 管的栅极、 栅极线或数据线）被细线化， 从而可以增加阵列基板的开口率， 增强背光的透过率， 并提升画质亮度。
当信号线为薄膜晶体管的栅极时， 由于栅极被细线化，所以栅极和源极、 漏极的重合区域可以被缩小，栅极和源极、漏极之间的耦合电容可以被减小， 薄膜晶体管的响应时间可以被缩短。
此外， 当信号线为薄膜晶体管的栅极时， 由于第一阻挡层和第二阻挡层 的制作材料均为绝缘材料， 所以薄膜晶体管可具有多层绝缘层结构， 从而能 够增大栅极的电容， 提高薄膜晶体管传输速度， 改善薄膜晶体管沟道特性。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种信号线的制作方法， 其中所述方法包括：
依次形成用于制作信号线的材料层、 用于制作第一阻挡层的材料层和用 于制作第二阻挡层的材料层；
通过构图工艺制得所述第一阻挡层和所述第二阻挡层； 以及
通过构图工艺制得所述信号线。
2、如权利要求 1所述方法，其中用于制作所述第一阻挡层的材料层的横 向刻蚀速度大于用于制作所述第二阻挡层的材料层的横向刻蚀速度。
3、如权利要求 1所述的方法，其中通过构图工艺制得所述第一阻挡层和 所述第二阻挡层的步骤包括：
采用干法刻蚀来对用于制作第一阻挡层的材料层和用于制作第二阻挡层 的材料层进行刻蚀。
4、如权利要求 1所述的方法，其中通过构图工艺制得所述信号线的步骤 包括：
采用湿法刻蚀来对用于制作信号线的材料层进行刻蚀。
5、如权利要求 1所述的方法，其中所述第一阻挡层和所述第二阻挡层之 间存在相反的应力。
6、如权利要求 2所述的方法， 其中所述第一阻挡层的材料为氧化硅， 所 述第二阻挡层的材料为氮化硅。
7、一种阵列基板的制作方法， 其中所述方法包括制作信号线的步骤， 并 且所述信号线由如权利要求 1-6所述的信号线的制作方法来制作。
8、如权利要求 7所述的方法， 其中所述阵列基板包括薄膜晶体管、栅极 线和数据线， 所述薄膜晶体管位于栅极线与数据线的交叉位置处，
并且其中所述信号线为所述薄膜晶体管的栅极、 所述栅极线或所述数据 线。
9、如权利要求 8所述的方法， 其中所述阵列基板还包括公共电极线， 所 述信号线为所述公共电极线。
10、 一种阵列基板， 其中所述阵列基板包括信号线、 位于所述信号线上 的第一阻挡层和位于所述第一阻挡层上的第二阻挡层。
11、如权利要求 10所述的阵列基板，其中当从阵列基板所在的平面观察 时， 所述信号线和所述第一阻挡层相对于所述第二阻挡层向里凹进。
12、如权利要求 10所述的阵列基板,其中所迷阵列基板包括薄膜晶体管、 栅极线和数据线， 所述薄膜晶体管位于栅极线与数据线的交叉位置处 ,
并且其中所述信号线为所述薄膜晶体管的栅极、 所述栅极线或所述数据 线。
13、如权利要求 12所述的阵列基板，其中所述阵列 反还包括公共电极 线， 所述信号线为所述公共电极线。
14、如权利要求 12所述的阵列基板，其中所述阵列基板还包括基板和栅 极绝缘层，
并且其中当所述信号线为所述薄膜晶体管的栅极时 , 所述栅极位于所述 基板的上方， 所述第一阻挡层位于所述栅极上方， 所述第二阻挡层位于所述 第一阻挡层的上方、 栅极绝缘层的下方。
15、如权利要求 10所述薄膜晶体管，其中所述第一阻挡层的材料为氧化 硅， 并且所述第二阻挡层的材料为氮化硅。
16、如权利要求 10所述的阵列基板，其中所述信号线的宽度为 2〜2.5 m。
17、如权利要求 10所述的阵列基板，其中所述第一阻挡层和所述第二阻 挡层之间存在相反的应力。
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