WO2023138299A1 - 阵列基板及其制作方法、显示面板和显示装置 - Google Patents

阵列基板及其制作方法、显示面板和显示装置 Download PDF

Info

Publication number
WO2023138299A1
WO2023138299A1 PCT/CN2022/141290 CN2022141290W WO2023138299A1 WO 2023138299 A1 WO2023138299 A1 WO 2023138299A1 CN 2022141290 W CN2022141290 W CN 2022141290W WO 2023138299 A1 WO2023138299 A1 WO 2023138299A1
Authority
WO
WIPO (PCT)
Prior art keywords
common electrode
base substrate
contact pad
substrate
array substrate
Prior art date
Application number
PCT/CN2022/141290
Other languages
English (en)
French (fr)
Inventor
李志威
康报虹
Original Assignee
绵阳惠科光电科技有限公司
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 绵阳惠科光电科技有限公司, 惠科股份有限公司 filed Critical 绵阳惠科光电科技有限公司
Priority to EP22921720.3A priority Critical patent/EP4280280A1/en
Publication of WO2023138299A1 publication Critical patent/WO2023138299A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present application relates to the field of display panels, in particular to an array substrate and a manufacturing method thereof, a display panel and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • a thin film transistor liquid crystal display panel includes a data line (Data Line, DL)/source line, a scan line (Scan line, SL)/gate line, a common electrode line, and a thin film transistor.
  • Data Line, DL data line
  • scan line scan line
  • SL scan line
  • common electrode line common electrode line
  • thin film transistor thin film transistor
  • the present application provides an array substrate, and the array substrate includes a base substrate, a stacked structure, a common electrode line, and a conductive structure.
  • the base substrate has a first surface and a second surface opposite to each other.
  • the stacked structure is disposed on the first surface of the base substrate, and the stacked structure includes a contact pad, a common electrode layer, and a gate line.
  • the contact pad is disposed on the first surface of the base substrate.
  • a first via hole penetrating through the first surface and the second surface of the base substrate is formed on the base substrate at a position corresponding to the contact pad.
  • the common electrode layer is connected to the contact pad.
  • the gate lines are respectively isolated from the common electrode layer and the contact pads.
  • the common electrode lines are disposed on the second surface of the base substrate, and the orthographic projection of the gate lines on the plane where the common electrode lines are located overlaps at least partially with the common electrode lines.
  • the conductive structure is connected to the contact pad, and connected to the common electrode line through the first via hole.
  • the array substrate provided in the present application can reduce the wiring area on the first surface of the array substrate by arranging the gate lines and the common electrode lines on the opposite first surface and the second surface of the array substrate respectively, and at least partially overlap the gate lines and the common electrode lines, thereby increasing the area of the pixel electrode layer in each pixel unit, thereby increasing the aperture ratio of the pixel unit.
  • the present application also provides a display panel, the display panel includes a color filter substrate and an array substrate, and the array substrate is arranged opposite to the color filter substrate.
  • the array substrate includes a base substrate, a stacked structure, a common electrode line and a conductive structure.
  • the base substrate has a first surface and a second surface opposite to each other.
  • the stacked structure is disposed on the first surface of the base substrate, and the stacked structure includes a contact pad, a common electrode layer, and a gate line.
  • the contact pad is disposed on the first surface of the base substrate.
  • a first via hole penetrating through the first surface and the second surface of the base substrate is formed on the base substrate at a position corresponding to the contact pad.
  • the common electrode layer is connected to the contact pad.
  • the gate lines are respectively isolated from the common electrode layer and the contact pads.
  • the common electrode lines are disposed on the second surface of the base substrate, and the orthographic projection of the gate lines on the plane where the common electrode lines are located overlaps at least partially with the common electrode lines.
  • the conductive structure is connected to the contact pad, and connected to the common electrode line through the first via hole.
  • FIG. 1 is a schematic top view of a conventional array substrate.
  • FIG. 2 is a schematic top view of an array substrate provided by an embodiment of the present application.
  • Fig. 3 is a schematic cross-sectional structure diagram of the structure shown in Fig. 2 along the tangent line A-A.
  • FIG. 4 is another schematic cross-sectional structure diagram of the array substrate in FIG. 2 .
  • FIG. 5 is a schematic diagram of another cross-sectional structure of the structure shown in FIG. 2 along the tangent line A-A.
  • FIG. 6 is another schematic cross-sectional structure diagram of the array substrate in FIG. 2 .
  • FIG. 7 is a schematic flowchart of a method for fabricating an array substrate provided by an embodiment of the present application.
  • FIG. 8 is a detailed flowchart of step 72 in FIG. 7 .
  • FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • orientations or positional relationships indicated by the terms “upper”, “lower”, “left”, “right”, etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation on the present application.
  • the terms “first”, “second”, etc. are used for descriptive purposes only, and should not be construed as indicating or implying relative importance.
  • FIG. 1 is a schematic top view of an existing array substrate 100".
  • the array substrate 100" includes a plurality of gate lines (i.e. scanning lines) 121" extending along a first direction (the OX direction as shown in the figure), a plurality of common electrode lines 201" extending along the first direction and a plurality of source lines (i.e. data lines) 131" extending in a second direction (the OY direction as shown in the figure).
  • the plurality of gate lines 121" are in phase with the plurality of source lines 131" Intersect to define a plurality of pixel units 300" arranged in an array.
  • each pixel unit 300" includes a thin film transistor (Thin Film Transistor, TFT) 50", a pixel electrode layer 30" and a common electrode layer (not shown in the figure), the source 52" of the thin film transistor 50” is connected to the source line 131" nearby, the drain 53" of the thin film transistor 50” is connected to the pixel electrode layer 30", the gate 51" of the thin film transistor 50” is connected to the nearby gate line 121", and the common electrode layer is connected to the nearby gate line 121".
  • the common electrode lines 201" are connected. Since the gate lines 121", the source lines 131" and the common electrode lines 201" in the existing array substrate 100" each occupy a part of the wiring area, and they are all made of metal, which is opaque. In this way, the area of the pixel electrode layer 30" in each pixel unit 300" is small, resulting in a low aperture ratio of the pixel unit 300" in the array substrate 100".
  • the present application provides an array substrate 100, please refer to FIG. 2-FIG. 4 together.
  • the array substrate 100 provided in the present application arranges the common electrode lines 201 and the gate lines 121 on two opposite sides of the array substrate 100 respectively, and makes the projection of the gate lines 121 on the plane where the common electrode lines are located overlap at least partially with the common electrode lines, so as to reduce the wiring area on the array substrate 100, thereby increasing the area of the pixel electrode layer 30 in each pixel unit 300, thereby increasing the aperture ratio of the pixel unit 300.
  • the array substrate 100 includes a base substrate 10 , a stacked structure 200 , a common electrode line 201 and a conductive structure 40 .
  • the base substrate 10 has a first surface 110 and a second surface 120 opposite to each other.
  • the stacked structure 200 is disposed on the first surface 110 of the base substrate 10 , and the stacked structure 200 includes a contact pad 101 , a common electrode layer 20 and a gate line 121 .
  • the contact pad 101 is disposed on the first surface 110 of the base substrate 10 and connected to the common electrode layer 20 .
  • the gate line 121 is isolated from the common electrode layer 20 and the contact pad 101 respectively.
  • a first via hole 102 penetrating through the first surface 110 and the second surface 120 of the base substrate 10 is formed on the base substrate 10 at a position corresponding to the contact pad 101 .
  • the conductive structure 40 is connected to the contact pad 101 and connected to the common electrode line 201 through the first via hole 102 .
  • the shape of the first via hole 102 may be a circular hole, a square hole, or other shapes, which are not limited here.
  • the common electrode lines 201 are disposed on the second surface 120 of the base substrate 10 , and the orthographic projection of the gate lines 121 on the plane where the common electrode lines 201 are located overlaps at least partially with the common electrode lines 201 .
  • the orthographic projection of the gate line 121 on the plane where the common electrode line 201 is located completely covers the common electrode line 201 .
  • the gate lines 121 include a plurality of gate lines 121 extending along the first direction
  • the common electrode lines 201 include a plurality of common electrode lines 201 extending in the first direction
  • the plurality of gate lines 121 correspond to the plurality of common electrode lines 201 one by one.
  • the overlapping area of the gate line 121 and the common electrode line 201 is larger, the reduced wiring area on the first surface of the array substrate 100 is larger, which is more conducive to improving the aperture ratio of the pixel unit 300 .
  • the projection of each of the gate lines 121 on the plane where the common electrode lines 201 are located completely overlaps with each of the common electrode lines 201 . Since the wiring area on the common electrode line 201 accounts for about 10% of the pixel area in the existing array substrate, the array substrate 100 provided in this application can reduce the wiring area on the first surface 110 by 10%, increase the area of the pixel electrode layer 30 in each pixel unit 300 by 10%, and thus increase the aperture ratio of the pixel unit 300 by about 10%.
  • each of the pixel units 300 includes a contact pad 101 and a common electrode layer 20, and the base substrate 10 is formed with a first via hole 102 at a position corresponding to each of the contact pads 101, and each of the contact pads 101 is connected to each of the common electrode layers 20 in a one-to-one correspondence.
  • the base substrate 10 may be a hard substrate made of light-guiding and non-metallic materials with certain rigidity such as glass, quartz or public resin, or the base substrate 10 may also be a flexible substrate made of flexible materials such as polyimide (Polyimide, PI).
  • the material of the common electrode layer 20 may be metal oxides such as indium tin oxide (Indium Tin Oxide, ITO) and indium zinc oxide (Indium Zinc Oxide, IZO).
  • the conductive structure 40 can be formed by silver paste printing process.
  • the materials of the common electrode lines 201 , the gate lines 121 and the contact pads 101 may be the same or different, and are preferably conductive metals, such as at least one of molybdenum, aluminum, chromium, tungsten, tantalum, titanium, and copper.
  • the array substrate 100 provided in the present application can reduce the wiring area on the first surface 110 of the array substrate 100 by arranging the gate lines 121 and the common electrode lines 201 on the opposite first surface 110 and second surface 120 of the array substrate 100 respectively, and at least partially overlap the gate lines 121 and the common electrode lines 201 , thereby increasing the area of the pixel electrode layer 30 in each pixel unit 300 , thereby increasing the aperture ratio of the pixel unit 300 .
  • the number of layered structures included in the layered structure 200 and the positional relationship between layers of layered structures can be designed according to requirements, which are not limited in this application.
  • the gate line 121 in the stacked structure 200 is located at the same layer as the contact pad 101 , and both are disposed on the first surface 110 of the base substrate 10 .
  • the stacked structure 200 further includes a first insulating layer 11 , a drain-source layer, an active layer 54 , a second insulating layer 12 , a third insulating layer 13 and a pixel electrode layer 30 .
  • the gate line 121 is located at the same layer as the gate 51 .
  • the first insulating layer 11 covers the gate line 121 , the gate 51 and the contact pad 101 at the same time.
  • the source and drain layers and the active layer 54 are disposed on the first insulating layer 11 .
  • the drain-source layer includes a source 52 and a drain 53 , and the gate 51 , the source 52 , the drain 53 and the active layer 54 in the same pixel unit 300 together constitute a thin film transistor 50 .
  • the second insulating layer 12 covers both the source and drain layers and the active layer 54 .
  • the common electrode layer 20 is disposed on the second insulating layer 12 .
  • the third insulating layer 13 covers the common electrode layer 20 .
  • the pixel electrode layer 30 is disposed on the third insulating layer 13 . Exemplarily, the orthographic projections of the pixel electrode layer 30 and the common electrode layer 20 on the base substrate 10 overlap.
  • first insulating layer 11 and the second insulating layer 12 are formed with second via holes 122 corresponding to the positions of the contact pads 101 , and the common electrode layer 20 is connected to the contact pads 101 through the second via holes 122 .
  • each of the first insulating layer 11 and the second insulating layer 12 in each of the pixel units 300 is formed with one second via hole 122, and each of the common electrode layers 20 is connected to each of the contact pads 101 in a one-to-one correspondence through the corresponding second via hole 122.
  • the common electrode layer 20 ′ and the contact pad 101 ′ are located on the same layer, are connected to each other, and are both disposed on the first surface 110 ′ of the base substrate 10 ′.
  • the stacked structure 200' further includes a first insulating layer 11', a second insulating layer 12', a drain source layer, an active layer 54', a third insulating layer 13' and a pixel electrode layer 30'.
  • the first insulating layer 11' covers both the contact pad 101' and the common electrode layer 20'.
  • the gate line 121 ′ is located on the same layer as the gate 51 ′, and both are disposed on the first insulating layer 11 ′.
  • the second insulating layer 12' covers the gate line 121' and the gate 51'.
  • the drain-source layer is disposed on the second insulating layer 12', the drain-source layer includes a source 52' and a drain 53', and the gate 51', source 52', drain 53' and active layer 54' in the same pixel unit 300 together form a thin film transistor 50'.
  • the third insulating layer 13' covers the drain-source layer, and the pixel electrode layer 30' is disposed on the third insulating layer 13'.
  • the embodiment of the present application also provides a method for manufacturing an array substrate, as shown in FIG. 7 , the method includes the following steps:
  • the base substrate 10 has a first surface 110 and a second surface 120 opposite to each other.
  • the base substrate 10 may be a hard substrate made of light-guiding and non-metallic materials with certain rigidity such as glass, quartz or public resin, or the base substrate 10 may also be a flexible substrate made of flexible materials such as polyimide (Polyimide, PI).
  • Step 72 forming a stacked structure 200 on the first surface 110 of the base substrate 10 .
  • the stacked structure 200 includes a contact pad 101, a common electrode layer 20 and a gate line 121, the contact pad 101 is formed on the first surface 110 of the substrate 10, the common electrode layer 20 is connected to the contact pad 101, and the gate line 121 is isolated from the common electrode layer 20 and the contact pad 101 respectively.
  • Step 73 forming a first via hole 102 penetrating through the first surface 110 and the second surface 120 of the base substrate 10 at a position corresponding to the contact pad 101 on the base substrate 10 , the first via hole 102 exposing the contact pad 101 .
  • the shape of the first via hole 102 may be a circular hole, a square hole, or other shapes, which are not limited here. Since the area of a single pixel unit 300 is small, the size of the first via hole 102 needs to be controlled within a certain range. Preferably, the first via hole 102 is a circular hole with a diameter of about 10um, or a square hole with a side length of about 10um.
  • HF and O2 can be used to etch the glass (SiO2), and the first via hole 102 is formed by a cyclic dry etching process.
  • the cyclic dry etching process belongs to the prior art and will not be repeated here.
  • the base substrate 10 is made of glass, the requirements for the cyclic dry etching process are relatively high, otherwise, the substrate may be broken.
  • the present application also proposes that the base substrate 10 is made of polyimide, so that the first via hole 102 can be formed through exposure and development, the process is relatively simple, and the substrate will not be broken.
  • a patterned mask cover the second surface 120 of the base substrate 10 with a patterned mask (Mask), and selectively irradiate the second surface 120 of the base substrate 10 with ultraviolet light, and then use a developer to remove the polyimide of the illuminated part or the polyimide of the non-irradiated part, so that the pattern on the mask plate is formed on the base substrate 10, that is, the first via hole 102 is formed.
  • Step 74 forming common electrode lines 201 on the second surface 120 of the base substrate 10 , so that the orthographic projection of the gate lines 121 on the plane where the common electrode lines 201 are located overlaps at least partially with the common electrode lines 201 .
  • the common electrode lines 201 can be formed through one patterning process.
  • a plurality of common electrode lines 201 corresponding to the plurality of gate lines 121 are formed on the second surface 120 of the base substrate 10 through one patterning process, wherein the orthographic projections of the plurality of gate lines 121 on the plane where the common electrode lines 201 are located completely cover the plurality of common electrode lines 201, or, the orthographic projections of the plurality of common electrode lines 201 on the plane where the gate lines 121 are located completely cover the plurality of gate lines 121.
  • the "patterning process” mentioned in the embodiments of the present application includes the process of depositing a film layer, coating photoresist, mask exposure, developing, etching and stripping photoresist.
  • the deposition can be any one or more selected from sputtering, evaporation, and chemical vapor deposition
  • the coating can be used any one or more selected from spray coating and spin coating
  • the etching can be used any one or more selected from dry etching and wet etching.
  • Step 75 forming a conductive structure 40 in the first via hole 102 and a predetermined position on the second surface 120 of the base substrate 10, so that the contact pad 101 is connected to the common electrode line 201 near the first via hole 102 through the conductive structure 40.
  • the conductive structure 40 may be formed by a silver paste printing process, so that the contact pad 101 in each of the pixel units 300 is connected to the nearby common electrode line 201 through the corresponding first via hole 102 .
  • step 74 may be performed first, then step 73 is performed, and step 75 is finally performed.
  • step 73 may be performed first, then step 75 is performed, and step 74 is finally performed.
  • the step 72 specifically includes:
  • Step 721 forming the contact pad 101 and the gate line 121 on the first surface 110 of the base substrate 10 .
  • a gate 51 is further formed on the first surface 110 of the base substrate 10 .
  • the material of the contact pad 101 , the gate line 121 and the gate 51 is the same, and can be formed by one patterning process.
  • one contact pad 101 is formed in each of the pixel units 300 .
  • Step 722 forming a first insulating layer 11 on the contact pad 101 and the gate line 121 .
  • the first insulating layer 11 also covers the gate 51 .
  • the first insulating layer 11 may be made of materials such as silicon nitride, silicon oxide, or silicon oxynitride.
  • Step 723 forming a second insulating layer 12 on the first insulating layer 11 .
  • the step 723 specifically includes:
  • Step 723 a forming a drain-source layer and an active layer 54 on the first insulating layer 11 .
  • the active layer 54 can be a semiconductor active layer or an oxide active layer, for example, the active layer 54 is a semiconductor active layer made of semiconductor materials such as amorphous silicon or polycrystalline silicon.
  • the active layer 54 can be formed through one patterning process, and the drain and source layer can be formed through another patterning process.
  • Step 723b forming a second insulating layer 12 on the drain-source layer and the active layer 54 .
  • the second insulating layer 12 may be made of materials such as silicon nitride, silicon oxide, or silicon oxynitride.
  • Step 724 forming a second via hole 122 at the position of the first insulating layer and the second insulating layer 12 corresponding to the contact pad 101 , and the second via hole 122 exposes the contact pad 101 .
  • one second via hole 122 is formed in each of the first insulating layer and the second insulating layer 12 in each of the pixel units 300 .
  • Step 725 forming the common electrode layer 20 on the second insulating layer 12 and in the second via hole, so that the common electrode layer 20 is connected to the contact pad 101 through the second via hole. Specifically, the common electrode layer 20 in each of the pixel units 300 is connected to the corresponding contact pad 101 through the second via hole 122 .
  • the wiring area on the first surface 110 of the array substrate 100 can be reduced, thereby increasing the area of the pixel electrode layer 30 in each pixel unit 300 , thereby increasing the aperture ratio of the pixel unit 300 .
  • the present application also provides a display panel 1 , the display panel 1 includes a color filter substrate 600 , the above-mentioned array substrate 100 , and a sealant 500 , and the array substrate 100 is arranged opposite to the color filter substrate 600 .
  • the display panel 1 further includes a liquid crystal layer (not shown) filled between the color filter substrate 600 and the array substrate 100 , the sealant 500 is arranged around the liquid crystal layer, and the sealant 500 is used to seal the liquid crystal layer between the array substrate 100 and the color filter substrate 600 .
  • the display panel 1 may also include other structures, for example, a lower polarizer (not shown in the figure), an upper polarizer (not shown in the figure), etc., which are not limited here.
  • the display panel 1 may be a thin film transistor liquid crystal display panel (thin film transistor liquid crystal display, TFT-LCD) with various liquid crystal driving and display modes, including but not limited to twisted nematic (twisted nematic, TN) panels, vertical alignment (vertical alignment, VA) panels, in-plane switching (in-plane switching, IPS) panels, and the like.
  • TFT-LCD thin film transistor liquid crystal display
  • various liquid crystal driving and display modes including but not limited to twisted nematic (twisted nematic, TN) panels, vertical alignment (vertical alignment, VA) panels, in-plane switching (in-plane switching, IPS) panels, and the like.
  • the present application also provides a display device (not shown in the figure), which includes the above-mentioned display panel 1 .

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请提供一种阵列基板及其制作方法、显示面板和显示装置。阵列基板(100、100')中的层叠结构(200、200')包括接触垫(101、101')、公共电极层(20、20')以及栅极线(121、121')。接触垫(101、101')设置于衬底基板(10、10')的第一表面。阵列基板(100、100')中的公共电极线(201、201')设置于衬底基板(10、10')的第二表面，栅极线(121、121')在公共电极线(201、201')所在平面上的正投影与公共电极线(201、201')至少部分重叠，可以缩减阵列基板(100、100')的布线面积、提升开口率。

Description

阵列基板及其制作方法、显示面板和显示装置
本申请要求于2022年01月21日提交中国专利局、申请号为202210072612.6，申请名称为“阵列基板及其制作方法、显示面板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示面板领域，尤其涉及一种阵列基板及其制作方法、显示面板和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然构成现有技术。随着科技的发展和进步，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)是市场上应用最为广泛的显示器，特别是广泛应用在液晶电视上。
目前，薄膜晶体管液晶显示面板包含数据线(Data Line,DL)/源极线、扫描线(Scan line，SL)/栅极线、公共电极线、薄膜晶体管。现有的薄膜晶体管液晶显示面板中，扫描线和数据线相互垂直设置，公共电极线和扫描线相互平行间隔设置，由于各种信号线传导的信号不同，彼此之间需要相互隔离，并且各种信号线都为金属材质，具有不透光性，如此，造成像素的开口率较低，从而导致显示面板的显示亮度较低。
申请内容
本申请提供一种阵列基板，所述阵列基板包括衬底基板、层叠结构、公共电极线以及导电结构。所述衬底基板具有相对设置的第一表面和第二表面。所述层叠结构设置于所述衬底基板的第一表面上，所述层叠结构包括接触垫、公共电极层以及栅极线。其中，所述接触垫设置于所述衬底基板的第一表面上。所述衬底基板上对应于所述接触垫的位置形成有贯穿所述衬底基板的第一表面和第二表面的第一过孔。所述公共电极层与所述接触垫连接。所述栅极线分别与所述公共电极层、所述接触垫相互隔离。所述公共电极线设置于所述衬底基板的第二表面上，所述栅极线在所述公共电极线所在平面上的正投影与所述公共电极线至少部分重叠。所述导电结构与所述接触垫连接，并穿过所述第一过孔与所述公共电极线连接。
本申请提供的所述阵列基板通过将栅极线、公共电极线分别设置在所述阵列基板相对的第一表面和第二表面上，并使所述栅极线与所述公共电极线至少部分重叠，可以缩减所述阵列基板第一表面上的布线面积，从而增大各个像素单元中像素电极层的面积，进而提升所述像素单元的开口率。
本申请还提供一种显示面板，所述显示面板包括彩膜基板以及阵列基板，所述阵列基板与所述彩膜基板正对设置。其中，所述阵列基板包括衬底基板、层叠结构、公共电极线以及导电结构。所述衬底基板具有相对设置的第一表面和第二表面。所述层叠结构设置于所述衬底基板的第一表面上，所述层叠结构包括接触垫、公共电极层以及栅极线。其中，所述接触垫设置于所述衬底基板的第一表面上。所述衬底基板上对应于所述接触垫的位置形成有贯穿所述衬底基板的第一表面和第二表面的第一过孔。所述公共电极层与所述接触垫连接。所述栅极线分别与所述公共电极层、所述接触垫相互隔离。所述公共电极线设置于所述衬底基板的第二表面上，所述栅极线在所述公共电极线所在平面上的正投影与所述公共电极线至少部分重叠。所述导电结构与所述接触垫连接，并穿过所述第一过孔与所述公共电极线连接。
本申请的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显， 或通过本申请的实践了解到。
附图说明
图1是现有的阵列基板的俯视结构示意图。
图2是本申请实施例提供的一种阵列基板的俯视结构示意图。
图3是图2所示的结构沿切线A-A的一种剖面结构示意图。
图4是图2中阵列基板的另一剖面结构示意图。
图5是图2所示的结构沿切线A-A的另一种剖面结构示意图。
图6是图2中阵列基板的又一种剖面结构示意图。
图7是本申请实施例提供的阵列基板的制作方法的流程示意图。
图8是图7中步骤72的细化流程图。
图9是本申请实施例提供的一种显示面板的结构示意图。
如下具体实施方式将结合上述附图进一步说明本申请。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有付出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“上”、“下”、“左”、“右”等指示的方位或者位置关系为基于附图所示的方位或者位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性。
请参阅图1，图1是现有的阵列基板100"的俯视结构示意图。所述阵列基板100"包括沿第一方向(如图所示的OX方向)延伸的多条栅极线(即扫描线)121"、沿所述第一方向延伸的多条公共电极线201"以及沿第二方向(如图所示的OY方向)延伸的多条源极线(即数据线)131"。多条所述栅极线121"与多条所述源极线131"相交，定义出多个阵列排布的像素单元300"。其中，各个所述像素单元300"均包括薄膜晶体管(Thin Film Transistor，TFT)50"、像素电极层30"以及公共电极层(图中未示)，所述薄膜晶体管50"的源极52"与其附近的源极线131"连接，所述薄膜晶体管50"的漏极53"与所述像素电极层30"连接，所述薄膜晶体管50"的栅极51"与其附近的栅极线121"连接，所述公共电极层与附近的公共电极线201"连接。由于现有的阵列基板100"中的所述栅极线121"、所述源极线131"以及所述公共电极线201"各占据了一部分的布线面积，并且都为金属材质，具有不透光性，如此，造成各个像素单元300"中的像素电极层30"的面积较小，从而导致所述阵列基板100"中的像素单元300"的开口率较低。
为解决现有的阵列基板中的像素单元的开口率低的问题，本申请提供一种阵列基板100，请一同参阅图2-图4。本申请提供的所述阵列基板100通过将公共电极线201、栅极线121分别设置在所述阵列基板100相对的两面，并使所述栅极线121在所述公共电极线所在平面上的投影与所述公共电极线至少部分重叠，以缩减所述阵列基板100上的布线面积，从而增大各个像素单元300中像素电极层30的面积，进而提升所述像素单元300的开口率。
具体地，请参阅图3，所述阵列基板100包括衬底基板10、层叠结构200、公共电极线201以及导电结构40。其中，所述衬底基板10具有相对设置的第一表面110和第二表面120。
所述层叠结构200设置于所述衬底基板10的第一表面110上，所述层叠结构200包括接触垫101、公共电极层20以及栅极线121。所述接触垫101设置于所述衬底基板10的第一表面110上，且与所述公共电极层20连接。所述栅极线121分别与所述公共电极层20、所述接触垫101相互隔离。所述衬底基板10上对应于所述接触垫101的位置形成有贯穿所述衬底基板10的第一表面110和第二表面120的第一过孔102。所述导电结构40与所述接触垫101连接，并穿过所述第一过孔102与所述公共电极线201连接。所述第一过孔102的形状可以是圆形孔，也可以是方形孔，也可以是其他形状，此处不作限定。
所述公共电极线201设置于所述衬底基板10的第二表面120上，所述栅极线121在所述公共电极线201所在平面上的正投影与所述公共电极线201至少部分重叠。在本申请实施例中，所述栅极线121在所述公共电极线201所在平面上的正投影完全覆盖所述公共电极线201。具体地，所述栅极线121包括沿所述第一方向延伸的多条栅极线121，所述公共电极线201包括沿所述第一方向延伸的多条公共电极线201，多条所述栅极线121与多条所述公共电极线201一一对应。可以理解的是，当所述栅极线121与所述公共电极线201重叠的面积越大，所述阵列基板100的第一表面缩减的布线面积越大，越有利于提升所述像素单元300的开口率。优选地，各条所述栅极线121在所述公共电极线201所在平面上的投影与各条所述公共电极线201完全重叠。由于现有的阵列基板中，所述公共电极线201上的布线面积约占像素面积的10％，因此，采用本申请提供的所述阵列基板100，可以将所述第一表面110上的布线面积缩减10％，将各个所述像素单元300中的像素电极层30的面积增加10％，从而可以将所述像素单元300的开口率提升10％左右。
需要说明的是，在本申请实施例中，各个所述像素单元300均包括一个所述接触垫101与一公共电极层20，所述衬底基板10在对应于各个所述接触垫101的位置均形成有一个所述第一过孔102，各个所述接触垫101与各公共电极层20一一对应连接。
示例性地，所述衬底基板10可以为玻璃、石英或公共树脂等具有一定坚固性的导光且非金属材料制成的硬质基板，或者，所述衬底基板10也可以为采用聚酰亚胺(Polyimide，PI)等柔性材料制成的柔性基板。所述公共电极层20的材料可以为氧化铟锡(Indium Tin Oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)等金属氧化物。所述导电结构40可以通过银浆印刷工艺形成。所述公共电极线201、所述栅极线121以及所述接触垫101的材质可以相同，也可以不同，优选为导电金属，例如，为钼、铝、铬、钨、钽、钛、铜中的至少一种。
本申请提供的阵列基板100，通过将栅极线121、公共电极线201分别设置在所述阵列基板100相对的第一表面110和第二表面120上，并使所述栅极线121与所述公共电极线201至少部分重叠，可减少所述阵列基板100第一表面110上的布线面积，从而增大各个像素单元300中像素电极层30的面积，进而提升所述像素单元300的开口率。
需要说明的是，所述层叠结构200所包含的层状结构的数量以及各层层状结构之间的位置关系可以根据需求进行相应的设计，本申请不作限定。
示例性地，在一种实施例中，如图3-图4所示，所述层叠结构200中的栅极线121与所述接触垫101位于同一层，且均设置于所述衬底基板10的第一表面110上。所述层叠结构200还包括第一绝缘层11、漏源极层、有源层54、第二绝缘层12、第三绝缘层13以及像素电极层30。
具体地，所述栅极线121与栅极51位于同一层。所述第一绝缘层11同时覆盖所述栅极线121、所述栅极51和所述接触垫101。所述源漏极层和所述有源层54设置于所述第一绝缘层11上。所述漏源极层包括源极52和漏极53，同一像素单元300中的栅极51、源极52、漏极53以及有源层54共同构成一个所述薄膜晶体管50。所述第二绝缘层12同时覆盖所述源漏极层以及所述有源层54。所述公共电极层20设置于所述第二绝缘层12上。所述第三绝缘层13覆盖所述公共电极层20。所述像素电极层30设置于所述第三绝缘层13上。示例性地，所述像素电极层30和所述公共电极层20在所述衬底基板10上的正投影重叠。
进一步地，所述第一绝缘层11和所述第二绝缘层12对应于所述接触垫101的位置形成有第二过孔122，所述公共电极层20通过所述第二过孔122与所述接触垫101连接。具体地，在本申请实施例中，各个所述像素单元300中的第一绝缘层11和第二绝缘层12均形成有一个所述第二过孔122，各所述公共电极层20均通过对应的第二过孔122与各个所述接触垫101一一对应连接。
在另一种实施例中，如图5-图6所示，所述公共电极层20'与所述接触垫101'位于同一层，并相互连接，且均设置于所述衬底基板10'的第一表面110'上。所述层叠结构200'还包括第一绝缘层11'、第二绝缘层12'、漏源极层、有源层54'、第三绝缘层13'以及像素电极层30'。
具体地，所述第一绝缘层11'同时覆盖所述接触垫101'以及所述公共电极层20'。所述栅极线121'与栅极51'位于同一层，且均设置于所述第一绝缘层11'上。所述第二绝缘层12'覆盖所述栅极线121'和所述栅极51'。所述漏源极层设置于所述第二绝缘层12'上，所述漏源极层包括源极52'和漏极53'，同一像素单元300中的栅极51'、源极52'、漏极53'以及有源层54'共同构成一个所述薄膜晶体管50'。所述第三绝缘层13'覆盖所述漏源极层，所述像素电极层30'设置于所述第三绝缘层13'上。
基于同样的发明构思，本申请实施例还提供一种阵列基板的制作方法，如图7所示，所述方法包括以下步骤：
步骤71，提供衬底基板10。所述衬底基板10具有相对设置的第一表面110和第二表面120。示例性地，所述衬底基板10可以为玻璃、石英或公共树脂等具有一定坚固性的导光且非金属材料制成的硬质基板，或者，所述衬底基板10也可以为采用聚酰亚胺(Polyimide，PI)等柔性材料制成的柔性基板。
步骤72，在所述衬底基板10的第一表面110上形成层叠结构200。其中，所述层叠结构200包括接触垫101、公共电极层20以及栅极线121，所述接触垫101形成于所述衬底基板10的第一表面110上，所述公共电极层20与所述接触垫101连接，所述栅极线121分别与所述公共电极层20、所述接触垫101相互隔离。
步骤73，在所述衬底基板10上对应于所述接触垫101的位置形成贯穿所述衬底基板10的第一表面110和第二表面120的第一过孔102，所述第一过孔102暴露出所述接触垫101。
需要说明的是，所述第一过孔102的形状可以是圆形孔，也可以是方形孔，也可以是其他形状，此处不作限定。由于单个所述像素单元300的面积较小，所述第一过孔102的大小需要控制在一定范围，优选地，所述第一过孔102是直径为10um左右的圆形孔，或者是边长为10um左右的方形孔。当所述衬底基板10为玻璃材质时，可以利用HF和O2对玻璃(SiO2)进行刻蚀，通过循环干法刻蚀工艺形成所述第一过孔102，所述循环干法刻蚀工艺属于现有技术，此处不再进行赘述。由于每个所述像素单元300内均形成有一个所述第一过孔102，因此所述衬底基板10上的第一过孔102的数量较多且排布密集，当所述衬底基板10为玻璃 材质时，对循环干法刻蚀工艺的要求较高，否则，可能造成基板碎裂。本申请还提出将所述衬底基板10选为聚酰亚胺材质，如此，可以通过曝光、显影的方式形成所述第一过孔102，工艺相对简单，且不会出现基板碎裂的情况。具体地，用带有图案的掩膜板(Mask)覆盖所述衬底基板10的第二表面120，并对所述衬底基板10的第二表面120进行选择性紫外线照射，再用显影液除去受到光照的部分的聚酰亚胺或未被光照的部分的聚酰亚胺，使所述衬底基板10上形成所述掩膜板上的图案，即形成所述第一过孔102。
步骤74，在所述衬底基板10的第二表面120上形成公共电极线201，使得所述栅极线121在所述公共电极线201所在平面上的正投影与所述公共电极线201至少部分重叠。在本申请实施例中。示例性地，所述公共电极线201可以通过一次构图工艺形成。具体地，通过一次构图工艺在所述衬底基板10的第二表面120上形成与多条所述栅极线121一一对应的多条公共电极线201，其中，多条所述栅极线121在所述公共电极线201所在平面上的正投影完全覆盖多条所述公共电极线201，或者，多条所述公共电极线201在所述栅极线121所在平面上的正投影完全覆盖多条所述栅极线121。
本申请实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理流程。沉积可以采用选自溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。以上各个处理流程均属于现有技术，此处不再进行赘述。
步骤75，在所述第一过孔102中以及所述衬底基板10的第二表面120上的预设部位形成导电结构40，使得所述接触垫101通过所述导电结构40与所述第一过孔102附近的所述公共电极线201连接。示例性地，可以通过银浆印刷工艺形成所述导电结构40，以使得每个所述像素单元300中的所述接触垫101通过对应的所述第一过孔102与附近的所述公共电极线201连接。
需要说明的是，本申请不对所述步骤73-步骤75的执行顺序进行限定，只要步骤75在步骤73之后就可以。在另一种实施例中，可以先执行步骤74，再执行步骤73，最后执行步骤75。在又一种实施例中，也可以先执行步骤73，再执行步骤75，最后执行步骤74。
如前文所述，所述层叠结构200所包含的层状结构的数量以及各层层状结构之间的位置关系可以根据需求进行相应的设计，所述步骤72中的具体流程与所述层叠结构200的特征相对应，此处不作限定。示例性地，在一种实施例中，如图8所示，所述步骤72具体包括：
步骤721，在所述衬底基板10的第一表面110上形成所述接触垫101和所述栅极线121。在本实施例中，在所述衬底基板10的第一表面110上还形成有栅极51。示例性地，所述接触垫101、所述栅极线121以及所述栅极51的材质相同，可以通过一次构图工艺形成。具体地，各个所述像素单元300中均形成有一所述接触垫101。
步骤722，在所述接触垫101和所述栅极线121上形成第一绝缘层11。在本实施例中，所述第一绝缘层11还覆盖所述栅极51。示例性地，所述第一绝缘层11可以采用氮化硅、氧化硅或氮氧化硅等材料。
步骤723，在所述第一绝缘层11上形成第二绝缘层12。
在本申请实施例中，所述步骤723具体包括：
步骤723a，在所述第一绝缘层11上形成漏源极层和有源层54。所述有源层54可以为半导体有源层或氧化物有源层，例如，所述有源层54为采用非晶硅或多晶硅等半导体材料制成 的半导体有源层。示例性地，所述有源层54可以通过一次构图工艺形成，所述漏源极层可以通过另一次构图工艺形成。
步骤723b，在所述漏源极层和所述有源层54上形成第二绝缘层12。示例性地，所述第二绝缘层12可以采用氮化硅、氧化硅或氮氧化硅等材料。
步骤724，在所述第一绝缘层和所述第二绝缘层12对应于所述接触垫101的位置形成第二过孔122，所述第二过孔122暴露出所述接触垫101。具体地，各个所述像素单元300中的第一绝缘层和第二绝缘层12均形成有一个所述第二过孔122。
步骤725，在所述第二绝缘层12上和所述第二过孔中形成所述公共电极层20，使得所述公共电极层20通过所述第二过孔与所述接触垫101连接。具体地，各个所述像素单元300中的所述公共电极层20通过所述第二过孔122与对应的接触垫101连接。
本申请提供的阵列基板的制作方法，通过将栅极线121、公共电极线201分别形成于所述阵列基板100相对的第一表面110和第二表面120上，并使所述栅极线121与所述公共电极线201至少部分重叠，可以减少所述阵列基板100第一表面110上的布线面积，从而增大各个像素单元300中像素电极层30的面积，进而提升所述像素单元300的开口率。
基于同样的发明构思，请参阅图9，本申请还提供一种显示面板1，所述显示面板1包括彩膜基板600、上述的阵列基板100以及封框胶500，所述阵列基板100与所述彩膜基板600正对设置。所述显示面板1还包括填充于所述彩膜基板600和所述阵列基板100之间的液晶层(图中未示)，所述封框胶500环绕设置于所述液晶层四周，所述封框胶500用于将所述液晶层封闭在所述阵列基板100和所述彩膜基板600之间。当然，所述显示面板1还可以包括其他结构，例如，下偏光板(图中未示)、上偏光板(图中未示)等等，此处不作限制。
示例性地，所述显示面板1可以为各种液晶驱动和显示模式的薄膜晶体管液晶显示面板(thin film transistor liquid crystal display，TFT-LCD)，包括但不限于扭曲向列型(twisted nematic，TN)面板、垂直配向型(vertical alignment，VA)面板、平面转换型(in-plane switching，IPS)面板等。
基于同样的发明构思，本申请还提供一种显示装置(图中未示)，所述显示装置包括上述的显示面板1。
尽管已经示出和描述了本申请的实施例，本领域的普通技术人员可以理解：在不脱离本申请的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本申请的范围由权利要求及其等同物限定。

Claims (12)

  1. 一种阵列基板，所述阵列基板包括：
    衬底基板，具有相对设置的第一表面和第二表面；以及
    层叠结构，设置于所述衬底基板的第一表面上；
    其中，所述层叠结构包括：
    接触垫，设置于所述衬底基板的第一表面上；所述衬底基板上对应于所述接触垫的位置形成有贯穿所述衬底基板的第一表面和第二表面的第一过孔；
    公共电极层，与所述接触垫连接；以及
    栅极线，分别与所述公共电极层、所述接触垫相互隔离；
    所述阵列基板还包括：
    公共电极线，设置于所述衬底基板的第二表面上，所述栅极线在所述公共电极线所在平面上的正投影与所述公共电极线至少部分重叠；以及
    导电结构，与所述接触垫连接，并穿过所述第一过孔与所述公共电极线连接。
  2. 如权利要求1所述阵列基板，其中，所述层叠结构中的栅极线与所述接触垫位于同一层，且均设置于所述衬底基板的第一表面上；
    所述层叠结构还包括：
    第一绝缘层，同时覆盖所述栅极线和所述接触垫；以及
    第二绝缘层，设置于所述第一绝缘层上；
    所述公共电极层设置于所述第二绝缘层上；所述第一绝缘层和所述第二绝缘层对应于所述接触垫的位置形成有第二过孔，所述公共电极层通过所述第二过孔与所述接触垫连接。
  3. 如权利要求1所述的阵列基板，其中，所述层叠结构中的公共电极层与所述接触垫位于同一层，且均设置于所述衬底基板的第一表面上；
    所述层叠结构还包括第一绝缘层，所述第一绝缘层同时覆盖所述公共电极层和所述接触垫；
    所述栅极线设置于所述第一绝缘层上。
  4. 如权利要求1所述的阵列基板，其中，所述栅极线在所述公共电极线所在平面上的正投影完全覆盖所述公共电极线。
  5. 如权利要求1所述的阵列基板，其中，所述公共电极线在所述栅极线所在平面上的正投影完全覆盖所述栅极线。
  6. 如权利要求1所述阵列基板，其中，所述衬底基板的材质为玻璃或聚酰亚胺。
  7. 一种阵列基板的制作方法，其中，所述方法包括：
    提供衬底基板，所述衬底基板具有相对设置的第一表面和第二表面；
    在所述衬底基板的第一表面上形成层叠结构；其中，所述层叠结构包括接触垫、公共电极层以及栅极线，所述接触垫形成于所述衬底基板的第一表面上，所述公共电极层与所述接触垫连接，所述栅极线分别与所述公共电极层、所述接触垫相互隔离；
    在所述衬底基板上对应于所述接触垫的位置形成贯穿所述衬底基板的第一表面和第二表面的第一过孔；
    在所述衬底基板的第二表面上形成公共电极线，使得所述栅极线在所述公共电极线所在平面上的正投影与所述公共电极线至少部分重叠；以及
    在所述第一过孔中以及所述衬底基板的第二表面上的预设部位形成导电结构，使得所述接触垫通过所述导电结构与所述第一过孔附近的所述公共电极线连接。
  8. 如权利要求7所述的制作方法，其中，所述在所述衬底基板的第一表面上形成层叠结构，具体包括：
    在所述衬底基板的第一表面上形成所述接触垫和所述栅极线；
    在所述接触垫和所述栅极线上形成第一绝缘层；
    在所述第一绝缘层上形成第二绝缘层；
    在所述第一绝缘层和所述第二绝缘层对应于所述接触垫的位置形成第二过孔；以及
    在所述第二绝缘层上和所述第二过孔中形成所述公共电极层，使得所述公共电极层通过所述第二过孔与所述接触垫连接。
  9. 如权利要求8所述的制作方法，其中，所述在所述衬底基板的第二表面上形成公共电极线，具体包括：
    在所述衬底基板的第二表面上形成与所述栅极线的对应的公共电极线；其中，所述栅极线在所述公共电极线所在平面上的正投影完全覆盖所述公共电极线。
  10. 如权利要求8所述的制作方法，其中，所述在所述衬底基板的第二表面上形成公共电极线，具体包括：
    在所述衬底基板的第二表面上形成与所述栅极线的对应的公共电极线；其中，所述公共电极线在所述栅极线所在平面上的正投影完全覆盖所述栅极线。
  11. 一种显示面板，包括：
    彩膜基板；以及
    阵列基板，所述阵列基板与所述彩膜基板正对设置；
    所述阵列基板包括：
    衬底基板，具有相对设置的第一表面和第二表面；以及
    层叠结构，设置于所述衬底基板的第一表面上；
    其中，所述层叠结构包括：
    接触垫，设置于所述衬底基板的第一表面上；所述衬底基板上对应于所述接触垫的位置形成有贯穿所述衬底基板的第一表面和第二表面的第一过孔；
    公共电极层，与所述接触垫连接；以及
    栅极线，分别与所述公共电极层、所述接触垫相互隔离；
    所述阵列基板还包括：
    公共电极线，设置于所述衬底基板的第二表面上，所述栅极线在所述公共电极线所在平面上的正投影与所述公共电极线至少部分重叠；以及
    导电结构，与所述接触垫连接，并穿过所述第一过孔与所述公共电极线连接。
  12. 一种显示装置，所述显示装置包括显示面板；所述显示面板包括：
    彩膜基板；以及
    阵列基板，所述阵列基板与所述彩膜基板正对设置；
    所述阵列基板包括：
    衬底基板，具有相对设置的第一表面和第二表面；以及
    层叠结构，设置于所述衬底基板的第一表面上；
    其中，所述层叠结构包括：
    接触垫，设置于所述衬底基板的第一表面上；所述衬底基板上对应于所述接触垫的位置形成有贯穿所述衬底基板的第一表面和第二表面的第一过孔；
    公共电极层，与所述接触垫连接；以及
    栅极线，分别与所述公共电极层、所述接触垫相互隔离；
    所述阵列基板还包括：
    公共电极线，设置于所述衬底基板的第二表面上，所述栅极线在所述公共电极线所在平面上的正投影与所述公共电极线至少部分重叠；以及
    导电结构，与所述接触垫连接，并穿过所述第一过孔与所述公共电极线连接。
PCT/CN2022/141290 2022-01-21 2022-12-23 阵列基板及其制作方法、显示面板和显示装置 WO2023138299A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP22921720.3A EP4280280A1 (en) 2022-01-21 2022-12-23 Array substrate and method for manufacturing same, display panel, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210072612.6 2022-01-21
CN202210072612.6A CN114488636B (zh) 2022-01-21 2022-01-21 阵列基板及其制作方法、显示面板和显示装置

Publications (1)

Publication Number Publication Date
WO2023138299A1 true WO2023138299A1 (zh) 2023-07-27

Family

ID=81472993

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/141290 WO2023138299A1 (zh) 2022-01-21 2022-12-23 阵列基板及其制作方法、显示面板和显示装置

Country Status (4)

Country Link
US (1) US11721705B1 (zh)
EP (1) EP4280280A1 (zh)
CN (1) CN114488636B (zh)
WO (1) WO2023138299A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114488636B (zh) * 2022-01-21 2022-10-25 绵阳惠科光电科技有限公司 阵列基板及其制作方法、显示面板和显示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101517472A (zh) * 2006-09-19 2009-08-26 夏普株式会社 液晶显示装置
CN102967971A (zh) * 2012-11-02 2013-03-13 京东方科技集团股份有限公司 阵列基板以及显示装置
CN103474436A (zh) * 2013-09-18 2013-12-25 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN103499906A (zh) * 2013-10-15 2014-01-08 京东方科技集团股份有限公司 一种阵列基板、其制备方法及显示装置
CN105161495A (zh) * 2015-07-23 2015-12-16 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板
US20180012948A1 (en) * 2016-07-05 2018-01-11 Innolux Corporation Array substrate structure and display device
CN110412806A (zh) * 2019-08-05 2019-11-05 京东方科技集团股份有限公司 阵列基板及制作方法、显示面板及制作方法和显示装置
CN111128025A (zh) * 2019-12-30 2020-05-08 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
CN114488636A (zh) * 2022-01-21 2022-05-13 绵阳惠科光电科技有限公司 阵列基板及其制作方法、显示面板和显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104965336A (zh) * 2015-07-30 2015-10-07 深圳市华星光电技术有限公司 Coa阵列基板及液晶面板
CN105226068B (zh) * 2015-09-14 2018-01-26 京东方科技集团股份有限公司 一种双面显示基板及其制备方法和显示装置
US10241609B2 (en) * 2015-12-30 2019-03-26 Lg Display Co., Ltd. Display device with touch sensor
CN106409796A (zh) * 2016-10-25 2017-02-15 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置及其制作方法
CN109786391B (zh) * 2017-11-10 2021-08-03 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN113433745A (zh) * 2021-06-07 2021-09-24 深圳市华星光电半导体显示技术有限公司 显示面板及拼接显示屏

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101517472A (zh) * 2006-09-19 2009-08-26 夏普株式会社 液晶显示装置
CN102967971A (zh) * 2012-11-02 2013-03-13 京东方科技集团股份有限公司 阵列基板以及显示装置
CN103474436A (zh) * 2013-09-18 2013-12-25 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN103499906A (zh) * 2013-10-15 2014-01-08 京东方科技集团股份有限公司 一种阵列基板、其制备方法及显示装置
CN105161495A (zh) * 2015-07-23 2015-12-16 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板
US20180012948A1 (en) * 2016-07-05 2018-01-11 Innolux Corporation Array substrate structure and display device
CN110412806A (zh) * 2019-08-05 2019-11-05 京东方科技集团股份有限公司 阵列基板及制作方法、显示面板及制作方法和显示装置
CN111128025A (zh) * 2019-12-30 2020-05-08 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
CN114488636A (zh) * 2022-01-21 2022-05-13 绵阳惠科光电科技有限公司 阵列基板及其制作方法、显示面板和显示装置

Also Published As

Publication number Publication date
US11721705B1 (en) 2023-08-08
US20230238391A1 (en) 2023-07-27
CN114488636A (zh) 2022-05-13
CN114488636B (zh) 2022-10-25
EP4280280A1 (en) 2023-11-22

Similar Documents

Publication Publication Date Title
US8264652B2 (en) Liquid crystal display device with a data link connecting a data pad and data line
US7889304B2 (en) Liquid crystal display and fabricating method thereof
TWI440945B (zh) 用於邊緣場切換模式液晶顯示裝置之陣列基板及其製造方法
US7894032B2 (en) Liquid crystal display device having particular structure for data line, source electrode, drain electrode and pixel electrode
US7782436B2 (en) Liquid crystal display device
US7626206B2 (en) Liquid crystal display device and fabricating method thereof
US8013969B2 (en) Liquid crystal display device comprising a protective film so that the protective film borders with one end of a transparent conductive pattern
KR102012854B1 (ko) 액정표시장치용 어레이기판 및 그 제조방법
US8179510B2 (en) Liquid crystal display device and fabricating method thereof
US8405788B2 (en) TFT-LCD array substrate and manufacturing method thereof
US20070002249A1 (en) Liquid crystal display device and fabricating method thereof
US8400600B2 (en) Liquid crystal display device and fabricating method thereof
JP5007171B2 (ja) 薄膜トランジスタアレイ基板、その製造方法、及び表示装置
US20100165281A1 (en) Liquid crystal display device
US8817214B2 (en) Liquid crystal display and fabricating method thereof
US7485907B2 (en) Array substrate for liquid crystal display device and the seal pattern in the periphery of the display
WO2023138299A1 (zh) 阵列基板及其制作方法、显示面板和显示装置
US20090091675A1 (en) Liquid crystal display device and manufacturing method thereof
CN112578585B (zh) 显示面板及其制备方法、显示装置
WO2020082459A1 (zh) 一种显示面板的制作方法和显示面板
US7563655B2 (en) Method of fabricating the liquid crystal display device
JP2008076431A (ja) 表示装置およびその製造方法
CN114823782A (zh) 显示基板、其制作方法及显示装置
CN110426905A (zh) 彩膜阵列基板的制备方法及彩膜阵列基板
KR20070072115A (ko) 액정표시소자 및 그 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22921720

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022921720

Country of ref document: EP

Effective date: 20230817