WO2014112402A1 - Method for manufacturing electronic device - Google Patents

Method for manufacturing electronic device Download PDF

Info

Publication number
WO2014112402A1
WO2014112402A1 PCT/JP2014/050049 JP2014050049W WO2014112402A1 WO 2014112402 A1 WO2014112402 A1 WO 2014112402A1 JP 2014050049 W JP2014050049 W JP 2014050049W WO 2014112402 A1 WO2014112402 A1 WO 2014112402A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
electronic device
electrode pattern
ink
Prior art date
Application number
PCT/JP2014/050049
Other languages
French (fr)
Japanese (ja)
Inventor
水上　誠
慎也 奥
時任　静士
民徹 朱
鈴木　良和
Original Assignee
株式会社ブイ・テクノロジー
国立大学法人山形大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ブイ・テクノロジー, 国立大学法人山形大学 filed Critical 株式会社ブイ・テクノロジー
Priority to KR1020157019970A priority Critical patent/KR102051699B1/en
Priority to CN201480004865.3A priority patent/CN104919573B/en
Publication of WO2014112402A1 publication Critical patent/WO2014112402A1/en

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/48—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
    • C23C16/483—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation using coherent light, UV to IR, e.g. lasers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/047—Coating on selected surface areas, e.g. using masks using irradiation by energy or particles
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H10K71/611—Forming conductive regions or layers, e.g. electrodes using printing deposition, e.g. ink jet printing

Definitions

  • the present invention relates to the formation of electrodes in electronic devices such as diodes and transistors, and more particularly to a method for manufacturing an electronic device having an electrode pattern formed by a coating method.
  • electrode formation using printing has been performed as a method for reducing the cost of capital investment, enabling mass production, and offering low cost merit.
  • the printing method is expected as a technology in the green innovation field that is friendly to the global environment because it requires less raw materials and chemicals than photolithography.
  • a printing technique capable of dealing with a small variety of products is desired.
  • an ink jet method As a specific method for forming an electrode pattern by a printing method, there are various methods such as an ink jet method, letterpress printing, gravure printing, spray printing, slit coating method, and screen printing.
  • an effective printing method for fine wiring is an ink jet method, relief printing, and gravure printing.
  • letterpress printing and gravure printing are inferior in on-demand properties in that a plate is used.
  • the ink jet system which does not require a plate is excellent in on-demand characteristics.
  • FIG. 4 and 5 show conceptual diagrams when fine wiring is performed on a substrate by an ink jet method.
  • A shows the state of the ink immediately after the ink is dropped
  • (b) shows the state of the ink after evaporation
  • (c) shows the state of the ink after drying.
  • the line width is wider than the set width d.
  • FIG. 4 since the wettability of the substrate 11 to the ink 15 is high, the line width is wider than the set width d.
  • Patent Document 1 describes that the surface energy is changed by irradiating the wettability control layer with ultraviolet rays to control the range in which the ink spreads.
  • Japanese Patent Application Laid-Open No. H10-228561 describes using a phenomenon in which water repellent behavior occurs from a smooth surface by dropping ink onto a convex region in order to control the range in which the ink spreads.
  • the present invention has been made to solve the above technical problem, and provides a method of manufacturing an electronic device having an electrode pattern that can be formed on demand and can be formed on demand. It is intended to provide.
  • An electronic device manufacturing method includes a first layer having an electrode pattern shape on a substrate, made of a material different from the substrate and having a higher surface energy than the substrate, and an upper surface of the first layer.
  • the first layer is formed by a gas curtain laser CVD method. By using the gas curtain laser CVD method, a high-definition electrode pattern can be easily configured.
  • the method for manufacturing an electronic device includes a base layer made of a material different from the substrate, having a lower surface energy than the substrate, and an upper surface of the base layer.
  • An electrode pattern-shaped first layer made of a material different from the base layer and having a surface energy higher than that of the base layer, and a second layer formed of conductive nano ink on the top surface of the first layer.
  • the first layer is formed by a gas curtain laser CVD method.
  • the first layer is a material having a surface energy higher than the surface energy of the substrate or the underlayer, and is a metal, an oxide or a nitride thereof, or a mixture of two or more thereof, or an organic compound. It is formed by.
  • an electronic device in which a high-definition electrode pattern is formed on demand can be manufactured by a simple method without using a vacuum chamber or photolithography.
  • FIGS. 2A and 2B are conceptual cross-sectional views for explaining a process of forming the electrode pattern of FIG. It is a conceptual sectional view when fine wiring is performed on a substrate with high wettability by an ink jet method, (a) is immediately after ink dropping, (b) is during solvent evaporation, (c) is the state of ink after drying. Show.
  • An electronic device manufacturing method includes a first layer having an electrode pattern shape on a substrate, made of a material different from the substrate and having a higher surface energy than the substrate, and an upper surface of the first layer. And a method of manufacturing an electronic device including a second layer formed of conductive nano ink.
  • the first layer is formed by a gas curtain laser CVD method.
  • FIG. 1 shows a conceptual diagram of an electrode pattern structure of the above-described aspect of an electronic device according to the present invention.
  • a first layer 2 and a second layer 3 are formed on a substrate 1.
  • the first layer 2 is made of a material different from that of the substrate 1, has a surface energy higher than that of the substrate 1, and is formed in an electrode pattern shape.
  • the second layer 3 is formed of a conductive nano ink.
  • FIG. 3 is a conceptual diagram for explaining the process of forming the electrode pattern shown in FIG.
  • a first layer 2 having a surface energy higher than that of the substrate 1 is formed in an electrode pattern shape on the substrate 1.
  • a boundary surface having different surface energy is formed between the substrate 1 and the first layer 2.
  • the conductive nano ink 5 is dropped on the first layer 2, immediately after that, the ink spreads out from the width of the first layer 2 so as to partially contact the surface of the substrate 1 (FIG. 3 ( a)).
  • the solvent of the ink is evaporated, the conductive nano ink 5 is self-organized and stays gathered only on the upper surface of the first layer 2 having a high surface energy, and is prevented from spreading further (FIG.
  • the second layer 3 formed by drying the conductive nano ink 5 is formed only on the upper surface of the first layer 2, and a fine electrode pattern is formed with a width substantially equal to that of the first layer 2. be able to.
  • the method for manufacturing an electronic device includes a base layer made of a material different from the substrate, having a lower surface energy than the substrate, and an upper surface of the base layer.
  • An electrode pattern-shaped first layer made of a material different from the base layer and having a surface energy higher than that of the base layer, and a second layer formed of conductive nano ink on the top surface of the first layer. It is a manufacturing method of the provided electronic device. Also in this method, the first layer is formed by a gas curtain laser CVD method.
  • FIG. 2 the conceptual diagram of the electrode pattern structure of the said aspect of the electronic device which concerns on this invention is shown.
  • a base layer 4 is formed between the substrate 1 and the first layer 2.
  • the underlayer 4 is made of a material different from that of the substrate 1 and has a lower surface energy than that of the substrate 1.
  • the first layer 2 on the upper surface of the underlayer 4 is made of a material different from that of the underlayer 4, has a surface energy higher than that of the underlayer 4, and is formed in an electrode pattern shape.
  • the second layer 3 is formed of a conductive nano ink. Such formation of the underlayer 4 is effective when the surface energy of the substrate 1 is approximately equal to or greater than the surface energy of the first layer 2.
  • the conductive nano ink can be easily attached only on the first layer 2.
  • An electrode pattern can be formed. Therefore, it is not necessary to form the underlayer 4 when the surface energy of the substrate 1 is sufficiently lower than that of the first layer 2, and the electrode pattern may be formed with a layer structure as shown in FIG.
  • the formation process of the electrode pattern structure shown in FIG. 2 is the same as the process shown in FIG. 3 except that the substrate 1 is replaced with the substrate 1 having the base layer 4 in FIG.
  • the first layer 2 is formed by a gas curtain laser CVD method.
  • FIG. 6 shows a conceptual diagram of an example of an apparatus used in the gas curtain type laser CVD method.
  • a gas window 102 having a laser beam introduction window 101 is installed on the substrate 1 or the underlayer 4 so as to cover it with a slight gap.
  • a gas introduction space 103 is formed below the laser beam introduction window 101 of the gas window 102, and a source gas supply passage 104 and a purge gas supply passage 105 are provided toward the gas introduction space 103.
  • a suction exhaust passage 106 is provided around the gas introduction space 103 of the gas window 102.
  • a gas window as described in JP 2010-215947 A can be preferably used.
  • a source gas supply passage 104 and a purge gas supply passage 105 are respectively supplied from a source gas supply passage 104 and a purge gas supply passage 105 to a gas introduction space 103 of a gas window 102 covering the upper surface of the substrate 1 or the base layer 4 where the first layer 2 is formed.
  • gas is exhausted from the suction / exhaust passage 106, and a predetermined laser beam L is irradiated from the laser beam introduction window 101 to perform CVD at the irradiation spot.
  • the first layer 2 is formed at a desired location while relatively moving the gas window 102 and the laser beam irradiation spot of the substrate 1 or the base layer 4.
  • the source gas is locally contained in the laser beam irradiation spot by the so-called gas curtain 107 to prevent the leakage of the source gas and the mixing of air from the surrounding atmosphere. Therefore, laser CVD can be performed without requiring vacuum equipment such as a vacuum chamber.
  • the first layer 2 having a fine pattern corresponding to the laser beam width can be formed on the surface of the substrate 1 or the underlayer 4, and the conductive nano ink is formed on the upper surface thereof.
  • the second layer 3 By forming the second layer 3 using, it becomes possible to form a fine electrode pattern with a width substantially equal to that of the first layer 2.
  • high-definition electrode patterns can be easily formed without using equipment such as photolithography and a vacuum chamber that require a large amount of materials and energy.
  • the formed film contains more oxygen, nitrogen, etc. than the laser CVD method using a vacuum chamber, and an oxide film or a nitride film may be formed in combination with a metal film. .
  • the material of the substrate 1 is, for example, glass, polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), polymethyl methacrylate (PMMA), polytetrafluoroethylene (PTFE), or the like.
  • Plastic material can be used.
  • the base layer 4 is formed when the surface energy of the substrate 1 is equal to or larger than that of the first layer 2 and is made of a material having a surface energy lower than that of the first layer 2.
  • a polymer such as polyvinyl alcohol (PVA), polystyrene (PS), polyvinylphenol (PVP), and various fluorine-based polymers is used in addition to the PC, PET, PP, PMMA, and PTFE. be able to.
  • the first layer 2 is made of a material having a surface energy higher than the surface energy of the substrate 1 or the underlayer 4 that is directly below it.
  • any one or a mixture of two or more of metals or oxides or nitrides thereof, or an organic compound can be used.
  • those that can be easily formed by laser light irradiation are preferable, and examples thereof include metals such as tungsten, molybdenum, nickel, and chromium, and organometallic compounds containing these metals.
  • the second layer 3 is formed of a conductive nano ink, and as a material thereof, a suitable electrode material in an electronic device is used, specifically, among silver, gold, copper, and indium tin oxide. Any 1 type or a 2 or more types of mixture is mentioned.
  • a conductive nano ink a commercially available one can be applied, and as a coating method thereof, a spin coating method, an ink jet method, a slit coating method, a die coating method, or the like can be used. A coating method that does not use a plate is preferable, and printing by an inkjet method is particularly efficient and preferable.
  • the electrode pattern structure of the electronic device as shown in FIG. 2 was produced by the following procedure. First, PTFE having a surface energy lower than that of the glass substrate 1 is formed on the cleaned glass substrate 1 at a thickness of 300 nm by a spin coating method (4000 rpm) and thermally cured at 150 ° C. to form the underlayer 4 (surface energy: 8.7 mN / m).
  • laser is supplied to the upper surface of the underlayer 4 while supplying hexacarbonyl tungsten (W (CO) 6 ) as a source gas and Ar as a purge gas.
  • W (CO) 6 hexacarbonyl tungsten
  • Ar Ar
  • Irradiate light wavelength 349 nm, width 5 ⁇ m
  • decompose into W and CO by photoreaction and thermal reaction
  • deposit a tungsten film with the width of laser light and form the first layer 2 (surface energy: 30 mN / m) Formed.
  • a silver nano paste (Harima Kasei Co., Ltd .; NPS-JL) as a conductive nano ink is formed on the upper surface of the first layer 2 by a spin coating method (4000 rpm), and baked on a hot plate at 100 ° C. for 30 minutes.
  • the second layer 3 can be formed with a width substantially equal to that of the first layer 2 and that an electrode pattern of fine wiring can be formed.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Toxicology (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Provided is a method for manufacturing an electronic device which can be produced on-demand and has an electrode pattern which can be formed simply with high degree of fineness. A first electrode pattern-shape layer (1) made of a material different from a substrate (1) and having a surface energy higher than the substrate (1) is formed on the substrate (1) with the gas-curtain laser CVD method, and a second layer (2) is formed with a conductive nano-ink on the upper surface of the first layer (1), and thus an electrode pattern for an electronic device is formed.

Description

電子デバイスの製造方法Manufacturing method of electronic device
　本発明は、ダイオード、トランジスタ等の電子デバイスにおける電極の形成に関し、より詳細には、塗布法により形成される電極パターンを備えた電子デバイスの製造方法に関する。 The present invention relates to the formation of electrodes in electronic devices such as diodes and transistors, and more particularly to a method for manufacturing an electronic device having an electrode pattern formed by a coating method.
　電子回路は、年々小型化が進み、それに伴って電極も微細配線化が進んでいる。このように微細配線化された電極の作製には、通常、フォトリソグラフィが用いられている。
　しかしながら、フォトリソグラフィプロセスを用いたリフトオフやウエットエッチングでは、レジスト塗布、乾燥、露光、現像及び膜のエッチング等において、大量の溶剤や化学薬品、電力が使用されるため、地球環境への負荷が大きい。 Electronic circuits have been miniaturized year by year, and along with this, electrodes have been made finer. Photolithography is usually used for producing such finely wired electrodes.
However, in lift-off and wet etching using a photolithographic process, a large amount of solvent, chemicals, and electric power are used in resist coating, drying, exposure, development, film etching, and the like, so the load on the global environment is large. .
　これに対しては、近年、設備投資の負担が軽く、大量生産が可能であり、低コストメリットを望める方法として、印刷を用いた電極形成が行われるようになってきた。印刷法は、フォトリソグラフィに比べて使用原材料や化学薬品が少量で済むため、地球環境に優しいグリーンイノベーション分野の技術として期待されている。印刷法においては、さらに、少量多品種に対応できる印刷技術が望まれている。 In response to this, in recent years, electrode formation using printing has been performed as a method for reducing the cost of capital investment, enabling mass production, and offering low cost merit. The printing method is expected as a technology in the green innovation field that is friendly to the global environment because it requires less raw materials and chemicals than photolithography. In the printing method, further, a printing technique capable of dealing with a small variety of products is desired.
　印刷法により電極パターンを形成する具体的な方法としては、インクジェット方式、凸版印刷、グラビア印刷、スプレー印刷、スリットコート法、スクリーン印刷等、様々な方法がある。この中でも、微細配線に効果的な印刷方法は、インクジェット方式、凸版印刷及びグラビア印刷である。
　しかしながら、凸版印刷及びグラビア印刷は、版を用いる点でオンデマンド性に劣る。これに対して、版を必要としないインクジェット方式は、オンデマンド性に優れていると言える。 As a specific method for forming an electrode pattern by a printing method, there are various methods such as an ink jet method, letterpress printing, gravure printing, spray printing, slit coating method, and screen printing. Among these, an effective printing method for fine wiring is an ink jet method, relief printing, and gravure printing.
However, letterpress printing and gravure printing are inferior in on-demand properties in that a plate is used. On the other hand, it can be said that the ink jet system which does not require a plate is excellent in on-demand characteristics.
　ただし、インクジェット方式で微細配線を行う場合、基板に着弾したインクが如何に広がらずに指定位置に確実に形成することができるかが重要なポイントとなる。
　図４，５に、インクジェット方式で基板上に微細配線を行った場合の概念図を示す。それぞれ、（ａ）はインク滴下直後、（ｂ）は溶媒蒸発時、（ｃ）は乾燥後のインクの状態を示したものである。
　図４においては、基板１１のインク１５に対する濡れ性が高いため、設定幅ｄ以上に線幅が広がっている。一方、図５においては、基板２１のインク２５に対する撥液性が高いため、インク２５が定着せずに基板の端に移動し、線幅も狭くなっている。
　このように、インクジェット方式では、基板の濡れ性によりインクの線幅が変化するという現象が生じる。 However, when fine wiring is performed by an ink jet method, an important point is how the ink that has landed on the substrate can be reliably formed at a specified position without spreading.
4 and 5 show conceptual diagrams when fine wiring is performed on a substrate by an ink jet method. (A) shows the state of the ink immediately after the ink is dropped, (b) shows the state of the ink after evaporation, and (c) shows the state of the ink after drying.
In FIG. 4, since the wettability of the substrate 11 to the ink 15 is high, the line width is wider than the set width d. On the other hand, in FIG. 5, since the liquid repellency of the substrate 21 to the ink 25 is high, the ink 25 moves to the end of the substrate without being fixed, and the line width is also narrowed.
Thus, in the ink jet system, a phenomenon occurs in which the line width of the ink changes due to the wettability of the substrate.
　この対策として、例えば、特許文献１に、濡れ性制御層に紫外線を照射することにより表面エネルギーを変化させて、インクが広がる範囲を制御することが記載されている。
　また、特許文献２には、インクが広がる範囲の制御のために、凸領域にインクを滴下することで平滑面より撥水的な挙動が起こる現象を利用することが記載されている。 As a countermeasure against this, for example, Patent Document 1 describes that the surface energy is changed by irradiating the wettability control layer with ultraviolet rays to control the range in which the ink spreads.
Japanese Patent Application Laid-Open No. H10-228561 describes using a phenomenon in which water repellent behavior occurs from a smooth surface by dropping ink onto a convex region in order to control the range in which the ink spreads.
特開２００７－１５０２４６号公報JP 2007-150246 A 特開２００４－１４１８５６号公報JP 2004-141856 A
　しかしながら、上記特許文献１に記載された方法では、紫外線のエネルギーに反応して濡れ性が変化するような特殊な制御層を形成する必要があり、また、前記制御層を有機トランジスタのゲート絶縁膜として用いる場合は、絶縁性やトランジスタ特性の点で問題が生じるおそれがある。
　一方、上記特許文献２に記載された方法では、濡れ性を制御するための凹凸層を基板に形成する必要があり、このような凹凸を高精度で形成するためにはフォトリソグラフィ技術を用いなければならない。 However, in the method described in Patent Document 1, it is necessary to form a special control layer whose wettability changes in response to ultraviolet energy, and the control layer is formed as a gate insulating film of an organic transistor. When used as, there is a possibility that problems may occur in terms of insulation and transistor characteristics.
On the other hand, in the method described in Patent Document 2, it is necessary to form a concavo-convex layer for controlling wettability on the substrate, and in order to form such concavo-convex with high accuracy, a photolithography technique must be used. I must.
　したがって、高精細な電極パターンを単純な構造で簡単にオンデマンドに対応して形成することができる方法が望まれている。 Therefore, there is a demand for a method capable of forming a high-definition electrode pattern with a simple structure and easily corresponding to on-demand.
　本発明は、上記技術的課題を解決するためになされたものであり、オンデマンドでの対応が可能であり、高精細で簡便に形成することができる電極パターンを備えた電子デバイスの製造方法を提供することを目的とするものである。 The present invention has been made to solve the above technical problem, and provides a method of manufacturing an electronic device having an electrode pattern that can be formed on demand and can be formed on demand. It is intended to provide.
　本発明に係る電子デバイスの製造方法は、基板上に、前記基板とは異なる材質からなり、前記基板よりも高い表面エネルギーを持つ、電極パターン形状の第一層と、前記第一層の上面に、導電性ナノインクにより形成された第二層とを備えた電子デバイスの製造方法において、前記第一層をガスカーテン方式レーザＣＶＤ法により形成することを特徴とする。
　ガスカーテン方式レーザＣＶＤ法を用いることにより、高精細な電極パターンを容易に構成することが可能となる。 An electronic device manufacturing method according to the present invention includes a first layer having an electrode pattern shape on a substrate, made of a material different from the substrate and having a higher surface energy than the substrate, and an upper surface of the first layer. In the manufacturing method of the electronic device provided with the second layer formed of the conductive nano ink, the first layer is formed by a gas curtain laser CVD method.
By using the gas curtain laser CVD method, a high-definition electrode pattern can be easily configured.
　また、本発明に係る他の態様の電子デバイスの製造方法は、基板上に、前記基板とは異なる材質からなり、前記基板よりも低い表面エネルギーを持つ下地層と、前記下地層の上面に、前記下地層とは異なる材質からなり、前記下地層よりも高い表面エネルギーを持つ、電極パターン形状の第一層と、前記第一層の上面に、導電性ナノインクにより形成された第二層とを備えた電子デバイスの製造方法において、前記第一層をガスカーテン方式レーザＣＶＤ法により形成することを特徴とする。
　基板の表面エネルギーが、第一層の表面エネルギーと同等程度又はより大きい場合には、このように基板と第一層との間に、基板よりも表面エネルギーが低い下地層を介在させ、かつ、ガスカーテン方式レーザＣＶＤ法を用いることにより、上記の場合と同様に、高精細な電極パターンの形成が可能となる。 In addition, the method for manufacturing an electronic device according to another aspect of the present invention includes a base layer made of a material different from the substrate, having a lower surface energy than the substrate, and an upper surface of the base layer. An electrode pattern-shaped first layer made of a material different from the base layer and having a surface energy higher than that of the base layer, and a second layer formed of conductive nano ink on the top surface of the first layer. In the electronic device manufacturing method, the first layer is formed by a gas curtain laser CVD method.
When the surface energy of the substrate is equal to or larger than the surface energy of the first layer, an underlayer having a surface energy lower than that of the substrate is interposed between the substrate and the first layer, and By using the gas curtain laser CVD method, a high-definition electrode pattern can be formed as in the above case.
　前記第一層は、前記基板又は前記下地層の表面エネルギーより高い表面ネルギーを持つ材質として、金属又はその酸化物もしくは窒化物のうちのいずれか１種もしくは２種以上の混合物、又は、有機化合物により形成される。 The first layer is a material having a surface energy higher than the surface energy of the substrate or the underlayer, and is a metal, an oxide or a nitride thereof, or a mixture of two or more thereof, or an organic compound. It is formed by.
　本発明によれば、真空チャンバやフォトリソグラフィを用いることなく、オンデマンドに対応して高精細な電極パターンが形成された電子デバイスを簡便な方法で製造することができる。 According to the present invention, an electronic device in which a high-definition electrode pattern is formed on demand can be manufactured by a simple method without using a vacuum chamber or photolithography.
本発明に係る電子デバイスの電極パターン構造の一態様を示す概念断面図である。It is a conceptual sectional view showing one mode of an electrode pattern structure of an electronic device concerning the present invention. 本発明に係る電子デバイスの電極パターン構造の他の態様を示す概念断面図である。It is a conceptual sectional view showing other modes of an electrode pattern structure of an electronic device concerning the present invention. 図１の電極パターンが形成される過程を説明するための概念断面図であり、（ａ）はインク滴下直後、（ｂ）は溶媒蒸発時、（ｃ）は乾燥後のインクの状態を示す。FIGS. 2A and 2B are conceptual cross-sectional views for explaining a process of forming the electrode pattern of FIG. インクジェット方式で濡れ性が高い基板上に微細配線を行った場合の概念断面図であり、（ａ）はインク滴下直後、（ｂ）は溶媒蒸発時、（ｃ）は乾燥後のインクの状態を示す。It is a conceptual sectional view when fine wiring is performed on a substrate with high wettability by an ink jet method, (a) is immediately after ink dropping, (b) is during solvent evaporation, (c) is the state of ink after drying. Show. インクジェット方式で撥液性が高い基板上に微細配線を行った場合の概念断面図であり、（ａ）はインク滴下直後、（ｂ）は溶媒蒸発時、（ｃ）は乾燥後のインクの状態を示す。It is a conceptual sectional view at the time of performing fine wiring on a substrate with high liquid repellency by an ink jet method, (a) immediately after ink dropping, (b) during solvent evaporation, (c) ink state after drying Indicates. ガスカーテン方式レーザＣＶＤ装置の概念図を示す。The conceptual diagram of a gas curtain system laser CVD apparatus is shown.
　以下、本発明について図面を参照して詳細に説明する。
　本発明に係る電子デバイスの製造方法は、基板上に、前記基板とは異なる材質からなり、前記基板よりも高い表面エネルギーを持つ、電極パターン形状の第一層と、前記第一層の上面に、導電性ナノインクにより形成された第二層とを備えた電子デバイスを製造する方法である。そして、前記第一層をガスカーテン方式レーザＣＶＤ法により形成することを特徴としている。 Hereinafter, the present invention will be described in detail with reference to the drawings.
An electronic device manufacturing method according to the present invention includes a first layer having an electrode pattern shape on a substrate, made of a material different from the substrate and having a higher surface energy than the substrate, and an upper surface of the first layer. And a method of manufacturing an electronic device including a second layer formed of conductive nano ink. The first layer is formed by a gas curtain laser CVD method.
　図１に、本発明に係る電子デバイスの上記の態様の電極パターン構造の概念図を示す。図１に示したように、本発明に係る電子デバイスは、基板１上に、第一層２及び第二層３が形成されている。第一層２は、基板１とは異なる材質で、基板１よりも高い表面エネルギーを持ち、電極パターン形状に形成される。そして、第二層３は、導電性ナノインクにより形成される。 FIG. 1 shows a conceptual diagram of an electrode pattern structure of the above-described aspect of an electronic device according to the present invention. As shown in FIG. 1, in the electronic device according to the present invention, a first layer 2 and a second layer 3 are formed on a substrate 1. The first layer 2 is made of a material different from that of the substrate 1, has a surface energy higher than that of the substrate 1, and is formed in an electrode pattern shape. The second layer 3 is formed of a conductive nano ink.
　図３に、図１に示す電極パターンが形成される過程を説明するための概念図を示す。まず、基板１上に、基板１よりも高い表面エネルギーを持つ第一層２を電極パターン形状に形成しておく。これにより、基板１と第一層２との間に表面エネルギーが異なる境界面が形成される。そして、第一層２の上に、導電性ナノインク５を滴下すると、その直後は、第一層２の幅からはみ出して、基板１表面にも一部接触するようにインクが広がる（図３（ａ）参照）。その後、インクの溶媒が蒸発していくと、導電性ナノインク５は自己組織的に、表面エネルギーが高い第一層２の上面のみに集まって留まり、それ以上広がることが抑制される（図３（ｂ）参照）。この状態で乾燥させると、第一層２の上面のみに導電性ナノインク５が乾燥して生成した第二層３が形成され、第一層２とほぼ同等の幅で微細な電極パターンを形成することができる。 FIG. 3 is a conceptual diagram for explaining the process of forming the electrode pattern shown in FIG. First, a first layer 2 having a surface energy higher than that of the substrate 1 is formed in an electrode pattern shape on the substrate 1. As a result, a boundary surface having different surface energy is formed between the substrate 1 and the first layer 2. Then, when the conductive nano ink 5 is dropped on the first layer 2, immediately after that, the ink spreads out from the width of the first layer 2 so as to partially contact the surface of the substrate 1 (FIG. 3 ( a)). Thereafter, when the solvent of the ink is evaporated, the conductive nano ink 5 is self-organized and stays gathered only on the upper surface of the first layer 2 having a high surface energy, and is prevented from spreading further (FIG. 3 ( b)). When dried in this state, the second layer 3 formed by drying the conductive nano ink 5 is formed only on the upper surface of the first layer 2, and a fine electrode pattern is formed with a width substantially equal to that of the first layer 2. be able to.
　また、本発明に係る他の態様の電子デバイスの製造方法は、基板上に、前記基板とは異なる材質からなり、前記基板よりも低い表面エネルギーを持つ下地層と、前記下地層の上面に、前記下地層とは異なる材質からなり、前記下地層よりも高い表面エネルギーを持つ、電極パターン形状の第一層と、前記第一層の上面に、導電性ナノインクにより形成された第二層とを備えた電子デバイスの製造方法である。そして、この方法においても、前記第一層をガスカーテン方式レーザＣＶＤ法により形成することを特徴としている。 In addition, the method for manufacturing an electronic device according to another aspect of the present invention includes a base layer made of a material different from the substrate, having a lower surface energy than the substrate, and an upper surface of the base layer. An electrode pattern-shaped first layer made of a material different from the base layer and having a surface energy higher than that of the base layer, and a second layer formed of conductive nano ink on the top surface of the first layer. It is a manufacturing method of the provided electronic device. Also in this method, the first layer is formed by a gas curtain laser CVD method.
　図２に、本発明に係る電子デバイスの上記の態様の電極パターン構造の概念図を示す。図２においては、基板１と第一層２との間に、下地層４が形成されている。下地層４は、基板１とは異なる材質で、基板１よりも低い表面エネルギーを持つ。そして、下地層４の上面の第一層２は、下地層４とは異なる材質で、下地層４よりも高い表面エネルギーを持ち、電極パターン形状に形成される。また、第二層３は、導電性ナノインクにより形成される。
　このような下地層４の形成は、基板１の表面エネルギーが、第一層２の表面エネルギーと同等程度又はより大きい場合に有効である。基板１よりも表面エネルギーが低い下地層４上に、表面エネルギーがより高い第一層２を形成することにより、導電性ナノインクが第一層２上にのみ付着しやすくさせることができ、微細な電極パターンを形成することができる。
　したがって、下地層４は、基板１の表面エネルギーが第一層２よりも十分に低い場合には、形成する必要はなく、図１に示すような層構造で電極パターンを形成すればよい。
　なお、図２に示す電極パターン構造の形成過程は、図３において、基板１が下地層４を備えた基板１に代わる以外は、図３に示す過程と同様である。 In FIG. 2, the conceptual diagram of the electrode pattern structure of the said aspect of the electronic device which concerns on this invention is shown. In FIG. 2, a base layer 4 is formed between the substrate 1 and the first layer 2. The underlayer 4 is made of a material different from that of the substrate 1 and has a lower surface energy than that of the substrate 1. The first layer 2 on the upper surface of the underlayer 4 is made of a material different from that of the underlayer 4, has a surface energy higher than that of the underlayer 4, and is formed in an electrode pattern shape. The second layer 3 is formed of a conductive nano ink.
Such formation of the underlayer 4 is effective when the surface energy of the substrate 1 is approximately equal to or greater than the surface energy of the first layer 2. By forming the first layer 2 having a higher surface energy on the base layer 4 having a surface energy lower than that of the substrate 1, the conductive nano ink can be easily attached only on the first layer 2. An electrode pattern can be formed.
Therefore, it is not necessary to form the underlayer 4 when the surface energy of the substrate 1 is sufficiently lower than that of the first layer 2, and the electrode pattern may be formed with a layer structure as shown in FIG.
The formation process of the electrode pattern structure shown in FIG. 2 is the same as the process shown in FIG. 3 except that the substrate 1 is replaced with the substrate 1 having the base layer 4 in FIG.
　上記のような本発明に係る電子デバイスの製造方法においては、いずれも、第一層２は、ガスカーテン方式レーザＣＶＤ法により形成される。
　図６に、ガスカーテン方式レーザＣＶＤ法に用いられる装置の一例の概念図を示す。図６に示すガスカーテン方式レーザＣＶＤ装置１００においては、基板１又は下地層４上に、レーザ光導入窓１０１を備えたガスウィンドウ１０２がわずかに隙間を空けて覆うように設置されている。ガスウィンドウ１０２のレーザ光導入窓１０１下方には、ガス導入用空間１０３が形成され、このガス導入用空間１０３に向けて、ソースガス供給通路１０４及びパージガス供給通路１０５が設けられている。また、ガスウィンドウ１０２のガス導入用空間１０３の周囲には、吸引排気通路１０６が設けられている。
　なお、ガスウィンドウ１０２の具体的な構成としては、特開２０１０－２１５９４７号公報に記載されているようなガスウィンドウを好適に用いることができる。 In any of the electronic device manufacturing methods according to the present invention as described above, the first layer 2 is formed by a gas curtain laser CVD method.
FIG. 6 shows a conceptual diagram of an example of an apparatus used in the gas curtain type laser CVD method. In the gas curtain type laser CVD apparatus 100 shown in FIG. 6, a gas window 102 having a laser beam introduction window 101 is installed on the substrate 1 or the underlayer 4 so as to cover it with a slight gap. A gas introduction space 103 is formed below the laser beam introduction window 101 of the gas window 102, and a source gas supply passage 104 and a purge gas supply passage 105 are provided toward the gas introduction space 103. A suction exhaust passage 106 is provided around the gas introduction space 103 of the gas window 102.
As a specific configuration of the gas window 102, a gas window as described in JP 2010-215947 A can be preferably used.
　この装置１００では、第一層２の形成箇所となる基板１又は下地層４の上面を覆ったガスウィンドウ１０２のガス導入用空間１０３に、ソースガス供給通路１０４及びパージガス供給通路１０５からそれぞれ、ソースガス及びパージガスを供給すると同時に、吸引排気通路１０６からガス排気を行いつつ、レーザ光導入窓１０１から所定のレーザ光Ｌを照射して、照射スポットにてＣＶＤを行う。そして、このガスウィンドウ１０２と、基板１又は下地層４のレーザ光照射スポットとを相対的に移動させながら、所望箇所に第一層２を形成していく。
　このように、ガスカーテン方式レーザＣＶＤ法においては、レーザ光照射スポットに、いわゆるガスのカーテン１０７でソースガスを局所的に封じ込め、原料ガスのリークと周囲の雰囲気からの空気等の混入を防ぐことができるため、真空チャンバ等の真空設備を要することなく、レーザＣＶＤを行うことができる。 In this apparatus 100, a source gas supply passage 104 and a purge gas supply passage 105 are respectively supplied from a source gas supply passage 104 and a purge gas supply passage 105 to a gas introduction space 103 of a gas window 102 covering the upper surface of the substrate 1 or the base layer 4 where the first layer 2 is formed. At the same time as supplying the gas and the purge gas, gas is exhausted from the suction / exhaust passage 106, and a predetermined laser beam L is irradiated from the laser beam introduction window 101 to perform CVD at the irradiation spot. Then, the first layer 2 is formed at a desired location while relatively moving the gas window 102 and the laser beam irradiation spot of the substrate 1 or the base layer 4.
As described above, in the gas curtain laser CVD method, the source gas is locally contained in the laser beam irradiation spot by the so-called gas curtain 107 to prevent the leakage of the source gas and the mixing of air from the surrounding atmosphere. Therefore, laser CVD can be performed without requiring vacuum equipment such as a vacuum chamber.
　したがって、前記ガスカーテン方式レーザＣＶＤ法によれば、基板１又は下地層４の表面に、レーザ光幅に対応した微細なパターンの第一層２を形成することができ、その上面に導電性ナノインクを用いて第二層３を形成することにより、第一層２とほぼ同等の幅で微細な電極パターンを形成することが可能となる。しかも、大量の材料やエネルギーを要するフォトリソグラフィや真空チャンバ等の設備を用いることなく、高精細な電極パターン形成を簡便に行うことが可能となる。
　ただし、真空設備を使用しないことにより、真空チャンバを用いるレーザＣＶＤ法よりも形成膜中に酸素や窒素等が多く含まれ、酸化膜や窒化膜が金属膜と混在して形成される場合もある。 Therefore, according to the gas curtain type laser CVD method, the first layer 2 having a fine pattern corresponding to the laser beam width can be formed on the surface of the substrate 1 or the underlayer 4, and the conductive nano ink is formed on the upper surface thereof. By forming the second layer 3 using, it becomes possible to form a fine electrode pattern with a width substantially equal to that of the first layer 2. In addition, high-definition electrode patterns can be easily formed without using equipment such as photolithography and a vacuum chamber that require a large amount of materials and energy.
However, by not using vacuum equipment, the formed film contains more oxygen, nitrogen, etc. than the laser CVD method using a vacuum chamber, and an oxide film or a nitride film may be formed in combination with a metal film. .
　本発明においては、基板１の材質としては、例えば、ガラス、又は、ポリカーボネート（ＰＣ）、ポリエチレンテレフタレート（ＰＥＴ）、ポリプロピレン（ＰＰ）、ポリメチルメタクリレート（ＰＭＭＡ）、ポリテトラフルオロエチレン（ＰＴＦＥ）等のプラスチック材を用いることができる。 In the present invention, the material of the substrate 1 is, for example, glass, polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), polymethyl methacrylate (PMMA), polytetrafluoroethylene (PTFE), or the like. Plastic material can be used.
　下地層４は、上述したように、基板１の表面エネルギーが第一層２と同等である場合又はより大きい場合に形成され、第一層２よりも低い表面エネルギーを持つ材質で構成される。例えば、基板１がガラスの場合、上記ＰＣ、ＰＥＴ、ＰＰ、ＰＭＭＡ、ＰＴＦＥの他に、ポリビニールアルコール（ＰＶＡ）、ポリスチレン（ＰＳ）、ポリビニルフェノール（ＰＶＰ）や各種フッ素系ポリマー等のポリマーを用いることができる。 As described above, the base layer 4 is formed when the surface energy of the substrate 1 is equal to or larger than that of the first layer 2 and is made of a material having a surface energy lower than that of the first layer 2. For example, when the substrate 1 is glass, a polymer such as polyvinyl alcohol (PVA), polystyrene (PS), polyvinylphenol (PVP), and various fluorine-based polymers is used in addition to the PC, PET, PP, PMMA, and PTFE. be able to.
　また、第一層２は、上述したように、その直下層となる基板１又は下地層４の表面エネルギーより高い表面ネルギーを持つ材質で構成される。具体的には、金属又はその酸化物もしくは窒化物のうちのいずれか１種もしくは２種以上の混合物、又は、有機化合物を用いることができる。特に、レーザ光の照射によって容易に成膜可能であるものが好ましく、例えば、タングステン、モリブデン、ニッケル、クロム等の金属やこれらを含む有機金属化合物が挙げられる。 Further, as described above, the first layer 2 is made of a material having a surface energy higher than the surface energy of the substrate 1 or the underlayer 4 that is directly below it. Specifically, any one or a mixture of two or more of metals or oxides or nitrides thereof, or an organic compound can be used. In particular, those that can be easily formed by laser light irradiation are preferable, and examples thereof include metals such as tungsten, molybdenum, nickel, and chromium, and organometallic compounds containing these metals.
　一方、第二層３は、導電性ナノインクにより形成されるが、その材質としては、電子デバイスにおける好適な電極材料が用いられ、具体的には、銀、金、銅及び酸化インジウムスズのうちのいずれか１種又は２種以上の混合物が挙げられる。
　導電性ナノインクは市販のものを適用することができ、その塗布方法としては、スピンコート法、インクジェット法、スリットコート法、ダイコート法等を用いることができるが、オンデマンドに対応する観点からは、版を用いない塗布方法が好ましく、特に、インクジェット方式による印刷が効率的であり好ましい。 On the other hand, the second layer 3 is formed of a conductive nano ink, and as a material thereof, a suitable electrode material in an electronic device is used, specifically, among silver, gold, copper, and indium tin oxide. Any 1 type or a 2 or more types of mixture is mentioned.
As the conductive nano ink, a commercially available one can be applied, and as a coating method thereof, a spin coating method, an ink jet method, a slit coating method, a die coating method, or the like can be used. A coating method that does not use a plate is preferable, and printing by an inkjet method is particularly efficient and preferable.
　以下、本発明を実施例に基づいて、さらに具体的に説明するが、本発明は下記実施例により制限されるものではない。
　以下に示す手順で、図２に示すような電子デバイスの電極パターン構造を作製した。
　まず、洗浄したガラス基板１上に、ガラス基板１より表面エネルギーが低いＰＴＦＥをスピンコート法（４０００ｒｐｍ）で厚さ３００ｎｍで成膜し、１５０℃で熱硬化させて、下地層４（表面エネルギー：８．７ｍＮ／ｍ）を形成した。
　次に、ガスカーテン方式レーザＣＶＤ装置（オムロンレーザーフロント株式会社製）を用いて、下地層４の上面に、ソースガスとしてヘキサカルボニルタングステン（Ｗ（ＣＯ）６）、パージガスとしてＡｒを供給しながらレーザ光（波長３４９ｎｍ、幅５μｍ）を照射し、光反応及び熱反応によりＷとＣＯに分解し、レーザ光の幅でタングステン膜を堆積させて、第一層２（表面エネルギー：３０ｍＮ／ｍ）を形成した。
　そして、第一層２の上面に、導電性ナノインクとして銀ナノペースト（ハリマ化成株式会社；ＮＰＳ－ＪＬ）をスピンコート法（４０００ｒｐｍ）で成膜し、ホットプレート上で１００℃、３０分間焼成し、第二層３である銀電極（幅５．５μｍ）を形成した。
　このように、第二層３を第一層２とほぼ同等の幅で形成することができ、微細配線の電極パターンの形成が可能であることが認められた。 EXAMPLES Hereinafter, although this invention is demonstrated further more concretely based on an Example, this invention is not restrict | limited by the following Example.
The electrode pattern structure of the electronic device as shown in FIG. 2 was produced by the following procedure.
First, PTFE having a surface energy lower than that of the glass substrate 1 is formed on the cleaned glass substrate 1 at a thickness of 300 nm by a spin coating method (4000 rpm) and thermally cured at 150 ° C. to form the underlayer 4 (surface energy: 8.7 mN / m).
Next, using a gas curtain type laser CVD apparatus (made by OMRON Laser Front Co., Ltd.), laser is supplied to the upper surface of the underlayer 4 while supplying hexacarbonyl tungsten (W (CO) 6 ) as a source gas and Ar as a purge gas. Irradiate light (wavelength 349 nm, width 5 μm), decompose into W and CO by photoreaction and thermal reaction, deposit a tungsten film with the width of laser light, and form the first layer 2 (surface energy: 30 mN / m) Formed.
Then, a silver nano paste (Harima Kasei Co., Ltd .; NPS-JL) as a conductive nano ink is formed on the upper surface of the first layer 2 by a spin coating method (4000 rpm), and baked on a hot plate at 100 ° C. for 30 minutes. A silver electrode (width 5.5 μm) as the second layer 3 was formed.
Thus, it was recognized that the second layer 3 can be formed with a width substantially equal to that of the first layer 2 and that an electrode pattern of fine wiring can be formed.
　１，１１，２１　基板
　２　　　　　　　第一層
　３　　　　　　　第二層
　４　　　　　　　下地層
　５，１５，２５　インク
　１００　　　　　ガスカーテン方式レーザＣＶＤ装置
　１０１　　　　　レーザ光導入窓
　１０２　　　　　ガスウィンドウ
　１０３　　　　　ガス導入用空間
　１０４　　　　　ソースガス供給通路
　１０５　　　　　パージガス供給通路
　１０６　　　　　吸引排気通路
　１０７　　　　　ガスカーテン 1,11,21 Substrate 2 First layer 3 Second layer 4 Underlayer 5, 15, 25 Ink 100 Gas curtain type laser CVD apparatus 101 Laser light introduction window 102 Gas window 103 Gas introduction space 104 Source gas supply passage 105 Purge gas Supply passage 106 Suction / exhaust passage 107 Gas curtain

Claims (3)

  1. 　基板上に、前記基板とは異なる材質からなり、前記基板よりも高い表面エネルギーを持つ、電極パターン形状の第一層と、前記第一層の上面に、導電性ナノインクにより形成された第二層とを備えた電子デバイスの製造方法において、
    　前記第一層をガスカーテン方式レーザＣＶＤ法により形成することを特徴とする電子デバイスの製造方法。     A first layer of an electrode pattern shape made of a material different from that of the substrate on the substrate and having a surface energy higher than that of the substrate, and a second layer formed of conductive nano ink on the upper surface of the first layer In an electronic device manufacturing method comprising:
    A method of manufacturing an electronic device, wherein the first layer is formed by a gas curtain laser CVD method.
  2. 　基板上に、前記基板とは異なる材質からなり、前記基板よりも低い表面エネルギーを持つ下地層と、前記下地層の上面に、前記下地層とは異なる材質からなり、前記下地層よりも高い表面エネルギーを持つ、電極パターン形状の第一層と、前記第一層の上面に、導電性ナノインクにより形成された第二層とを備えた電子デバイスの製造方法において、
    　前記第一層をガスカーテン方式レーザＣＶＤ法により形成することを特徴とする電子デバイスの製造方法。     On the substrate, a base layer made of a material different from the substrate and having a lower surface energy than the substrate, and on the top surface of the base layer, made of a material different from the base layer and having a surface higher than the base layer In a method of manufacturing an electronic device having energy, a first layer of an electrode pattern shape, and a second layer formed of a conductive nano ink on the upper surface of the first layer,
    A method of manufacturing an electronic device, wherein the first layer is formed by a gas curtain laser CVD method.
  3. 　前記第一層が、金属又はその酸化物もしくは窒化物のうちのいずれか１種もしくは２種以上の混合物、又は、有機化合物からなることを特徴とする請求項１又は２に記載の電子デバイスの製造方法。 3. The electronic device according to claim 1, wherein the first layer is made of a metal, an oxide or a nitride thereof, a mixture of two or more of them, or an organic compound. Production method.
PCT/JP2014/050049 2013-01-17 2014-01-07 Method for manufacturing electronic device WO2014112402A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020157019970A KR102051699B1 (en) 2013-01-17 2014-01-07 Method for manufacturing electronic device
CN201480004865.3A CN104919573B (en) 2013-01-17 2014-01-07 The manufacture method of electronic equipment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013006358A JP6002894B2 (en) 2013-01-17 2013-01-17 Manufacturing method of electronic device
JP2013-006358 2013-01-17

Publications (1)

Publication Number Publication Date
WO2014112402A1 true WO2014112402A1 (en) 2014-07-24

Family

ID=51209495

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/050049 WO2014112402A1 (en) 2013-01-17 2014-01-07 Method for manufacturing electronic device

Country Status (5)

Country Link
JP (1) JP6002894B2 (en)
KR (1) KR102051699B1 (en)
CN (1) CN104919573B (en)
TW (1) TWI619154B (en)
WO (1) WO2014112402A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022004230A1 (en) * 2020-06-29 2022-01-06 株式会社ブイ・テクノロジー Processing device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104597640B (en) * 2015-02-12 2017-06-27 深圳市华星光电技术有限公司 Array base palte and its method for repairing disconnected lines

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004296424A (en) * 2003-03-11 2004-10-21 Advanced Lcd Technologies Development Center Co Ltd Method for forming metal layer, metal layer, and display device using metal layer
JP2006066675A (en) * 2004-08-27 2006-03-09 Seiko Epson Corp Wiring pattern, its formation method, electro-optical device, and electronic machine
JP2006225705A (en) * 2005-02-16 2006-08-31 Laserfront Technologies Inc Gas window and chemical vapor deposition apparatus
JP2008112958A (en) * 2006-10-03 2008-05-15 Sony Corp Processing equipment, and manufacturing device of wiring substrate
JP2010141048A (en) * 2008-12-10 2010-06-24 Ricoh Co Ltd Method of manufacturing laminated structure, method of manufacturing organic thin film transistor and method of manufacturing organic thin film transistor array
JP2010199285A (en) * 2009-02-25 2010-09-09 Ricoh Co Ltd Manufacturing method of wiring board, electronic element, and display
JP2011187750A (en) * 2010-03-09 2011-09-22 Ricoh Co Ltd Method of manufacturing organic thin film transistor, method of manufacturing organic thin film transistor array, and method of manufacturing display device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3036687B2 (en) * 1997-05-23 2000-04-24 日本電気株式会社 Laser CVD equipment
JPH11311806A (en) * 1998-04-28 1999-11-09 Matsushita Electric Ind Co Ltd Liquid crystal display panel and its manufacture
JP4245850B2 (en) * 2002-03-19 2009-04-02 シャープ株式会社 Manufacturing method of electronic device
GB2391385A (en) 2002-07-26 2004-02-04 Seiko Epson Corp Patterning method by forming indent region to control spreading of liquid material deposited onto substrate
JP2007150246A (en) 2005-11-02 2007-06-14 Ricoh Co Ltd Organic transistor and display device
JP4403427B2 (en) * 2006-10-06 2010-01-27 ソニー株式会社 LASER PROCESSING DEVICE, LASER PROCESSING METHOD, WIRING BOARD MANUFACTURING METHOD, DISPLAY DEVICE MANUFACTURING METHOD, AND WIRING BOARD
GB2444491A (en) * 2006-12-06 2008-06-11 Univ Muenster Wilhelms Selective growth of organic molecules
JP4730623B2 (en) * 2008-07-24 2011-07-20 ソニー株式会社 THIN FILM TRANSISTOR, METHOD FOR PRODUCING THIN FILM TRANSISTOR, AND ELECTRONIC DEVICE
JP2010212587A (en) * 2009-03-12 2010-09-24 Ricoh Co Ltd Organic thin film transistor, method for producing organic thin film transistor, organic thin film transistor array and display
DE102010020994B4 (en) * 2010-01-27 2022-01-27 Interpane Entwicklungs-Und Beratungsgesellschaft Mbh Method of making a coated article using texture etching

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004296424A (en) * 2003-03-11 2004-10-21 Advanced Lcd Technologies Development Center Co Ltd Method for forming metal layer, metal layer, and display device using metal layer
JP2006066675A (en) * 2004-08-27 2006-03-09 Seiko Epson Corp Wiring pattern, its formation method, electro-optical device, and electronic machine
JP2006225705A (en) * 2005-02-16 2006-08-31 Laserfront Technologies Inc Gas window and chemical vapor deposition apparatus
JP2008112958A (en) * 2006-10-03 2008-05-15 Sony Corp Processing equipment, and manufacturing device of wiring substrate
JP2010141048A (en) * 2008-12-10 2010-06-24 Ricoh Co Ltd Method of manufacturing laminated structure, method of manufacturing organic thin film transistor and method of manufacturing organic thin film transistor array
JP2010199285A (en) * 2009-02-25 2010-09-09 Ricoh Co Ltd Manufacturing method of wiring board, electronic element, and display
JP2011187750A (en) * 2010-03-09 2011-09-22 Ricoh Co Ltd Method of manufacturing organic thin film transistor, method of manufacturing organic thin film transistor array, and method of manufacturing display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022004230A1 (en) * 2020-06-29 2022-01-06 株式会社ブイ・テクノロジー Processing device
JP7496601B2 (en) 2020-06-29 2024-06-07 株式会社ブイ・テクノロジー Processing Equipment

Also Published As

Publication number Publication date
KR20150106414A (en) 2015-09-21
JP2014138107A (en) 2014-07-28
JP6002894B2 (en) 2016-10-05
CN104919573A (en) 2015-09-16
TW201432800A (en) 2014-08-16
CN104919573B (en) 2017-09-19
KR102051699B1 (en) 2019-12-03
TWI619154B (en) 2018-03-21

Similar Documents

Publication Publication Date Title
US7176053B1 (en) Laser ablation method for fabricating high performance organic devices
US6927108B2 (en) Solution-processed thin film transistor formation method
Smits et al. Laser induced forward transfer of graphene
KR102540865B1 (en) A method and system for forming a patterned metal film on a substrate
JP4745062B2 (en) Flat panel display device and manufacturing method thereof
JP4502382B2 (en) Organic transistor
KR20070092663A (en) Device fabrication by ink-jet printing materials into bank structures, and embossing tool
JP2005311325A5 (en)
US8413576B2 (en) Method of fabricating a structure
JP2008311630A (en) Formation of self-aligned via hole in polymer thin film
JP6002894B2 (en) Manufacturing method of electronic device
JP4652866B2 (en) Organic transistor
JP2008073911A (en) Screen printing method, screen printing machine and manufacturing method of organic thin-film transistor
JP5017338B2 (en) Manufacturing method of organic transistor
KR100945729B1 (en) Selectable surface modification using self assembled monolayer for ink-jet process of organic electronic devices
JP6094738B2 (en) Electronic device and manufacturing method thereof
JP2006114581A (en) Organic field effect transistor and manufacturing method therefor
JP5017339B2 (en) Manufacturing method of organic transistor
JP5453793B2 (en) Laminated structure manufacturing method, organic thin film transistor manufacturing method, and organic thin film transistor array manufacturing method
JP2008244262A (en) Method for manufacturing organic semiconductor element
JP6620556B2 (en) Functional material lamination method and functional material laminate
JP2005086188A (en) Formation method for film pattern and formation equipment, and circuit element
JP2007081165A (en) Method of manufacturing organic transistor
JP2005032759A (en) Method of forming multilayer wiring, method of manufacturing wiring board, and method of manufacturing device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14740318

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20157019970

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 14740318

Country of ref document: EP

Kind code of ref document: A1