WO2014107936A1 - 一种超低功耗的低压差稳压电源电路与射频识别标签 - Google Patents

一种超低功耗的低压差稳压电源电路与射频识别标签 Download PDF

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WO2014107936A1
WO2014107936A1 PCT/CN2013/073893 CN2013073893W WO2014107936A1 WO 2014107936 A1 WO2014107936 A1 WO 2014107936A1 CN 2013073893 W CN2013073893 W CN 2013073893W WO 2014107936 A1 WO2014107936 A1 WO 2014107936A1
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type mos
mos transistor
threshold unit
drain
terminal
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PCT/CN2013/073893
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English (en)
French (fr)
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吴边
徐伟
韩富强
漆射虎
罗远明
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卓捷创芯科技（深圳）有限公司
无锡智速科技有限公司
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Publication of WO2014107936A1 publication Critical patent/WO2014107936A1/zh
Priority to US14/794,049 priority Critical patent/US20150310324A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0701—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Definitions

  • the invention relates to the technical field of radio frequency identification, in particular to an ultra-low power low-dropout regulated power supply circuit and a radio frequency identification tag comprising the low-dropout regulated power supply circuit.
  • Low dropout regulated power supply (Low Dropout Regulator, LDO) circuit modules are widely used in the field of integrated circuit chips. Their main function is to stabilize the input supply voltage through a high gain error correction differential amplifier, a power transistor, and a negative feedback loop. The voltage of the power supply after pressing, and effectively suppress the disturbance and noise caused by the input power in the frequency range of the unity gain bandwidth of the negative feedback loop, thereby providing an ideal power supply to the load on the chip, and its circuit structure diagram As shown in Figure 1.
  • the low-dropout regulated power supply is characterized by a small difference between the input supply voltage and the output supply voltage. Because of the loop gain of the negative feedback loop, the output supply voltage can maintain good stability without changing the input voltage. Changes, which are especially important for battery-powered mobile devices.
  • the voltage value (Vout) outputted by the low-dropout regulated power supply circuit is reference voltage (Vref) input from the negative input terminal of the error correction differential amplifier, and the resistance value of the positive input terminal of the low-dropout regulated power supply circuit to the error correction differential amplifier.
  • (R1) is determined by the ratio of the resistance value of the positive input terminal of the error correction differential amplifier to the resistance value of the ground (R2), that is,
  • Vout Vref•(1+R1/R2)
  • Low dropout regulated power supply circuit is passive radio frequency identification (Radio Frequency Identification, RFID) An integral part of the tag chip.
  • RFID Radio Frequency Identification
  • the passive RFID tag itself does not have a battery, it relies on the electromagnetic energy sent by the card reader. Because of its simple structure and economical utility, it has been widely used in logistics management, asset tracking and mobile medical.
  • a passive RFID tag When a passive RFID tag is in operation, it absorbs the electromagnetic energy emitted by the reader from the surrounding environment. After absorbing the energy, the passive RFID tag rectifies a part of the energy into a DC power source, and the DC power source is input as an input signal to the low-dropout power supply circuit module, and the power supply output after the voltage regulation is used for the internal circuit of the passive RFID tag; The source RFID tag also inputs another portion of the energy into the internal modem circuit. The modem circuit demodulates the amplitude modulated signal carried in the energy and transmits the demodulated signal to the digital baseband portion of the passive RFID tag for processing. Since passive RFID tags are not battery-powered, their power consumption needs to be extremely small to work. This imposes high low-power design requirements on the design of all circuit modules on passive RFID tag chips.
  • the power consumption of the low-dropout regulated power supply circuit is roughly consumed by the error-correcting differential amplifier, as well as the voltage divider resistor (R1 and R2).
  • the load current driven by the low-dropout regulated power supply circuit reaches a minimum, that is, zero load, the power consumption of the above two parts still exists.
  • the low power design of the error correction differential amplifier itself is not within the scope of the problem addressed by the techniques disclosed herein.
  • the present application proposes an embodiment for reducing the power consumed by the voltage dividing resistor in the low dropout regulated power supply circuit.
  • the power consumption of the low-dropout regulated power supply circuit on the voltage dividing resistor is determined by the reference reference voltage Vref and the resistance value of the positive input terminal of the error correction differential amplifier to the ground (R2).
  • the current flowing through R2 is:
  • Vref The typical value of Vref is 1.0V.
  • the current value set on this branch is 100nA.
  • the technical problem to be solved by the embodiments of the present invention is to provide an ultra-low power low-dropout regulated power supply circuit, and a radio frequency identification tag including the low-dropout regulated power supply circuit, which meets the existing pure-resistance device Under the premise of the circuit performance that can be achieved, the low power consumption and low cost requirements of the low-dropout regulated power supply circuit are realized.
  • An ultra-low power low-dropout regulated power supply circuit comprising an error correction differential amplifier, a MOS transistor, and a first voltage dividing resistor and a second voltage dividing resistor, wherein the negative input terminal of the error correction differential amplifier is connected to a bandgap reference voltage
  • the positive input terminal is grounded through a second voltage dividing resistor, and the output end thereof is connected to the gate of the MOS transistor.
  • the source of the MOS transistor and the input end of the error correction differential amplifier are respectively connected to the input power source, and the drain of the MOS transistor passes through the first A voltage dividing resistor is connected to the positive input of the error correction differential amplifier.
  • the low-dropout regulated power supply circuit further includes a first threshold unit connected between the positive input terminal of the error correction differential amplifier and the first voltage dividing resistor for reducing a voltage difference between the positive input terminal and the voltage output terminal of the error correction differential amplifier;
  • a second threshold unit between the positive input terminal and the second voltage dividing resistor of the error correction differential amplifier for reducing the voltage difference between the positive input terminal and the ground terminal of the error correction differential amplifier.
  • the first threshold unit and the second threshold unit are respectively a series connected diode, or a P-type MOS tube, or an N-type MOS tube, and the diodes serially connected in the first threshold unit and the second threshold unit, Or the number of P-type MOS tubes, or N-type MOS tubes is the same.
  • Another object of embodiments of the present invention is to provide a radio frequency identification tag including the low voltage difference power supply circuit described above.
  • the ultra-low power low-dropout regulated power supply circuit of the present invention uses the first threshold unit and the second threshold unit respectively in the first voltage dividing resistor and the second voltage dividing resistor branch, and utilizes the threshold unit
  • the threshold characteristic inherent to the diode or MOS transistor of the conduction pass, the voltage difference between the positive input terminal and the voltage output terminal of the error correction differential amplifier and the positive input terminal to the ground terminal of the error correction differential amplifier are respectively assumed by the threshold, and then connected in series with The voltage remaining on the resistor can reach a small value, so that the power consumption consumed by the resistor is effectively reduced.
  • the structure of the series connected diode or MOS tube on the resistance branch proposed by the present application can greatly reduce the overall area of the chip, thereby reducing the cost, compared with the conventional structure of using the resistor alone. the goal of.
  • Figure 1 is a circuit diagram of a conventional low-dropout regulated power supply circuit
  • FIG. 2 is a graph showing input-output characteristics of a conventional low-dropout regulated power supply circuit
  • FIG. 3 is a structural diagram of a low-dropout regulated power supply circuit used in the present invention.
  • Embodiment 4 is a structural diagram of Embodiment 1 of a low-dropout regulated power supply circuit used in the present invention
  • Embodiment 2 is a structural diagram of Embodiment 2 of a low-dropout regulated power supply circuit used in the present invention
  • Embodiment 3 is a structural diagram of Embodiment 3 of a low-dropout regulated power supply circuit used in the present invention.
  • Embodiment 7 is a structural diagram of Embodiment 4 of a low-dropout regulated power supply circuit used in the present invention.
  • Embodiment 8 is a structural diagram of Embodiment 5 of a low-dropout regulated power supply circuit used in the present invention.
  • Fig. 9 is a graph showing the input-output characteristic of the low-dropout regulated power supply circuit used in the present invention.
  • FIG. 1 is a circuit diagram of a conventional low-dropout regulated power supply circuit including an error correction differential amplifier AMP, a P-type MOS transistor PM1, and a first voltage dividing resistor R1 and a second voltage dividing resistor R2.
  • the error correction differential amplifier AMP power terminal is connected to the input power source Vin, the negative input terminal is connected to the bandgap reference voltage Vref, the positive input terminal is grounded through the second voltage dividing resistor R2, and the output terminal is connected to the P-type MOS transistor PM1 gate.
  • a P1 MOS transistor PM1 source is connected to the input power source Vin, and a drain is connected to the positive input terminal of the error correction differential amplifier AMP through the first voltage dividing resistor R1, and the drain of the P-type MOS transistor is connected to the drain Low-power difference power supply circuit power output Vout .
  • the low-dropout regulated power supply is characterized by a small difference between the input supply voltage and the output supply voltage. Because of the loop gain of the negative feedback loop, the output supply voltage can maintain good stability without changing the input voltage. Change, its working principle is:
  • the output voltage Vout decreases, that is, the output voltage does not rise with the increase of the input voltage; similarly, when the input voltage Vin decreases, the output voltage Vout rises by the action of the negative feedback loop, that is, the output voltage does not follow the input.
  • the voltage is lowered and lowered, that is, the output power supply voltage maintains good stability without changing with the input voltage, and its input-output characteristic curve is shown in FIG. 2.
  • An ultra-low power low-dropout regulated power supply circuit according to the present invention, the circuit further comprising a first threshold unit connected between the positive input terminal of the error correction differential amplifier AMP and the first voltage dividing resistor R1, and error correction a second threshold unit between the positive input terminal of the differential amplifier AMP and the second voltage dividing resistor R2, as shown in FIG.
  • the first threshold unit and the second threshold unit may be connected in series with a diode or MOS tube having a unidirectional conduction function between the positive input terminal of the error correction differential amplifier AMP and the first voltage dividing resistor R1 and the second voltage dividing resistor R2.
  • the first threshold unit and the unidirectional device connected in the second threshold unit should maintain strict symmetry, ie Not only do the types of unidirectional via devices be the same, but also the number of unidirectional via devices in the two threshold cells is the same.
  • the connection structure is as shown in FIG. 4.
  • the first threshold unit is at least one diode, and the at least one diode cathode end is connected to an adjacent diode anode terminal to form a series structure, and the first diode anode end is connected to the first voltage dividing resistor R1 as the first threshold unit.
  • the second threshold unit is at least one diode, and the at least one diode cathode end is connected to the adjacent diode anode terminal to form a series structure, and the first diode anode end is connected to the error correction differential amplifier AMP positive input end is the second The input terminal of the threshold unit, the last diode cathode end is connected to the second voltage dividing resistor R2 as the output end of the second threshold unit.
  • the number of diodes of the first threshold unit is the same as the number of diodes of the second threshold unit. Since the typical Vref value is 1.2 volts, a very high Vref value is very uncommon, and the threshold voltage of the diode is typically 0.7 volts. When the number of diodes connected in series is equal to or more than two, Vref will appear. If the value is lower than the turn-on voltage of the threshold cell, the threshold cell cannot be turned on. Therefore, the form of more than two diodes is only present in the case where the rare Vref value is high.
  • a diode D1 and a D2 are connected in series in the first threshold unit and the second threshold unit, respectively.
  • the connection structure is as shown in FIG. 5.
  • the first threshold unit is at least one P-type MOS transistor, and the drain terminal of the at least one P-type MOS transistor is connected to a source terminal of an adjacent P-type MOS transistor to form a series structure, and a gate of each P-type MOS transistor is connected thereto.
  • a drain, a source of the first P-type MOS transistor is connected to the first voltage dividing resistor R1 as an input terminal of the first threshold unit, and a drain of the last P-type MOS transistor is connected to an error correction differential amplifier AMP
  • the positive input terminal is an output end of the first threshold unit;
  • the second threshold unit is at least one P-type MOS transistor, and the drain terminal of the at least one P-type MOS transistor is connected to a source terminal of an adjacent P-type MOS transistor to form a series structure, and a gate of each P-type MOS transistor is connected thereto.
  • a drain, a source of the first P-type MOS transistor is connected to an error-correcting differential amplifier AMP, a positive input terminal is an input end of the second threshold unit, and a drain of the last P-type MOS transistor is connected to a second branch
  • the voltage resistor R2 is the output of the second threshold unit.
  • the number of P-type MOS transistors of the first threshold unit is the same as the number of P-type MOS transistors of the second threshold unit. Since the typical Vref value is 1.2 volts, a very high Vref value is very uncommon, and the threshold voltage of a P-type MOS transistor is typically 0.7 volts, when the number of P-type MOS transistors connected in series is equal to or more than two. When the Vref value is lower than the turn-on voltage of the threshold cell, the threshold cell cannot be turned on. Therefore, the form of the number of more than two P-type MOS tubes is only present in the case where the Vref value is not high.
  • the embodiment of the present invention connects a P-type MOS tube PM2 in series with the first threshold unit and the second threshold unit, respectively. Take PM3 as an example, as shown in Figure 5.
  • the drain terminals of the P-type MOS transistors are connected to the source terminals of the adjacent P-type MOS transistors to form a series structure
  • the first The source of the P-type MOS transistor is connected to the first voltage dividing resistor R1 as an input end of the first threshold unit
  • the drain of the last P-type MOS transistor is connected to the positive input terminal of the error correction differential amplifier AMP.
  • the output of the first threshold unit The gates of the P-type MOS transistors are connected to the drain of the last P-type MOS transistor; when a plurality of P-type MOS transistors are connected in series in the second threshold unit, the drain terminals of the P-type MOS transistors and the adjacent P-type MOS
  • the source terminal of the tube is connected to form a series structure, and the source of the first P-type MOS transistor is connected to the positive input terminal of the error correction differential amplifier AMP as the input end of the second threshold unit, and the drain of the last P-type MOS tube
  • the pole is connected to the second voltage dividing resistor R2 as an output terminal of the second threshold unit, and the gates of the P-type MOS transistors are all connected to the drain of the last P-type MOS transistor.
  • connection structure in which a plurality of P-type MOS transistor source and drain are connected in series, and all MOS transistor gates are connected to the drain of the last P-type MOS transistor, actually forms a MOS transistor of an ultra-long channel size, and its threshold value
  • the voltage is still only 0.7 volts, but its resistance is worth increasing, so that the current value becomes smaller, achieving the purpose of reducing power consumption.
  • the number of P-type MOS transistors of the first threshold unit is the same as the number of P-type MOS transistors of the second threshold unit, as shown in FIG. 6.
  • the connection structure is as shown in FIG. 7.
  • the first threshold unit is at least one N-type MOS transistor, and the source terminal of the at least one N-type MOS transistor is connected to a drain terminal of an adjacent N-type MOS transistor to form a series structure, and a gate of each N-type MOS transistor is connected thereto.
  • a drain, a drain of the first N-type MOS transistor is connected to the first voltage dividing resistor R1 as an input terminal of the first threshold unit, and a source of the last N-type MOS transistor is connected to an error correction differential amplifier AMP
  • the positive input terminal is an output end of the first threshold unit;
  • the second threshold unit is at least one N-type MOS transistor, and the at least one N-type MOS tube source terminal is connected to the drain terminal of the adjacent N-type MOS tube to form a series structure, and the gate of each N-type MOS tube is connected thereto.
  • a drain, a drain of the first N-type MOS transistor is connected to an error-correcting differential amplifier AMP, a positive input terminal is an input end of the second threshold unit, and a source of the last N-type MOS transistor is connected to a second branch
  • the voltage resistor R2 is the output of the second threshold unit.
  • the number of N-type MOS transistors of the first threshold unit is the same as the number of N-type MOS tubes of the second threshold unit. Since the typical Vref value is 1.2 volts, a very high Vref value is very uncommon, and the threshold voltage of an N-type MOS transistor is typically 0.7 volts, when the number of N-type MOS transistors connected in series is equal to or more than two. When the Vref value is lower than the turn-on voltage of the threshold cell, the threshold cell cannot be turned on. Therefore, the form of the number of the more than two types of N-type MOS tubes is only present in the case where the Vref value is not high.
  • the embodiment of the present invention is to connect an N-type MOS tube NM1 in the first threshold unit and the second threshold unit, respectively. Take NM2 as an example, as shown in Figure 7.
  • the source terminals of the N-type MOS transistors are connected to the drain terminals of the adjacent N-type MOS transistors to form a series structure
  • the first The drain of the N-type MOS transistor is connected to the first voltage dividing resistor R1 as an input terminal of the first threshold unit
  • the source of the last N-type MOS transistor is connected to the positive input terminal of the error correction differential amplifier AMP.
  • An output terminal of the first threshold unit, a gate of each N-type MOS transistor is connected to a drain of the first N-type MOS transistor; and when a plurality of N-type MOS transistors are serially connected in the second threshold unit, each N-type MOS
  • the tube source terminal is connected to the drain terminal of the adjacent N-type MOS transistor to form a series structure, and the drain of the first N-type MOS transistor is connected to the error-correcting differential amplifier AMP.
  • the positive input terminal is the input terminal of the second threshold unit.
  • the source of the last N-type MOS transistor is connected to the second voltage dividing resistor R2 as the output end of the second threshold unit, and the gates of the N-type MOS transistors are connected to the drain of the first N-type MOS transistor ;
  • connection structure in which a plurality of N-type MOS transistor source and drain are connected in series, and all MOS transistor gates are connected to the drain of the first N-type MOS transistor, actually forms an MOS transistor having an ultra-long channel size,
  • the threshold voltage is still only 0.7 volts, but its resistance is worth increasing, so that the current value becomes smaller, achieving the purpose of reducing power consumption.
  • the number of N-type MOS transistors of the first threshold unit is the same as the number of N-type MOS tubes of the second threshold unit, as shown in FIG.
  • FIG. 9 is a graph showing an input-output characteristic of a low-dropout regulated power supply circuit used in the present invention. It can be seen from the input-output characteristic curve that when the Vref value is higher than the turn-on voltage of the threshold unit to turn on the threshold unit,
  • the input-input characteristic curve of the low-dropout regulated power supply circuit used in the present invention is completely the same as the input-output characteristic curve of the existing low-dropout regulated power supply circuit shown in FIG. 2, that is, in the first voltage dividing resistor and the second
  • the structure in which the voltage dividing resistor branches are respectively connected in series with the first threshold unit and the second threshold unit does not have any influence on the performance of the low dropout power supply circuit.
  • the threshold unit device when an external constant current flows through the threshold unit device, the threshold unit device can enter the subthreshold region, the linear region, and the saturation according to the magnitude of the external constant current.
  • the field covered by this application is in the field of ultra low power RFID tag chips in which the current is on the order of less than 1 uA, in which the threshold cell device is in the subthreshold region.
  • the following analysis focuses on the impedance equivalence of threshold cell devices in the subthreshold region.
  • the equivalent resistance of the diode is the voltage difference across its PN junction divided by the current flowing through the PN junction.
  • the current flowing through the PN junction is a constant current input from the external PN junction, and the typical current of one branch in the ultra-low power passive RFID tag chip is 100 nA.
  • the voltage difference across the PN junction is the threshold turn-on voltage of the PN junction.
  • the typical value is 0.7V
  • the 7 megaohm resistance diode can be 2 microns square, or 4 square microns.
  • the equivalent resistance of the triode is the voltage difference between the source and the drain terminal divided by the current flowing in the channel formed between the source and the drain.
  • the gate of the triode is shorted to the drain, that is, the triode is connected in the form of a diode, and the current flowing in the channel formed between the source and the drain of the triode is a constant current input from the external, super
  • a typical current in a branch of a low-power passive RFID tag chip is 100nA.
  • the voltage difference between the source and the drain is the threshold conduction voltage of the MOS transistor due to its special diode connection.
  • the typical value is 0.7V.
  • the channel size of the 7 mega ohm triode can be 1 micron by 0.18 micron, or 0.18 square micron, in a 0.18 micron logic process.
  • a resistor made of ordinary polysilicon material is used to achieve a resistance of 7 megaohms, it will occupy 1.75 ⁇ 10 5 square micrometers, that is, the area occupied by the triode with a resistance of 7 megaohms is 7 megabytes relative to the resistance.
  • the area occupied by ohmic resistors is almost negligible. It can be concluded that under the premise of using the triode and the resistor to achieve the same function and consuming the same amount of power consumption, the circuit area occupied by the triode will be greatly reduced, thereby reducing the overall production cost of the chip.

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Abstract

一种超低功耗的低压差稳压电源电路及射频识别标签。该电路通过在第一分压电阻（R1）和第二分压电阻（R2）支路分别串接第一阈值单元和第二阈值单元，利用阈值单元内单向导通的二极管或MOS管所固有的阈值特性，纠错差分放大器的正输入端到电压输出端（Vout）以及纠错差分放大器的正输入端到地线端的电压差分别被该阈值单元所承担，则在与其串联的电阻上所剩的电压可以达到较小的数值，使得电阻上消耗的功耗得到了有效的降低。同时，在功耗相同的条件下，与常规的单独使用电阻的结构相比，釆用在电阻支路上串接二极管或MOS管的结构可大大缩小芯片的整体面积，从而达到降低成本的目的。

Description

一种超低功耗的低压差稳压电源电路与射频识别标签 技术领域
本发明涉及射频识别技术领域，具体是指一种超低功耗的低压差稳压电源电路，以及包含该低压差稳压电源电路的射频识别标签。
 背景技术
低压差稳压电源（Low Dropout Regulator，LDO）电路模块广泛运用在集成电路芯片领域，其主要作用是通过一个高增益的纠错差分放大器，一个功率管，和一个负反馈环路对输入的电源电压进行稳压，并输出稳压后的电源电压，并在负反馈环路单位增益带宽的频率范围内对输入电源所带来的扰动以及噪音进行有效的抑制，从而提供较为理想的电源给芯片上的负载，其电路结构图如图1所示。
低压差稳压电源的特点是当输入电源电压降低到与输出电源电压相差很小时，因为负反馈环路的环路增益作用，输出电源电压能够保持较好的稳定性而不随输入电压的变化而变化，这对于用电池供电的移动设备来说尤为重要。
低压差稳压电源电路输出的电压值(Vout)由纠错差分放大器负输入端所输入的参考基准电压（Vref），和低压差稳压电源电路输出端到纠错差分放大器正输入端的电阻值（R1）与纠错差分放大器正输入端的电阻值到地线的电阻值(R2)的比值所决定，即
Vout = Vref•(1+R1/R2)
低压差稳压电源电路是无源射频识别(Radio Frequency Identification，RFID)标签芯片中不可或缺的一部分。无源RFID标签本身不带电池，其依靠读卡器发送的电磁能量工作。由于它结构简单、经济实用，因而其在物流管理、资产追踪以及移动医疗领域获得了广泛的应用。
无源RFID标签工作时，其会从周围环境中吸收读卡器发送的电磁能量。无源RFID标签在吸收能量之后，将一部分能量整流为直流电源，该直流电源作为输入信号输入到低压差稳压电源电路模块中，稳压之后的电源输出供无源RFID标签内部电路工作；无源RFID标签还将另一部分能量输入内部的调制解调电路。调制解调电路会对该能量中携带的幅度调制信号进行解调，并将解调后的信号发送给无源RFID标签的数字基带部分处理。由于无源RFID标签没有电池供电的特点，其消耗的功耗需要达到极其微小的程度才可以工作，这对无源RFID标签芯片上所有电路模块的设计提出了较高的低功耗设计要求。
低压差稳压电源电路的功耗大致消耗在纠错差分放大器，以及分压电阻（R1和 R2）上。当该低压差稳压电源电路驱动的负载电流达到最小，即零负载的情况下，上述两个部分的功率消耗仍然存在。纠错差分放大器本身的低功耗设计不在本申请所公开的技术所解决的问题范畴。本申请提出了一种降低低压差稳压电源电路中分压电阻上消耗的功率的实施方案。
低压差稳压电源电路在分压电阻上的功率消耗是由参考基准电压Vref和纠错差分放大器正输入端的电阻值到地线的电阻值(R2)来决定的。R2上流过的电流为：
IR2=Vref / R2
其中Vref选取的典型值为1.0V,在无源RFID标签中为了达到低功耗的要求,如果在这条支路上设定的电流值为100nA, 那么需要的电阻R2会是1.0V/100nA=10兆欧姆。例如在0.18微米的逻辑工艺上，普通的多晶硅电阻的方块阻值为10欧姆/方块，R2=10兆欧姆的电阻将会占用100万个方块。如果该低压差稳压电源的输出电压设定在1.8伏，R1=8兆欧姆，即R1电阻需要超过80万个方块。根据0.18微米工艺的电阻最小宽度500纳米，上述180万个方块的总和将会占用0.5um*0.5um*1800000=0.45平方毫米的面积。如果考虑到消除工艺偏差带来的非理想因素，上述180万个方块的单位尺寸会选取比最小的500纳米更大的尺寸，那么在两个电阻上的面积总和将会成倍增加，使得该低压差稳压电源电路的设计达不到低成本的设计要求。
 技术问题
本发明实施例所要解决的技术问题在于，提供一种超低功耗的低压差稳压电源电路，以及包含该低压差稳压电源电路的射频识别标签，在满足现有的用纯电阻器件所能达到的电路性能前提下，实现了低压差稳压电源电路所需要达到的低功耗和低成本要求。
 技术解决方案
为实现上述目的，本发明所采取的技术方案为：
一种超低功耗的低压差稳压电源电路，包括纠错差分放大器、MOS管以及第一分压电阻和第二分压电阻，所述纠错差分放大器负输入端连接至带隙基准电压，其正输入端通过第二分压电阻接地，其输出端连接至MOS管栅极，所述MOS管源极与纠错差分放大器电源输入端分别连接至输入电源，MOS管漏极通过第一分压电阻连接至纠错差分放大器正输入端，
所述低压差稳压电源电路还包括连接至纠错差分放大器正输入端与第一分压电阻之间的第一阈值单元，用于降低纠错差分放大器正输入端到电压输出端的电压差；
及纠错差分放大器正输入端与第二分压电阻之间的第二阈值单元，用于降低纠错差分放大器正输入端到地线端的电压差。
所述第一阈值单元与第二阈值单元分别为串接的二极管，或P型MOS管，又或者是N型MOS管，且所述第一阈值单元与第二阈值单元内串接的二极管，或P型MOS管，或N型MOS管数量相同。
本发明实施例的另一目的在于提供一种包括上述低压差稳压电源电路的射频识别标签。
 有益效果
本发明所述一种超低功耗的低压差稳压电源电路通过在第一分压电阻和第二分压电阻支路分别串接第一阈值单元和第二阈值单元，利用阈值单元内单向导通的二极管或MOS管所固有的阈值特性，纠错差分放大器正输入端到电压输出端以及纠错差分放大器正输入端到地线端的电压差分别被该阈值所承担，则在与其串联的电阻上所剩的电压可以达到较小的数值，使得电阻上消耗的功耗得到了有效的降低。同时，在功耗相同的条件下，采用本申请所提出的在电阻支路上串接二极管或MOS管的结构较之常规的单独使用电阻的结构，可大大缩小芯片的整体面积，从而达到降低成本的目的。
 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有低压差稳压电源电路结构图；
图2是现有低压差稳压电源电路输入-输出特性曲线图；
图3是本发明采用的低压差稳压电源电路结构图；
图4是本发明采用的低压差稳压电源电路实施例一结构图；
图5是本发明采用的低压差稳压电源电路实施例二结构图；
图6是本发明采用的低压差稳压电源电路实施例三结构图；
图7是本发明采用的低压差稳压电源电路实施例四结构图；
图8是本发明采用的低压差稳压电源电路实施例五结构图；
图9是本发明采用的低压差稳压电源电路输入-输出特性曲线图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示为现有低压差稳压电源电路结构图，该低压差稳压电源电路包括纠错差分放大器AMP、P型MOS管PM1以及第一分压电阻R1和第二分压电阻R2，所述纠错差分放大器AMP电源端连接至输入电源Vin，其负输入端连接至带隙基准电压Vref，正输入端通过第二分压电阻R2接地，输出端连接至P型MOS管PM1栅极，所述P型MOS管PM1源极连接至输入电源Vin，漏极通过第一分压电阻R1连接至纠错差分放大器AMP正输入端,同时，该P型MOS管的漏极连接至该低压差稳压电源电路的电源输出端Vout 。
低压差稳压电源的特点是当输入电源电压降低到与输出电源电压相差很小时，因为负反馈环路的环路增益作用，输出电源电压能够保持较好的稳定性而不随输入电压的变化而变化，其工作原理为：
当输入电压Vin升高时，流过P型MOS管PM1的电流升高，则第一分压电阻R1两端的电压升高，使纠错差分放大器AMP正输入端的电压值升高，经过该纠错差分放大器AMP放大作用后其输出端的电压升高，即P型MOS管PM1的栅极电压升高，使P型MOS管PM1的栅源电压VGS降低，则流过P型MOS管PM1的电流降低，输出电压Vout降低，即输出电压不随输入电压升高而升高；同理，当输入电压Vin降低时，经过该负反馈环路的作用，使输出电压Vout升高，即输出电压不随输入电压降低而降低，即输出电源电压保持较好的稳定性而不随输入电压的变化而变化，其输入输出特性曲线如图2所示。
该低压差稳压电源电路中，第二分压电阻R2上的电流为:IR2=Vref/R2,
电阻R2的功率为：PR2= Vref 2/R2,
第一分压电阻R1上的电流为:IR1= IR2=Vref/R2,
电阻R1的功率为：PR1= IR1 2•R1= Vref 2•R1/R22。
由上述可以看出，若要降低第二分压电阻R2的功耗，则必须增大电阻R2的阻抗。根据Vout = Vref•(1+R1/R2)，在Vout 和 Vref保持不变的前提下，增大电阻R2的阻抗，则必须增大第一分压电阻R1的阻抗，增大电阻R1及电阻R2的阻抗导致的直接原因就是增大了芯片的整体面积，导致生产成本增加。
本发明所述一种超低功耗的低压差稳压电源电路，该电路还包括连接至纠错差分放大器AMP正输入端与第一分压电阻R1之间的第一阈值单元，及纠错差分放大器AMP正输入端与第二分压电阻R2之间的第二阈值单元,如图3所示，利用第一阈值单元及第二阈值单元内单向导通元器件所固有的阈值特性，纠错差分放大器AMP正输入端到电压输出端Vout的电压差以及纠错差分放大器AMP正输入端到地线端的电压差分别被该阈值所承担，则在与其串联的电阻上所剩的电压差可以降低到较小的数值，即电阻上消耗的功耗得到了有效的降低，而无需通过增大电阻阻抗的方式来达到降低功耗的目的。上述理论用公式表述如下：
第二分压电阻R2上的电流为:IR2=(Vref-Vth）/R2,
电阻R2的功率为：PR2= (Vref-Vth）2/R2，
第一分压电阻R1上的电流为:IR1= IR2=(Vref-Vth）/R2，
电阻R1的功率为：PR1= IR1 2•R1= (Vref-Vth）2•R1/R22。
所述第一阈值单元及第二阈值单元可采用具有单向导通功能的二极管或MOS管串联连接于纠错差分放大器AMP正输入端与第一分压电阻R1和第二分压电阻R2之间，为消除单向导通器件的阈值电压随工艺参数波动和温度漂移所带来的影响，所述第一阈值单元与第二阈值单元内所连接的单向导通器件应保持严格的对称性，即不但要求单向导通器件的类型相同，还需保证两个阈值单元内单向导通器件的数量也相同。
当所述阈值单元采用的单向导通器件为至少一个二极管时，其连接结构如图4所示。
所述第一阈值单元为至少一个二极管，所述至少一个二极管阴极端与相邻二极管阳极端连接形成串联结构，第一个二极管阳极端连接至第一分压电阻R1为所述第一阈值单元的输入端，最后一个二极管阴极端连接至纠错差分放大器AMP正输入端为所述第一阈值单元的输出端；
所述第二阈值单元为至少一个二极管，所述至少一个二极管阴极端与相邻二极管阳极端连接形成串联结构，第一个二极管阳极端连接至纠错差分放大器AMP正输入端为所述第二阈值单元的输入端，最后一个二极管阴极端连接至第二分压电阻R2为所述第二阈值单元的输出端。
所述第一阈值单元的二极管数量与第二阈值单元的二极管数量相同。由于典型的Vref值为1.2伏，很高的Vref数值是很不常见的，并且二极管的阈值电压典型的值为0.7伏，当串接的二极管数量等于或多于两个时，便会出现Vref值低于阈值单元的导通电压的情况，导致阈值单元无法导通。所以多于两个二极管数量的形式仅仅存在于不多见的Vref数值很高的情况，本发明实施例以分别在第一阈值单元及第二阈值单元串接一个二极管D1和D2为例，如图4。
当所述阈值单元采用的单向导通器件为至少一个P型MOS管时，其连接结构如图5所示。
所述第一阈值单元为至少一个P型MOS管，所述至少一个P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，各P型MOS管的栅极连接至其漏极，第一个所述P型MOS管的源极连接至第一分压电阻R1为所述第一阈值单元的输入端，最后一个P型MOS管的漏极连接至纠错差分放大器AMP正输入端为所述第一阈值单元的输出端；
所述第二阈值单元为至少一个P型MOS管，所述至少一个P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，各P型MOS管的栅极连接至其漏极，第一个所述P型MOS管的源极连接至纠错差分放大器AMP正输入端为所述第二阈值单元的输入端，最后一个P型MOS管的漏极连接至第二分压电阻R2为所述第二阈值单元的输出端。
所述第一阈值单元的P型MOS管数量与第二阈值单元的P型MOS管数量相同。由于典型的Vref值为1.2伏，很高的Vref数值是很不常见的，并且P型MOS管的阈值电压典型的值为0.7伏，当串接的P型MOS管数量等于或多于两个时，便会出现Vref值低于阈值单元的导通电压的情况，导致阈值单元无法导通。所以多于两个P型MOS管数量的形式仅仅存在于不多见的Vref数值很高的情况，本发明实施例以分别在第一阈值单元及第二阈值单元串接一个P型MOS管PM2和PM3为例，如图5。
作为本发明的又一实施例，当第一阈值单元内串接多个P型MOS管时，各P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，第一个所述P型MOS管的源极连接至第一分压电阻R1为所述第一阈值单元的输入端，最后一个P型MOS管的漏极连接至纠错差分放大器AMP正输入端为所述第一阈值单元的输出端, 各P型MOS管的栅极均连接至最后一个P型MOS管的漏极；当第二阈值单元内串接多个P型MOS管时，各P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，第一个所述P型MOS管的源极连接至纠错差分放大器AMP正输入端为所述第二阈值单元的输入端，最后一个P型MOS管的漏极连接至第二分压电阻R2为所述第二阈值单元的输出端，各P型MOS管的栅极均连接至最后一个P型MOS管的漏极。
上述采用多个P型MOS管源漏极串接，所有MOS管栅极连接至最后一个P型MOS管漏极的连接结构，实际上是形成了一个超长沟道尺寸的MOS管，其阈值电压仍然只有0.7伏，但是其电阻值得以增加，从而使得电流值变小，达到降低功耗的目的。并且，所述第一阈值单元的P型MOS管数量与第二阈值单元的P型MOS管数量相同，如图6所示。
当所述阈值单元采用的单向导通器件为至少一个N型MOS管时，其连接结构如图7所示。
所述第一阈值单元为至少一个N型MOS管，所述至少一个N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，各N型MOS管的栅极连接至其漏极，第一个所述N型MOS管的漏极连接至第一分压电阻R1为所述第一阈值单元的输入端，最后一个N型MOS管的源极连接至纠错差分放大器AMP正输入端为所述第一阈值单元的输出端；
所述第二阈值单元为至少一个N型MOS管，所述至少一个N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，各N型MOS管的栅极连接至其漏极，第一个所述N型MOS管的漏极连接至纠错差分放大器AMP正输入端为所述第二阈值单元的输入端，最后一个N型MOS管的源极连接至第二分压电阻R2为所述第二阈值单元的输出端。
所述第一阈值单元的N型MOS管数量与第二阈值单元的N型MOS管数量相同。由于典型的Vref值为1.2伏，很高的Vref数值是很不常见的，并且N型MOS管的阈值电压典型的值为0.7伏，当串接的N型MOS管数量等于或多于两个时，便会出现Vref值低于阈值单元的导通电压的情况，导致阈值单元无法导通。所以多于两个N型MOS管数量的形式仅仅存在于不多见的Vref数值很高的情况，本发明实施例以分别在第一阈值单元及第二阈值单元串接一个N型MOS管NM1和NM2为例，如图7。
作为本发明的又一实施例，当第一阈值单元内串接多个N型MOS管时，各N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至第一分压电阻R1为所述第一阈值单元的输入端，最后一个N型MOS管的源极连接至纠错差分放大器AMP正输入端为所述第一阈值单元的输出端，各N型MOS管的栅极均连接至第一个N型MOS管的漏极；当第二阈值单元内串接多个N型MOS管时，各N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至纠错差分放大器AMP正输入端为所述第二阈值单元的输入端，最后一个N型MOS管的源极连接至第二分压电阻R2为所述第二阈值单元的输出端，各N型MOS管的栅极均连接至第一个N型MOS管的漏极；
上述采用多个N型MOS管源漏极串接，所有MOS管栅极连接至第一个N型MOS管漏极的连接结构，实际上是形成了一个超长沟道尺寸的MOS管，其阈值电压仍然只有0.7伏，但是其电阻值得以增加，从而使得电流值变小，达到降低功耗的目的。并且，所述第一阈值单元的N型MOS管数量与第二阈值单元的N型MOS管数量相同，如图8所示。
图9是本发明采用的低压差稳压电源电路的输入-输出特性曲线图，由该输入-输出特性曲线可看出，当Vref值高于阈值单元的导通电压使阈值单元导通时，本发明采用的低压差稳压电源电路的输入-输入特性曲线完全相同于图2中示出的现有低压差稳压电源电路的输入-输出特性曲线，即在第一分压电阻和第二分压电阻支路分别串接第一阈值单元和第二阈值单元的结构对低压差稳压电源电路的性能不会产生任何的影响。
根据单向导通器件（如二极管或者三极管）的阈值特性，当有外部恒定电流流过该阈值单元器件时，根据该外部恒定电流的大小，可使阈值单元器件进入亚阈值区、线性区和饱和区三种不同的工作区域。本申请所涉及的领域为超低功耗射频识别标签芯片领域，电路中电流为小于1uA的数量级，在该数量级的电流环境下，阈值单元器件处于亚阈值区。以下分析重点阐述阈值单元器件在亚阈值区的阻抗等效性。
以二极管为例，二极管的等效电阻为其P-N结两端的电压差除以流过P-N结的电流。本申请所用的二极管连接方式中，P-N结流过的电流为P-N结外部输入的恒定电流，超低功耗的无源射频识别标签芯片中一个支路的典型电流为100nA。当外部电流流过P-N结的时候，其造成P-N结两端的电压差即为该P-N结的阈值导通电压，典型值为0.7V，则该二极管的等效电阻为 0.7V / 100nA = 7 兆欧姆。在0.18微米的逻辑工艺上，该7兆欧姆电阻值的二极管的尺寸可以为2微米见方，即4平方微米的面积。作为对比，如果用普通的多晶硅材料做的电阻，要达到７兆欧姆的电阻值，以其典型的10欧姆／方块的方块电阻值，必须有70万个电阻方块。如果取500纳米作为电阻方块的边长尺寸，70万个电阻方块将占用 700000*500纳米*500纳米＝1.75X105平方微米，即阻值为7兆欧姆的二极管所占用的面积相对于阻值为7兆欧姆的电阻所占用的面积几乎可以忽略不计。由此可以得出，在分别采用二极管和电阻实现相同的功能，消耗相同大小的功耗的前提下，用二极管所占用的电路面积将被大大缩小，从而降低了芯片整体的生产成本。
以三极管为例，三极管的等效电阻为其源极漏极端的电压差除以源极漏极之间形成的沟道中所流过的电流值。本申请中，三极管的栅极与漏极短接，即三极管采用的是二极管形式的连接方式，则三极管源极漏极之间形成的沟道中所流过的电流为外部输入的恒定电流，超低功耗的无源射频识别标签芯片中一个支路的典型电流为100nA。当外部电流流过沟道时，由于其特殊的二极管形式的连接方式，源极与漏极之间的电压差即为该MOS 管的阈值导通电压，典型值为0.7V。于是该MOS管的等效电阻即为0.7V / 100 nA =7兆欧姆。在0.18微米的逻辑工艺上，该7兆欧姆三极管的沟道尺寸可以为1微米×0.18微米，即0.18平方微米的面积。作为对比，如果用普通的多晶硅材料做的电阻，要达到７兆欧姆的电阻值，将占用1.75X105平方微米，即阻值为7兆欧姆的三极管所占用的面积相对于阻值为7兆欧姆的电阻所占用的面积几乎可以忽略不计。由此可以得出，在分别采用三极管和电阻实现相同的功能，消耗相同大小的功耗的前提下，用三极管所占用的电路面积将被大大缩小，从而降低了芯片整体的生产成本。

Claims (7)

  1. 一种超低功耗的低压差稳压电源电路，包括纠错差分放大器、MOS管以及第一分压电阻和第二分压电阻，所述纠错差分放大器负输入端连接至带隙基准电压，所述纠错差分放大器正输入端通过第二分压电阻接地，所述纠错差分放大器输出端连接至MOS管栅极，所述MOS管源极与纠错差分放大器电源输入端分别连接至输入电源，MOS管漏极通过第一分压电阻连接至纠错差分放大器正输入端，其特征在于，
    所述低压差稳压电源电路还包括连接至纠错差分放大器正输入端与第一分压电阻之间的第一阈值单元，用于降低纠错差分放大器正输入端到电压输出端的电压差；
    及纠错差分放大器正输入端与第二分压电阻之间的第二阈值单元，用于降低纠错差分放大器正输入端到地线端的电压差。
  2. 根据权利要求1所述的超低功耗的低压差稳压电源电路，其特征在于，所述第一阈值单元为至少一个二极管，所述至少一个二极管中、任一二极管阴极端与相邻二极管阳极端连接形成串联结构，第一个二极管阳极端连接至所述第一分压电阻并作为所述第一阈值单元的输入端，最后一个二极管阴极端连接至所述纠错差分放大器正输入端并作为所述第一阈值单元的输出端；
    所述第二阈值单元为至少一个二极管，所述第二阈值单元的所述至少一个二极管中、任一阴极端与相邻二极管阳极端连接形成串联结构，第一个二极管阳极端连接至所述纠错差分放大器正输入端并作为所述第二阈值单元的输入端，最后一个二极管阴极端连接至所述第二分压电阻并作为所述第二阈值单元的输出端；
    且所述第一阈值单元的二极管数量与第二阈值单元的二极管数量相同。
  3. 根据权利要求1所述的超低功耗的低压差稳压电源电路，其特征在于，所述第一阈值单元为至少一个P型MOS管，所述至少一个P型MOS管中、任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，各P型MOS管的栅极连接至其漏极，第一个所述P型MOS管的源极连接至所述第一分压电阻并作为所述第一阈值单元的输入端，最后一个P型MOS管的漏极连接至所述纠错差分放大器正输入端并作为所述第一阈值单元的输出端；
    所述第二阈值单元为至少一个P型MOS管，所述第二阈值单元的至少一个P型MOS管中、任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，各P型MOS管的栅极连接至其漏极，第一个所述P型MOS管的源极连接至所述纠错差分放大器正输入端为所述第二阈值单元的输入端，最后一个P型MOS管的漏极连接至所述第二分压电阻并作为所述第二阈值单元的输出端；
    且所述第一阈值单元的P型MOS管数量与第二阈值单元的P型MOS管数量相同。
  4. 根据权利要求1所述的超低功耗的低压差稳压电源电路，其特征在于，所述第一阈值单元为至少一个P型MOS管，所述至少一个P型MOS管中、任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，第一个所述P型MOS管的源极连接至所述第一分压电阻并作为所述第一阈值单元的输入端，最后一个P型MOS管的漏极连接至所述纠错差分放大器正输入端并作为所述第一阈值单元的输出端, 各P型MOS管的栅极均连接至最后一个P型MOS管的漏极；
    所述第二阈值单元为至少一个P型MOS管，所述第二阈值单元的至少一个P型MOS管中、任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，第一个所述P型MOS管的源极连接至所述纠错差分放大器正输入端并作为所述第二阈值单元的输入端，最后一个P型MOS管的漏极连接至所述第二分压电阻并作为所述第二阈值单元的输出端，各P型MOS管的栅极均连接至最后一个P型MOS管的漏极；
    且所述第一阈值单元的P型MOS管数量与第二阈值单元的P型MOS管数量相同。
  5. 根据权利要求1所述的超低功耗的低压差稳压电源电路，其特征在于，所述第一阈值单元为至少一个N型MOS管，所述至少一个N型MOS管中、任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，各N型MOS管的栅极连接至其漏极，第一个所述N型MOS管的漏极连接至所述第一分压电阻并作为所述第一阈值单元的输入端，最后一个N型MOS管的源极连接至所述纠错差分放大器正输入端并作为所述第一阈值单元的输出端；
    所述第二阈值单元为至少一个N型MOS管，所述第二阈值单元的至少一个N型MOS管中、任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，各N型MOS管的栅极连接至其漏极，第一个所述N型MOS管的漏极连接至所述纠错差分放大器正输入端并作为所述第二阈值单元的输入端，最后一个N型MOS管的源极连接至所述第二分压电阻并作为所述第二阈值单元的输出端；
    且所述第一阈值单元的N型MOS管数量与第二阈值单元的N型MOS管数量相同。
  6. 根据权利要求1所述的超低功耗的低压差稳压电源电路，其特征在于，所述第一阈值单元为至少一个N型MOS管，所述至少一个N型MOS管中、任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至所述第一分压电阻并作为所述第一阈值单元的输入端，最后一个N型MOS管的源极连接至所述纠错差分放大器正输入端并作为所述第一阈值单元的输出端，各N型MOS管的栅极均连接至第一个N型MOS管的漏极；
    所述第二阈值单元为至少一个N型MOS管，所述第二阈值单元的至少一个N型MOS管中、任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至所述纠错差分放大器正输入端并作为所述第二阈值单元的输入端，最后一个N型MOS管的源极连接至所述第二分压电阻并作为所述第二阈值单元的输出端，各N型MOS管的栅极均连接至第一个N型MOS管的漏极；
    且所述第一阈值单元的N型MOS管数量与第二阈值单元的N型MOS管数量相同。
  7. 一种射频识别标签，其特征在于，所述射频识别标签包括如权利要求1-6中任一所述的超低功耗的低压差稳压电源电路。
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