Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
  • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
  • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/005—Processes
  • H01L33/0093—Wafer bonding; Removal of the growth substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
  • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
  • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
  • H01L33/40—Materials therefor
  • H01L33/42—Transparent materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
  • H01L33/52—Encapsulations
  • H01L33/54—Encapsulations having a particular shape

Definitions

• Embodiments of the present invention relate to the field of integrated circuit design and manufacture. More specifically, embodiments of the present invention relate to systems and methods for high performance light emitting diodes with vias.
• LEDs Light emitting diodes
• area-illumination applications for example, architectural lighting, residential illumination, industrial lighting, outdoor lighting, theatrical lighting and the like.
• Conventional light emitting diodes typically have electrical contacts facing in the same direction, e.g., away from a substrate.
• LEDs may have electrical contacts at two different levels, e.g., in a "stair TSRA-02012-1003/ACM/NAO 1 step" arrangement. However, the electrical contacts are still typically facing in the same direction.
• an article of manufacture includes a light emitting diode.
• the light emitting diode includes a plurality of filled vias configured to connect a doped region on one side of the light emitting diode to a plurality of contacts on the other side of the light emitting diode.
• the filled vias may comprise less that 10% of a surface area of the light emitting diode.
• a light emitting diode apparatus includes an n- doped semiconductor region, a multiple quantum well (MQW) region disposed on said n- doped semiconductor region and a p-doped semiconductor region disposed on said MQW.
• MQW multiple quantum well
• the apparatus also includes a plurality of filled vias through TSRA-02012-1003/ACM/NAO 3 said p- doped semiconductor region and through said MQW region, contacting said n-doped semiconductor region. Both terminals of said light emitting diode apparatus are on the same side of said light emitting diode apparatus as said p- doped semiconductor region.
• an apparatus in accordance with yet another embodiment of the present invention, includes a light emitting diode.
• the light emitting diode includes an n-doped semiconductor region, a multiple quantum well (MQW) region disposed on said n-doped semiconductor region and a p-doped semiconductor region disposed on said MQW region.
• the apparatus includes a plurality of filled vias through said p-doped
• the apparatus further includes a conductive pattern supported by said carrier substrate and metal for electrically coupling said plurality of filled vias to said conductive pattern.
• the carrier substrate may be configured to couple thermal energy away from said light emitting diode.
• FIG. 1A illustrates a high performance light emitting diode (LED) with vias, in accordance with embodiments of the present invention.
• Figure IB illustrates a high performance light emitting diode (LED) with vias 101, in accordance with additional embodiments of the present invention.
• FIG. 1C illustrates a high performance light emitting diode (LED) with vias 102, in accordance with further embodiments of the present invention.
• LED light emitting diode
• Figures 2A, 2B, 2C, 2D, 2E, 2F and 2G illustrate an exemplary process for forming a light emitting diode sub-assembly, in accordance with
• Figures 3A, 3B, 3C, 3D and 3E illustrate an exemplary process for forming a carrier wafer sub-assembly, in accordance with embodiments of the present invention.
• Figures 3F, 3G and 3H illustrate an exemplary alternative process for forming a carrier wafer sub-assembly, in accordance with embodiments of the present invention.
• Figure 31 illustrates an alternative embodiment of a carrier wafer subassembly, in accordance with embodiments of the present invention.
• Figure 3 J illustrates an alternative embodiment of a carrier wafer subassembly, in accordance with the present invention.
• Figures 4A, 4B, 4C and 4D illustrate an exemplary process for joining a light emitting diode sub-assembly to a carrier wafer sub-assembly, in accordance with embodiments of the present invention.
• Figure 5 illustrates a perspective sectional view of a high efficiency light emitting diode (LED) with vias, in accordance with embodiments of the present invention.
• Figure 6 illustrates an example of an application of a high efficiency light emitting diode with vias, in accordance with embodiments of the present invention.
• calculating or “determining” or “measuring” or “gathering” or “running” or the like refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's TSRA-02012-1003/ACM/NAO 9 registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
• via may be used to describe or refer to a hole or a filled hole, generally used to electrically couple circuit elements at different levels of a multi-level structure.
• vias may also have a "trench" structure, e.g., a hole or filled hole in which the length is much greater than the width.
• trench e.g., a hole or filled hole in which the length is much greater than the width.
• vias may be illustrated as generally circular in vertical cross section. However, it is to be understood that vias and/or filled vias may have any suitable shape.
• FIG. 1A illustrates a high performance light emitting diode (LED) with vias 100, in accordance with embodiments of the present invention.
• Light emitting diode 100 comprises a substrate 110.
• the substrate 110 may comprise any suitable material, including silicon, glass, metals or alloys, ceramics, and the like. As will be further described later, substrate 110 may not utilized in the formation of semiconducting materials, and may be chosen, e.g., for reasons of mechanical strength, thermal properties, electrical properties, and the like.
• Insulation 112 and 116 may comprise, for example, silicon dioxide (S1O2), silicon nitride (S13N4), benzo-cyclo-butene (BCB), spin-on glass, and the like.
• S1O2 silicon dioxide
• S13N4 silicon nitride
• BCB benzo-cyclo-butene
• spin-on glass and the like.
• patterned metal 115 routes electrical signals for the LED, as will be described further below.
• Patterned metal 115 may comprise, for example, aluminum (Al), copper (Cu), nickel (Ni), gold (Au) and the like.
• Light emitting diode 100 additionally comprises lower metal 120.
• Lower metal 120 contacts conductive portions of paternal metal 115.
• Lower metal 120 may comprise copper (Cu), nickel (Ni), gold (Au), tin (Sn) and the like.
• the material chosen should be selected to effective bonding to upper metal 130.
• Upper metal 130 is bonded to lower metal 120.
• Upper metal 130 may comprise copper (Cu), nickel (Ni), gold (Au), tin (Sn) and the like.
• the material chosen should be selected to effective bonding to lower metal 120.
• Upper metal 130 is in electrical contact with contact 155 and or via 140.
• Filled vias 140 provides an electrical path from patterned metal 115, through some instances of lower metal 120 and upper metal 130, to the n- type semiconducting material, e.g., n-gallium nitride (n-GaN), of the light emitting diode proper.
• Filled vias 140 may form an array of separated pillars, in some embodiments.
• Filled vias 140 may from long trenches (in a TSRA-02012-1003/ACM/NAO 1 1 direction parallel to the MQW plan), in some embodiments.
• Filled vias 140 may from an enclosed loop of thin side walls wrapping around the device, in some embodiments.
• filled vias 140 may directly contact optional layer 170 of a transparent conductive material, further described below.
• Filled vias 140 may comprise, for example, chrome/gold (Cr/Au),
• titanium/gold titanium/aluminum/nickel/gold (Ti/Al/Ni/Au) stacks, and the like.
• vias 140 may also be described as a "trench" structure, e.g., a filled hole in which the length, e.g., perpendicular to the plane of Figure 1A, of vias 140 is much greater than their width.
• vias may be illustrated as generally circular in vertical cross section. However, it is to be understood that vias and/or filled vias may have any suitable shape.
• Contact 155 provides electrical contact from some instances of upper metal 130 to the p-type semiconducting material, e.g., p-gallium nitride (p- GaN), of the light emitting diode proper.
• Contact 155 may comprise, for example, chrome/gold (Cr/Au), nickel/gold (Ni/Au), nickel palladium/gold (Ni/Pd/Au) stacks, and the like.
• Light emitting diode 100 further comprises insulating structures 150.
• Insulating structure 150 insulate the p-type semiconducting material from filled vias 140 and from some upper metal 130.
• Light emitting diode 100 comprises a stack of active materials 190 that emits light.
• stack 190 may comprise a p-type semiconducting material, e.g., p-gallium nitride (p-GaN), multiple quantum wells (MQW) and n-type semiconducting material, e.g., n-gallium nitride (n-GaN).
• the top surface 160, e.g., n-GaN, of the active stack 190 may be roughened in order to improve light extraction, in accordance with embodiments of the present invention.
• Light emitting diode 100 comprise an optional layer 170 of a
• Light emitting diode 100 may further optionally comprise a layer 180 forming a lens or encapsulant.
• Layer 180 may be transparent, and may be designed to optically enhance light emission and/or directionality, of light emitting diode 100.
• Layer 180 may also comprise a phosphor layer, e.g., for producing light responsive to receiving light energy from a light emitting diode.
• Figure IB illustrates a high performance light emitting diode (LED) with vias 101, in accordance with embodiments of the present invention.
• LED light emitting diode
• the filled vias 140 are extended to contact layer 170 of a transparent conductive material.
• Figure 1C illustrates a high performance light emitting diode (LED) with vias 102, in accordance with embodiments of the present invention.
• the layer 170 of a transparent conductive material is supported by a metal grid 145.
• Metal grid 145 may comprise any suitable materials, including the exemplary materials previously describe for filled vias 140.
• silver is a good choice for metal grid 145, due to its excellent conductivity and semi-transparency at small thickness, e.g. less than about 20 nm.
• FIGS 2A through 2G illustrate an exemplary process 200 for forming a light emitting diode sub-assembly 201, in accordance with embodiments of the present invention. Processes for formation of a carrier wafer sub ⁇ assembly and joining of the light emitting diode sub-assembly 201 with the carrier wafer sub-assembly will be further described below.
• a gallium nitride (GaN) multiple quantum well (MQW) light emitting diode is formed on a sapphire (crA ⁇ Os) substrate
• TSRA-02012-1003/ACM/NAO 14 illustrated formation may be via any suitable process and materials.
• an n-type layer 294 e.g., comprising n doped gallium nitride (n- GaN) is formed on substrate 292.
• Substrate 292 may comprise a crystalline material that is lattice-matched for gallium nitride, e.g., sapphire (C1-AI2O3) or silicon carbide (SiC).
• a five-period multiple quantum well structure 296 comprising, for example, periods of a 2.5 nm thick 85% gallium, 15% indium nitride layer alternating with a ll nm thick GaN layer is formed on n-type layer 294.
• a p-type layer 298, e.g., comprising p-doped gallium nitride (p- GaN) is formed on top of the MQW 296.
• the diode structure is formed continuously over substantially all of the substrate, although this is not required. It is to be appreciated that embodiments in accordance with the present invention are well suited to other types of light emitting diodes comprising different materials.
• Figure 2B illustrates defining an area for continued processing of light emitting devices on substrate 292, in accordance with embodiments of the present invention.
• the illustrated defining may be via any suitable process and materials.
• a portion of the semiconducting stack is etched away via inductively coupled plasma reactive ion etching (RIE), or other suitable process, defining a perimeter and forming an area of a light emitting diode material.
• RIE plasma reactive ion etching
• the LED stack may be about 5.215 ⁇ thick, in an
• the etching should be deeper than the stack, e.g., about 6 ⁇ ,
• TSRA-02012-1003/ACM/NAO 15 to ensure complete removal of the semiconducting materials and exposure of the substrate. Any photoresist should be removed, as well.
• FIG. 2C illustrates opening of vias 240, through p-layer 298 and MQW layer 296, to the n-type layer 294, in accordance with embodiments of the present invention.
• the illustrated opening may be via any suitable process and materials.
• a plurality of via 240 is formed via inductively coupled plasma reactive ion etching (RIE), or other suitable process.
• RIE reactive ion etching
• the etching to open the vias should be to a lesser depth than the previous etching.
• the etching of vias 240 should terminate in n- type layer 294, and should not remove all of n-type layer 294. It is appreciated that more than the illustrated one via 240 may be formed in this manner.
• the vias may be on about 10 ⁇ to about 200 ⁇ centers, with a diameter of about 10 ⁇ to about 200 ⁇ , for example. It is appreciated that vias 240 are well suited to non-circular cross-section(s), in accordance embodiments of the present invention.
• Figure 2D illustrates formation of metal contacts 255 to p-type layer
• a negative tone mask of photoresist e.g., of at least 10 ⁇ in thickness, may be used to form a stack of 100 nm of chromium (Cr) and 300 nm of gold (Au), e.g., via sputtering or TSRA-02012-1003/ACM/NAO 16 electron beam ("e-beam") deposition. Any photoresist should be subsequently removed, as well. Then the deposition may be followed by annealing in an oxygen (O2) atmosphere at about 550 °C for about five minutes.
• O2 oxygen
• Figure 2E illustrates deposition of an insulator 250 over all exposed surfaces, in accordance with embodiments of the present invention. It is appreciated that contacts 255 are covered, as well.
• the illustrated deposition may be via any suitable process and materials. For example, 500 nm of silicon dioxide (S1O2) may be deposited by Plasma-enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).
• PECVD Plasma-enhanced chemical vapor deposition
• LPCVD low pressure chemical vapor deposition
• Figure 2F illustrates opening or uncovering of the contacts 255, in accordance with embodiments of the present invention.
• the illustrated removal of material may be via any suitable process and materials.
• photolithographic, wet and/or dry etching processes may be used to selectively etch the insulator 250 from the top surfaces of contacts 255.
• Figure 2G illustrates formation of upper metal bonding pads 230, in accordance with embodiments of the present invention.
• the illustrated forming may be via any suitable process and materials. For example, a seed layer of about 100 nm of nickel (Ni) is deposited. It is appreciated that a mask is not required. Next, spin coating may be used to apply a negative tone mask of photoresist, e.g., of at least 10 ⁇ in thickness.
• the upper metal bonding pads 230 comprising, for example, 2.75 ⁇ of copper (Cu), 100 nm of nickel (Ni) and 255 nm of gold (Au), may be electroplated.
• the seed layer may be subsequently etched off by dipping in nitric acid (HNO3). Accordingly, a first sub-assembly 201 is formed.
• FIGS 3A through 3E illustrate an exemplary process 300 for forming a carrier wafer sub-assembly 301, in accordance with embodiments of the present invention. Exemplary processes for joining of the light emitting diode sub-assembly 201 with the carrier wafer sub-assembly 301 will be further described below.
• a metal layer 315 is deposited on an insulated substrate, in accordance with embodiments of the present invention.
• the illustrated deposition may be via any suitable process and materials.
• the insulated substrate may comprise, for example, a stack of silicon (Si) 310 and an insulator 312, e.g., silicon dioxide (S1O2).
• the silicon dioxide may be thermally grown, in some embodiments.
• the stack of materials may also comprise ceramic, glass, tungsten, molybdenum, invar, aluminum, nickel, steel, brass and/or copper in some embodiments.
• the substrate should have a high thermal conductivity. For example, the substrate thermal conductivity should be greater than about lOW/mK.
• the substrate 310 may be greater than about 100 ⁇ thick and insulator 312 may TSRA-02012-1003/ACM/NAO 18 be about 500 nm thick, in some embodiments.
• a conducting layer 315 e.g., about 1 ⁇ thick, is deposited on top of the insulating layer 312.
• Layer 315 should be suitable for patterning, and may comprise, for example, aluminum (Al), copper (Cu), nickel (Ni), gold (Au) and the like.
• portions of metal layer 315 are etched to form a circuit pattern, in accordance with embodiments of the present invention.
• the illustrated etching may be via any suitable process and materials, including, for example, photolithographic processes.
• Figure 3C illustrates deposition of an insulating layer 316 onto the top surface of patterned metal layer 315, in accordance with embodiments of the present invention.
• the illustrated deposition may be via any suitable process and materials.
• insulating layer 316 may comprise silicon dioxide (S1O2), silicon nitride (S13N4), benzo-cyclo-butene (BCB), spin-on glass, ceramic tungsten and the like. Insulating layer 316 may be about 500 nm thick, in some embodiments.
• vias are opened in insulating layer 316, in accordance with embodiments of the present invention.
• the illustrated opening may be via any suitable process and materials.
• the insulating material may be selectively etched using wet and/or dry etching.
• Figure 3E illustrates formation of lower metal bonding pads 320, in accordance with embodiments of the present invention.
• the illustrated forming may be via any suitable process and materials. For example, a seed layer of about 100 nm of nickel (Ni) is deposited. It is appreciated that a mask is not required. Next, spin coating may be used to apply a negative tone mask of photoresist, e.g., of at least 10 ⁇ in thickness. Photolithography is used to define the bonding pads.
• the lower metal bonding pads 320 comprising, for example, 8 ⁇ of copper (Cu), 255 nm of nickel (Ni), 20 ⁇ of tin (Sn) andlO nm of gold (Au), may be electroplated.
• the seed layer may be subsequently etched off by dipping in nitric acid (HNO3). Accordingly, a second sub-assembly 301 is formed.
• FIGS 3F through 3H illustrate an exemplary alternative process 330 for forming a carrier wafer sub-assembly 302, in accordance with embodiments of the present invention. Exemplary processes for joining of the light emitting diode sub-assembly 201 with the carrier wafer sub-assembly 302 will be further described below.
• a substrate 310 is etched to form vias through the entire thickness of the substrate wafer.
• Any suitable process may be used, for example, deep reactive ion etching (RIE).
• RIE deep reactive ion etching
• the illustrated via holes are depicted in cross section, and do not result in separate pieces of TSRA-02012-1003/ACM/NAO 20 substrate.
• the sidewall of the via holes is passivated with insulating layer 336.
• the passivating material may be silicon dioxide (Si02), deposited by either thermal growth, plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD) processes.
• Figure 3H illustrates filling of the vias, in accordance with
• a metal seed layer for example, Ti/Cu, Ta/Cu, W/Cu and/or TiW/Cu, is blanket deposited, followed by photolithography patterning to expose the through -substrate -vias. Then an electroplating process is applied to the wafer, in order to fill the through- substrate-vias 338 with Cu and Sn (after the full thickness is filled up with Cu). Then the seed layer out of the through- substrate- vias is removed by wet etching, forming wafer subassembly 302.
• the substrate wafer 310 can also be etched deeply, leaving a thin layer of substrate material remaining, and this thin layer can be finally polished off after other process operations are complete, e.g., after seed layer removal.
• Figure 31 illustrates an alternative embodiment 340 of a carrier wafer subassembly 303, in accordance with embodiments of the present invention.
• insulator 312a, metal 315a and insulator 316a are modified TSRA-02012-1003/ACM/NAO 21 from the forms 312, 315 and 316 ( Figure 3E) to allow some instances of filled vias 320b to make contact with a conductive substrate 310a.
• Conductive substrate 310a may comprise any suitable material, for example a metal or alloy, and may server multiple functions, including, for example, the functions of a mechanical substrate, one electrode of an LED assembly, and as a heat sink.
• Figure 3J illustrates an alternative embodiment 350 of a carrier wafer subassembly 304, in accordance with the present invention.
• wafer subassembly 304 In contrast to wafer subassembly 301 ( Figure 3E), wafer subassembly lacks insulator 312 deposited on substrate 310a. Rather, patterned metal 315b is deposited directly onto substrate 310a, via any suitable process. An additional patterned metal 318 is deposited onto insulator 316b. Some filled metal vias 320c contact patterned metal 318 while some filled metal vias 320c contact patterned metal 315b.
• Figures 4A through 4D illustrate an exemplary process 400 for joining light emitting diode sub-assembly 201 to carrier wafer sub-assembly 301 (or 302, 303, 304), in accordance with embodiments of the present invention.
• Figure 4A illustrates the joining of sub-assembly 201 with sub ⁇ assembly 301, in accordance with embodiments of the present invention.
• the light emitting diode sub-assembly 201 is inverted.
• the joining may be via TSRA-02012-1003/ACM/NAO 22 any suitable process and materials.
• a thermo compression wafer bonding process may be utilized.
• the back side of substrate 292 may be polished on the back side, e.g., the top as illustrated in Figure 4A, which may improve transparency and aid alignment of the two sub-assemblies 201, 301, from the back side of substrate 292.
• the substrate 292 of sub-assembly 201 is removed, in accordance with embodiments of the present invention.
• the removal may be via any suitable process and materials.
• the substrate 292 may be removed by a laser lift off process, or may be polished off, e.g., via chemical mechanical polishing, or lapping.
• Figure 4C illustrates etching of the top, in the view of Figure 4C, surface of the light emitting diode, e.g., layer 294 ( Figure 2A).
• the etching may be via any suitable process and materials, and may remove, for example, about 1.65 ⁇ of material.
• the top surface of the light emitting diode, e.g., layer 294 ( Figure 2A) may be roughened, in accordance with embodiments of the present invention. The roughening may enhance light output, and may be accomplished via any suitable process.
• Figure 4D illustrates a deposition of optional layer 470 of transparent conductive material, e.g., indium tin oxide (ITO).
• ITO indium tin oxide
• the deposition may be via TSRA-02012-1003/ACM/NAO 23 any suitable process and materials.
• 250 nm of ITO may be sputtered and then annealed in a nitrogen (N 2 ) atmosphere for about four hours at about 180 °C.
• N 2 nitrogen
• a shadow mask is generally needed before depositing the ITO 470.
• the mask may be the same as or similar to a mask utilized in defining an array area, as illustrated in Figure 2A.
• Figure 4D further illustrates the formation of a layer 480 forming a lens or encapsulant.
• Layer 480 may be transparent, and may be designed to optically enhance light emission and/or directionality, of a light emitting diode.
• Layer 480 may also comprise a phosphor layer, e.g., for producing light responsive to receiving light energy from a light emitting diode.
• substrate 292 may comprise a "2- inch" sapphire wafer.
• the resulting light emitting diode with vias may have on the order of three square inches of light emitting diode surface.
• the structures disclosed herein may advantageously provide sufficient thermal conduction to extract heat from such a large device.
• the wafer may be singulated, e.g., cut between vias and contact structures, into smaller-area light emitting diodes.
• the high efficiency light emitting diode with vias may be coupled to a heat sink, e.g., on the bottom of substrate 310.
• Figure 5 illustrates a perspective sectional view of a high efficiency light emitting diode (LED) with vias 500, in accordance with embodiments of the present invention.
• Light emitting diode 500 may generally correspond to light emitting diode 100 of Figure 1A.
• Light emitting diode 500 comprises a stack of light emitting materials 540.
• Materials stack 540 may generally correspond to LED stack 190 ( Figure 1A), e.g., layers 294-298 of Figure 2A.
• light emitting diode 500 comprises a transparent contact 510 on its top.
• Transparent contact 510 may generally correspond to transparent layer 170 of Figure 1A.
• Light emitting diode 500 comprises a plurality of filled vias 520. Filled vias 520 may conduct electricity to the n-type material of the light emitting diode 540. Filled vias 520 generally correspond to filled vias 140 of Figure 1A.
• the vias 520 should represent less than 10% of the top surface area of light emitting diode 500.
• the vias 520 should be spaced no more than about 200 ⁇ apart.
• light emitting diode 500 comprises a plurality of contacts 530. Contacts 530 may conduct electricity to
• Contacts 530 may generally correspond to contacts 155 of Figure 1A.
• Figure 6 illustrates an example of an application of a high efficiency light emitting diode with vias, e.g., a high efficiency light emitting diode with vias 100, in accordance with embodiments of the present invention.
• Light appliance 600 is well suited to a variety of lighting applications, including domestic, industrial and landscape lighting.
• Light appliance 600 is also well suited to stage or theatrical lighting.
• Light appliance 600 comprises a base 610.
• base 610 is an Edison type base. It is appreciated that embodiments in accordance with the present invention are well suited to other types of bases, including, for example, GU, bayonet, bipin, wedge, stage pin or other types of bases.
• Light appliance 600 additionally comprises a body portion 620 that houses power conditioning electronics (not shown) that convert 110 V AC input electrical power (or 220 V AC, or other selected input electrical power) to electrical power suitable for driving a plurality of light emitting diode devices 640.
• Body portion 620 may also comprise, or couple to, optional heat sink features (not shown).
• Light appliance 600 may additionally comprise optional optics 630.
• Optics 630 comprise diffusers and/or lenses for focusing and/or diffusing light from the plurality of light emitting diode devices 640 into a desired pattern.
• Light appliance 600 comprises a plurality of high efficiency light emitting diode with vias devices. Individual instances of plurality of high efficiency light emitting diode with vias devices may correspond to assemblies previously described herein.
• light appliance 600 may include one or more instances of a high efficiency light emitting diode with vias 100. Each instance of a high efficiency light emitting diode with vias 100 may comprise one or more light emitting diodes. It is appreciated that not all high efficiency light emitting diode with vias 100 need be identical, and that not all light emitting diodes in a single instance of high efficiency light emitting diode with vias 100 need be identical.
• appliance 600 may comprise a plurality of individual, different, LED devices.
• an electronic device may be a blue light emitting diode comprising a sapphire substrate.
• Another instance of an electronic device may be a green light emitting diode comprising a gallium phosphide (GaP) substrate.
• Another instance of an electronic device may be a red light emitting diode comprising a gallium arsenide (GaAs) substrate.
• the three instances of electronic devices may be arranged such that the light from such three colors may be TSRA-02012-1003/ACM/NAO 27 combined to produce a variety of spectral colors.
• a plurality of light emitting diode devices may operate in combination to produce a "white" light output.
• device 600 may include additional electronics associated with the LED devices.
• additional electronics may comprise circuits to implement a white balance among tri-color LEDs.
• Embodiments in accordance with the present invention provide systems and methods for high performance light emitting diodes with vias.
• embodiments in accordance with the present invention provide systems and methods for high performance light emitting diodes with vias that enable wafer level packaging, improved thermal conduction and electrical field distribution, and further enable electrical contacts on opposite sides.
• embodiments in accordance with the present invention provide systems and methods for high performance light emitting diodes with vias that are compatible and complementary with existing systems and methods of integrated circuit design, manufacturing and test.

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• 2013
  • 2013-12-09 WO PCT/US2013/073849 patent/WO2014105403A1/en active Application Filing
  • 2013-12-16 TW TW102146483A patent/TWI559575B/zh active

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