WO2014101103A1 - Générateur d'horloge et circuit à capacités commutées le comprenant - Google Patents

Générateur d'horloge et circuit à capacités commutées le comprenant Download PDF

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Publication number
WO2014101103A1
WO2014101103A1 PCT/CN2012/087834 CN2012087834W WO2014101103A1 WO 2014101103 A1 WO2014101103 A1 WO 2014101103A1 CN 2012087834 W CN2012087834 W CN 2012087834W WO 2014101103 A1 WO2014101103 A1 WO 2014101103A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock signal
clock
overlapping
phase
signal
Prior art date
Application number
PCT/CN2012/087834
Other languages
English (en)
Chinese (zh)
Inventor
刘松
杨飞琴
吴柯
Original Assignee
香港中国模拟技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 香港中国模拟技术有限公司 filed Critical 香港中国模拟技术有限公司
Priority to US14/758,345 priority Critical patent/US20150341040A1/en
Priority to PCT/CN2012/087834 priority patent/WO2014101103A1/fr
Publication of WO2014101103A1 publication Critical patent/WO2014101103A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
    • H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H03K3/0322—Ring oscillators with differential cells
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator

Definitions

  • the present invention relates to the field of integrated circuit (IC) design technology, and relates to a clock generator, and more particularly to a clock generator which can generate a multi-phase non-overlapping clock signal and is affected by a PVT factor, and a switched capacitor circuit including an application clock generator.
  • IC integrated circuit
  • Figure 1 shows a two-phase non-overlapping clock signal (Two-phase None-Overlapping)
  • Multiphase non-overlapping clock signals such as those shown in Figure 1 are widely used in integrated circuits, and the higher the timing accuracy, the better the performance of the integrated circuit.
  • a two-phase non-overlapping clock signal as an example, it is widely used in Switch-Capacitor Circuits.
  • ADC analog-to-digital converter
  • the implementation of the sampling and amplification functions of the switched-capacitor circuit 'need to provide clock signal control; to avoid the appearance in the switched-capacitor circuit
  • the phenomenon of "charge sharing" of i reduces the destructiveness of information reliability due to "charge sharing”.
  • the switching circuit usually uses a two-phase non-overlapping clock signal as shown in FIG.
  • FIG. 2 is a circuit diagram showing a conventional clock generator for generating a two-phase non-overlapping clock signal as shown in FIG. 1.
  • the inverter 10 is used to implement clock flipping; the input clock of the NAND gate N1 is connected to the reference clock signal, and the other end is input of the clock2 signal, and the NAND gate
  • the output end of N1 is output to the first group of inverters ( ⁇ 1/ ⁇ 12/ ⁇ 3) formed by serial connection in series; the clock signal (10 output) after the flipping of one input terminal of the NAND gate N2, and the clockl signal input to the other end,
  • the output of the NAND gate N2 is output to a second group of inverters (I21/I22/I23) formed in series in series.
  • the closed-loop circuit composed of NAND gates (Nl, N2) and two sets of inverters (II 1/I12/I13 and I21/I22/I23) can guarantee the time interval ⁇ between clockl and clock2, and the specific time interval ⁇
  • the size can also be determined by the delay ( ⁇ ) of the first set of inverters (I11/I12/I13) or the second set of inverters (I21/I22/I23).
  • the present invention provides the following technical solutions.
  • a comparison module (34) for comparing a frequency of the standard clock signal (clock4) and a frequency of the third clock signal (clock3)';
  • the bias signal is fed back to the ring oscillator (32) to adjust the frequency of the third clock signal (clock3) until the frequency of the third clock signal (clock3) and the standard clock.
  • the frequencies of the signals (cl 0C k4) are compared in the comparison module (34) to be substantially equal;
  • the bias signal is fed back to the non-overlapping clock signal generating module (31) to reduce the offset of the two-phase clock time interval ( ⁇ ).
  • a clock generator according to an embodiment of the present invention, wherein the non-overlapping clock signal generating module (31) and the ring oscillator (32) are adjacently arranged in a chip and are formed in synchronization with the same process.
  • the delay generated by the inverter used ( ⁇ ) is in the non-overlapping clock signal generation module (31)
  • a clock generator according to still another embodiment of the present invention, wherein the offset of the two-phase clock time interval ( ⁇ ) is caused by the multiphase non-overlapping clock signal being affected by process, voltage and/or temperature factors.
  • the third clock signal (clock3) is affected by the process, voltage, and/or temperature factors substantially the same as the process of the multiphase non-overlapping clock signal. , voltage and / or temperature are affected by the chapter.
  • the non-overlapping clock signal generating module (31) is a current controllable non-overlapping clock signal generating module (31), and the ring oscillator (32) is current controllable.
  • the ring oscillator (32), the bias signal is a bias current signal.
  • the bias current signal adjusts a current magnitude according to a comparison result of the comparison module (34) to correct a frequency of the third clock signal (clock3) and a two-phase clock. Time interval ( ⁇ ).
  • the bias signal is biased to all of the gates of the ring oscillator (32), the bias signals being also biased to the non-overlapping clock signal generation All the gates of module (31).
  • the multi-phase non-overlapping clock signal may be a multi-phase non-overlapping clock of two or more phases: ⁇ , ⁇ .
  • the reference clock signal generated by the pass-through crystal is input to the non-overlapping clock signal generating block (31).
  • the standard clock signal (clock4) is unaffected by process, voltage and/or temperature factors.
  • a switched capacitor circuit comprising any of the clock generators described above, the multiphase non-overlapping clock signal output by the clock generator being applied in the switching circuit.
  • the clock generator and the switched capacitor circuit provided by the invention form a feedback loop (ie, a compensation loop or a compensation system) through a ring oscillator, a frequency detection module, a comparison module, a programmable number, a generation module, and a bias signal feedback adjustment loop.
  • the frequency of the clock signal output by the oscillator is equal to the frequency of the standard clock signal : '
  • the two-phase clock interval of the multi-phase non-overlapping clock signal can also be corrected in real time or at one time, and the two-phase clock time interval is reduced.
  • the offset of ⁇ is such that it is largely unaffected by factors such as PVT.
  • the two-phase clock time interval ⁇ of the multi-phase non-overlapping clock signal output by the clock generator is stable and high in accuracy, and the performance of the switched capacitor circuit using the clock generator is good.
  • Figure 1 is a schematic diagram of a two-phase non-overlapping clock signal.
  • FIG. 3 is a schematic structural diagram of a clock generator according to an embodiment of the invention.
  • the following is a description of some of the various possible embodiments of the present invention, which are intended to provide a basic understanding of the invention and are not intended to identify key or critical elements of the invention. It is to be understood that, in accordance with the technical scope of the present invention, those skilled in the art can propose other implementations that are interchangeable without departing from the spirit of the invention. Therefore, the following detailed description and the accompanying drawings are merely illustrative of the embodiments of the invention, and are not intended to
  • the clock generator 30 is used to generate a two-phase non-overlapping clock signal, ie, a clock *g ⁇ * Factory King: JL signal generation module 31, non-overlapping clock signal generation module 31 can refer to the input one way ci ⁇
  • the reference clock signal can be, but is not limited to, generated by an over-crystal. Specifically, as shown in FIG.
  • the clock generator 30 further includes a ring oscillator 32.
  • the ring oscillator 32 may specifically be composed mainly of a NAND gate and a plurality of inverters.
  • the delay ⁇ ⁇ generated by the plurality of inverters determines the The frequency of the clock signal clock3 output by the ring oscillator 32.
  • the layout layout of the inverter is also the same.
  • the ring oscillator 32 have the same process (ie, the same manufacturing process) as the non-overlapping clock signal generating module 31, the same voltage (ie, the power supply voltage is the same), the same temperature (ie, the same ambient temperature), and the output of the ring oscillator 32.
  • the influence of the PVT of the clock signal clock3 is substantially the same as the influence of the PVT of the output clock signals clockl and clock2 of the non-overlapping clock signal generating module 31.
  • the frequency change caused by the clock signal clock3 being affected by the PVT can reflect the clockl and clock2
  • the offset of the two-phase clock interval ⁇ In this embodiment, the frequency of clock3 is determined by the delay ⁇ of the plurality of series inverters used by it.
  • the ratio between the on state (ON) and the off state (.OFF) is also the same as the ratio between the on state (ON) and the off state GOFF of the clock signal clockl or clock2.
  • ⁇ 1 ⁇
  • the frequency ⁇ of the clock information clock3 is one-nth of the clock signal clock1 or clock2
  • the PVT affects the ring oscillator 32 by 5 and the PVT pair non-overlapping clock signal generating module 31 The impact is equally consistent.
  • the output terminal 351 of the programmable bias signal generating module 35 outputs the bias signal pi to the ring oscillator 32, and the output terminal 352 outputs the bias signal p2 to the non-overlapping clock signal generating module 31, the bias signal.
  • P2 and pi are the same signals.
  • the bias signals pi and p2 are the same 0 bias current signals.
  • the magnitudes of the bias signals pi and p2 can be adjusted to be output according to the comparison of the frequencies £ and f4 in the comparison module 34.
  • the bias signals pi and p2 can be set as a bias voltage signal whose voltage magnitude can be adjustably changed according to the comparison result, thereby correcting the frequency of the third clock signal clock3 and the two-phase clock time interval ⁇ .
  • the bias signals pi and p2 can be set as a bias voltage signal whose voltage magnitude can be adjustably changed according to the comparison result, thereby correcting the frequency of the third clock signal clock3 and the two-phase clock time interval ⁇ .
  • the bias current signal pi can be biased to all gates of the ring oscillator 32 (eg, NAND gates, inverters), that is, the output 351 is coupled to all gates of the ring oscillator 32.
  • the bias current signal p2 can also be biased to all gates (eg, NAND gates, inverters) of the non-overlapping clock signal generation module 31, and the output 352 is coupled to all of the non-overlapping clock signal generation modules 31.
  • the bias current signal p2 can be generated by mirroring the bias current signal pi current.
  • the "programmable" in the programmable bias signal generation module 35 reflects the adjustable size of the output bias signal.
  • a clock generator for multiphase non-overlapping clock signals For example, if it is necessary to generate a multi-phase non-overlapping clock signal of three-phase three-phase or more, the non-overlapping clock signal generating module 31 is equivalently converted to have a function of generating a three-phase or three-phase non-overlapping clock signal function.
  • the overlapping clock signal generating module may be used, and other modules (for example, the frequency detecting module 33, the comparing module 34, and the programmable bias signal generating module (5) are configured to be adaptively changed, and may not be substantially changed.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

La présente invention concerne le domaine de la conception des circuits intégrés. Un générateur d'horloge (30) et un circuit à capacités commutées le comprenant sont décrits. Le générateur d'horloge (30) comprend : un module de génération de signal d'horloge non chevauchant (31), et un oscillateur annulaire (32), un module de détection de fréquence (33), un module de comparaison (34) et un module de génération de signal de décalage programmable (35) qui sont utilisés pour former une boucle de rétroaction. Un signal de décalage généré par le module de génération de signal de décalage programmable (35) est réinjecté et introduit dans l'oscillateur annulaire (32), afin de réguler la fréquence d'un troisième signal d'horloge délivré par l'oscillateur annulaire (32) jusqu'à ce que la fréquence du troisième signal d'horloge et la fréquence d'un signal d'horloge standard soient fondamentalement égales l'une à l'autre dans le module de comparaison (34). Le signal de décalage est réinjecté et introduit dans le module de génération de signal d'horloge non chevauchant (31) afin de réduire le décalage d'un intervalle de temps d'horloge à deux phases. L'intervalle de temps d'horloge à deux phases d'un signal d'horloge non chevauchant multi-phase délivré par le générateur d'horloge (30) est stable et à haute précision. Le circuit à capacités commutées utilisant le générateur d'horloge (30) possède de bonnes performances.
PCT/CN2012/087834 2012-12-28 2012-12-28 Générateur d'horloge et circuit à capacités commutées le comprenant WO2014101103A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/758,345 US20150341040A1 (en) 2012-12-28 2012-12-28 Clock Generator and Switch-capacitor Circuit Comprising the Same
PCT/CN2012/087834 WO2014101103A1 (fr) 2012-12-28 2012-12-28 Générateur d'horloge et circuit à capacités commutées le comprenant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2012/087834 WO2014101103A1 (fr) 2012-12-28 2012-12-28 Générateur d'horloge et circuit à capacités commutées le comprenant

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WO2014101103A1 true WO2014101103A1 (fr) 2014-07-03

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WO (1) WO2014101103A1 (fr)

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US10756710B2 (en) 2017-04-11 2020-08-25 Chaologix, Inc. Integrated ring oscillator clock generator
CN114896936B (zh) * 2022-02-16 2023-04-07 上海先楫半导体科技有限公司 一种环形振荡器及其布局布线结构

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