Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3802—Instruction prefetching
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3802—Instruction prefetching
  • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
  • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3824—Operand accessing
  • G06F9/383—Operand prefetching
  • G06F9/3832—Value prediction for operands; operand history buffers
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
  • G06F2212/60—Details of cache memory
  • G06F2212/608—Details relating to cache mapping
  • G06F2212/6082—Way prediction in set-associative cache
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• a first technique stores the last (previous) "next way” for each cache line (i.e., a single "next way”). Based on the single "next way", the instruction cache enables a single driver that corresponds to the single "next way.” When the correct way is not driven (i.e., not provided to the multiplexer), a misprediction occurs and a second access to the instruction cache data array is performed that drives the correct way (based on a completed tag lookup operation or a signal provided from control logic). When using the first technique, accuracy of predicting the correct "next way” is an issue because predictability of a given program (e.g., multiple instructions) may be erratic. Accordingly, the last "next way" for a cache line is not necessarily a good predictor and frequent mispredictions occur.
• FIG. 4 is a flow diagram of a second illustrative embodiment of a method to perform way prediction
• the data array 110 may include a plurality of ways 120-124 that each include a
• multiplexer may determine whether the contents provided via the enabled drivers 140- 144 includes one or more instruction to be executed next (e.g., after the instruction(s) corresponding to the last cache line fetched). If the ways enabled according to the prediction mask 152 set to the prediction mask value do not provide the one or more instructions to be executed next (e.g., the prediction mask does not predict a correct next way to be driven), a misprediction occurs. In a particular embodiment, the control logic 150 determines whether a misprediction occurs based on whether or not a multiplexer selects an output of the data array 110 that corresponds to a predicted way identified by the prediction mask 152.
• the control logic 150 may receive an instruction address associated with an instruction stored in a cache line (e.g., a way) of the data array 110. Based on the instruction address, the control logic 150 may identify a particular prediction mask value associated with the instruction address. For example, the control logic 150 may identify the particular prediction mask value from the plurality of prediction mask values that each correspond to a cache line of the data array 110. After the particular prediction mask value is identified, the control logic 150 may set one or more bits of the prediction mask 152 based on the particular prediction mask value identified so that value of the prediction mask 152 is the same value as the particular prediction mask value.
• a power benefit may be realized on each data access of the instruction cache 102.
• a misprediction should only occur once for each successor way because, after a misprediction, a bit of the multi-bit way prediction mask 152 is updated to identify the particular cache line as a successor.
• the control logic 150 may set a value of the prediction mask 152.
• the value set for the prediction mask 152 may correspond to a particular cache line 220a-d of the data array 110 that was last accessed.
• the value of the prediction mask 152 may predict (e.g., identify) a "next way" (e.g., a subsequent way) with respect to the particular cache line 220a-d that was last fetched.
• the value set for the prediction mask 152 may correspond to the cache line A 220a.
• the prediction mask 152 of FIG. 2 may include four (4) bits, where each bit corresponds to a different way, and thus a different driver 240a-d, respectively.
• control logic 150 may also initialize a particular prediction mask value when
• the control logic 150 may determine (e.g., identify) which way is accessed next (e.g., subsequent to the particular cache line as a successor way). Upon determining the successor way, the control logic 150 may set a bit of the corresponding prediction mask value to identify the successor way.
• the control logic 150 may also determine (e.g., detect) whether a misprediction occurs as a result of the prediction mask 152 being applied to the data array 110. For example, when the prediction mask 152 is set to a value of a particular prediction mask value corresponding to a particular cache line 220a-d of the data array 110, the control logic 150 may determine whether the particular prediction mask value resulted in a misprediction. When the particular prediction mask value resulted in the misprediction, the control logic 150 may identify the correct way to be driven (e.g., the correct driver to be enabled) and update the particular prediction mask value based on the identified correct way.
• the correct way to be driven e.g., the correct driver to be enabled
• the third way corresponding to the cache line C 220c is identified by the control logic 150 as the correct way and the control logic 150 updates the cache line A prediction mask value 254 to "0011" reflecting the determination that the third way associated with the cache line C 220c is also a successor to the cache line A 220a.
• the tag portion 274 may be provided to the tag array 280 in parallel with the control logic 150 applying the prediction mask 152 (associated with an instruction currently being executed) that predicts one or more ways that may be associated with an instruction to be executed next.
• the tag portion 274 may be provided to the tag array 280 after (e.g., in response to) a misprediction.
• the tag array 280 may identify the location (e.g., a cache line or way) in the data array 110 that includes the instruction to be executed next.
• the tag array 280 may provide the location to the multiplexer 160 as the way select signal.
• a particular instruction is fetched from a particular cache line 220a-d of the data array 110 and executed (by an execution unit). Based on the particular instruction being fetched and/or executed, the control logic 150 identifies a prediction mask value corresponding to the particular cache line. The control logic 150 may set the prediction mask 152 to the prediction mask value to selectively enable one or more drivers 240a-d of the data array 110. When the one or more drivers 240a-d are enabled, contents of selected cache lines (e.g., one or more of the cache lines 220a-d) corresponding to the one or more enabled drivers (e.g., one or more of the drivers 240a- d) may be provided to the multiplexer 260.
• selected cache lines e.g., one or more of the cache lines 220a-d
• enabled drivers e.g., one or more of the drivers 240a- d
• the instruction cache may include the instruction cache 102 of FIG. 1.
• the method 300 may be performed by the control logic 150 of FIG. 1.
• a multi-bit way prediction mask corresponding to a cache line may be set to an initial value, at 302, and the cache line may be fetched, at 304.
• the multi-bit way prediction mask may be associated with an instruction cache including a data array having a plurality of cache lines.
• the value of the multi-bit way prediction mask may correspond to a cache line included in the data array of the instruction cache.
• the multi-bit prediction mask may be the prediction mask 152 and the data array may be the data array 110 of FIG. 1.
• the value of the multi-bit way prediction mask value corresponding to the first cache line is not updated when the second cache line is determined not to be the first cache line. Rather, when the second cache line is determined, at 418, not to be the first cache line, processing advances to 408, and the multi-bit predication mask value corresponding to the first cache line is not updated based on data (e.g., the second contents) being loaded into the second cache line.
• the apparatus may also include means for providing the multi-bit way prediction mask to a plurality of line drivers of the data array.
• the means for providing may include the control logic 150 of FIGS. 1-2, the processor 610, the control logic 686 of FIG. 6, one or more other devices or circuits configured to provide the multi-bit way prediction mask, or any combination thereof.

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• General Engineering & Computer Science (AREA)
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• Memory System Of A Hierarchy Structure (AREA)
• Advance Control (AREA)

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• 2012
  • 2012-12-20 US US13/721,317 patent/US9304932B2/en not_active Expired - Fee Related
• 2013
  • 2013-12-20 CN CN201380065463.XA patent/CN104854557B/zh active Active
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