WO2019010703A1 - 读、部分写数据方法以及相关装置 - Google Patents

读、部分写数据方法以及相关装置 Download PDF

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Publication number
WO2019010703A1
WO2019010703A1 PCT/CN2017/093009 CN2017093009W WO2019010703A1 WO 2019010703 A1 WO2019010703 A1 WO 2019010703A1 CN 2017093009 W CN2017093009 W CN 2017093009W WO 2019010703 A1 WO2019010703 A1 WO 2019010703A1
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Prior art keywords
cache line
cache
data
request
write
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PCT/CN2017/093009
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English (en)
French (fr)
Inventor
罗日新
李渊
袁泉
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华为技术有限公司
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Priority to CN201780092956.0A priority Critical patent/CN110832466B/zh
Priority to PCT/CN2017/093009 priority patent/WO2019010703A1/zh
Publication of WO2019010703A1 publication Critical patent/WO2019010703A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of computer technologies, and in particular, to a method for reading and partially writing data and related devices.
  • a terminal device such as a computer uses a distributed large data processing framework (Spark) application based on a resilient distributed dataset (RDD) as an example.
  • Spark distributed large data processing framework
  • RDD resilient distributed dataset
  • the data is mostly RDD.
  • the data conversion operation needs to read data from the main memory into the cache (Cache), and then write to the Cache or main memory after the processor changes.
  • the RDD transformation operation will generate a new RDD.
  • the data needs to be read into the Cache from the main memory.
  • the transformed data will eventually be replaced and written into the main memory due to the capacity.
  • the processor will The converted data is written from the register to the Cache.
  • the possibility of a cache miss occurs.
  • the Cache Miss the data needs to be read from the main memory (or the next level cache) to the Cache.
  • the amount of processed data is much larger than the Cache capacity, and frequent data exchange between the Cache and the Cache and the main storage is required.
  • the transformed data will not be used very quickly.
  • the data stored in the cache in the main memory (or the next level cache) will not be used, and the cache will be occupied for a long time, which will reduce the actual cache utilization. .
  • the embodiment of the invention provides a method for reading and partially writing data and related devices, which can reduce the frequency of data exchange between the memory and the Cache in the process of partially writing data, and improve the data processing efficiency of the Cache.
  • an embodiment of the present invention provides a method for partially writing data, including:
  • the cache controller receives a partial write request, the size of the data carried by the partial write request is smaller than the size of the cacheable data of the cache line, and the data carried by the partial write request is written to the corresponding address in the cache line, and the write of the cache line is updated.
  • Mask and update the state of the cache line.
  • the state of the cache line includes a partial write state; the partial write state is used to indicate that the data portion of the cache line is valid; and the write mask is used to indicate the location of the data that has been written in the cache line.
  • the execution body of the partial write data method may also be a cache including the cache controller, a processor including the cache, an electronic terminal including the processor, and the like.
  • the cached data state includes a partial write state, and the location of the data that has been written is marked by a write mask.
  • the data carried by the partial write request is written to the request address.
  • the corresponding position in the cache line does not need to read the data in the memory, and does not need to update the data to the memory after the partial writing is completed, thereby reducing the frequency of data exchange between the memory and the Cache in the process of partially writing data, and improving the Cache. Data processing efficiency.
  • the implementation manner in which the cache controller writes the data carried by the partial write request to the corresponding location in the cache line may be:
  • a cache line is allocated for the partial write request, and the data carried by the partial write request is written to the corresponding location in the allocated cache line.
  • the cache controller may update the write mask of the cache line.
  • the cache controller may update the write mask of the cache line according to the request address, that is, the write address corresponding to the request address in the cache line.
  • the mask is marked with 1.
  • the cache controller may further: write the data of the cache line into the memory or the next level cache, and initialize the cache.
  • a write mask for the row; at this point, one implementation of the state in which the cache controller updates the cache line may be that the cache controller updates the state of the cache line to an invalid state.
  • the write mask when the write mask is all 1, the data in the cache line is updated to the memory, and the cache line is released, thereby improving the utilization of the cache.
  • the cache controller may further: initialize the write mask of the cache line; at this time, the cache controller updates the state of the cache line.
  • An implementation manner may be: updating the state of the cache line to a modified state.
  • the write mask when the write mask is all 1, the state of the cache line is modified to the M state, and the data in the cache line is not updated to the memory, thereby further reducing the data exchange frequency between the memory and the Cache, and reducing the memory bandwidth occupation. Improve the data processing efficiency of Cache.
  • the embodiment of the present invention further provides a method for reading data, including:
  • the cache controller receives the first read request; the first read request is used to request to read the corresponding data of the first request address in the cache line; and the first request address corresponds to the cache line in the first read request where the cache hit occurs When part or all of the data does not exist, according to the write mask of the hit cache line, the data read from the memory corresponding to the first request address or the corresponding lower level cache is merged into the cache line of the hit, And updating the state of the merged cache line and the write mask; and reading the data corresponding to the first request address in the merged cache line; wherein the state of the cache line includes a partial write state; the partial write state is used to indicate The data portion of the cache line is valid; the write mask is used to indicate the location of the data that has been written in the cache line.
  • the execution body of the read data method may also be a cache including the cache controller, a processor including the cache, an electronic terminal including the processor, and the like.
  • the cached data state includes a partial write state, and the location of the data that has been written is marked by a write mask.
  • the first read request hits and hits the cache line.
  • the data read from the memory corresponding to the first request address or the corresponding lower level cache is merged to the hit according to the write mask of the hit cache line.
  • the frequency of data exchange between the memory and the Cache in the process of reading data is reduced, and the data processing efficiency of the Cache is improved.
  • the cache controller may further receive a second read request, where the second read request is used to request to read data corresponding to the second request address in the cache line; when the second read request occurs, a cache hit occurs and hits The state of the cache line is not in the partial write state; or, when the second read request has a cache hit, the state of the hit cache line is the partial write state and the write mask corresponding to the second request address in the hit cache line is At 1 o'clock, the cache controller can directly read the data corresponding to the second request address in the cache line of the hit, and reduce the frequency of data exchange between the memory and the Cache during the process of reading data. Improve the data processing efficiency of Cache.
  • part or all of the data corresponding to the first request address does not exist in the cache line of the hit: the state of the hit cache line is a partial write state and the first request address corresponding to the cache line in the hit corresponds to The write masks are not all 1. at this time,
  • An embodiment in which the cache controller merges data read from the memory corresponding to the request address or the corresponding lower level cache into the cache line of the hit may be: the memory corresponding to the first location or The data in the next level cache is written to the first position in the cache line of the hit; the first position includes the position in the cache line of the hit with a write mask of 0, wherein the cache line after the write The data of one location and the data of the second location form a merged cache line; the second location includes a location where the write mask is 1 in the cache line of the hit.
  • an embodiment of the present invention further provides a cache memory, including: a cache controller and a cache line area; the cache line area includes a plurality of cache lines, where the cache line includes a data field, an address field, and a status Field and write mask field; where
  • the data field is used to store data
  • the address field is used to indicate address information of data stored in the cache line
  • the status field is used to indicate a status of the cache line; the status includes a partial write status; and the partial write status is used to indicate that a data portion of the cache line is valid;
  • the write mask field is configured to store a write mask, where the write mask is used to indicate a location of data that has been written in the cache line;
  • the cache controller is configured to receive the request and respond to the request, update a status of the cache line in response to the request, and a write mask.
  • the cached data state includes a partial write state and marks the location of the data that has been written by a write mask.
  • the data state of the cache includes a partial write state, and the location of the data that has been written is marked by the write mask, which can reduce the data exchange frequency of the memory and the Cache during the data processing process, and improve the data processing of the Cache. effectiveness.
  • the size of the write mask field is n/8 bytes, and n is the maximum number of bytes in which the cache line can store data.
  • the request includes a partial write request
  • the cache controller is specifically configured to execute:
  • the size of the data carried by the partial write request is smaller than the size of the cacheable data of the cache line;
  • the buffer controller performs a data write request address carried by the partial write request in a corresponding position in the cache line, including:
  • the cache line allocated for the partial write request is carried by the partial write request Data is written to the corresponding location of the request address in the allocated cache line.
  • the performing, by the cache controller, the updating the write mask of the cache line comprises: the cache controller updating a write mask of the cache line according to the request address.
  • the cache controller is further configured to: write data of the cache line into a memory or a next level cache, and initialize the cache.
  • the write mask of the line is further configured to: write data of the cache line into a memory or a next level cache, and initialize the cache.
  • Updating the state of the cache line by the cache controller includes: the cache controller updating the state of the cache line to an invalid state.
  • the cache controller is further configured to: initialize a write mask of the cache line;
  • Updating the state of the cache line by the cache controller includes: the cache controller updating a state of the cache line to a modified state.
  • the request includes a first read request
  • the cache controller is specifically configured to execute:
  • the first read request is for requesting to read data corresponding to the first request address in the cache line;
  • the memory corresponding to the request address or the data read in the corresponding lower level cache is merged into the cache line of the hit, and the state of the merged cache line and the write mask are updated;
  • Reading data corresponding to the first request address in the merged cache line is
  • control buffer is further configured to:
  • the second read request is for requesting to read data corresponding to the second request address in the cache line;
  • the state of the hit cache line is not a partial write state; or, when the second read request has a cache hit, the state of the hit cache line is a partial write And the data corresponding to the second request address is read in the cache line of the hit when the write mask corresponding to the second request address in the hit cache line is 1.
  • the part or all of the data corresponding to the request address does not exist in the cache line of the hit includes: the state of the hit cache line is a partial write state and the request address in the hit cache line The corresponding write masks are not all 1;
  • the Cache Controller executing the merging data read from the memory corresponding to the request address or the corresponding lower level cache into the cache line of the hit includes:
  • the first location includes a write mask in the cache line of the hit a position of 0;
  • the data of the first location and the data of the second location in the cache line after the write form a merged cache line; the second location includes a location where the write mask is 1 in the cache line of the hit. .
  • an embodiment of the present invention further provides a cache memory, including: a cache controller, a cache line area, and a mask area, where the cache line area includes a plurality of cache lines; the cache line includes a data field, a first address field, a status field, and a mask index field; the mask area includes a mask line corresponding to the cache line, the mask line package Including the mask field; where
  • the cache line includes a data field for storing data
  • the first address field is used to indicate address information of data stored by the cache line
  • the status field is used to indicate a status of the cache line; the status includes a partial write status; and the partial write status is used to indicate that a data portion of the cache line is valid;
  • the mask index field is used to indicate address information of a write mask field of the cache line
  • the write mask field is configured to store a write mask, where the write mask is used to indicate a location of data that has been written in a cache line corresponding to the mask row;
  • the cache controller is configured to receive the request and respond to the request, update a status of the cache line in response to the request, and a write mask.
  • the data state of the cache includes a partial write state, and the location of the data that has been written is marked by the write mask, which can reduce the data exchange frequency of the memory and the Cache during the data processing process, and improve the data processing of the Cache. effectiveness.
  • the mask index field is address information of the mask area; the mask line further includes a second address field, and the second address field is used to indicate a cache line corresponding to the mask line.
  • the size of the write mask field is n/8 bytes, and n is the maximum number of bytes in which the cache line can store data.
  • the request includes a partial write request
  • the cache controller is specifically configured to execute:
  • the size of the data carried by the partial write request is smaller than the size of the cacheable data of the cache line;
  • the buffer controller performs a data write request address carried by the partial write request in a corresponding position in the cache line, including:
  • the cache line allocated for the partial write request writes data carried by the partial write request to the corresponding location in the allocated cache line.
  • the performing, by the cache controller, the updating of the write mask corresponding to the cache line includes: the cache controller updating a write mask corresponding to the cache line according to the request address.
  • the cache controller is further configured to: write data of the cache line into a memory or a next level cache, and initialize the cache. a corresponding write mask of the row or a mask row corresponding to the cache line;
  • Updating the state of the cache line by the cache controller includes: the cache controller updating the state of the cache line to an invalid state.
  • the cache controller is further configured to: initialize a write mask of the cache line or release a mask corresponding to the cache line Row;
  • Updating the state of the cache line by the cache controller includes: the cache controller updating a state of the cache line to a modified state.
  • the request includes a first read request
  • the cache controller is specifically configured to execute:
  • the first read request is for requesting to read data corresponding to the first request address in the cache line;
  • the write mask corresponding to the hit cache line When a cache hit occurs in the first read request and some or all of the data corresponding to the first request address does not exist in the cache line that is hit, according to the write mask corresponding to the hit cache line, the The memory corresponding to the first request address or the data read in the corresponding lower level cache is merged into the cache line of the hit, and the state of the merged cache line is updated, and the corresponding write of the cache line is updated. Masking or releasing the mask line corresponding to the cache line;
  • Reading data corresponding to the first request address in the merged cache line is
  • control buffer is further configured to:
  • the second read request is for requesting to read data corresponding to the second request address in the cache line;
  • the state of the hit cache line is not a partial write state; or, when the second read request has a cache hit, the state of the hit cache line is a partial write And the data corresponding to the second request address is read in the cache line of the hit when the write mask corresponding to the second request address in the hit cache line is 1.
  • the part or all of the data corresponding to the request address does not exist in the cache line of the hit includes: the state of the hit cache line is a partial write state and the request address in the hit cache line The corresponding write masks are not all 1;
  • the Cache Controller executing the merging data read from the memory corresponding to the request address or the corresponding lower level cache into the cache line of the hit includes:
  • the first location includes a write mask in the cache line of the hit a position of 0;
  • the data of the first location and the data of the second location in the cache line after the write form a merged cache line; the second location includes a location where the write mask is 1 in the cache line of the hit. .
  • an embodiment of the present invention further provides a cache controller, including:
  • a receiving unit configured to receive a partial write request, where a size of the data carried by the partial write request is smaller than a size of the cacheable data of the cache line;
  • a writing unit configured to write data carried by the partial write request to a corresponding location in the cache line
  • An update unit configured to update a write mask of the cache line; and update a state of the cache line;
  • the state of the cache line includes a partial write state; the partial write state is used to indicate that a data portion of the cache line is valid; and the write mask is used to indicate data that has been written in the cache line. position.
  • the writing unit is specifically configured to:
  • the cache line hits the cache line, and the data carried by the partial write request is written to the corresponding location in the cache line of the hit request address;
  • the cache line is allocated for the partial write request, and the number of the partial write request is carried The corresponding location in the allocated cache line is written to the request address.
  • the update unit when the update unit is configured to update the write mask of the cache line, the update unit is configured to: update a write mask of the cache line according to the request address.
  • the writing unit is further configured to: write data of the cache line into a memory or a next level cache;
  • the updating unit is further configured to: initialize a write mask of the cache line;
  • the updating unit is configured to update the state of the cache line to: update the state of the cache line to an invalid state.
  • the updating unit is further configured to: initialize a write mask of the cache line;
  • the updating unit is configured to update the state of the cache line to: update the state of the cache line to a modified state.
  • an embodiment of the present invention further provides a cache controller, including:
  • a receiving unit configured to receive a first read request, where the first read request is used to request to read data corresponding to the first request address in the cache line;
  • a merging unit configured to: when a cache hit occurs in the first read request and a part or all of data corresponding to the first request address does not exist in a cache line that is hit, according to a write mask of the hit cache line, Merging data read from the memory corresponding to the first request address or the corresponding lower level cache into the cache line of the hit;
  • a reading unit configured to read data corresponding to the first request address in the merged cache line.
  • the state of the cache line includes a partial write state; the partial write state is used to indicate that a data portion of the cache line is valid; and the write mask is used to indicate data that has been written in the cache line. position.
  • the receiving unit is further configured to: receive a second read request, where the second read request is used to request to read data corresponding to the second request address in the cache line;
  • the reading unit is further configured to: when a cache hit occurs in the second read request and the state of the hit cache line is not in a partial write state; or, when the second read request occurs in a cache hit, When the state of the cache line of the hit is a partial write state and the write mask corresponding to the second request address in the hit cache line is 1, the second request address is read in the cache line of the hit. Corresponding data.
  • the part or all of the data corresponding to the first request address does not exist in the cache line of the hit includes: the state of the hit cache line is a partial write state and the cache line of the hit The write mask corresponding to the first request address is not all 1; the merging unit is specifically configured to:
  • the first location includes a write mask in the cache line of the hit a position of 0;
  • the data of the first location and the data of the second location in the cache line after the write form a merged cache line; the second location includes a location where the write mask is 1 in the cache line of the hit. .
  • the embodiment of the present invention further provides a processor, including at least one core and at least one high speed A buffer memory; the cache memory is any one of the cache memories of the third aspect or the fourth aspect.
  • an embodiment of the present invention further provides a terminal, including a processor, a memory, the processor is connected to the memory, the memory is used to store data and instructions, and the processor is in a seventh aspect. Any of the processors described.
  • FIG. 1 is a schematic block diagram of a computer processing system according to an embodiment of the present invention.
  • FIG. 2 is a schematic frame diagram of a Cache according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of another Cache according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of migration of another MESIP protocol state according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of migration of a MESIP protocol state according to an embodiment of the present invention.
  • FIG. 6 is a schematic flowchart of a Cache partial write data according to an embodiment of the present invention.
  • FIG. 7 is a schematic explanatory diagram of a state change of a cache line of an E state in a partial write data process according to an embodiment of the present invention.
  • FIG. 8 is a schematic explanatory diagram of a state change of a M-state cache line in a partial write data process according to an embodiment of the present invention.
  • FIG. 9 is a schematic explanatory diagram of a state change of a P-state cache line in a partial write data process according to an embodiment of the present invention.
  • FIG. 10 is a schematic explanatory diagram of a state change of another P-state cache line in a partial write data process according to an embodiment of the present invention.
  • FIG. 11 is a schematic explanatory diagram of a state change of an I-state cache line in a partial write data process according to an embodiment of the present invention.
  • FIG. 12 is a schematic flowchart of a Cache read data according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of a state change of a P-state cache line in a process of reading target data according to an embodiment of the present invention
  • FIG. 14 is a schematic flowchart of a Cache write data according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a cache controller according to an embodiment of the present invention.
  • FIG. 16 is a schematic structural diagram of another cache controller according to an embodiment of the present invention.
  • FIG. 17 is a schematic structural diagram of a processor according to an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
  • processor central processing unit (CPU), cache memory (Cache), The relationship between memory (also known as main memory).
  • the CPU, the Cache and the memory involved in the present invention can be applied to an electronic terminal, and the electronic terminal can include a processor and a memory, and the electronic terminal can include a computer, a smart phone, a tablet, a smart TV, a smart bracelet, and a VR glasses.
  • a wearable device such as a smart watch, an in-vehicle terminal, or the like is not limited in the present invention.
  • FIG. 1 is a schematic block diagram of a computer processing system including a processor, a cache memory, and a memory according to an embodiment of the present invention.
  • the processor may be a single-core processor or a multi-core processor, that is, includes a first core CPU and a second core CPU, and the current processor may include three levels of cache memory, which are respectively level 1 caches (also called L1 Cache), Level 2 cache (also known as L2 Cache) and Level 3 cache (also known as L3 Cache).
  • level 1 caches also called L1 Cache
  • Level 2 cache also known as L2 Cache
  • Level 3 cache also known as L3 Cache
  • the L1 Cache is composed of an instruction cache and a data cache.
  • the L2 Cache or the L3 Cache may include data and instructions.
  • the L1 Cache and the L2 Cache are unique to each core, and the L3 Cache is shared by all cores in the same CPU.
  • the Cache is divided into multiple cache lines. Each cache line can be 64 bits.
  • the cache line is the minimum unit of the Cache and the lower level cache, or the Cache and memory data exchange.
  • the cache line in the Cache may include a data area and a flag area; the data area may include a data field for storing data, and the flag area may include an address field, a status field, and the like.
  • the state of the cache line may also be referred to as the state of the cache line.
  • FIG. 2 is a schematic diagram of a Cache according to an embodiment of the present invention.
  • the cache memory shown in FIG. 2 may include a cache controller 20 and a cache line area 21; the cache line area 21 includes a plurality of cache lines, such as, for example, a cache line 211, a cache line 212, a cache line 213, etc., and the cache line may include a data field, an address field, a status field, and a write mask field; wherein
  • Data fields are used to store data
  • the address field is used to indicate address information of data stored in the cache line
  • the status field is used to indicate the status of the cache line; the status includes a partial write status; the partial write status is used to indicate that the data portion of the cache line is valid;
  • the write mask field is used to store the write mask, and the write mask is used to indicate the location of the data that has been written in the cache line;
  • the cache controller 20 is configured to receive the request and respond to the request, update the status of the cache line of the response request, and the write mask.
  • the state of the cache line includes a modified state (also referred to as an M state), an exclusive state (also referred to as an E state), a shared state (also referred to as an S state), and an invalid state. (invalid) state (also called I state) and partial writed state (also called P state);
  • the cache controller 20 is configured to receive a request and respond to the request, update a status of a cache line responsive to the request, and a write mask.
  • the size of the data of the cache line in the partial write state is smaller than the size of the storable data of the cache line, and the data part of the cache line is valid, and the data in the corresponding memory is inconsistent.
  • the address field is used to store the address of the data stored in the corresponding cache line.
  • Information which can be the physical address in the memory where the data is stored.
  • the state of the Cache defines a P state in addition to the M, E, S, and I states, and the cache line in the P state is inconsistent with the data in the memory and passes the write mask. To indicate the location of the data that has been written, so that in the process of partially writing data or reading data, the data exchange between the memory and the Cache is reduced, and the data processing efficiency of the Cache is improved.
  • FIG. 3 is a schematic diagram of another Cache according to an embodiment of the present invention.
  • the cache memory shown in FIG. 3 may include: a cache controller 30, a cache line area 31, and a mask area 32.
  • the cache line area 31 includes a plurality of cache lines, such as a cache line 311, a cache line 312, and a cache line 313.
  • the cache line includes a data field, a first address field, a status field, and a mask index field;
  • the mask area 32 includes a mask line corresponding to the cache line, for example, a mask line 321 corresponding to the cache line 311, and a cache line 313
  • mask region 32 may further include a null mask row 323, and the mask row includes a write mask field;
  • the cache line includes a data field for storing data
  • the first address field is used to indicate address information of data stored in the cache line
  • the status field is used to indicate the status of the cache line; the status includes a partial write status; the partial write status is used to indicate that the data portion of the cache line is valid;
  • the mask index field is used to indicate address information of a write mask field of the cache line
  • the write mask field is used to store the write mask, and the write mask is used to indicate the location of the data that has been written in the cache line corresponding to the mask row;
  • the cache controller is configured to receive the request and respond to the request, update the status of the cache line of the response request, and the write mask.
  • the mask index field stores the address information of the mask area 32; the mask line further includes a second address field, and the second address field is used to indicate the cache line corresponding to the mask line.
  • FIG. 4 is a schematic diagram of another Cache according to an embodiment of the present invention.
  • the cache memory shown in FIG. 4 may include: a cache controller 40, a cache line area 41, and a mask area 42.
  • the cache line area 41 includes a plurality of cache lines, such as a cache line 411, a cache line 412, and a cache line 413.
  • the cache line includes a data field, a first address field, a status field, and a mask index field;
  • the mask area 42 includes a mask line corresponding to the cache line, for example, a mask line 421 corresponding to the cache line 411, and a cache line 413
  • the corresponding mask row 422, the mask area 42 may further include an empty mask row 423.
  • the mask area 42 includes a second address field and a write mask field, and the mask index field It is the address information of the mask area 42.
  • the first address field may be address information of the memory corresponding to the cache line, and the address information may be a physical address in the memory where the data is stored.
  • the second address field may be the same as the address information in the first address field of the cache line corresponding to the mask row, or may be the address information of the cache line corresponding to the mask row in the cache.
  • the mask area may be a fixed storage area in the Cache or a variable storage area.
  • the mask area may store only the write mask corresponding to the cache line in the P state.
  • the mask index field in the non-P state may be empty, or may be the address information of the mask row whose write mask is all 0.
  • the mask index field in the non-P state may also be the same as the content of the mask index field corresponding to the cache line of the P state.
  • the number of cache lines can be greater than the number of mask rows, and the number of cache lines in the P state is not greater than the total number of cache lines.
  • the number of mask rows is not less than the number of cache lines in the P state.
  • a mask row needs to be allocated.
  • the write mask of the cache line of the newly added P state can be written to the idle mask row, and the address information of the idle mask row is Update to the mask index field corresponding to the cache line of the newly added P state.
  • the write mask of the cache line of the newly added P state can be written to the idle mask row, and updated to the newly added P state.
  • the mask index field corresponding to the cache line, for the mask area of the variable area the address information of the changed mask area needs to be updated for all the mask index fields.
  • a partial mask area needs to be released by an algorithm to provide an idle mask line.
  • the method for releasing the mask area may be: the cache controller writes the data of the cache line corresponding to the partial mask row to the next level cache or memory, and releases the idle cache line and the idle mask line.
  • the state of the Cache defines a P state in addition to the M, E, S, and I states, and the cache line in the P state is inconsistent with the memory data, and passes through Write a mask to indicate the location where the data has been written, so that in the process of partially writing data or reading data, the data exchange between the memory and the Cache is reduced, and the data processing efficiency of the Cache is improved.
  • the byte is a unit of information transmission or storage, and one byte is equal to 8-bit binary.
  • the size of the write mask field is n/8 bytes, and n is the number of bytes of data stored in the cache line in the partial write state.
  • the initial state of the write mask is all 0, and after the partial write data, the write mask corresponding to the partially written position is 1.
  • the Cache shown in FIG. 2, FIG. 3, or FIG. 4 may be any one of an L1 Cache, an L2 Cache, or an L3 Cache.
  • the address information involved in the Cache shown in FIG. 2, FIG. 3 or FIG. 4 may be an address range or a start address.
  • the address information of the address field tag in the cache line 211 is "0x0000", and the data size that can be stored in the cache line 211 is fixed, such as 32 bits in FIG. 2, so that the address range of the memory in which the data is located can be determined.
  • the address field can also be marked as "0x0000-0x001F".
  • state of the cache line may also include an O (owned) state, an F (forward) state, and the like, which are not limited in the present invention.
  • the cache line may further include an error-correcting code (ECC) field.
  • ECC error-correcting code
  • cache controller 20 is used to implement various steps in the method embodiment of the present invention. For details, refer to the related description in the method embodiment of the present invention, and details are not described herein again.
  • each cache line has five states, which can be represented by three or four bits, which are shown in the following table:
  • the cache lines of the M, E, and P states have unique data, wherein the data in the M and P states is dirty (that is, inconsistent with the data in the memory), and the data in the E state is clean (ie, Consistent with the data in memory).
  • the cache line of the S state whose data is shared with the cache of other cores. Only clean data can be shared by multiple Caches.
  • the cache line of the I state has invalid data.
  • FIG. 5 is a schematic diagram of migration of a MESIP protocol state according to an embodiment of the present invention.
  • Local Read represents the value in the kernel read buffer line
  • Local Write represents the value in the kernel write cache line
  • Remote Read indicates that other kernels read the values in other cache cache lines
  • Remote Write indicates other kernel writes.
  • Local Write Partial indicates the value in the partial cache of the kernel, and the write mask is not all 1 after the partial write is completed.
  • the Local Write Full event is triggered, the data of the cache line is written into the main memory (or the next level Cache), and the cache line is released, and the state of the cache line is changed to I; or , mark the status of this cache line as M.
  • the direction of the arrow indicates the direction in which this cache line state is migrated.
  • the Cache can import the data A from the memory or import the data A from other Caches, and different processors will There are different options.
  • the MESI protocol does not define these details, only the migration between states is defined. The description of the migration process between the following MESIP states assumes that the Cache imports data A from memory.
  • the initial write mask can be that the write mask of the cache line is all marked as 0.
  • the initial write mask may also be to release the mask row corresponding to the cache line.
  • the Cache's cache controller is responsible for listening to the memory read and write operations of its own CPU (including read/write/partial write hits and misses), and is also responsible for listening to the memory read and write activities of other CPUs on the bus (including reading). /Write/partial write hits and misses) and handle the Cache of the confidant accordingly. All processes must maintain Cache consistency to conform to the MESIP conversion rules.
  • state of the data may also include an O (owned) state, an F (forward) state, and the like.
  • the MESIP protocol may also be evolved into a MOESIP protocol, a MESIFP protocol, etc., and the present invention is not limited.
  • the CPU or the kernel may send a request to the cache controller, and the format of the request may include a type field, an address field, a data field, etc., respectively, for indicating the request type (eg, read, write, partial write, etc.), request address, request carrying The data.
  • the request address is the address of the memory.
  • the processor When the CPU needs to request to read, write or partially write the data A in the main memory, the processor first checks whether there is the data A from the Cache. If the data A is present in a cache line of the Cache, the processor can immediately read, write or partially write data from the cache line. If the data A is not present in all the cache lines in the Cache, it is a Cache Miss. When the Cache is missing, that is, when Cache Miss occurs, the cache controller newly allocates a cache line in the Cache and reads the data A from the main memory (or the next level Cache) into the Cache. When Cache Miss, a new cache line needs to be allocated. At this time, the Cache is likely to have no idle cache line. It is necessary to sacrifice the original cache line. Existing LRU, FIFO and other algorithms are used to implement the release of the cache line.
  • the data stored in the cache line also exists in the memory, and the address in which the memory stores the data has a mapping relationship with the cache line.
  • the data stored in the cache line is inconsistent or partially in memory, and the cache line and the address of the memory are also mapped.
  • the address information stored in the address field of the cache line may be the address of the stored data in the memory.
  • the cache controller can detect whether the request is hit according to the address information stored in the address field.
  • FIG. 6 is a schematic flowchart of a Cache partial write data according to an embodiment of the present invention.
  • the processing method includes:
  • Step S61 The cache controller receives a partial write request.
  • the partial write request is used to indicate that the data written by the partial write request is written to the request address at a corresponding position in the cache line.
  • the size of the data carried by the partial write request is smaller than the size of the cacheable data of the cache line.
  • the request address can be an address range, such as "0x0000-0x000F", the data carried by the partial write request is 2 characters; or "0x000F-0x0017", and the data carried by the partial write request is 1 character.
  • the size of the data carried by the partial write request is smaller than the size of the complete data that the data field of the cache line can store.
  • the request address may also be an initial address, such as "0x0000”.
  • the byte of the data carried by the partial write request is a fixed value, such as 2 bytes.
  • Step S62 It is judged whether the partial write request is hit.
  • the cache controller detects whether the address field of the cache line includes an address that is consistent with or corresponds to the request address. If yes, for example, the request address is “0x000F”, the cache line corresponding to the request address exists in the cache, and the cache line The address field is marked as "0x0000" size 32 or the address field is marked as "0x0000-0x001F", then a partial write request hits, and the cache controller can perform step S63.
  • the cache controller may perform step S64.
  • Step S63 Write the data carried by the partial write request to the corresponding location in the cache line of the hit request address.
  • the request address is “0x000F”
  • the data carried by the partial write request is “E”
  • the cache controller writes the data “E” carried by the partial write request to the location of the corresponding request address in the cache line.
  • Step S64 Allocating a cache line, and carrying the partial write request carrying the data write request address at a corresponding position in the allocated cache line.
  • the cache controller allocates a new cache line for the partial write request in the cache, and initializes the write buffer of the allocated cache line to 0, and establishes a correspondence with the memory.
  • the update address field is the memory address corresponding to the request address
  • the data stored in the allocated cache line is empty, that is, " ⁇ ", where ⁇ indicates that the stored data is invalid, and then the partial write request is carried.
  • the data write request address is in the corresponding position in the allocated cache line. At this time, the data stored in the allocated cache line is " ⁇ E ⁇ ".
  • the cache controller when the partial write request is missed, the cache controller also needs to allocate a new mask row, and initializes the write mask of the allocated mask row to 0.
  • the cache controller can directly write the data carried by the partial write request in the allocated cache line, and read the data of the memory, and after the partial write is completed, the cache line is not updated yet.
  • Data to memory can reduce data exchange between Cache and memory, reduce the occupation of memory bandwidth, and thus increase the data processing rate.
  • Step S65 Update the write mask of the cache line.
  • the cache controller may update the write mask according to the request address, that is, update the write mask of the request address to the corresponding position in the cache line to 1.
  • Step S66 It is judged whether the write mask of the updated cache line is all ones.
  • the cache controller may perform steps S67, S69, or perform steps S68, S69.
  • Step S67 Write the data of the cache line into the memory or the next level cache, and initialize the write mask of the cache line. For details, refer to the related description in the first mode of transition in the embodiment shown in FIG. 10, and the present invention is not described herein.
  • Step S68 Initialize the write mask of the cache line. For details, refer to the related description in the second mode of the embodiment shown in FIG. 10, and the present invention is not described herein.
  • Step S69 Update the state of the cache line.
  • the cache controller can update the state of the cache line.
  • step S62 if the cached behavior of the E state or the S state is hit, the E state is example.
  • FIG. 7 is a schematic explanatory diagram of a state change of a cache line of an E state in a partial write data process according to an embodiment of the present invention.
  • the data stored in the cache line is "ABCD”, and the write mask is "0000".
  • the data of the cache line is modified to "ABED", the status changes to the M state, and the initial write mask is "0000".
  • FIG. 8 is a diagram showing a state change of a M-state cache line in a partial write data process according to an embodiment of the present invention. Schematic diagram. Before step S63, the data stored in the cache line does not exist in the memory. As shown in FIG. 8, it is assumed that the data currently stored in the cache line is "MNOP", and the data stored in the file is "ABCD", after passing through steps S63, S65, and S69. The data of the cache line is modified to "MNEP", the write mask and the state remain unchanged.
  • FIG. 9 is a diagram showing a state change of a P-state cache line in a partial write data process according to an embodiment of the present invention. Schematic diagram.
  • the data stored in the cache line does not exist in the memory (for example, the data is " ⁇ S ⁇ ", where S is the data written in the newly allocated cache line), as shown in FIG.
  • the data of the cache line is " ⁇ S ⁇ " as an example.
  • the data stored in the file is "ABCD" and the write mask is "0100”.
  • the data of the cache line is modified to " ⁇ SE ⁇ ”
  • the write mask is updated to “0110”
  • the status is unchanged, and it is the P status.
  • step S62 if the cached behavior P state is hit, please refer to FIG. 10, which is a state change of another P-state cache line in the process of partially writing data according to an embodiment of the present invention.
  • FIG. 10 is a state change of another P-state cache line in the process of partially writing data according to an embodiment of the present invention.
  • the data stored in the cache line does not exist in the memory (for example, the data is "RS ⁇ T", wherein R, S, and T are the data written in the cache line in the previous or previous times) 10 taking the data of the cache line as "RS ⁇ T" as an example, the data stored in the file is "ABCD", and the write mask is "1101".
  • the data of the cache line is modified to " RSET", the write mask is updated to "1111", triggering the Local Write Full event. After the Local Write Full event is triggered, there are two ways to change the cache line:
  • the first mode of transition after steps S67 and S69, the cache inline data "RSET" is updated into the memory, the cache line is released, the state is changed to the I state, and the write mask is initialized ("0000" or the mask row is Released, there is no corresponding write mask), there is no corresponding relationship between the cache line and the memory.
  • the data can be updated to the memory to avoid frequent data exchange between the Cache and the memory caused by frequent updates to the memory, which can reduce the occupation of memory bandwidth and release the Cache in time to improve the utilization of the Cache.
  • the second mode of transition after steps S68 and S69, the data in the cache line is “RSET”, the state of the update cache line is M state, the write mask is initialized (for “0000” or the mask row is released, there is no corresponding Write mask).
  • This conversion method can reduce the exchange of data between the Cache and the memory, thereby increasing the data processing rate.
  • step S62 if it is not hit, the cache controller allocates a new cache line, and the allocated cache behavior is I state.
  • FIG. 11 is a schematic explanatory diagram of a state change of an I-state cache line in a partial write data process according to an embodiment of the present invention.
  • the cache line Before step S64, there is no corresponding relationship between the cache behavior I state and the memory "ABCD". As shown in FIG. 11, the cache line has no data " ⁇ ”, and the stored data is "ABCD”.
  • steps S64 and S65 the cache line is partially written to "E", the data of the cache line is " ⁇ E ⁇ ", the state is changed to the P state, and the write mask is updated to "0010".
  • FIG. 12 is a schematic flowchart of a Cache read data according to an embodiment of the present invention.
  • the method for reading data by the Cache includes:
  • Step S121 The cache controller receives the read request.
  • the read request includes a request address for requesting to read data corresponding to the request address in the Cache.
  • the read request may be a first read request or a second read request, where the first read request is used to request data corresponding to the first request address in the cache line; the second read request is used to request The data corresponding to the second request address in the cache line.
  • the request address can be an address range such as "0x0000-0x000F” or "0x000F-0x0017".
  • the request address may also be an initial address, such as "0x0000", in which case the byte of the data requested to be read is a fixed value, such as 2 bytes.
  • the request address is “0x0008”, and the size of the data corresponding to the request address is 1 character, which will be described as an example.
  • Step S122 Determine whether the read request is hit.
  • the method for determining whether the read request is hit is similar to the method for determining whether the partial write request is hit in the step S62 in the embodiment shown in FIG. 6, and the step S62 is omitted.
  • the data corresponding to the request address in the cache is cached in the cache, and the cache line of the hit may be a cache line in the S, E, and M states, or may be a cache line in the P state, and the cache controller Step S123 can be performed.
  • the cache controller may perform step S125.
  • Step S123 It is determined whether all data corresponding to the request address in the cache line of the hit exists.
  • the cache controller may execute step S126 to return the data. At this point, the state of the hit cache line remains the same.
  • the data stored in the cache line is consistent with the memory, and the data read by the cache controller is “B”.
  • the data stored in the cache line is inconsistent with the memory, and the data stored in the cache line is the latest data.
  • the data stored in the cache line of the M state is “MNOP”, and the data read by the cache controller is "N”.
  • the cache controller may further determine whether the data corresponding to the request address in the hit cache line exists according to the write mask of the hit cache line. It can be understood that, when the write mask corresponding to the request address in the hit cache line is not all 1, the part or all of the data corresponding to the request address does not exist in the cache line of the hit, and the cache controller may perform step S124; otherwise If the write mask corresponding to the request address in the hit cache line is 1, the data corresponding to the request address exists in the cache line that is hit, and the cache controller may perform step S126. Returning data, for example, if the data stored in the cache line of the hit is " ⁇ E ⁇ ", the cache controller returns the data "E".
  • Step S124 According to the write mask of the hit cache line, the data read from the memory corresponding to the request address or the corresponding next level cache is merged into the cache line of the hit, and the state of the merged cache line and the write mask are updated. code.
  • the memory corresponding to the first location or the data in the next level cache is written to a first location in the hit cache line, where the first location includes a location in the cache line where the write mask is 0.
  • the data of the first location in the cache line after the write and the data of the second location form a merged cache line; and the second location includes the location of the write buffer of the hit cache line of 1. That is to say, the data corresponding to the position where the write mask is 0 in the hit cache line is updated to the corresponding data in the memory, and the data corresponding to the position where the write mask is 1 in the hit cache line does not change.
  • the state of the merged cache line is updated to the M state, and the write mask is initialized. Corresponding to the Cache shown in FIG. 3 or FIG. 4, the mask row can also be released.
  • FIG. 13 is a schematic explanatory diagram of a state change of a P-state cache line in a process of reading data according to an embodiment of the present invention.
  • the data stored in the cache line of the hit is " ⁇ E ⁇ ", the state is P state, the write mask is "0010”, and the corresponding data in the memory is "ABCD";
  • the data stored in the cache line of the hit is "ABED”, the state is M state, the write mask is initialized to "0000", and the corresponding data in the memory is "ABCD”.
  • Step S125 Allocating a cache line, and reading data from the memory corresponding to the request address or the corresponding next level cache to the allocated cache line.
  • the cache controller may allocate a new cache line, and read data such as “ABCD” from the memory corresponding to the request address or the corresponding next level cache to the allocated cache line.
  • the allocated cache line stores the data as "ABCD”, the state is the E state, and the write mask is "0000".
  • the data is the data corresponding to the requested address in the allocated cache line, that is, "B".
  • the cache line of the E state may not include the mask line and the write mask.
  • Step S126 In response to the read request, return data corresponding to the request address.
  • the cache controller reads the data corresponding to the request address from the hit cache line or the allocated cache line, and returns to the CPU.
  • FIG. 14 is a schematic flowchart of a Cache write data according to an embodiment of the present invention.
  • the method for the Cache to write data includes:
  • Step S141 The cache controller receives the write request.
  • the write request is used to indicate that the data carried by the write request is written to the cache line corresponding to the request address in the cache line.
  • the write event is a modification of the data of the entire cache line.
  • the size of the data carried by the write request is equal to the size of the data that the data field of the cache line can store.
  • the request address may be an address range, such as “0x0000-0x001F”, the data carried by the write request is 4 characters, or may be an initial address, such as “0x0000”.
  • the byte of the data carried by the write request is a fixed value. Like 4 byte.
  • Step S142 Determine whether the write request is hit.
  • the cache controller detects whether the address field of the cache line includes an address that is consistent with or corresponds to the request address. If yes, for example, if there is a cache line corresponding to the request address in the cache, the address field of the cache line is marked as “0x0000”. "The size 32 or the address field is marked as "0x0000-0x001F", then the partial write request hits, and the cache controller can execute step S143.
  • the cache line of the hit can be a cache line of the M, S or E state, or a cache line of the P state.
  • the cache controller may perform step S144.
  • Step S143 Write the data carried by the write request into the cache line of the hit.
  • the cache controller writes the data "EFGH" carried by the write request to the cache line of the hit.
  • Step S144 Allocating a cache line, and writing data carried by the write request to the allocated cache line.
  • the cache controller allocates a new cache line in the cache, initializes the allocated cache line with a write mask of 0, and establishes a correspondence with the memory (for example, the update address field is the request address).
  • the data stored in the allocated cache line is empty, that is, " ⁇ ", where ⁇ indicates that the stored data is invalid, and the write request carrying data is written to the allocated cache line.
  • the allocated cache line is The stored data is "EFGH".
  • Step S145 Update the state of the cache line.
  • control buffer can update the status of the hit cache line to M.
  • step S145 further includes updating the write mask to "0000" or releasing the mask line corresponding to the hit cache line.
  • FIG. 15 is a schematic structural diagram of a cache controller according to an embodiment of the present invention.
  • the cache controller 150 is configured to implement the foregoing method for partially writing data, and may include:
  • the receiving unit 151 is configured to receive a partial write request, where a size of the data carried by the partial write request is smaller than a size of the cacheable data of the cache line;
  • the writing unit 152 is configured to write the data carried by the partial write request to a location corresponding to the request address in the cache line;
  • An update unit 153 configured to update a write mask of the cache line; and update a state of the cache line;
  • the state of the cache line includes a partial write state; the partial write state is used to indicate that a data portion of the cache line is valid; and the write mask is used to indicate data that has been written in the cache line. position.
  • the writing unit 152 yuan is specifically used for:
  • the cache line hits the cache line, and the data carried by the partial write request is written to the corresponding location in the cache line of the hit request address;
  • the cache line is allocated for the partial write request, and the data carried by the partial write request is written to the corresponding location in the allocated cache line of the request address.
  • the updating unit 153 is configured to: when updating the write mask of the cache line, specifically: Updating the write mask of the cache line according to the request address.
  • the writing unit 152 is further configured to: write data of the cache line into a memory or a next level cache;
  • the updating unit 153 is further configured to: initialize a write mask of the cache line, and update a state of the cache line to an invalid state.
  • the updating unit 153 is further configured to: initialize a write mask of the cache line, and update a state of the cache line to a modified state.
  • FIG. 16 is a schematic structural diagram of another cache controller according to an embodiment of the present invention.
  • the cache controller 160 implements the foregoing method for reading data, and may include:
  • the receiving unit 161 is configured to receive a first read request, where the first read request is used to request to read data corresponding to the first request address in the cache line;
  • the merging unit 162 is configured to: when the first read request occurs a cache hit and the part of the data corresponding to the first request address does not exist in the cache line of the hit, the write mask of the cache line according to the hit Merging data read from the memory corresponding to the first request address or the corresponding lower level cache into the cache line of the hit;
  • the updating unit 163 is configured to update a state of the merged cache line and a write mask.
  • the reading unit 164 is configured to read data corresponding to the first request address in the merged cache line.
  • the state of the cache line includes a partial write state; the partial write state is used to indicate that a data portion of the cache line is valid; and the write mask is used to indicate data that has been written in the cache line. position.
  • the receiving unit 161 is further configured to: receive a second read request, where the second read request is used to request to read data corresponding to the second request address in the cache line;
  • the reading unit 164 is further configured to: when a cache hit occurs in the second read request and the state of the hit cache line is not in a partial write state; or, when the second read request occurs in a cache hit, When the state of the cache line of the hit is a partial write state and the write mask corresponding to the second request address in the hit cache line is 1, the second request is read in the cache line of the hit. The data corresponding to the address.
  • the part or all of the data corresponding to the first request address does not exist in the cache line of the hit includes: the state of the hit cache line is a partial write state and the cache line of the hit The write mask corresponding to the first request address is not all 1; the merging unit 162 is specifically configured to:
  • the first location includes a write mask in the cache line of the hit a position of 0;
  • the data of the first location and the data of the second location in the cache line after the write form a merged cache line; the second location includes a location where the write mask is 1 in the cache line of the hit. .
  • FIG. 17 is a schematic structural diagram of a processor according to an embodiment of the present invention.
  • the processor may include at least one core 171 and at least one cache. 172.
  • the cache 172 can be the Cache shown in FIG. 2, FIG. 3 or FIG.
  • FIG. 18 is a schematic structural diagram of a processor according to an embodiment of the present invention.
  • the terminal may include a processor 181 and a memory 182, and the processor 181 is connected to
  • the processor 181 is configured to store data and instructions, and the processor 181 is configured to invoke instructions stored in the memory 182 to implement various functions of the terminal.
  • the processor 182 can be the processor shown in FIG.
  • the processor 181 is the control center of the terminal, and connects various parts of the entire terminal using various interfaces and lines, by executing or executing computer programs and/or modules stored in the memory 182, and calling data stored in the memory 182, executing The terminal's various functions and processing data, so as to monitor the terminal as a whole.
  • the processor 182 may include one or more processing cores; preferably, the processor 181 may integrate an application processor and a modem processor, where the application processor mainly processes an operating system, a user interface, an application, and the like.
  • the modem processor primarily handles wireless communications. It can be understood that the above modem processor may not be integrated into the processor 181.
  • the memory 182 can be used to store computer programs and modules, and the processor 181 can execute various functional applications and data processing by running computer programs and modules stored in the memory 182.
  • the memory 182 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application required for at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may be stored according to The data created by the use of the terminal (such as the parking lot map, geographic location, etc. described in the embodiments of the present invention) and the like.
  • memory 182 can include high speed random access memory, and can also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
  • the terminal can also include a communication interface, an input device or an output device, and the like. It should be noted that the communication interface, the input device, the output device, and the like do not necessarily belong to the terminal, and may be omitted as needed within the scope of not changing the essence of the invention.
  • the input device can be used to receive input numeric or character information and to generate keyboard, mouse, joystick, optical or trackball signal inputs related to user settings and function controls.
  • Input devices can also include touch-sensitive surfaces as well as other input devices.
  • a touch-sensitive surface also known as a touch display panel or touchpad, collects touch operations on or near the user (eg, the user uses a finger, stylus, etc., any suitable object or accessory on a touch-sensitive surface or is touch sensitive Operation near the surface), and drive the corresponding connecting device according to a preset program.
  • the output device can be used to display information input by the user or information provided to the user and various graphical user interfaces of the terminal (such as the mobile track display interface described in the embodiments of the present invention), and the graphical user interfaces can be graphically, Text, icons, videos, and any combination of them.
  • the output device may include a display panel or the like.
  • the communication interface is configured to establish a communication channel, the terminal is connected to the communication peer through the communication channel, and the data is exchanged with the communication peer through the communication channel.

Abstract

一种部分写数据方法，包括：缓存控制器（20，30，40，150，160）接收部分写请求（S61）；所述部分写请求携带的数据的大小小于缓存行（211，212，213，311，312，313，411，412，413）可缓存数据的大小；将部分写请求携带的数据写入请求地址在缓存行（211，212，213，311，312，313，411，412，413）中对应的位置，更新缓存行（211，212，213，311，312，313，411，412，413）的写掩码（S65），以及更新缓存行（211，212，213，311，312，313，411，412，413）的状态（S69，S145）。一种读数据方法，以及相关装置。通过在缓存行（211，212，213，311，312，313，411，412，413）的状态中增加部分写状态，以及通过写掩码来表示该缓存行（211，212，213，311，312，313，411，412，413）中已被写入的数据的位置，使得缓存控制器（20，30，40，150，160）在部分写或读数据过程中，减少内存与高速缓冲存储器（172）的数据交换，提高高速缓冲存储器（172）的数据处理效率。

Description

读、部分写数据方法以及相关装置 技术领域
本发明涉及计算机技术领域，尤其涉及一种读、部分写数据方法以及相关装置。
背景技术
目前，计算机等终端设备在数据处理过程，以基于弹性分布式数据集(resilient distributed dataset，RDD)的分布式大数据处理框架(Spark)应用为例，在处理器运行过程中，数据大多以RDD的形式存在于内存中，针对RDD的操作主要是变换和运算。
数据转换操作需要从主存将数据读入到高速缓冲存储器(Cache)中，经过处理器变换后再写入到Cache或者主存中。通常，RDD的变换操作会产生新的RDD，RDD变换过程中需要将数据从主存中读入Cache，变换后的数据因为容量的原因最终会被替换写入到主存中，当处理器将变换后的数据从寄存器写入到Cache中，可能性会发生未命中(Cache Miss)，当Cache Miss发生时，需要从主存(或者下一级Cache中)去读取数据到Cache中。
因而，在大数据场景下，处理数据量远大于Cache容量，需要频繁的Cache之间、Cache与主存之间的数据交换。变换后的数据并不会很快用到，将主存(或下一级Cache)中读取到Cache中的数据，并不会被用到，较长时间占用Cache，使得实际Cache利用率降低。
发明内容
本发明实施例提供了一种读、部分写数据方法以及相关装置，可以减少在部分写数据过程中内存与Cache的数据交换频率，提高Cache的数据处理效率。
第一方面，本发明实施例提供了一种部分写数据方法，包括：
缓存控制器接收部分写请求，该部分写请求携带的数据的大小小于缓存行可缓存数据的大小,将部分写请求携带的数据写入请求地址在缓存行中对应的位置，更新缓存行的写掩码，以及更新缓存行的状态。其中，缓存行的状态包括部分写状态；部分写状态用于指示所述缓存行的数据部分有效；写掩码用于指示缓存行中已被写入的数据的位置。
可以理解，该部分写数据方法的执行主体还可以是包括该缓存控制器的Cache、包括上述Cache的处理器、包括上述处理器的电子终端等。
本发明实施例中，缓存的数据状态包括部分写状态，并通过写掩码来标志已被写入的数据的位置，在部分写数据过程中，将部分写请求携带的数据写入请求地址在缓存行中对应的位置，不需要从内存中读入中的数据，也不需要在部分写完成后将数据更新到内存，进而减少在部分写数据过程中内存与Cache的数据交换频率，提高Cache的数据处理效率。
本发明一实施例中，缓存控制器将部分写请求携带的数据写入请求地址在所述缓存行中对应的位置的实施方式可以是：
在部分写请求发生缓存命中时，将部分写请求携带的数据写入请求地址在命中的缓存行中对应的位置；或，
在部分写请求未命中时，为部分写请求分配缓存行，将部分写请求携带的数据写入请求地址在分配的缓存行中对应的位置。
本发明一实施例中，缓存控制器更新所述缓存行的写掩码的实施方式可以是：缓存控制器根据请求地址更新所述缓存行的写掩码，即将缓存行中请求地址对应的写掩码标记为1。
本发明一实施例中，当更新后的缓存行的写掩码全为1时，缓存控制器还可以：将该缓存行的数据写入内存或下一级高速缓冲存储器中，并初始化该缓存行的写掩码；此时，缓存控制器更新缓存行的状态的一种实施方式可以是：缓存控制器更新该缓存行的状态为无效状态。
本发明实施例中，在写掩码全为1时，才将缓存行内的数据更新到内存，并释放缓存行，提高Cache的利用率。
本发明一实施例中，当更新后的缓存行的写掩码全为1时，缓存控制器还可以：初始化该缓存行的写掩码；此时，缓存控制器更新缓存行的状态的一种实施方式可以是：更新缓存行的状态为修改状态。
本发明实施例中，在写掩码全为1时，而修改缓存行的状态为M状态，而不将缓存行内的数据更新到内存，进一步减少内存与Cache的数据交换频率，减少内存宽带占用，提高Cache的数据处理效率。
第二方面，本发明实施例还提供了一种读数据方法，包括：
缓存控制器接收第一读请求；第一读请求用于请求读取第一请求地址在缓存行中对应的数据；当第一读请求发生缓存命中且命中的缓存行中该第一请求地址对应的数据部分或全部不存在时，根据命中的缓存行的写掩码，将从第一请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到命中的缓存行中，并更新合并后的缓存行的状态以及写掩码；以及，在合并后的缓存行中读取第一请求地址对应的数据；其中，缓存行的状态包括部分写状态；部分写状态用于指示缓存行的数据部分有效；写掩码用于指示所述缓存行中已被写入的数据的位置。
可以理解，该读数据方法的执行主体还可以是包括该缓存控制器的Cache、包括上述Cache的处理器、包括上述处理器的电子终端等。
本发明实施例中，缓存的数据状态包括部分写状态，并通过写掩码来标记已被写入的数据的位置，在读数据过程中，第一读请求命中且命中的缓存行中该第一请求地址对应的数据部分或全部不存在时，才根据命中的缓存行的写掩码，将从第一请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到命中的缓存行中，减少在读数据过程中内存与Cache的数据交换频率，提高Cache的数据处理效率。
本发明一实施例中，缓存控制器还可以接收第二读请求，该第二读请求用于请求读取第二请求地址在缓存行中对应的数据；当第二读请求发生缓存命中且命中的缓存行的状态不为部分写状态时；或，当第二读请求发生缓存命中，命中的缓存行的状态为部分写状态且命中的缓存行中第二请求地址对应的写掩码都为1时，缓存控制器可以直接在命中的缓存行中读取第二请求地址对应的数据，减少在读数据过程中内存与Cache的数据交换频率， 提高Cache的数据处理效率。
本发明一实施例中，在命中的缓存行中第一请求地址对应的数据部分或全部不存在即为：命中的缓存行的状态为部分写状态且命中的缓存行中第一请求地址对应的写掩码不都为1。此时，
缓存控制器器将从请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中的一种实施方式可以是：将第一位置对应的内存或下一级高速缓冲存储器中的数据，写入命中的缓存行中的第一位置；该第一位置包括命中的缓存行中写掩码为0的位置，其中，写入后的缓存行中第一位置的数据与第二位置的数据，形成合并后的缓存行；第二位置包括命中的缓存行中写掩码为1的位置。
第三方面，本发明实施例还提供了一种高速缓冲存储器，包括：缓存控制器以及缓存行区；所述缓存行区包括多个缓存行，所述缓存行包括数据字段、地址字段、状态字段以及写掩码字段；其中，
所述数据字段用于存储数据；
所述地址字段用于指示所述缓存行所存储数据的地址信息；
所述状态字段用于指示所述缓存行的状态；所述状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；
所述写掩码字段用于存储写掩码，所述写掩码用于指示所述缓存行中已被写入的数据的位置；
所述缓存控制器用于接收请求并响应所述请求，更新响应所述请求的缓存行的状态以及写掩码。
缓存的数据状态包括部分写状态，并通过写掩码来标志已被写入的数据的位置，
本发明实施例中，缓存的数据状态包括部分写状态，并通过写掩码标志已被写入的数据的位置，可减少在数据处理过程中内存与Cache的数据交换频率，提高Cache的数据处理效率。
本发明一实施例中，写掩码字段的大小为n/8字节，n为缓存行可存储数据的最大字节数。
本发明一实施例中，请求包括部分写请求，缓存控制器具体用于执行：
接收所述部分写请求；所述部分写请求携带的数据的大小小于所述缓存行可缓存数据的大小；
将所述部分写请求携带的数据写入请求地址在所述缓存行中对应的位置；
更新所述缓存行的写掩码；
更新所述缓存行的状态。
可选地，所述缓存控制器执行将所述部分写请求携带的数据写入请求地址在所述缓存行中对应的位置包括：
在所述部分写请求发生缓存命中时，将所述部分写请求携带的数据写入所述请求地址在所述命中的缓存行中对应的位置；或，
在所述部分写请求未命中时，为所述部分写请求分配的缓存行，将部分写请求携带的 数据写入所述请求地址在所述分配的缓存行中对应的位置。
可选地，所述缓存控制器执行所述更新所述缓存行的写掩码包括：所述缓存控制器根据所述请求地址更新所述缓存行的写掩码。
可选地，当更新后的写掩码全为1时，所述缓存控制器还用于执行：将所述缓存行的数据写入内存或下一级高速缓冲存储器中，并初始化所述缓存行的写掩码；
所述缓存控制器更新所述缓存行的状态包括：所述缓存控制器更新所述缓存行的状态为无效状态。
可选地，当更新后所述缓存行的的写掩码全为1时，所述缓存控制器还用于执行：初始化所述缓存行的写掩码；
所述缓存控制器更新所述缓存行的状态包括：所述缓存控制器更新所述缓存行的状态为修改状态。
本发明一实施例中，请求包括第一读请求，缓存控制器具体用于执行：
接收所述第一读请求；所述第一读请求用于请求读取第一请求地址在所述缓存行中对应的数据；
当所述第一读请求发生缓存命中且在命中的缓存行中所述第一请求地址对应的数据部分或全部不存在时，根据所述命中的缓存行的写掩码，将从所述第一请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中，并更新合并后的缓存行的状态以及写掩码；
在所述合并后的缓存行中读取所述第一请求地址对应的数据。
可选地，所述控制缓存器还用于执行：
接收第二读请求；所述第二读请求用于请求读取第二请求地址在缓存行中对应的数据；
当所述第二读请求发生缓存命中且所述命中的缓存行的状态不为部分写状态时；或，当所述第二读请求发生缓存命中，所述命中的缓存行的状态为部分写状态且所述命中的缓存行中第二所述请求地址对应的写掩码都为1时，在所述命中的缓存行中读取所述第二请求地址对应的数据。
可选地，所述在命中的缓存行中所述请求地址对应的数据部分或全部不存在包括：所述命中的缓存行的状态为部分写状态且所述命中的缓存行中所述请求地址对应的写掩码不都为1；
所述缓存控制器执行所述将从所述请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中包括：
将第一位置对应的内存或下一级高速缓冲存储器中的数据，写入所述命中的缓存行中的所述第一位置；所述第一位置包括所述命中的缓存行中写掩码为0的位置；
其中，写入后的缓存行中所述第一位置的数据与第二位置的数据，形成合并后的缓存行；所述第二位置包括所述命中的缓存行中写掩码为1的位置。
第四方面，本发明实施例还提供了一种高速缓冲存储器，包括：缓存控制器、缓存行区以及掩码区，所述缓存行区包括多个缓存行；所述缓存行包括数据字段、第一地址字段、状态字段以及掩码索引字段；所述掩码区包括与所述缓存行对应的掩码行，所述掩码行包 括写掩码字段；其中，
所述缓存行包括数据字段用于存储数据；
所述第一地址字段用于指示所述缓存行所存储数据的地址信息；
所述状态字段用于指示所述缓存行的状态；所述状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；
所述掩码索引字段用于指示所述缓存行的写掩码字段的地址信息；
所述写掩码字段用于存储写掩码，所述写掩码用于指示所述掩码行对应的缓存行中已被写入的数据的位置；
所述缓存控制器用于接收请求并响应所述请求，更新响应所述请求的缓存行的状态以及写掩码。
本发明实施例中，缓存的数据状态包括部分写状态，并通过写掩码标志已被写入的数据的位置，可减少在数据处理过程中内存与Cache的数据交换频率，提高Cache的数据处理效率。
本发明一实施例中，所述掩码索引字段为掩码区的地址信息；掩码行还包括第二地址字段，第二地址字段用于指示掩码行对应的缓存行。
本发明一实施例中，写掩码字段的大小为n/8字节，n为缓存行可存储数据的最大字节数。
本发明一实施例中，请求包括部分写请求，缓存控制器具体用于执行：
接收所述部分写请求；所述部分写请求携带的数据的大小小于所述缓存行可缓存数据的大小；
将所述部分写请求携带的数据写入请求地址在所述缓存行中对应的位置；
更新所述缓存行对应的写掩码；
更新所述缓存行的状态。
可选地，所述缓存控制器执行将所述部分写请求携带的数据写入请求地址在所述缓存行中对应的位置包括：
在所述部分写请求发生缓存命中时，将所述部分写请求携带的数据写入所述请求地址在所述命中的缓存行中对应的位置；或，
在所述部分写请求未命中时，为所述部分写请求分配的缓存行，将部分写请求携带的数据写入所述请求地址在所述分配的缓存行中对应的位置。
可选地，所述缓存控制器执行所述更新所述缓存行对应的写掩码包括：所述缓存控制器根据所述请求地址更新所述缓存行对应的写掩码。
可选地，当更新后的写掩码全为1时，所述缓存控制器还用于执行：将所述缓存行的数据写入内存或下一级高速缓冲存储器中，并初始化所述缓存行对应的写掩码或释放所述缓存行对应的掩码行；
所述缓存控制器更新所述缓存行的状态包括：所述缓存控制器更新所述缓存行的状态为无效状态。
可选地，当更新后所述缓存行的的写掩码全为1时，所述缓存控制器还用于执行：初始化所述缓存行的写掩码或释放所述缓存行对应的掩码行；
所述缓存控制器更新所述缓存行的状态包括：所述缓存控制器更新所述缓存行的状态为修改状态。
本发明一实施例中，请求包括第一读请求，缓存控制器具体用于执行：
接收所述第一读请求；所述第一读请求用于请求读取第一请求地址在所述缓存行中对应的数据；
当所述第一读请求发生缓存命中且在命中的缓存行中所述第一请求地址对应的数据部分或全部不存在时，根据所述命中的缓存行对应的写掩码，将从所述第一请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中，并更新合并后的缓存行的状态，以及，更新该缓存行对应的写掩码或释放该缓存行对应的掩码行；
在所述合并后的缓存行中读取所述第一请求地址对应的数据。
可选地，所述控制缓存器还用于执行：
接收第二读请求；所述第二读请求用于请求读取第二请求地址在缓存行中对应的数据；
当所述第二读请求发生缓存命中且所述命中的缓存行的状态不为部分写状态时；或，当所述第二读请求发生缓存命中，所述命中的缓存行的状态为部分写状态且所述命中的缓存行中第二所述请求地址对应的写掩码都为1时，在所述命中的缓存行中读取所述第二请求地址对应的数据。
可选地，所述在命中的缓存行中所述请求地址对应的数据部分或全部不存在包括：所述命中的缓存行的状态为部分写状态且所述命中的缓存行中所述请求地址对应的写掩码不都为1；
所述缓存控制器执行所述将从所述请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中包括：
将第一位置对应的内存或下一级高速缓冲存储器中的数据，写入所述命中的缓存行中的所述第一位置；所述第一位置包括所述命中的缓存行中写掩码为0的位置；
其中，写入后的缓存行中所述第一位置的数据与第二位置的数据，形成合并后的缓存行；所述第二位置包括所述命中的缓存行中写掩码为1的位置。
第五方面，本发明实施例还提供了一种缓存控制器，包括：
接收单元，用于接收部分写请求,所述部分写请求携带的数据的大小小于所述缓存行可缓存数据的大小；
写入单元，用于将所述部分写请求携带的数据写入请求地址在所述缓存行中对应的位置；
更新单元，用于更新所述缓存行的写掩码；以及，更新所述缓存行的状态；
其中，所述缓存行的状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；所述写掩码用于指示所述缓存行中已被写入的数据的位置。
本发明一实施例中，所述写入单元具体用于：
在所述部分写请求发生缓存命中时，所述缓存行为命中的缓存行，将所述部分写请求携带的数据写入所述请求地址在命中的缓存行中对应的位置；或，
在所述部分写请求未命中时，为所述部分写请求分配缓存行，将部分写请求携带的数 据写入所述请求地址在分配的缓存行中对应的位置。
本发明一实施例中，所述更新单元用于更新所述缓存行的写掩码时具体用于：根据所述请求地址更新所述缓存行的写掩码。
本发明一实施例中，当更新后的所述缓存行的写掩码全为1时，
所述写入单元还用于：将所述缓存行的数据写入内存或下一级高速缓冲存储器中；
所述更新单元还用于：初始化所述缓存行的写掩码；
所述更新单元用于更新所述缓存行的状态时具体用于：更新所述缓存行的状态为无效状态。
本发明一实施例中，当更新后所述缓存行的的写掩码全为1时，
所述更新单元还用于：初始化所述缓存行的写掩码；
所述更新单元用于更新所述缓存行的状态时具体用于：更新所述缓存行的状态为修改状态。
第六方面，本发明实施例还提供了一种缓存控制器，包括：
接收单元，用于接收第一读请求；所述第一读请求用于请求读取第一请求地址在缓存行中对应的数据；
合并单元，用于当所述第一读请求发生缓存命中且在命中的缓存行中所述第一请求地址对应的数据部分或全部不存在时，根据所述命中的缓存行的写掩码，将从所述第一请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中；
更新单元，用于更新合并后的缓存行的状态以及写掩码；
读取单元，用于在所述合并后的缓存行中读取所述第一请求地址对应的数据。
其中，所述缓存行的状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；所述写掩码用于指示所述缓存行中已被写入的数据的位置。
本发明一实施例中，所述接收单元还用于：接收第二读请求；所述第二读请求用于请求读取第二请求地址在缓存行中对应的数据；
所述读取单元还用于：当所述第二读请求发生缓存命中且所述命中的缓存行的状态不为部分写状态时；或，当所述第二读请求发生缓存命中，所述命中的缓存行的状态为部分写状态且所述命中的缓存行中所述第二请求地址对应的写掩码都为1时，在所述命中的缓存行中读取所述第二请求地址对应的数据。
本发明一实施例中，所述在命中的缓存行中所述第一请求地址对应的数据部分或全部不存在包括：所述命中的缓存行的状态为部分写状态且所述命中的缓存行中所述第一请求地址对应的写掩码不都为1；所述合并单元具体用于：
将第一位置对应的内存或下一级高速缓冲存储器中的数据，写入所述命中的缓存行中的所述第一位置；所述第一位置包括所述命中的缓存行中写掩码为0的位置；
其中，写入后的缓存行中所述第一位置的数据与第二位置的数据，形成合并后的缓存行；所述第二位置包括所述命中的缓存行中写掩码为1的位置。
第七方面，本发明实施例还提供了一种处理器，包括至少一个内核以及至少一个高速 缓冲存储器；高速缓冲存储器为第三方面或第四方面所述的任一种高速缓冲存储器。
第八方面，本发明实施例还提供了一种终端，包括处理器、存储器，所述处理器连接到所述存储器，所述存储器用于存储数据和指令，所述处理器为第七方面所述的任一种处理器。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。
图1是本发明实施例提供的一种计算机处理系统的示意性框架图；
图2是本发明实施例提供的一种Cache示意性框架图；
图3是本发明实施例提供的另一种Cache示意性框架图；
图4是本发明实施例提供的又一种MESIP协议状态的迁移示意图
图5是本发明实施例提供的一种MESIP协议状态的迁移示意图；
图6是本发明实施例提供的一种Cache部分写数据的流程示意图
图7是本发明实施例提供的一种E状态的缓存行在部分写数据过程中状态变化的示意说明图；
图8是本发明实施例提供的一种M状态的缓存行在部分写数据过程中状态变化的示意说明图；
图9是本发明实施例提供的一种P状态的缓存行在部分写数据过程中状态变化的示意说明图；
图10是本发明实施例提供的另一种P状态的缓存行在部分写数据过程中状态变化的示意说明图；
图11是本发明实施例提供的一种I状态的缓存行在部分写数据过程中状态变化的示意说明图；
图12是本发明实施例提供的一种Cache读数据的流程示意图；
图13是本发明实施例提供的一种P状态缓存行在读目标数据过程中状态变化的示意说明图
图14是本发明实施例提供的一种Cache写数据的流程示意图；
图15是本发明实施例提供的一种缓存控制器的结构示意图；
图16是本发明实施例提供的另一种缓存控制器的结构示意图；
图17是本发明实施例提供的一种处理器的结构示意图；
图18是本发明实施例提供的一种终端的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
下面介绍本发明涉及的处理器(central processing unit，CPU)、高速缓冲存储器(Cache)、 内存(也称主存储器(main memory))之间的关系。
可以理解，本发明涉及的CPU、Cache和内存可以应用于电子终端中，电子终端可以包括处理器和内存，该电子终端可以包括计算机，智能手机，平板电脑，智能电视，智能手环、VR眼镜、智能手表等可穿戴设备，车载终端等，本发明不作限制。
高速缓冲存储器是介于CPU与内存之间的高速小容量的存储器，由静态存储芯片(static random access memory，SRAM)组成，其速度接近CPU的速度，存在多级的分层架构。请参阅图1，图1是本发明实施例提供的一种处理器、高速缓冲存储器以及内存所组成的计算机处理系统的示意性框架图。处理器可以是单核处理器也可以是多核处理器，即包括第一核CPU、第二核CPU，现处理器可以包括三个级别的高速缓存存储器，分别为一级高速缓冲存储器(也称L1 Cache)、二级高速缓冲存储器(也称L2 Cache)和三级高速缓冲存储器(也称L3 Cache)。其中，L1 Cache由指令Cache和数据Cache组成，L2 Cache或L3 Cache可以包括数据和指令，L1 Cache和L2 Cache为每个核独有，L3 Cache为同一个CPU中所有的核共享。
Cache被分为多个缓存行(Cache line)，每个缓存行可以是64比特(byte)，缓存行是Cache与下级Cache，或Cache与内存数据交换的最小单位。
Cache中缓存行可以包括数据区以及标志区；数据区可以包括数据字段用于存储数据，标志区可以包括地址字段、状态字段等。
需要说明的是，本发明各个实施例中，缓存行的状态也可以称为缓存行的状态。
下面介绍本发明涉及的一种Cache：
请参阅图2，图2是本发明实施例提供的一种Cache示意性框架图。如图2所示高速缓冲存储器可以包括缓存控制器20以及缓存行区21；缓存行区21包括多个缓存行，比如，如缓存行211、缓存行212、缓存行213等，缓存行可以包括数据字段、地址字段、状态字段以及写掩码字段；其中，
数据字段用于存储数据；
地址字段用于指示缓存行所存储数据的地址信息；
状态字段用于指示缓存行的状态；状态包括部分写状态；部分写状态用于指示缓存行的数据部分有效；
写掩码字段用于存储写掩码，写掩码用于指示缓存行中已被写入的数据的位置；
缓存控制器20用于接收请求并响应请求，更新响应请求的缓存行的状态以及写掩码。
本发明一实施例中，缓存行的状态包括修改(modified)状态(也称M状态)、专有(exclusive)状态(也称E状态)、共享(shared)状态(也称S状态)、无效(invalid)状态(也称I状态)以及部分写(partial writed)状态(也称P状态)；
所述缓存控制器20用于接收请求并响应所述请求，更新响应所述请求的缓存行的状态以及写掩码。
其中，部分写状态下的缓存行的数据的大小小于该缓存行的可存储数据的大小，且该缓存行中的数据部分有效，与该其对应的内存中的数据不一致。
需要说明的是，本发明实施例中，地址字段用于存储对应的缓存行所存储数据的地址 信息，该地址信息可以是内存中存储该数据的物理地址。
在图2所示的实施例中，Cache的状态除包括M、E、S、I状态之外，还定义了P状态，处于P状态下的缓存行与内存的数据不一致，并通过写掩码来表示已被写入的数据的位置，使得在部分写数据或读数据的过程中，减少内存与Cache的数据交换，提高Cache的数据处理效率。
下面介绍本发明涉及的另一种Cache：
请参阅图3，图3是本发明实施例提供的另一种Cache示意性框架图。如图3所示高速缓冲存储器可以包括：缓存控制器30、缓存行区31以及掩码区32，缓存行区31包括多个缓存行，比如，缓存行311、缓存行312、缓存行313；缓存行包括数据字段、第一地址字段、状态字段以及掩码索引字段；掩码区32包括与缓存行对应的掩码行，比如，与缓存行311对应的掩码行321、与缓存行313对应的掩码行322，掩码区32还可以包括空掩码行323，掩码行包括写掩码字段；其中，
缓存行包括数据字段用于存储数据；
第一地址字段用于指示缓存行所存储数据的地址信息；
状态字段用于指示缓存行的状态；状态包括部分写状态；部分写状态用于指示缓存行的数据部分有效；
掩码索引字段用于指示缓存行的写掩码字段的地址信息；
写掩码字段用于存储写掩码，写掩码用于指示掩码行对应的缓存行中已被写入的数据的位置；
缓存控制器用于接收请求并响应请求，更新响应请求的缓存行的状态以及写掩码。
本发明一实施例中，掩码索引字段存储掩码区32的地址信息；掩码行还包括第二地址字段，第二地址字段用于指示掩码行对应的缓存行。
请参阅图4，图4是本发明实施例提供的又一种Cache示意性框架图。如图4所示高速缓冲存储器可以包括：缓存控制器40、缓存行区41以及掩码区42，缓存行区41包括多个缓存行，比如，缓存行411、缓存行412、缓存行413；缓存行包括数据字段、第一地址字段、状态字段以及掩码索引字段；掩码区42包括与缓存行对应的掩码行，比如，与缓存行411对应的掩码行421、与缓存行413对应的掩码行422，掩码区42还可以包括空掩码行423，与图3中各个单元不同的是，掩码区42包括第二地址字段以及写掩码字段，该掩码索引字段为掩码区42的地址信息。
需要说明的是，本发明实施例中，第一地址字段可以为该缓存行对应内存的地址信息，该地址信息可以是内存中存储该数据的物理地址。第二地址字段可以是与该掩码行对应的缓存行中第一地址字段内的地址信息相同，也可以是该掩码行对应的缓存行在Cache中的地址信息。
还需要说明的是，掩码区可以是Cache中固定存储区域，也可以是可变存储区域。掩码区可以仅存储处于P状态的缓存行对应的写掩码。对于图3或图4所示的Cache，非P状态下的掩码索引字段可以为空，也可以为写掩码全为0的掩码行的地址信息。对于图4 所示的Cache，非P状态下的掩码索引字段还可以同P状态的缓存行对应的掩码索引字段的内容相同。
可以理解，掩码行只需要与处于P状态的缓存行一一对应，因而，缓存行的数目可以大于掩码行的数目，处于P状态的缓存行的个数不大于缓存行的总个数，掩码行的个数不小于处于P状态的缓存行的个数。
本发明一实施例中，当新增P状态的缓存行时，需要分配掩码行。对于图3所示的Cache，当掩码区包括空闲掩码行时，可以将新增P状态的缓存行的写掩码写入到空闲掩码行，以及将该空闲掩码行的地址信息更新至该新增的P状态的缓存行对应的掩码索引字段。对于图4所示的Cache，当掩码区包括空闲掩码行时，可以将新增P状态的缓存行的写掩码写入到空闲掩码行，以及更新至该新增的P状态的缓存行对应的掩码索引字段，对于可变区域的掩码区，还需要将变化后的掩码区的地址信息更新所有的掩码索引字段。对于固定区域的掩码区，当掩码区全部被占用时，需要通过算法释放部分掩码区，以提供空闲掩码行。其中，释放掩码区的方法可以是：缓存控制器将部分掩码行对应的缓存行的数据写入到下一级Cache或者内存，释放出空闲缓存行以及空闲掩码行。
在图3或图4所示的实施例中，Cache的状态除包括M、E、S、I状态之外，还定义了P状态，处于P状态下的缓存行与内存的数据不一致，并通过写掩码来表示已被写入数据的位置，使得在部分写数据或读数据的过程中，减少内存与Cache的数据交换，提高Cache的数据处理效率。
本发明一实施例中，字节是信息传输或存储的单位，一个字节等于8位二进制。对于图2、图3或图4所示的Cache，写掩码字段的大小为n/8字节，n为处于部分写状态下的缓存行中存储数据的字节数。对于新分配的缓存行，写掩码的初始状态全部为0，在部分写入数据之后，被部分写的位置对应的写掩码为1。
可选地，对于图2、图3或图4所示的Cache可以是L1 Cache、L2 Cache或L3 Cache中的任一Cache。
还需要说明的是，图2、图3或图4所示的Cache中涉及的地址信息可以是地址范围，也可以是起始地址。例如，在图2中，缓存行211中地址字段标记的地址信息“0x0000”，缓存行211内可存储的数据大小固定值，比如图2中的32bit，因而可以确定该数据所在内存的地址范围。可以理解，在图2所示的实施例中，该地址字段也可以标志为“0x0000-0x001F”。
还需要说明的是，缓存行的状态还可以包括O(owned)状态、F(forward)状态等，本发明不作限制。
还需要说明的是，对于图2图3或图4所示的Cache，缓存行还可以包括错误纠正码(error-correcting code，ECC)字段。
还需要说明的是，缓存控制器20用于实现本发明方法实施例中的各个步骤，具体可以参见本发明方法实施例中的相关表述，此处不再赘述。
下面介绍本发明涉及的Cache一致性协议MESIP：
在多核处理器中，多个核会共享一些数据，MESIP协议就包含了描述共享的状态。在MESI协议中，每个缓存行(Cache line)有5个状态，可以用3个或4个bit表示，它们分别如下表所示：
Figure PCTCN2017093009-appb-000001
其中，M、E和P状态的缓存行，其数据是独有的，其中，M和P状态下的数据是dirty的(即与内存的数据不一致)，E状态下的数据是clean的(即与内存的数据一致)。S状态的缓存行，其数据与其他核的Cache共享。只有clean的数据才能被多个Cache共享。I状态的缓存行，其数据为无效的。
请参阅图5，图5是本发明实施例提供的一种MESIP协议状态的迁移示意图。在图4中，Local Read表示本内核读本缓存行中的值，Local Write表示本内核写本缓存行中的值，Remote Read表示其它内核读其它Cache的缓存行中的值，Remote Write表示其它内核写其它Cache的缓存行中的值，Local Write Partial表示本内核部分写本Cache中的值，且部分写完成后写掩码不全为1。当更新后的写掩码全为1时，触发Local Write Full事件，将缓存行的数据写入主存(或下一级Cache)，释放本缓存行，本缓存行的状态变为I；或，将本缓存行的状态标记为M。箭头方向表示本缓存行状态的迁移方向。
当内核需要访问的数据A不在本Cache中，而其它Cache有数据A的备份时，本Cache既可以从内存中导入该数据A，也可以从其它Cache中导入该数据A，不同的处理器会有不同的选择。MESI协议为了使自己更加通用，没有定义这些细节，只定义了状态之间的迁移，下面的MESIP状态之间迁移过程的描述假设本Cache从内存中导入数据A。
通过下列各表描述MESIP状态之间迁移的过程：
Figure PCTCN2017093009-appb-000002
Figure PCTCN2017093009-appb-000003
Figure PCTCN2017093009-appb-000004
可以理解，初始化写掩码可以是该缓存行的写掩码全部标记为0。对于图3或图4所示的cache，初始化写掩码还可以是释放该缓存行对应的掩码行。
需要说明的是，Cache的缓存控制器除负责响应自己CPU的内存读写操作(包括读/写/部分写命中与未命中)外，还负责监听总线上其他CPU的内存读写活动(包括读/写/部分写命中与未命中)并对知己的Cache予以相应处理，所有的处理过程要维护Cache一致性，以符合MESIP的转换规则。
还需要说明的是，数据的状态还可以包括O(owned)状态、F(forward)状态等，MESIP协议还可以演化为MOESIP协议、MESIFP协议等，本发明不作限制。
下面介绍本发明实施例提供的一种由本发明实施例提供的Cache实现数据部分写的方法实施例。
CPU或内核可以向缓存控制器发送请求，该请求的格式可以包括类型字段、地址字段、数据字段等，分别用于指示请求类型(比如，读、写、部分写等)、请求地址、请求携带的数据。请求地址为内存的地址。
当CPU需要请求读、写或部分写主存中数据A时，处理器首先从Cache中检查是否有该数据A。如果Cache的某一缓存行中存在该数据A则命中(Cache Hit)，处理器可以立即从该缓存行中读、写或部分写数据。如果Cache中所有的缓存行都不存在该数据A时则为未命中(Cache Miss)。当Cache未命中时，即Cache Miss发生时，缓存控制器会在Cache中新分配一个缓存行并从主存(或下一级Cache)中读取数据A到Cache中。当Cache Miss时，需要新分配缓存行，此时Cache有很大可能不存在空闲的缓存行，需要牺牲掉原有的缓存行，现有LRU，FIFO等算法来实现缓存行的释放。
对于E状态或S状态下缓存行，缓存行存储的数据在内存中也存在，内存存储该数据的地址与缓存行具有映射关系。对于M状态或P状态的缓存行，缓存行存储的数据与内存中不一致或部分一直，缓存行与内存的地址也具有映射关系。缓存行的地址字段(对于图3或图4所示的Cache缓存行的地址字段即第一地址字段)存储的地址信息可以是存储的数据在内存中的地址。缓存控制器可以根据该地址字段存储的地址信息检测请求是否命中。
请参阅图6，图6是本发明实施例提供的一种Cache部分写数据的流程示意图。该处理方法包括：
步骤S61：缓存控制器接收部分写请求。该部分写请求用于指示将部分写请求携带的数据写入请求地址在缓存行中对应的位置。该部分写请求携带的数据的大小小于缓存行可缓存数据的大小。
假设缓存行可存储数据的最大大小为32位，即4个字符。内存存储数据“ABCD”地址为“0x0000-0x001F”。
请求地址可以是地址范围，比如“0x0000-0x000F”，部分写请求携带的数据为2个字符；或者“0x000F-0x0017”，部分写请求携带的数据为1个字符。部分写请求携带的数据的大小小于缓存行的数据字段可存储的完整的数据的大小。请求地址也可以是初始地址，比如“0x0000”，此时，部分写请求携带的数据的字节为固定值，比如2个字节。
步骤S62：判断部分写请求是否命中。
下面以请求地址为“0x000F”，部分写请求携带的数据为“E”为例来进行说明。
具体地，缓存控制器检测缓存行的地址字段中是否包括与请求地址一致或对应的地址，如果是，比如请求地址为“0x000F”，Cache中存在与该请求地址对应的缓存行，该缓存行的地址字段标记为“0x0000”大小32或者地址字段标记为“0x0000-0x001F”，则部分写请求命中，缓存控制器可以执行步骤S63。
当判断结果为否时，Cache中未缓存请求地址对应的数据，部分写请求未命中，缓存控制器可以执行步骤S64。
步骤S63：将部分写请求携带的数据写入请求地址在命中的缓存行中对应的位置。
例如，请求地址为“0x000F”，部分写请求携带的数据为“E”，缓存控制器将部分写请求携带的数据“E”写入到缓存行中对应请求地址的位置。
具体可以参见图7-10所示的实施例中相关描述，本发明不在赘述。
步骤S64：分配缓存行，将部分写请求携带数据写入请求地址在分配的缓存行中对应的位置。
对于图2所示的Cache，当部分写请求未命中时，缓存控制器在cache中为部分写请求分配新的缓存行，初始化该分配的缓存行的写掩码为0，与内存建立对应关系(即更新地址字段为请求地址对应的内存地址)，此时分配的缓存行中存储的数据为空，即“□□□□”，其中，□表示存储的数据无效，再将部分写请求携带的数据写入请求地址在分配的缓存行中对应的位置，此时，分配的缓存行中存储的数据为“□□E□”。
对于图3或图4所示的Cache，当部分写请求未命中时，缓存控制器还需要分配新的掩码行，初始化该分配的掩码行的写掩码为0。
可见，当部分写请求未命中时，缓存控制器可以直接在分配的缓存行中写入部分写请求携带的数据，而读取内存的数据，在部分写完成后，也暂不更新缓存行内的数据至内存，可以减少Cache与内存之间数据交换，减少内存带宽的占用，进而提高数据处理速率。
具体可以参见图11所示的实施例中相关描述，本发明不在赘述。
步骤S65：更新缓存行的写掩码。
具体地，步骤S63、S64之后，缓存控制器可以根据请求地址更新写掩码，即将请求地址在缓存行中对应的位置的写掩码更新为1。
对于各种状态下的缓存行写掩码的更新可以参见图7-11所示的实施例中相关描述，本发明不在赘述。
步骤S66：判断更新后的缓存行的写掩码是否全为1。
当更新后的写掩码全为1时，缓存控制器可以执行步骤S67、S69，或者执行步骤S68、S69。
步骤S67：将缓存行的数据写入内存或下一级高速缓冲存储器中，并初始化缓存行的写掩码。具体可以参见图10所示的实施例中第一种转变方式中的相关描述，本发明不在赘述。
步骤S68：初始化所述缓存行的写掩码。具体可以参见图10所示的实施例中第二种转变方式中的相关描述，本发明不在赘述。
步骤S69：更新缓存行的状态。
具体地，步骤S65、S67或S68之后，缓存控制器可以更新缓存行的状态。
对于各种状态下的缓存行状态的更新可以参见图7-11所示的实施例中相关描述，本发明不在赘述。
本发明一实施例中，在步骤S62中，若命中的缓存行为E状态或S状态，以E状态为 例。请参阅图7，图7是本发明实施例提供的一种E状态的缓存行在部分写数据过程中状态变化的示意说明图。步骤S63之前，缓存行存储的数据在内存中也存在，缓存行内存储的数据为“ABCD”，写掩码为“0000”在经过步骤S63、S65、S69之后，该缓存行的数据被修改为“ABED”，状态变为M状态，初始化写掩码为“0000”。
本发明一实施例中，在步骤S62中，若命中的缓存行为M状态，请参阅图8，图8是本发明实施例提供的一种M状态的缓存行在部分写数据过程中状态变化的示意说明图。步骤S63之前，缓存行存储的数据在内存中不存在，如图8，假设该缓存行当前存储的数据为“MNOP”，内存储的数据为“ABCD”，在经过步骤S63、S65、S69之后，该缓存行的数据被修改为“MNEP”，写掩码以及状态保持不变。
本发明一实施例中，在步骤S62中，若命中的缓存行为P状态，请参阅图9，图9是本发明实施例提供的一种P状态的缓存行在部分写数据过程中状态变化的示意说明图。步骤S63之前，缓存行存储的数据在内存中不存在(比如该数据为“□S□□”，其中，S为上一次在新分配的缓存行内部分写入的数据)，如图9，以缓存行的数据为“□S□□”为例，内存储的数据为“ABCD”，写掩码为“0100”，在经过步骤S63、S65、S69之后，该缓存行的数据被修改为“□SE□”，写掩码更新为“0110”，状态不变，为P状态。
本发明一实施例中，在步骤S62中，若命中的缓存行为P状态，请参阅图10，图10是本发明实施例提供的另一种P状态的缓存行在部分写数据过程中状态变化的示意说明图。步骤S63之前，缓存行存储的数据在内存中不存在(比如该数据为“RS□T”，其中，R、S、T为上一次或上多次在缓存行内部分写入的数据)如图10，以缓存行的数据为“RS□T”为例，内存储的数据为“ABCD”，写掩码为“1101”，在经过步骤S63、S65之后，该缓存行的数据被修改为“RSET”，写掩码更新为“1111”，触发Local Write Full事件，触发Local Write Full事件后缓存行存在以下两种转变方式：
第一种转变方式：经过步骤S67、S69后，缓存行内数据“RSET”被更新入内存,该缓存行被释放，状态变为I状态，写掩码初始化(为“0000”或掩码行被释放，不存在对应的写掩码)，缓存行与内存不存在对应关系。通过该转变方式可以在数据都变化后，更新至内存，避免频繁更新至内存导致的Cache与内存频繁的数据交换，可减少内存带宽的占用，且可以及时释放Cache，提高Cache的利用率。
第二种转变方式：经过步骤S68、S69后，缓存行内数据为“RSET”，更新缓存行的状态为M状态，写掩码初始化(为“0000”或掩码行被释放，不存在对应的写掩码)。通过该转变方式可以减少Cache与内存之间数据的交换，进而提高数据处理速率。
本发明一实施例中，在步骤S62中，若未命中，则缓存控制器分配新的缓存行，该分配的缓存行为I状态。请参阅图11，图11是本发明实施例提供的一种I状态的缓存行在部分写数据过程中状态变化的示意说明图。步骤S64之前，缓存行为I状态与内存“ABCD”不存在对应关系，如图11，缓存行无数据“□□□□”，内存储的数据为“ABCD”，在经 过步骤S64、S65之后，缓存行被部分写入“E”，缓存行的数据为“□□E□”，状态转变为P状态，写掩码更新为“0010”。
下面介绍本发明实施例提供的一种应用本发明实施例提供的Cache实现读的一实施例。
请参阅图12，图12是本发明实施例提供的一种Cache读数据的流程示意图。该Cache读数据的方法包括：
步骤S121：缓存控制器接收读请求。该读请求包括请求地址，用于请求在Cache中读取请求地址对应的数据。
可以理解，该读请求可以是第一读请求也可以是第二读请求，其中，第一读请求用于请求在缓存行中对第一请求地址对应的数据；第二读请求用于请求在缓存行中对第二请求地址对应的数据。
假设缓存行可存储数据的最大大小为32位，即4个字符。内存存储数据“ABCD”地址为“0x0000-0x001F”。
请求地址可以是地址范围，比如“0x0000-0x000F”或者“0x000F-0x0017”等。请求地址也可以是初始地址，比如“0x0000”，此时，请求读取的数据的字节为固定值，比如2个字节。
下面以请求地址为“0x0008”，该请求地址对应的数据的大小为1个字符，为例来进行说明。
步骤S122：判断读请求是否命中。
判断读请求是否命中的方法与图6所示的实施例中步骤S62中判断部分写请求是否命中的方法类同，请参阅步骤S62，本发明不在赘述。
当读请求命中时，则Cache中已缓存内存中请求地址对应的数据，该命中的缓存行可以是S、E、M状态下的缓存行，也可以是P状态下的缓存行，缓存控制器可以执行步骤S123。
当请求未命中时，缓存控制器可以执行步骤S125。
步骤S123：判断命中的缓存行中请求地址对应的数据是否全部存在。
若命中的缓存行为E状态、S状态或M状态的缓存行，则请求地址对应的数据一定存在于命中的缓存行，缓存控制器可以执执行步骤S126，返回数据。此时，命中的缓存行的状态保持不变。
可以理解，对于E状态、S状态的缓存行，缓存行存储的数据与内存一致，缓存控制器读取到的数据为“B”。对于M状态的缓存行，缓存行存储的数据与内存不一致，缓存行内存储的数据为最新的数据，比如该M状态的缓存行存储的数据为“MNOP”，缓存控制器读取到的数据为“N”。
若命中的缓存行为P状态的缓存行，缓存控制器进一步可以根据该命中的缓存行的写掩码判断命中的缓存行中请求地址对应的数据是否全部存在。可以理解，当命中的缓存行中请求地址对应的写掩码不都为1时，则请求地址对应的数据部分或全部不存在于该命中的缓存行中，缓存控制器可以执行步骤S124；否则，命中的缓存行中请求地址对应的写掩码都为1，则请求地址对应的数据存在命中的缓存行中，缓存控制器可以执行步骤S126， 返回数据，比如该命中的缓存行的内存储的数据为“□E□□”，则缓存控制器返回数据“E”。
步骤S124：根据命中缓存行的写掩码，将从请求地址对应的内存或对应的下一级Cache中读取数据合并到命中的缓存行中，并更新合并后的缓存行的状态以及写掩码。
具体地，将第一位置对应的内存或下一级高速缓冲存储器中的数据，写入命中的缓存行中的第一位置，该第一位置包括命中的缓存行中写掩码为0的位置，其中，写入后的缓存行中第一位置的数据与第二位置的数据，形成合并后的缓存行；第二位置包括命中的缓存行中写掩码为1的位置。也就是说，命中的缓存行中写掩码为0的位置对应的数据更新为内存中对应的数据，命中的缓存行中写掩码为1的位置对应的数据不变。进而，更新合并后的缓存行的状态为M状态，初始化写掩码。对应图3或图4所示的Cache，还可以释放该掩码行。
例如，请参阅图13，图13是本发明实施例提供的一种P状态缓存行在读数据过程中状态变化的示意说明图。如图13所示，在步骤S124之前，命中的缓存行内存储的数据为“□□E□”，状态为P状态，写掩码为“0010”，对应的内存中的数据为“ABCD”；在步骤S124之后，命中的缓存行内存储的数据为“ABED”，状态为M状态，写掩码初始化为“0000”，对应的内存中的数据为“ABCD”。
步骤S125：分配缓存行，从请求地址对应的内存或对应的下一级Cache中读取数据至分配的缓存行。
具体地，当读请求未命中时，缓存控制器可以分配新的缓存行，从请求地址对应的内存或对应的下一级Cache中读取数据比如“ABCD”到分配的缓存行，此时，该分配的缓存行存储的数据为“ABCD”，状态为E状态，写掩码为“0000”，数据即为分配的缓存行中对应请求地址的数据，即“B”。
可以理解，对于图3或图4所示的Cache，E状态的缓存行可以不包括掩码行以及写掩码。
步骤S126：响应读请求，返回该请求地址对应的数据。
具体地，步骤S125或S126之后，缓存控制器从命中的缓存行或分配的缓存行中读取请求地址对应的数据，返回至CPU。
下面介绍本发明实施例提供的一种应用本发明实施例提供的Cache实现写的一实施例。
请参阅图14，图14是本发明实施例提供的一种Cache写数据的流程示意图。该Cache写数据的方法包括：
步骤S141：缓存控制器接收写请求。该写请求用于指示将写请求携带的数据写入到缓存行中请求地址对应的缓存行。
可以理解，不同于部分写事件对缓存行中部分数据的修改，写事件是对整个缓存行的数据的修改。写请求携带的数据的大小等于缓存行的数据字段可存储的数据的大小。
假设缓存行可存储数据的最大大小为32位，即4个字符。内存存储数据“ABCD”地址为“0x0000-0x001F”。
请求地址可以是地址范围，比如“0x0000-0x001F”，写请求携带的数据为4个字符；也可以是初始地址，比如“0x0000”，此时，写请求携带的数据的字节为固定值，比如4个 字节。
下面以请求地址为“0x0000”，写请求携带的数据为“EFGH”为例来进行说明。
步骤S142：判断写请求是否命中。
具体地，缓存控制器检测缓存行的地址字段中是否包括与请求地址一致或对应的地址，如果是，比如Cache中存在与该请求地址对应的缓存行，该缓存行的地址字段标记为“0x0000”大小32或者地址字段标记为“0x0000-0x001F”，则部分写请求命中，缓存控制器可以执行步骤S143。
可以理解，命中的缓存行可以是M、S或E状态的缓存行，也可以是P状态的缓存行。
当判断结果为否时，Cache中未缓存请求地址对应的数据，部分写请求未命中，缓存控制器可以执行步骤S144。
步骤S143：将写请求携带的数据写入到命中的缓存行中。
例如，缓存控制器将写请求携带的数据“EFGH”写入到命中的缓存行中。
步骤S144：分配缓存行，将写请求携带的数据写入到分配的缓存行中。
当部分写请求未命中时，缓存控制器在缓存中分配新的缓存行，初始化该分配的缓存行的写掩码为0，与内存建立对应关系(比如更新地址字段为请求地址)，此时分配的缓存行中存储的数据为空，即“□□□□”，其中，□表示存储的数据无效，将写请求携带数据写入到分配的缓存行中，此时，分配的缓存行中存储的数据为“EFGH”。
步骤S145：更新缓存行的状态。
步骤S143或S144之后，控制缓存器可以更新命中的缓存行的状态为M。
当命中的缓存行处于P状态时，步骤S145还包括更新写掩码为“0000”或者释放该命中的缓存行对应的掩码行。
下面介绍本发明实施例涉及的缓存控制器：
请参阅图15，图15是本发明实施例提供的一种缓存控制器的结构示意图，该缓存控制器150用于实现上述部分写数据的方法，可以包括：
接收单元151，用于接收部分写请求,所述部分写请求携带的数据的大小小于所述缓存行可缓存数据的大小；
写入单元152，用于将所述部分写请求携带的数据写入请求地址在所述缓存行中对应的位置；
更新单元153，用于更新所述缓存行的写掩码；以及，更新所述缓存行的状态；
其中，所述缓存行的状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；所述写掩码用于指示所述缓存行中已被写入的数据的位置。
本发明一实施例中，所述写入单152元具体用于：
在所述部分写请求发生缓存命中时，所述缓存行为命中的缓存行，将所述部分写请求携带的数据写入所述请求地址在命中的缓存行中对应的位置；或，
在所述部分写请求未命中时，为所述部分写请求分配缓存行，将部分写请求携带的数据写入所述请求地址在分配的缓存行中对应的位置。
本发明一实施例中，所述更新单元153用于更新所述缓存行的写掩码时具体用于：根 据所述请求地址更新所述缓存行的写掩码。
本发明一实施例中，当更新后的所述缓存行的写掩码全为1时，
所述写入单元152还用于：将所述缓存行的数据写入内存或下一级高速缓冲存储器中；
所述更新单元153还用于：初始化所述缓存行的写掩码，更新所述缓存行的状态为无效状态。
本发明一实施例中，当更新后所述缓存行的的写掩码全为1时，
所述更新单元153还用于：初始化所述缓存行的写掩码，更新所述缓存行的状态为修改状态。
请参阅图16，图16是本发明实施例提供的另一种缓存控制器的结构示意图，该缓存控制器160实现上述读数据的方法，可以包括：
接收单元161，用于接收第一读请求；所述第一读请求用于请求读取第一请求地址在缓存行中对应的数据；
合并单元162，用于当所述第一读请求发生缓存命中且在命中的缓存行中所述第一请求地址对应的数据部分或全部不存在时，根据所述命中的缓存行的写掩码，将从所述第一请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中；
更新单元163，用于更新合并后的缓存行的状态以及写掩码；
读取单元164，用于在所述合并后的缓存行中读取所述第一请求地址对应的数据。
其中，所述缓存行的状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；所述写掩码用于指示所述缓存行中已被写入的数据的位置。
本发明一实施例中，所述接收单元161还用于：接收第二读请求；所述第二读请求用于请求读取第二请求地址在缓存行中对应的数据；
所述读取单元164还用于：当所述第二读请求发生缓存命中且所述命中的缓存行的状态不为部分写状态时；或，当所述第二读请求发生缓存命中，所述命中的缓存行的状态为部分写状态且所述命中的缓存行中所述第二请求地址对应的写掩码都为1时，在所述命中的缓存行中读取所述第二请求地址对应的数据。
本发明一实施例中，所述在命中的缓存行中所述第一请求地址对应的数据部分或全部不存在包括：所述命中的缓存行的状态为部分写状态且所述命中的缓存行中所述第一请求地址对应的写掩码不都为1；所述合并单元162具体用于：
将第一位置对应的内存或下一级高速缓冲存储器中的数据，写入所述命中的缓存行中的所述第一位置；所述第一位置包括所述命中的缓存行中写掩码为0的位置；
其中，写入后的缓存行中所述第一位置的数据与第二位置的数据，形成合并后的缓存行；所述第二位置包括所述命中的缓存行中写掩码为1的位置。
下面介绍本发明实施例提供的一种处理器，请参阅图17，图17是本发明实施例提供的一种处理器的结构示意图，该处理器可以包括至少一个内核171以及至少一个高速缓冲存储器172，高速缓冲存储172可以是图2、图3或图4所示的Cache。
下面介绍本发明实施例提供的一种终端，请参阅图18，图18是本发明实施例提供的一种处理器的结构示意图，该终端可以包括处理器181、存储器182，处理器181连接到处理器181，存储器182用于存储数据和指令，处理器181用于调用存储器182内存储的指令实现终端的各个功能。所述处理器182可以是图17所示的处理器。
处理器181是终端的控制中心，利用各种接口和线路连接整个终端的各个部分，通过运行或执行存储在存储器182内的计算机程序和/或模块，以及调用存储在存储器182内的数据，执行终端的各种功能和处理数据，从而对终端进行整体监控。可选的，处理器182可包括一个或多个处理核心；优选的，处理器181可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器181中。
可以理解，该存储器182可用于存储计算机程序以及模块，处理器181通过运行存储在存储器182的计算机程序以及模块，从而执行各种功能应用以及数据处理。存储器182可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据终端的使用所创建的数据(比如本发明实施例中所描述的停车场地图、地理位置等)等。此外，存储器182可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。
可以理解，该终端还可以包括通信接口、输入装置或输出装置等。需要说明的是，通信接口、输入装置或输出装置等并不属于终端的必须构成，完全可以根据需要在不改变发明的本质的范围内而省略。
输入装置可用于接收输入的数字或字符信息，以及产生与用户设置以及功能控制有关的键盘、鼠标、操作杆、光学或者轨迹球信号输入。输入装置还可包括触敏表面以及其他输入设备。触敏表面，也称为触摸显示面板或者触控板，可收集用户在其上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触敏表面上或在触敏表面附近的操作)，并根据预先设定的程式驱动相应的连接装置。
输出装置可用于显示由用户输入的信息或提供给用户的信息以及终端的各种图形用户界面(比如本发明实施例中所描述的移动轨迹显示界面置等)，这些图形用户界面可以由图形、文本、图标、视频和其任意组合来构成。输出装置可包括显示面板等。
通信接口用于建立通信信道，使终端通过所述通信信道以连接至通信对端，并通过所述通信信道与所述通信对端交互数据。
本发明实施例中所使用的技术术语仅用于说明特定实施例而并不旨在限定本发明。在本文中，单数形式“一”、“该”及“所述”用于同时包括复数形式，除非上下文中明确另行说明。进一步地，在说明书中所使用的用于“包括”和/或“包含”是指存在所述特征、整体、步骤、操作、元件和/或构件，但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、元件和/或构件。
在所附权利要求中对应结构、材料、动作以及所有装置或者步骤以及功能元件的等同 形式(如果存在的话)旨在包括结合其他明确要求的元件用于执行该功能的任何结构、材料或动作。本发明的描述出于实施例和描述的目的被给出，但并不旨在是穷举的或者将被发明限制在所公开的形式。

Claims (31)

  1. 一种部分写数据方法，其特征在于，包括：
    接收部分写请求,所述部分写请求携带的数据的大小小于缓存行可缓存数据的大小；
    将所述部分写请求携带的数据写入请求地址在所述缓存行中对应的位置；
    更新所述缓存行的写掩码；
    更新所述缓存行的状态；
    其中，所述缓存行的状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；所述写掩码用于指示所述缓存行中已被写入的数据的位置。
  2. 如权利要求1所述的方法，其特征在于，所述将所述部分写请求携带的数据写入请求地址在所述缓存行中对应的位置包括：
    在所述部分写请求发生缓存命中时，将所述部分写请求携带的数据写入所述请求地址在命中的缓存行中对应的位置；或，
    在所述部分写请求未命中时，为所述部分写请求分配缓存行，将所述部分写请求携带的数据写入所述请求地址在分配的缓存行中对应的位置。
  3. 如权利要求1或2所述的方法，其特征在于，
    所述更新所述缓存行的写掩码包括：根据所述请求地址更新所述缓存行的写掩码。
  4. 如权利要求1-3任一项所述的方法，其特征在于，当更新后的所述缓存行的写掩码全为1时，所述方法还包括：将所述缓存行的数据写入内存或下一级高速缓冲存储器中，并初始化所述缓存行的写掩码；
    所述更新所述缓存行的状态包括：更新所述缓存行的状态为无效状态。
  5. 如权利要求1-3任一项所述的方法，其特征在于，当更新后所述缓存行的的写掩码全为1时，所述方法还包括：初始化所述缓存行的写掩码；
    所述更新所述缓存行的状态包括：更新所述缓存行的状态为修改状态。
  6. 一种读数据方法，其特征在于，包括：
    接收第一读请求；所述第一读请求用于请求读取第一请求地址在缓存行中对应的数据；
    当所述第一读请求发生缓存命中且在命中的缓存行中所述第一请求地址对应的数据部分或全部不存在时，根据所述命中的缓存行的写掩码，将从所述第一请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中，并更新合并后的缓存行的状态以及写掩码；
    在所述合并后的缓存行中读取所述第一请求地址对应的数据；
    其中，所述缓存行的状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；所述写掩码用于指示所述缓存行中已被写入的数据的位置。
  7. 如权利要求6所述的方法，其特征在于，所述方法还包括：
    接收第二读请求；所述第二读请求用于请求读取第二请求地址在缓存行中对应的数据；
    当所述第二读请求发生缓存命中且所述命中的缓存行的状态不为部分写状态时；或，当所述第二读请求发生缓存命中，所述命中的缓存行的状态为部分写状态且所述命中的缓存行中所述第二请求地址对应的写掩码都为1时，在所述命中的缓存行中读取所述第二请求地址对应的数据。
  8. 如权利要求6所述的方法，其特征在于，所述在命中的缓存行中所述第一请求地址对应的数据部分或全部不存在包括：所述命中的缓存行的状态为部分写状态且所述命中的缓存行中所述第一请求地址对应的写掩码不都为1；
    所述将从所述请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中包括：
    将第一位置对应的内存或下一级高速缓冲存储器中的数据，写入所述命中的缓存行中的所述第一位置；所述第一位置包括所述命中的缓存行中写掩码为0的位置；
    其中，写入后的缓存行中所述第一位置的数据与第二位置的数据，形成合并后的缓存行；所述第二位置包括所述命中的缓存行中写掩码为1的位置。
  9. 一种高速缓冲存储器，其特征在于，包括：缓存控制器以及缓存行区；所述缓存行区包括多个缓存行，所述缓存行包括数据字段、地址字段、状态字段以及写掩码字段；其中，
    所述数据字段用于存储数据；
    所述地址字段用于指示所述缓存行所存储数据的地址信息；
    所述状态字段用于指示所述缓存行的状态；所述状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；
    所述写掩码字段用于存储写掩码，所述写掩码用于指示所述缓存行中已被写入的数据的位置；
    所述缓存控制器用于接收请求并响应所述请求，更新响应所述请求的缓存行的状态以及写掩码。
  10. 如权利要求9所述的高速缓冲存储器，其特征在于，所述写掩码字段的大小为n/8字节，所述n为所述缓存行可存储数据的最大字节数。
  11. 如权利要求9或10所述的高速缓冲存储器，其特征在于，所述请求包括部分写请求，所述缓存控制器具体用于执行：
    接收所述部分写请求；所述部分写请求携带的数据的大小小于所述缓存行可缓存数据的大小；
    将所述部分写请求携带的数据写入请求地址在所述缓存行中对应的位置；
    更新所述缓存行的写掩码；
    更新所述缓存行的状态。
  12. 如权利要求11所述的高速缓冲存储器，其特征在于，所述缓存控制器执行将所述部分写请求携带的数据写入请求地址在所述缓存行中对应的位置包括：
    在所述部分写请求发生缓存命中时，将所述部分写请求携带的数据写入所述请求地址在所述命中的缓存行中对应的位置；或，
    在所述部分写请求未命中时，为所述部分写请求分配的缓存行，将所述部分写请求携带的数据写入所述请求地址在所述分配的缓存行中对应的位置。
  13. 如权利要求11或12所述的高速缓冲存储器，其特征在于，所述缓存控制器执行所述更新所述缓存行的写掩码包括：所述缓存控制器根据所述请求地址更新所述缓存行的写掩码。
  14. 如权利要求11-13任一项所述的高速缓冲存储器，其特征在于，当更新后的写掩码全为1时，所述缓存控制器还用于执行：将所述缓存行的数据写入内存或下一级高速缓冲存储器中，并初始化所述缓存行的写掩码；
    所述缓存控制器更新所述缓存行的状态包括：所述缓存控制器更新所述缓存行的状态为无效状态。
  15. 如权利要求11-13任一项所述的高速缓冲存储器，其特征在于，当更新后所述缓存行的的写掩码全为1时，所述缓存控制器还用于执行：初始化所述缓存行的写掩码；
    所述缓存控制器更新所述缓存行的状态包括：所述缓存控制器更新所述缓存行的状态为修改状态。
  16. 如权利要求9或10所述的高速缓冲存储器，其特征在于，所述请求包括第一读请求，所述缓存控制器具体用于执行：
    接收所述第一读请求；所述第一读请求用于请求读取第一请求地址在所述缓存行中对应的数据；
    当所述第一读请求发生缓存命中且在命中的缓存行中所述第一请求地址对应的数据部分或全部不存在时，根据所述命中的缓存行的写掩码，将从所述第一请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中，并更新合并后的缓存行的状态以及写掩码；
    在所述合并后的缓存行中读取所述第一请求地址对应的数据。
  17. 如权利要求16所述的高速缓冲存储器，其特征在于，所述控制缓存器还用于执行：
    接收第二读请求；所述第二读请求用于请求读取第二请求地址在缓存行中对应的数据；
    当所述第二读请求发生缓存命中且所述命中的缓存行的状态不为部分写状态时；或， 当所述第二读请求发生缓存命中，所述命中的缓存行的状态为部分写状态且所述命中的缓存行中第二所述请求地址对应的写掩码都为1时，在所述命中的缓存行中读取所述第二请求地址对应的数据。
  18. 如权利要求16所述的高速缓冲存储器，其特征在于，所述在命中的缓存行中所述请求地址对应的数据部分或全部不存在包括：所述命中的缓存行的状态为部分写状态且所述命中的缓存行中所述请求地址对应的写掩码不都为1；
    所述缓存控制器执行所述将从所述请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中包括：
    将第一位置对应的内存或下一级高速缓冲存储器中的数据，写入所述命中的缓存行中的所述第一位置；所述第一位置包括所述命中的缓存行中写掩码为0的位置；
    其中，写入后的缓存行中所述第一位置的数据与第二位置的数据，形成合并后的缓存行；所述第二位置包括所述命中的缓存行中写掩码为1的位置。
  19. 一种高速缓冲存储器，其特征在于，包括：缓存控制器、缓存行区以及掩码区，所述缓存行区包括多个缓存行；所述缓存行包括数据字段、第一地址字段、状态字段以及掩码索引字段；所述掩码区包括与所述缓存行对应的掩码行，所述掩码行包括写掩码字段；其中，
    所述缓存行包括数据字段用于存储数据；
    所述第一地址字段用于指示所述缓存行所存储数据的地址信息；
    所述状态字段用于指示所述缓存行的状态；所述状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；
    所述掩码索引字段用于指示所述缓存行的写掩码字段的地址信息；
    所述写掩码字段用于存储写掩码，所述写掩码用于指示所述掩码行对应的缓存行中已被写入的数据的位置；
    所述缓存控制器用于接收请求并响应所述请求，更新响应所述请求的缓存行的状态以及写掩码。
  20. 如权利要求19所述的高速缓冲存储器，其特征在于，所述掩码索引字段存储所述掩码区的地址信息；所述掩码行还包括第二地址字段，所述第二地址字段用于指示所述掩码行对应的缓存行。
  21. 如权利要求19或20所述的高速缓冲存储器，其特征在于，所述写掩码字段的大小为n/8字节，所述n为所述缓存行可存储数据的最大字节数。
  22. 一种缓存控制器，其特征在于，包括：
    接收单元，用于接收部分写请求,所述部分写请求携带的数据的大小小于所述缓存行可缓存数据的大小；
    写入单元，用于将所述部分写请求携带的数据写入请求地址在所述缓存行中对应的位置；
    更新单元，用于更新所述缓存行的写掩码；以及，更新所述缓存行的状态；
    其中，所述缓存行的状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；所述写掩码用于指示所述缓存行中已被写入的数据的位置。
  23. 如权利要求22所述的缓存控制器，其特征在于，所述写入单元具体用于：
    在所述部分写请求发生缓存命中时，所述缓存行为命中的缓存行，将所述部分写请求携带的数据写入所述请求地址在命中的缓存行中对应的位置；或，
    在所述部分写请求未命中时，为所述部分写请求分配缓存行，将部分写请求携带的数据写入所述请求地址在分配的缓存行中对应的位置。
  24. 如权利要求22或23所述的缓存控制器，其特征在于，
    所述更新单元用于更新所述缓存行的写掩码时具体用于：根据所述请求地址更新所述缓存行的写掩码。
  25. 如权利要求22-24任一项所述的缓存控制器，其特征在于，当更新后的所述缓存行的写掩码全为1时，
    所述写入单元还用于：将所述缓存行的数据写入内存或下一级高速缓冲存储器中；
    所述更新单元还用于：初始化所述缓存行的写掩码；
    所述更新单元用于更新所述缓存行的状态时具体用于：更新所述缓存行的状态为无效状态。
  26. 如权利要求22-24任一项所述的缓存控制器，其特征在于，当更新后所述缓存行的的写掩码全为1时，
    所述更新单元还用于：初始化所述缓存行的写掩码；
    所述更新单元用于更新所述缓存行的状态时具体用于：更新所述缓存行的状态为修改状态。
  27. 一种缓存控制器，其特征在于，包括：
    接收单元，用于接收第一读请求；所述第一读请求用于请求读取第一请求地址在缓存行中对应的数据；
    合并单元，用于当所述第一读请求发生缓存命中且在命中的缓存行中所述第一请求地址对应的数据部分或全部不存在时，根据所述命中的缓存行的写掩码，将从所述第一请求地址对应的内存或对应的下一级高速缓冲存储器中读取的数据合并到所述命中的缓存行中；
    更新单元，用于更新合并后的缓存行的状态以及写掩码；
    读取单元，用于在所述合并后的缓存行中读取所述第一请求地址对应的数据；
    其中，所述缓存行的状态包括部分写状态；所述部分写状态用于指示所述缓存行的数 据部分有效；所述写掩码用于指示所述缓存行中已被写入的数据的位置。
  28. 如权利要求27所述的缓存控制器，其特征在于，
    所述接收单元还用于：接收第二读请求；所述第二读请求用于请求读取第二请求地址在缓存行中对应的数据；
    所述读取单元还用于：当所述第二读请求发生缓存命中且所述命中的缓存行的状态不为部分写状态时；或，当所述第二读请求发生缓存命中，所述命中的缓存行的状态为部分写状态且所述命中的缓存行中所述第二请求地址对应的写掩码都为1时，在所述命中的缓存行中读取所述第二请求地址对应的数据。
  29. 如权利要求27所述的缓存控制器，其特征在于，所述在命中的缓存行中所述第一请求地址对应的数据部分或全部不存在包括：所述命中的缓存行的状态为部分写状态且所述命中的缓存行中所述第一请求地址对应的写掩码不都为1；所述合并单元具体用于：
    将第一位置对应的内存或下一级高速缓冲存储器中的数据，写入所述命中的缓存行中的所述第一位置；所述第一位置包括所述命中的缓存行中写掩码为0的位置；
    其中，写入后的缓存行中所述第一位置的数据与第二位置的数据，形成合并后的缓存行；所述第二位置包括所述命中的缓存行中写掩码为1的位置。
  30. 一种处理器，其特征在于，包括至少一个内核以及至少一个高速缓冲存储器；所述高速缓冲存储器包括：缓存控制器以及缓存行区；所述缓存行区包括多个缓存行，所述缓存行包括数据字段、地址字段、状态字段以及写掩码字段；其中，
    所述数据字段用于存储数据；
    所述地址字段用于指示所述缓存行所存储数据的地址信息；
    所述状态字段用于指示所述缓存行的状态；所述状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；
    所述写掩码字段用于存储写掩码，所述写掩码用于指示所述缓存行中已被写入的数据的位置；
    所述缓存控制器用于接收所述内核发送的请求并响应所述请求，更新响应所述请求的缓存行的状态以及写掩码。
  31. 一种处理器，其特征在于，包括至少一个内核以及至少一个高速缓冲存储器；所述高速缓冲存储器包括：缓存控制器、缓存行区以及掩码区，所述缓存行区包括多个缓存行；所述缓存行包括数据字段、第一地址字段、状态字段以及写掩码字段；所述掩码区包括与所述缓存行对应的掩码行，所述掩码行包括写掩码字段；其中，
    所述缓存行包括数据字段用于存储数据；
    所述第一地址字段用于指示所述缓存行所存储数据的地址信息；
    所述状态字段用于指示所述缓存行的状态；所述状态包括部分写状态；所述部分写状态用于指示所述缓存行的数据部分有效；
    所述掩码索引字段用于指示所述缓存行对应的写掩码字段的地址信息；
    所述写掩码字段用于存储写掩码，所述写掩码用于指示所述掩码行对应的缓存行中已被写入的数据的位置；
    所述缓存控制器用于接收所述内核发送的请求并响应所述请求，更新响应所述请求的缓存行的状态以及写掩码。
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