CN104854557B - 存取高速缓存的设备和方法 - Google Patents

存取高速缓存的设备和方法 Download PDF

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Publication number
CN104854557B
CN104854557B CN201380065463.XA CN201380065463A CN104854557B CN 104854557 B CN104854557 B CN 104854557B CN 201380065463 A CN201380065463 A CN 201380065463A CN 104854557 B CN104854557 B CN 104854557B
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Prior art keywords
prediction mask
cache
line
value
cache line
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Chinese (zh)
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CN104854557A (zh
Inventor
彼得·G·萨索内
苏雷什·K·文库马汉提
卢西恩·科德雷斯库
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/608—Details relating to cache mapping
    • G06F2212/6082—Way prediction in set-associative cache
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
CN201380065463.XA 2012-12-20 2013-12-20 存取高速缓存的设备和方法 Active CN104854557B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/721,317 US9304932B2 (en) 2012-12-20 2012-12-20 Instruction cache having a multi-bit way prediction mask
US13/721,317 2012-12-20
PCT/US2013/077020 WO2014100632A1 (en) 2012-12-20 2013-12-20 Instruction cache having a multi-bit way prediction mask

Publications (2)

Publication Number Publication Date
CN104854557A CN104854557A (zh) 2015-08-19
CN104854557B true CN104854557B (zh) 2018-06-01

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CN201380065463.XA Active CN104854557B (zh) 2012-12-20 2013-12-20 存取高速缓存的设备和方法

Country Status (5)

Country Link
US (1) US9304932B2 (enExample)
EP (1) EP2936303B1 (enExample)
JP (1) JP6212133B2 (enExample)
CN (1) CN104854557B (enExample)
WO (1) WO2014100632A1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GR20150100422A (el) 2015-09-28 2017-05-15 Arm Limited Αποθηκευση δεδομενων
WO2019010703A1 (zh) * 2017-07-14 2019-01-17 华为技术有限公司 读、部分写数据方法以及相关装置
US11620229B2 (en) * 2020-02-21 2023-04-04 SiFive, Inc. Data cache with prediction hints for cache hits

Citations (8)

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US6016533A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array
US6356990B1 (en) * 2000-02-02 2002-03-12 International Business Machines Corporation Set-associative cache memory having a built-in set prediction array
CN1397874A (zh) * 2001-05-04 2003-02-19 智慧第一公司 高速缓存的快取线选取目标地址的装置及方法
CN1484788A (zh) * 2000-12-29 2004-03-24 英特尔公司 根据未命中距离将数据预取到高速缓存器中的系统和方法
US20050050278A1 (en) * 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
US20060174090A1 (en) * 2005-02-03 2006-08-03 Sartorius Thomas A Power efficient instruction prefetch mechanism
CN101313286A (zh) * 2005-12-22 2008-11-26 英特尔公司 多线程处理器中的性能优先化
US8046538B1 (en) * 2005-08-04 2011-10-25 Oracle America, Inc. Method and mechanism for cache compaction and bandwidth reduction

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US5142633A (en) 1989-02-03 1992-08-25 Digital Equipment Corporation Preprocessing implied specifiers in a pipelined processor
US5287467A (en) 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5604909A (en) 1993-12-15 1997-02-18 Silicon Graphics Computer Systems, Inc. Apparatus for processing instructions in a computing system
JP3589485B2 (ja) * 1994-06-07 2004-11-17 株式会社ルネサステクノロジ セットアソシアティブ方式のメモリ装置およびプロセッサ
US5848433A (en) * 1995-04-12 1998-12-08 Advanced Micro Devices Way prediction unit and a method for operating the same
US5781789A (en) * 1995-08-31 1998-07-14 Advanced Micro Devices, Inc. Superscaler microprocessor employing a parallel mask decoder
US5826071A (en) 1995-08-31 1998-10-20 Advanced Micro Devices, Inc. Parallel mask decoder and method for generating said mask
US5794028A (en) * 1996-10-17 1998-08-11 Advanced Micro Devices, Inc. Shared branch prediction structure
US5995749A (en) * 1996-11-19 1999-11-30 Advanced Micro Devices, Inc. Branch prediction mechanism employing branch selectors to select a branch prediction
US5845102A (en) * 1997-03-03 1998-12-01 Advanced Micro Devices, Inc. Determining microcode entry points and prefix bytes using a parallel logic technique
JP3469042B2 (ja) * 1997-05-14 2003-11-25 株式会社東芝 キャッシュメモリ
US7085920B2 (en) 2000-02-02 2006-08-01 Fujitsu Limited Branch prediction method, arithmetic and logic unit, and information processing apparatus for performing brach prediction at the time of occurrence of a branch instruction
US7406569B2 (en) * 2002-08-12 2008-07-29 Nxp B.V. Instruction cache way prediction for jump targets
JP3834323B2 (ja) * 2004-04-30 2006-10-18 日本電気株式会社 キャッシュメモリおよびキャッシュ制御方法
US8225046B2 (en) 2006-09-29 2012-07-17 Intel Corporation Method and apparatus for saving power by efficiently disabling ways for a set-associative cache
US20080147989A1 (en) * 2006-12-14 2008-06-19 Arm Limited Lockdown control of a multi-way set associative cache memory
US8151084B2 (en) * 2008-01-23 2012-04-03 Oracle America, Inc. Using address and non-address information for improved index generation for cache memories
US8522097B2 (en) * 2010-03-16 2013-08-27 Qualcomm Incorporated Logic built-in self-test programmable pattern bit mask
JP2011257800A (ja) * 2010-06-04 2011-12-22 Panasonic Corp キャッシュメモリ装置、プログラム変換装置、キャッシュメモリ制御方法及びプログラム変換方法
JP5954112B2 (ja) * 2012-10-24 2016-07-20 富士通株式会社 メモリ装置、演算処理装置、及びキャッシュメモリ制御方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6016533A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array
US6356990B1 (en) * 2000-02-02 2002-03-12 International Business Machines Corporation Set-associative cache memory having a built-in set prediction array
CN1484788A (zh) * 2000-12-29 2004-03-24 英特尔公司 根据未命中距离将数据预取到高速缓存器中的系统和方法
CN1397874A (zh) * 2001-05-04 2003-02-19 智慧第一公司 高速缓存的快取线选取目标地址的装置及方法
US20050050278A1 (en) * 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
US20060174090A1 (en) * 2005-02-03 2006-08-03 Sartorius Thomas A Power efficient instruction prefetch mechanism
US8046538B1 (en) * 2005-08-04 2011-10-25 Oracle America, Inc. Method and mechanism for cache compaction and bandwidth reduction
CN101313286A (zh) * 2005-12-22 2008-11-26 英特尔公司 多线程处理器中的性能优先化

Also Published As

Publication number Publication date
JP2016505971A (ja) 2016-02-25
JP6212133B2 (ja) 2017-10-11
US20140181405A1 (en) 2014-06-26
WO2014100632A1 (en) 2014-06-26
EP2936303A1 (en) 2015-10-28
EP2936303B1 (en) 2020-01-15
CN104854557A (zh) 2015-08-19
US9304932B2 (en) 2016-04-05

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