WO2014074486A1 - Group-iii nitride heterojunction bipolar transistors - Google Patents

Group-iii nitride heterojunction bipolar transistors Download PDF

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Publication number
WO2014074486A1
WO2014074486A1 PCT/US2013/068427 US2013068427W WO2014074486A1 WO 2014074486 A1 WO2014074486 A1 WO 2014074486A1 US 2013068427 W US2013068427 W US 2013068427W WO 2014074486 A1 WO2014074486 A1 WO 2014074486A1
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Prior art keywords
emitter
base
mesa
sidewall
layer structure
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PCT/US2013/068427
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French (fr)
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Ajay RAMAN
Umesh K. Mishra
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The Regents Of The University Of California
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Publication of WO2014074486A1 publication Critical patent/WO2014074486A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H01L21/30617—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • This invention relates to a method of fabricating transistors such as heterojunction bipolar transistors (HBT) using Group-Ill nitride semiconductor material.
  • HBT heterojunction bipolar transistors
  • a heterojunction bipolar transistor is a type of bipolar junction transistor (BJT) comprised of different materials for the emitter-base junction and the base-collector junction, thereby creating a heterojunction.
  • BJT bipolar junction transistor
  • the HBT improves on the BJT in that it can handle signals of very high frequencies, which makes it useful in modern ultrafast circuits and in applications requiring a high power efficiency.
  • Wide-bandgap semiconductors such as Group-Ill nitrides including gallium nitride (GaN) and indium gallium nitride (InGaN), are especially promising for use in HBTs.
  • dislocations can have a negative effect on the performance of HBTs grown using Group-Ill nitrides.
  • the performance of HBTs grown using Group-Ill nitrides can be improved through reductions in threading dislocation density, which mitigate the effects of carrier traps via fewer dislocations and reduced localized states.
  • the present invention discloses a wet-etch method for decreasing electron recombination at the sidewalls of an emitter mesa and extrinsic base surfaces in Group-Ill nitride based heterojunction bipolar transistors, thereby enhancing the performance of the devices.
  • Fabrication of Group-Ill nitride based heterojunction bipolar transistors typically involves a reactive-ion etch process step to form the emitter mesa, which creates defects at the mesa sidewalls and extrinsic base surfaces. These defects trap carriers and reduce current gain.
  • the wet-etch process described in this invention etches away a few nanometers of the Group-Ill nitride semiconductor material containing defects from the emitter mesa sidewalls and the extrinsic base surfaces, thereby removing carrier traps that limit current gain by decreasing electron recombination at the emitter mesa sidewalls and extrinsic base surfaces.
  • the wet etch process step can be implemented in, and integrated to, the device fabrication process.
  • FIG. 1 is a schematic of a heterojunction bipolar transistor according to one embodiment of the present invention.
  • FIG. 2 is schematic of a schematic of a layer structure for a heterojunction bipolar transistor according to one embodiment of the present invention.
  • FIG. 3 is a Secondary Ion Mass Spectrometry (SIMS) profile of the layer structure if FIG. 2
  • FIG. 4 shows the Common Emitter IV Characteristics (a) and Gummel Plots (b,c) of a GaN based heterojunction bipolar transistor with an InGaN base, wherein fabrication of this device proceeded without the wet-etch process of the present invention and Peak Current Gain is 5.
  • FIG. 5 shows the Common Emitter IV Characteristics and Gummel Plots of a GaN based heterojunction bipolar transistor with an InGaN base, wherein fabrication of this device included the wet-etch process of the present invention and Peak Current Gain is 7.
  • FIG. 1 is a schematic of a Group-Ill nitride based heterojunction bipolar transistor according to one embodiment of the present invention.
  • the Group-Ill nitride based heterojunction bipolar transistor 100 includes a collector 102, base 104 and emitter 106, wherein 108, 110 and 112 are contacts for the collector 102, base 104 and emitter 106, respectively.
  • Carrier traps 114 resulting from defects are located on both the mesa sidewalls of the emitter 106 and the extrinsic surfaces of the base 104.
  • FIG. 2 is a schematic of a layer structure for the Group-Ill nitride based heterojunction bipolar transistor of FIG.
  • the structure 200 includes a substrate 202, a 200 nm n-type GaN layer 204 doped with Si at a concentration of about 5el8 cm "3 , a 500 nm unintentionally doped (UID) GaN layer 206, a 30 nm graded UID GaN -> Ino.05Gao.95N layer 208, a 100 nm p-type
  • Layers 216, 214, 212 comprise the emitter 218; layer 210 comprises the base 220; layers 208, 206 comprise the collector 222; layer 204 comprises the sub-collector 224; and layer 202 comprises the substrate; as they exist prior to the etching of the mesa and the deposition of the contacts.
  • FIG. 3 shows the Secondary Ion Mass Spectrometry (SIMS) profile of the device of FIG. 2, which confirms the layer structure of the device.
  • SIMS Secondary Ion Mass Spectrometry
  • FIG. 4 is flowchart illustrating a method of fabricating a heterojunction bipolar transistor (HBT), according to one embodiment of the present invention.
  • Block 400 represents the step of creating a layer structure comprised of at least a collector, a base and an emitter for the heterojunction bipolar transistor, wherein the layer structure is comprised of Group-Ill nitride semiconductor materials, as shown in FIG. 2.
  • the Group-Ill nitride device layers are grown by Metal Organic Chemical Vapor Deposition (MOCVD) in, for example, a Thomas- SwanTM MOCVD reactor.
  • MOCVD Metal Organic Chemical Vapor Deposition
  • Block 402 represents the step of etching the layer structure to form at least one mesa having at least one sidewall for the emitter and to expose at least one extrinsic surface of the base, resulting in the mesa structure shown in FIG. 1.
  • the mesa structure is formed by a reactive ion etching (RIE) of the layer structure, which creates defects at the sidewalls of the mesa of the emitter and the extrinsic surfaces of the base, wherein the defects trap carriers and reduce current gain.
  • RIE reactive ion etching
  • Blocks 404-408 represents the step of wet etching the sidewalls of the mesa for the emitter and the extrinsic surfaces of the base, to remove defects from the sidewalls of the mesa for the emitter and the extrinsic surfaces of the base, thereby reducing carrier traps that limit current gain for the heterojunction bipolar transistor by decreasing electron recombination at the sidewalls of the mesa of the emitter and the extrinsic surfaces of the base.
  • the layer structure is immersed (at step 404) in an approximately 0.01 M solution of potassium hydroxide (KOH) for about 5 minutes under ultraviolet (UV) illumination (at step 406) at a wavelength of about 365 nm with an intensity of about 15 mW/cm 2 , which results in the etch of about 1-10 nanometers of the Group-Ill nitride semiconductor material from the sidewalls of the mesa of the emitter and the extrinsic surfaces of the base, and then the layer structure is rinsed (at step 408) in deionized (DI) water for 2 minutes.
  • KOH potassium hydroxide
  • UV illumination at step 406
  • DI deionized
  • Block 410 represents the step of depositing contacts on the layer structure after the wet-etching step is performed, resulting in the final device structure shown in FIG. 1.
  • Block 412 represents this end result, the final device structure shown in FIG. 1 comprising a heterojunction bipolar transistor (HBT), having a layer structure comprised of at least a collector, a base and an emitter, wherein the layer structure is comprised of Group-Ill nitride semiconductor materials.
  • HBT heterojunction bipolar transistor
  • the layer structure comprises an etched layer structure that forms at least one mesa that has at least one sidewall for the emitter and that exposes at least one extrinsic surface of the base, wherein the sidewall of the mesa for the emitter is a wet-etched sidewall and the extrinsic surface of the base is a wet-etched extrinsic surface, thereby removing carrier traps that limit current gain for the heterojunction bipolar transistor by decreasing electron recombination at the sidewalls of the mesa of the emitter and the extrinsic surfaces of the base.
  • the effects of the wet etching process can best be illustrated by comparing a GaN-based heterojunction bipolar transistor that is not wet-etched to a GaN-based heterojunction bipolar transistor that is wet-etched, in the manner described above. More specifically, the effects of the wet etching process can best be illustrated by comparing device performance with and without the etch of the mesa sidewalls of the emitter and the extrinsic surfaces of the base to remove defects that result in carrier traps.
  • FIG. 5 shows the Common Emitter IV Characteristics (a) and Gummel Plots (b,c) of a GaN-based heterojunction bipolar transistor with an InGaN base, wherein the wet-etch process of the present invention has not been applied to the device.
  • FIG. 5(a) is a graph that plots VC E (V) vs. Ic (mA), namely, the voltage across the collector-emitter junction vs. the collector current
  • FIG. 5(b) is a graph that plots V BE (V) vs. Ic, I B (A), namely, the voltage across the base-emitter junction vs. the collector current and the base current
  • FIG. 6 shows the Common Emitter IV Characteristics and Gummel Plots of a GaN-based heterojunction bipolar transistor with an InGaN base, wherein fabrication of the device included the wet-etch process of the present invention.
  • FIG. 6(a) is a graph that plots VC E (V) vs. Ic (mA), namely, the voltage across the collector-emitter junction vs. the collector current
  • FIG. 6(b) is a graph that plots V BE (V) vs. Ic, I B (A), namely, the voltage across the base-emitter junction vs. the collector current and the base current
  • the wet-etching method of the present invention results in improved performance.
  • the Group-Ill nitride based heterojunction bipolar transistor that is wet-etched has improved performance as compared to a Group-Ill nitride based heterojunction bipolar transistor that is not wet-etched, wherein the improved performance comprises:
  • VA Early voltage
  • compositions and materials within the scope of the invention may further include quantities of dopants and/or other impurity materials and/or other inclusional materials.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A method of fabricating a heterojunction bipolar transistor (HBT), including (a) fabricating or obtaining a Group-Ill based heterojunction bipolar transistor structure; (b) etching the Group-Ill based heterojunction bipolar transistor structure to form an emitter mesa having sidewalls and exposing extrinsic base surfaces; and then (c) wet etching nanometers of the Group-Ill nitride semiconductor materials from the emitter mesa sidewalls and the extrinsic base surfaces containing defects, thereby removing carrier traps that limit current gain by decreasing electron recombination at the sidewalls of the mesa of the emitter and the extrinsic surfaces of the base.

Description

METHOD TO DECREASE ELECTRON RECOMBINATION AT
SIDEWALLS OF AN EMITTER MESA AND EXTRINSIC BASE SURFACES IN GROUP-III NITRIDE HETEROJUNCTION BIPOLAR TRANSISTORS
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit under 35 U.S.C Section 119(e) of the following co-pending and commonly-assigned patent application:
U.S. Provisional Patent Application Serial No. 61/723,502, filed on November 7, 2012, by Ajay Raman and Umesh K. Mishra, and entitled "METHOD TO
DECREASE ELECTRON RECOMBINATION AT SIDEWALLS OF EMITTER MESA AND EXTRINSIC BASE SURFACE IN GAN HETEROJUNCTION BIPOLAR TRANSISTORS," attorney's docket number 30794.478-US-P1 (2013- 383-1);
which application is incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention.
This invention relates to a method of fabricating transistors such as heterojunction bipolar transistors (HBT) using Group-Ill nitride semiconductor material.
2. Description of the Related Art.
A heterojunction bipolar transistor (HBT) is a type of bipolar junction transistor (BJT) comprised of different materials for the emitter-base junction and the base-collector junction, thereby creating a heterojunction. The HBT improves on the BJT in that it can handle signals of very high frequencies, which makes it useful in modern ultrafast circuits and in applications requiring a high power efficiency.
Wide-bandgap semiconductors, such as Group-Ill nitrides including gallium nitride (GaN) and indium gallium nitride (InGaN), are especially promising for use in HBTs. However, dislocations can have a negative effect on the performance of HBTs grown using Group-Ill nitrides. Specifically, the performance of HBTs grown using Group-Ill nitrides can be improved through reductions in threading dislocation density, which mitigate the effects of carrier traps via fewer dislocations and reduced localized states.
What is needed, then, are improved techniques for fabricating Group-Ill nitride based heterojunction bipolar transistors. The present invention satisfies this need. SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a wet-etch method for decreasing electron recombination at the sidewalls of an emitter mesa and extrinsic base surfaces in Group-Ill nitride based heterojunction bipolar transistors, thereby enhancing the performance of the devices. Fabrication of Group-Ill nitride based heterojunction bipolar transistors typically involves a reactive-ion etch process step to form the emitter mesa, which creates defects at the mesa sidewalls and extrinsic base surfaces. These defects trap carriers and reduce current gain. The wet-etch process described in this invention etches away a few nanometers of the Group-Ill nitride semiconductor material containing defects from the emitter mesa sidewalls and the extrinsic base surfaces, thereby removing carrier traps that limit current gain by decreasing electron recombination at the emitter mesa sidewalls and extrinsic base surfaces. The wet etch process step can be implemented in, and integrated to, the device fabrication process.
BRIEF DESCRIPTION OF THE DRAWINGS
Referring now to the drawings in which like reference numbers represent corresponding parts throughout: FIG. 1 is a schematic of a heterojunction bipolar transistor according to one embodiment of the present invention.
FIG. 2 is schematic of a schematic of a layer structure for a heterojunction bipolar transistor according to one embodiment of the present invention.
FIG. 3 is a Secondary Ion Mass Spectrometry (SIMS) profile of the layer structure if FIG. 2
FIG. 4 shows the Common Emitter IV Characteristics (a) and Gummel Plots (b,c) of a GaN based heterojunction bipolar transistor with an InGaN base, wherein fabrication of this device proceeded without the wet-etch process of the present invention and Peak Current Gain is 5.
FIG. 5 shows the Common Emitter IV Characteristics and Gummel Plots of a GaN based heterojunction bipolar transistor with an InGaN base, wherein fabrication of this device included the wet-etch process of the present invention and Peak Current Gain is 7.
DETAILED DESCRIPTION OF THE INVENTION
In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.
Technical Description
FIG. 1 is a schematic of a Group-Ill nitride based heterojunction bipolar transistor according to one embodiment of the present invention. The Group-Ill nitride based heterojunction bipolar transistor 100 includes a collector 102, base 104 and emitter 106, wherein 108, 110 and 112 are contacts for the collector 102, base 104 and emitter 106, respectively. Carrier traps 114 resulting from defects are located on both the mesa sidewalls of the emitter 106 and the extrinsic surfaces of the base 104. FIG. 2 is a schematic of a layer structure for the Group-Ill nitride based heterojunction bipolar transistor of FIG. 1, prior to etching the mesa and depositing the contacts, according to one embodiment of the present invention. The structure 200 includes a substrate 202, a 200 nm n-type GaN layer 204 doped with Si at a concentration of about 5el8 cm"3, a 500 nm unintentionally doped (UID) GaN layer 206, a 30 nm graded UID GaN -> Ino.05Gao.95N layer 208, a 100 nm p-type
Ino.05Gao.95N layer 210 doped with Mg at a concentration of about 5el8 cm"3, a 30 nm n-type graded Ino.05Gao.95N -> GaN layer 212 doped with Si at a concentration of about lei 9 cm"3, a 100 nm n-type GaN layer 214 doped with Si at a concentration of about 5el8 cm"3, and a 20 nm n-type GaN layer 216 doped with Si at a concentration of about lel9 cm"3. Layers 216, 214, 212 comprise the emitter 218; layer 210 comprises the base 220; layers 208, 206 comprise the collector 222; layer 204 comprises the sub-collector 224; and layer 202 comprises the substrate; as they exist prior to the etching of the mesa and the deposition of the contacts.
FIG. 3 shows the Secondary Ion Mass Spectrometry (SIMS) profile of the device of FIG. 2, which confirms the layer structure of the device.
FIG. 4 is flowchart illustrating a method of fabricating a heterojunction bipolar transistor (HBT), according to one embodiment of the present invention.
Block 400 represents the step of creating a layer structure comprised of at least a collector, a base and an emitter for the heterojunction bipolar transistor, wherein the layer structure is comprised of Group-Ill nitride semiconductor materials, as shown in FIG. 2. Specifically, at step 400, the Group-Ill nitride device layers are grown by Metal Organic Chemical Vapor Deposition (MOCVD) in, for example, a Thomas- Swan™ MOCVD reactor.
Block 402 represents the step of etching the layer structure to form at least one mesa having at least one sidewall for the emitter and to expose at least one extrinsic surface of the base, resulting in the mesa structure shown in FIG. 1. Specifically, at step 402, the mesa structure is formed by a reactive ion etching (RIE) of the layer structure, which creates defects at the sidewalls of the mesa of the emitter and the extrinsic surfaces of the base, wherein the defects trap carriers and reduce current gain.
Blocks 404-408 represents the step of wet etching the sidewalls of the mesa for the emitter and the extrinsic surfaces of the base, to remove defects from the sidewalls of the mesa for the emitter and the extrinsic surfaces of the base, thereby reducing carrier traps that limit current gain for the heterojunction bipolar transistor by decreasing electron recombination at the sidewalls of the mesa of the emitter and the extrinsic surfaces of the base. Specifically, at steps 404-408, after the mesa structure is formed in step 402, the layer structure is immersed (at step 404) in an approximately 0.01 M solution of potassium hydroxide (KOH) for about 5 minutes under ultraviolet (UV) illumination (at step 406) at a wavelength of about 365 nm with an intensity of about 15 mW/cm2, which results in the etch of about 1-10 nanometers of the Group-Ill nitride semiconductor material from the sidewalls of the mesa of the emitter and the extrinsic surfaces of the base, and then the layer structure is rinsed (at step 408) in deionized (DI) water for 2 minutes.
Block 410 represents the step of depositing contacts on the layer structure after the wet-etching step is performed, resulting in the final device structure shown in FIG. 1.
Finally, Block 412 represents this end result, the final device structure shown in FIG. 1 comprising a heterojunction bipolar transistor (HBT), having a layer structure comprised of at least a collector, a base and an emitter, wherein the layer structure is comprised of Group-Ill nitride semiconductor materials. The layer structure comprises an etched layer structure that forms at least one mesa that has at least one sidewall for the emitter and that exposes at least one extrinsic surface of the base, wherein the sidewall of the mesa for the emitter is a wet-etched sidewall and the extrinsic surface of the base is a wet-etched extrinsic surface, thereby removing carrier traps that limit current gain for the heterojunction bipolar transistor by decreasing electron recombination at the sidewalls of the mesa of the emitter and the extrinsic surfaces of the base. The effects of the wet etching process can best be illustrated by comparing a GaN-based heterojunction bipolar transistor that is not wet-etched to a GaN-based heterojunction bipolar transistor that is wet-etched, in the manner described above. More specifically, the effects of the wet etching process can best be illustrated by comparing device performance with and without the etch of the mesa sidewalls of the emitter and the extrinsic surfaces of the base to remove defects that result in carrier traps.
FIG. 5 shows the Common Emitter IV Characteristics (a) and Gummel Plots (b,c) of a GaN-based heterojunction bipolar transistor with an InGaN base, wherein the wet-etch process of the present invention has not been applied to the device.
Specifically, FIG. 5(a) is a graph that plots VCE (V) vs. Ic (mA), namely, the voltage across the collector-emitter junction vs. the collector current; FIG. 5(b) is a graph that plots VBE (V) vs. Ic, IB (A), namely, the voltage across the base-emitter junction vs. the collector current and the base current; and FIG. 5(c) is a graph that plots VBE (V) vs. β (IC/IB), namely, the voltage across the base-emitter junction vs. the common- emitter current gain, wherein the Peak Current Gain = 5.
FIG. 6 shows the Common Emitter IV Characteristics and Gummel Plots of a GaN-based heterojunction bipolar transistor with an InGaN base, wherein fabrication of the device included the wet-etch process of the present invention. Specifically, FIG. 6(a) is a graph that plots VCE (V) vs. Ic (mA), namely, the voltage across the collector-emitter junction vs. the collector current; FIG. 6(b) is a graph that plots VBE (V) vs. Ic, IB (A), namely, the voltage across the base-emitter junction vs. the collector current and the base current; and FIG. 6(c) is a graph that plots VBE (V) vs. β (IC/IB), namely, the voltage across the base-emitter junction vs. the common-emitter current gain, wherein the Peak Current Gain = 7.
It can be seen from a comparison of FIGS. 5 and 6, that the wet-etching method of the present invention results in improved performance. Specifically, the Group-Ill nitride based heterojunction bipolar transistor that is wet-etched has improved performance as compared to a Group-Ill nitride based heterojunction bipolar transistor that is not wet-etched, wherein the improved performance comprises:
1) an increase in current gain in a device that has been wet-etched as compared to a device that has not been wet-etched; and
2) an increase in Early voltage (VA) of a device that has been wet-etched as compared to a device that has not been wet-etched.
Nomenclature
The terms "(Al,In,B,Ga)N" or "Group-Ill nitride" or "Ill-nitride" or "nitride" as used herein refer to any composition or material related to (Al,In,B,Ga)N semiconductors having the formula AlwInxByGazN where 0 < w < l, 0 < x < l, 0 ≤ y≤ l, 0 < z < l, and w + x + y + z = 1. These terms as used herein are intended to be broadly construed to include respective nitrides of the single species, Al, In, B, Ga, as well as binary, ternary and quaternary compositions of such Group III metal species. When two or more of the (Al,In,B,Ga)N component species are present, all possible compositions, including stoichiometric proportions as well as off- stoichiometric proportions (with respect to the relative mole fractions present of each of the (Al,In,B,Ga)N component species that are present in the composition), can be employed within the broad scope of this invention. Further, compositions and materials within the scope of the invention may further include quantities of dopants and/or other impurity materials and/or other inclusional materials.
Conclusion
This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many
modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

WHAT IS CLAIMED IS:
1. A method of fabricating a heterojunction bipolar transistor (HBT), comprising:
(a) creating a layer structure comprised of at least a collector, a base and an emitter for the heterojunction bipolar transistor, wherein the layer structure is comprised of Group-Ill nitride semiconductor materials;
(b) etching the layer structure to form at least one mesa having at least one sidewall for the emitter and to expose at least one extrinsic surface of the base; and
(c) wet etching the sidewall of the mesa for the emitter and the extrinsic surface of the base, to remove defects from the sidewall of the mesa for the emitter and the extrinsic surface of the base, thereby removing carrier traps that limit current gain for the heterojunction bipolar transistor by decreasing electron recombination at the sidewall of the mesa for the emitter and the extrinsic surface of the base.
2. The method of claim 1 , wherein the layer structure is grown by Metal Organic Chemical Vapor Deposition (MOCVD).
3. The method of claim 1, wherein the etching step (b) comprises a reactive ion etching of the layer structure, which creates defects at the sidewall of the mesa of the emitter and the extrinsic surface of the base, and the defects trap carriers and reduce current gain.
4. The method of claim 1, wherein the wet etching step (c) comprises wet etching the sidewall of the mesa for the emitter of the heterojunction bipolar transistor and the extrinsic surface of the base of the heterojunction bipolar transistor, under ultraviolet illumination and using a solution of potassium hydroxide (KOH).
5. The method of claim 4, wherein the layer structure is immersed in an approximately 0.01 M solution of the potassium hydroxide for about 5 minutes under the ultraviolet illumination at a wavelength of about 365 nm with an intensity of about 15 mW/cm2, which results in the wet-etching of the sidewall of the mesa of the emitter and the extrinsic surface of the base.
6. The method of claim 1, wherein the wet-etching step (c) etches away about 1-10 nanometers of the Group-Ill nitride semiconductor material from the sidewall of the mesa of the emitter and the extrinsic surface of the base, thereby removing the defects resulting in the carrier traps that limit the current gain.
7. The method of claim 1, wherein the wet-etching step (c) results in decreasing electron recombination at the sidewall of the mesa of the emitter and the extrinsic surface of the base as compared to a sidewall of a mesa of an emitter and an extrinsic surface of a base that are not wet-etched.
8. The method of claim 1 , wherein the heterojunction bipolar transistor that is wet-etched has improved performance as compared to a heterojunction bipolar transistor that is not wet-etched.
9. The method of claim 8, wherein the improved performance comprises an increase in current gain.
10. The method of claim 9, wherein the current gain has a peak current gain of at least 7.
11. The method of claim 8, wherein the improved performance comprises an increase in Early voltage (VA).
12. The method of claim 1, further comprising depositing contacts on the layer structure after the wet-etching step (c) is performed.
13. A heterojunction bipolar transistor (HBT), comprising:
a layer structure comprised of at least a collector, a base and an emitter for the heterojunction bipolar transistor, wherein the layer structure is comprised of Group-Ill nitride semiconductor materials;
the layer structure comprising an etched layer structure that forms at least one mesa that has at least one sidewall for the emitter and that exposes at least one extrinsic surface of the base; and
the sidewall of the mesa for the emitter comprising a wet-etched sidewall and the extrinsic surface of the base comprising a wet-etched extrinsic surface;
thereby removing carrier traps that limit current gain for the heterojunction bipolar transistor by decreasing electron recombination at the sidewall of the mesa for the emitter and the extrinsic surface of the base.
14. A heterojunction bipolar transistor (HBT), comprising: a layer structure comprised of at least a collector, a base and an emitter for the heterojunction bipolar transistor, wherein the layer structure is comprised of Group-Ill nitride semiconductor materials; the layer structure comprising an etched layer structure that forms at least one mesa that has at least one sidewall for the emitter and that exposes at least one extrinsic surface of the base; and the sidewall of the mesa for the emitter comprising a wet-etched sidewall and the extrinsic surface of the base comprising a wet-etched extrinsic surface; the heterojunction bipolar transistor fabricated by a process, comprising:
(a) creating a layer structure comprised of at least a collector, a base and an emitter for the heterojunction bipolar transistor, wherein the layer structure is comprised of Group-Ill nitride semiconductor materials; (b) etching the layer structure to form at least one mesa having at least one sidewall for the emitter and to expose at least one extrinsic surface of the base; and
(c) wet etching the sidewall of the mesa for the emitter and the extrinsic surface of the base, to remove defects from the sidewalls of the mesa for the emitter and the extrinsic surfaces of the base, thereby removing carrier traps that limit current gain for the heterojunction bipolar transistor by decreasing electron recombination at the sidewall of the mesa for the emitter and the extrinsic surface of the base.
PCT/US2013/068427 2012-11-07 2013-11-05 Group-iii nitride heterojunction bipolar transistors WO2014074486A1 (en)

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