JP6538608B2 - Method of manufacturing heterojunction bipolar transistor - Google Patents

Description

The present invention relates to a method of manufacturing a heterojunction bipolar transitional scan data using wide-gap material to the collector layer.

InP-based heterojunction bipolar transistors (HBTs) are ultrafast devices capable of achieving cutoff frequencies approaching 1 THz. One of the important indexes of high-speed performance is the product (f _T × BV) of current gain cutoff frequency (f _T ) and withstand voltage (BV). The larger this value, the more compatible high-speed performance and high withstand voltage performance. Means a device. Therefore, achieving a higher breakdown voltage while maintaining f _T is important for further improving the performance of InP HBTs.

  The breakdown voltage of the HBT is defined by the breakdown voltage between the emitter and the collector at the emitter ground base opening, which depends on the breakdown voltage of the base-collector junction. Therefore, applying a wide band gap material to the collector layer is effective for increasing the breakdown voltage of the HBT.

For example, in a general InP-based HBT, the base layer is formed of narrow band gap InGaAs, GaAsSb, InGaAsSb or the like doped to 10 ¹⁹ cm ^-3 or more. This HBT has two collector layers: a single heterojunction bipolar transistor (SHBT) that uses the same narrow band gap material as the base layer, and a double heterojunction bipolar transistor (DHBT) that uses InP with a large band gap in the collector layer. There is a kind. When comparing the two, DHBT tends to have higher f _T × BV.

For example, in Non-Patent Document 1, in a DHBT in which the base layer is composed of GaAsSb and the collector layer is composed of InP, compatibility between a withstand voltage of 6.5 V and an f _T of 470 GHz is reported (f _T × BV > 3000 GHz x V).

  Furthermore, InP-based DHBT is an advantageous device also from the viewpoint of drive voltage. The driving voltage of the HBT depends on the built-in potential of the base-emitter junction. This is determined by the doping conditions of the emitter contact layer and the emitter layer, the doping concentration and band gap of the base layer, and the conduction band offset at the emitter-base junction. When an InP-based material is applied to DHBT, basically, the base layer is made of InGaAs, GaAsSb, or InGaAsSb. These materials have small band gaps as compared to Si, GaAs, and GaN, and thus can lower the driving voltage as compared to other HBTs.

  In order to further increase the breakdown voltage of such DHBT, it is conceivable to apply a wide band gap material to the collector layer. As a semiconductor material having a wider band gap than that of the conventional material, InP, GaAs, ZnSe, GaN, AlN, SiC, diamond (C), etc. may be mentioned.

  However, both materials have smaller lattice constants than InP-based materials. For this reason, when the collector layer is formed of the wide gap material described above by a film forming technique such as epitaxial crystal growth, large lattice mismatch can be easily relaxed. The crystal quality of the collector layer and the crystal quality of the other semiconductor layers are impaired by the crystal defects introduced in this relaxation process.

  In the HBT, the deterioration of the crystal quality of the base layer causes a decrease in current gain, and the deterioration of the crystal quality of the collector layer causes a decrease in breakdown voltage, an increase in leakage current, and the like. Furthermore, since the lifetime of the device itself is reduced, it is difficult to form a wide gap collector / narrow bandgap base junction by epitaxial growth.

  On the other hand, there has been reported a technique for producing an HBT structure having a wide band gap collector and applied to a GaAs base by directly bonding wafers epitaxially grown on different substrates (non-patent document) 2). In this technique, an n-type GaAs emitter contact layer, an n-type composition graded AlGaAs emitter layer, a p-type GaAs base layer, and a GaAs setback layer are formed on a GaAs substrate. An n-type GaN subcollector layer and an n-type GaN collector layer are formed on another sapphire substrate.

  The two are bonded to each other by bonding the setback layer and the collector layer, and directly bonding them by wafer bonding, and the HBT wafer is manufactured by removing the GaAs substrate. After this, a mesa structure is formed on the sapphire substrate by typical HBT fabrication semiconductor process technology to fabricate an HBT device.

  As described above, by forming the wide band gap collector layer by the bonding method, it is possible to further increase the breakdown voltage of a GaAs-based or InP-based HBT excellent in high-speed performance. In addition, low drive voltage, which is a feature of InP DHBT, can be realized simultaneously. Further, by using the set back layer, the layer of low crystal quality at the bonding interface is separated from the base layer to suppress the deterioration of the bias characteristics. Therefore, by forming a base layer from an InP-based material, an emitter layer from a wide gap material such as GaN, and forming such a structure by a technique such as wafer bonding, low drive voltage, high withstand voltage, and high It is considered that DHBT having high frequency characteristics can be realized.

Huiming Xu, Barry Wu, Eric W. Iverson, Thomas S. Low, and Milton Feng, "0.5 THz Performance of a Type-II DHBT with a Doping-Graded and Constant-Composition GaAsSb Base", IEEE ELECTRONIC LETTERS, vol. 35, no. 1, pp. 24-26, 2014. Chuanxin Lian, Huili Grace Xing, Chad S. Wang, David Brown, and Lee McCarthy, "Gain degradation mechanisms in wafer fused AlGaAs / GaAs / GaN heterojunction bipolar transistors", Applied Physics Letters, vol. 91, 063502, 2007. C. G. Van de Walle, "Universal alignment of hydrogen levels in semiconductors, insulators and solutions", Nature, vol. 423, pp. 626-628, 2003.

However, the above-described technology has the following problems. For example, when the collector layer is made of a wide gap material such as GaN, the difference in band gap between the base layer (setback layer) and the collector layer is large, and the energy at the conduction band edge of the collector layer tends to be high. If the band gap of the base layer is small and the energy of the conduction band edge of the base layer is lower than the conduction band edge of the collector layer, it acts as a barrier to electrons traveling in the base layer from the emitter side to the collector side, charging decrease of f _T is caused by the time increases. As described above, conventionally, there has been a problem that the characteristic (current gain cutoff frequency f _T ) is lowered due to the band gap energy difference.

  The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to suppress deterioration of characteristics due to a difference in band gap energy between a collector layer and a base layer.

Heterojunction bipolar transistor has a collector layer consisting of GaN or SiC is formed on the substrate, and the setback layer of a III-V compound semiconductor formed on the collector layer, on the setback layer A base layer made of a Group III-V compound semiconductor containing Ga, As, Sb, an emitter layer made of a Group III-V compound semiconductor different from the base layer formed on the base layer, and a collector layer The setback layer is composed of a group III-V compound semiconductor different from the base layer, and the collector has a collector electrode to be connected, a base electrode to be connected to the base layer, and an emitter electrode to be connected to the emitter layer. It is considered as the band gap energy between the layer and the base layer.

  In the heterojunction bipolar transistor, the setback layer may be made of InP or InAlAs.

  In the heterojunction bipolar transistor, the substrate may be made of any one of SiC, Si and GaN.

  A method of manufacturing a heterojunction bipolar transistor according to the present invention comprises: forming an emitter forming layer of III-V compound semiconductor on a growth substrate of III-V compound semiconductor; III-V compound containing Ga, As, Sb A first step of sequentially forming a base formation layer of semiconductor and a setback formation layer of III-V compound semiconductor, and a second step of forming a collector formation layer of GaN or SiC on the substrate; A third step of bonding the setback formation layer and the collector formation layer together, and setting the collector formation layer, the setback formation layer, the base formation layer, and the collector formation layer in this order on the substrate; After the formation layer and the collector formation layer are bonded to each other, a fourth step of removing the growth substrate, and after removing the growth substrate, emitter formation , Forming the base formation layer, the setback formation layer, and the collector formation layer, and forming the collector layer formed on the substrate, the setback layer formed on the collector layer, and the setback layer A fifth step of forming a base layer and an emitter layer formed on the base layer, a collector electrode connected to the collector layer, a base electrode connected to the base layer, and an emitter electrode connected to the emitter layer And a sixth step of forming the setback layer, wherein the setback layer is composed of a group III-V compound semiconductor different from the base layer, and serves as a band gap energy between the collector layer and the base layer.

  In the method of manufacturing the heterojunction bipolar transistor, the setback layer may be made of InP or InAlAs.

  In the method of manufacturing the heterojunction bipolar transistor, the substrate may be made of any one of SiC, Si and GaN.

  As described above, according to the present invention, the setback layer is composed of a group III-V compound semiconductor different from the base layer, and has the band gap energy between the collector layer and the base layer, The excellent effect of suppressing the deterioration of the characteristics due to the band gap energy difference between the collector layer and the base layer is obtained.

FIG. 1 is a cross-sectional view showing the configuration of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2 is a band diagram showing a band structure between a collector layer made of GaN and a base layer made of InGaAs. FIG. 3A is a cross-sectional view showing a state in each process for illustrating the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 3B is a cross-sectional view showing a state in each process for illustrating the method of manufacturing the heterojunction bipolar transistor according to the embodiment of the present invention. FIG. 3C is a cross-sectional view showing a state in each process for illustrating the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 3D is a cross-sectional view showing a state in each process for illustrating the method of manufacturing the heterojunction bipolar transistor according to the embodiment of the present invention. FIG. 3E is a cross-sectional view showing a state in each process for illustrating the method of manufacturing the heterojunction bipolar transistor according to the embodiment of the present invention. FIG. 3F is a cross-sectional view showing a state in each process for illustrating the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 3G is a cross-sectional view showing a state in each process for illustrating the method of manufacturing the heterojunction bipolar transistor according to the embodiment of the present invention. FIG. 3H is a cross-sectional view showing a state in each process for illustrating the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Figure 1 is a cross-sectional view showing the structure of a heterojunction bipolar transistor.

  The heterojunction bipolar transistor includes a collector layer 102 formed on a substrate 101, a setback layer 103 formed on the collector layer 102, and a base layer 104 formed on the setback layer 103. And an emitter layer 105 formed on the base layer 104.

  The substrate 101 may be made of, for example, any of SiC, Si, and GaN. The collector layer 102 is made of GaN or SiC. The collector layer 102 may be made of, for example, GaN (n-GaN) doped with n-type impurities.

  The setback layer 103 is made of a group III-V compound semiconductor different from the base layer 104. Further, the setback layer 103 is made to have a band gap energy between the collector layer 102 and the base layer 104. The setback layer 103 may be made of, for example, InP (n-InP) or InAlAs (n-InAlAs) doped with an n-type impurity.

The base layer 104 is made of a group III-V compound semiconductor containing Ga, As, and Sb. The base layer 104 may be made of, for example, GaAsSb (p ⁺ -GaAsSb) or InGaAsSb (p ⁺ -InGaAsSb) heavily doped with a p-type impurity. The emitter layer 105 is made of a group III-V compound semiconductor different from the base layer 104. The emitter layer 105 may be made of, for example, InP (n-InP) doped with an n-type impurity.

The heterojunction bipolar transistor also includes a collector electrode 111 electrically connected to the collector layer 102. In the embodiment, the subcollector layer 107 is formed on the substrate 101 via the buffer layer 106, and the collector layer 102 is formed on the subcollector layer 107. The buffer layer 106 is made of, for example, AlN, and the subcollector layer 107 is made of, for example, GaN (n ⁺ -GaN) heavily doped with n-type impurities. Further, collector layer 102 is formed in a mesa having a smaller area than subcollector layer 107, and collector electrode 111 is formed on and in contact with subcollector layer 107 around the mesa. The collector electrode 111 may be made of, for example, a metal material such as W, Mo, Au, Ti, or Pt.

  The heterojunction bipolar transistor also includes a base electrode 112 electrically connected to the base layer 104. The base layer 104 (setback layer 103) is formed in a mesa having the same area as the collector layer 102, and the emitter layer 105 is a mesa (emitter mesa) smaller than the base layer 104. A base electrode 112 is formed on and in contact with the base layer 104 around the emitter mesa. The base electrode 112 may be made of, for example, a metal material such as W, Mo, Au, Ti, or Pt.

The heterojunction bipolar transistor also includes an emitter electrode 113 electrically connected to the emitter layer 105. An emitter contact layer 108 made of, for example, InGaAs (n ⁺ -InGaAs) heavily doped with n-type impurities is formed on the emitter layer 105. Emitter electrode 113 is formed on and in contact with emitter contact layer 108. The emitter electrode 113 may be made of, for example, a metal material such as W, Mo, Au, Ti, or Pt.

In the embodiment, the protective layer 121 covering the side surfaces of the emitter layer 105 and the emitter contact layer 108 is provided. The protective layer 121 may be made of, for example, silicon nitride (SiN _x ). The base electrode 112 is disposed around the protective layer 121.

  According to the heterojunction bipolar transistor in the embodiment, since the setback layer 103 is provided, it is possible to suppress the deterioration of the characteristics due to the quality deterioration of the interface due to bonding and the deterioration of the characteristics due to the band gap energy difference. .

  First, also in the embodiment, since the setback layer 103 is provided, the bonding junction between the setback layer 103 and the collector layer 102 is separated from the base layer 104.

  In the technique of Non-Patent Document 2, a decrease in current gain due to the deterioration of the crystal quality of the GaAs base layer accompanying high temperature heat treatment at the time of bonding has been reported. According to this report, in the GaAs base / GaN collector structure, the current gain is reduced to a half or less under the heat treatment condition of 550 ° C. or more at the time of bonding.

  In GaAs-based HBTs, it is suggested that heat treatment at 450 ° C or less does not cause degradation of device characteristics, but in InP DHBTs, the upper limit of the process temperature generally accepted for the DHBT manufacturing process is generally Because it is even lower than GaAs and GaN, bonding techniques at lower temperatures are required.

  However, when bonding a device at a low temperature, in general, a decrease in bonding strength is likely to be caused, and limitations such as recovery of crystal quality due to heat treatment occur, so it is easy to obtain a desired crystal quality is not.

  As described above, the junction surface tends to have a high crystal defect density, but since the layer with low crystal quality at such junction interface is separated from the base layer 104 by providing the setback layer 103, the device characteristic deterioration can be suppressed. . This effect is obtained as the setback layer 103 is thicker. On the other hand, since the setback layer 103 is made of a group III-V compound semiconductor whose band gap energy is larger than that of the base layer 104 unlike the base layer 104, the withstand voltage decreases with the increase in the thickness of the setback layer 103. Can reduce the effects of

  Next, it will be described that the collector layer 102 is made of GaN or SiC. Generally, if the collector layer is made of a wide gap material than that of InP, a withstand voltage higher than that of the conventional InP HBT can be realized. Such materials include GaN, AlN, SiC, ZnSe, GaAs, diamond and the like. Among these materials, collector materials that can exhibit higher effects are SiC and GaN.

Here, attention is focused on the energy at the conduction band edge. It is desirable for the collector layer to be a material whose conduction band edge energy is as low as possible compared to the base layer. In Non-Patent Document 3, the conduction band edge energy and the valence band edge energy of each material system are compared, but according to this report, AlN has a larger band gap than GaN, so Energy is also high. Therefore, when the collector layer is made of AlN, the conduction band edge energy becomes very high with respect to the base layer made of GaAsSb. As a result, f _T degradation is likely to occur due to an increase in charging time. Therefore, it is not desirable to construct the collector layer from AlN.

  Next, by using a ternary or higher mixed crystal material, the conduction band edge energy of the collector layer can be reduced. For example, by forming the collector layer from InGaN or InAlN in which an appropriate In composition is selected, the conduction band edge energy can be lower than that of GaN and the band gap can be larger than that of InP. However, it is known that the thermal conductivity of the ternary mixed crystal or higher nitride semiconductor is significantly reduced as compared with the binary mixed crystal material to cause the reduction of the heat dissipation. In a heterojunction bipolar transistor, the decrease in heat dissipation causes a decrease in reliability and device characteristics due to the increase in device temperature, so it is desirable that the collector layer be made of a binary mixed crystal or a single element material.

  From the above point of view, SiC, GaN and GaAs can be mentioned as candidate materials for the collector layer of the heterojunction bipolar transistor in the embodiment, and among them, SiC and GaN have a larger band gap and high heat dissipation and insulation. It is an optimal collector layer material from the viewpoint of having a breakdown field.

  Next, it will be described that the base layer 104 is formed of a III-V group compound semiconductor containing Ga, As, and Sb. The valence band edge energy of the group III-V compound semiconductor is largely affected by the group V material, and the higher the Sb composition, the higher the valence band edge energy tends to be. Although the conduction band edge energy of various materials is compared in Non-patent Document 3, InGaAs, which is a mixed crystal of InAs and GaAs, has a conduction band edge energy compared to GaAsSb, which is a mixed crystal of GaAs and GaSb. Tend to be higher.

  FIG. 2B shows a band diagram of a DHBT in which the base layer 302 made of InGaAs is in direct contact with the collector layer 301 made of GaN. InGaAs is generally used widely in the base layer of InP-based DHBT, but as shown in (b) of FIG. 2, the conduction band energy difference between the base layer 302 and the collector layer 301 becomes extremely large, and the emitter It is a big barrier for electrons traveling from the side to the collector side.

  If the base layer 104 made of InGaAsSb is provided on the collector layer 102 made of GaN via the setback layer 103 made of InP in the configuration described above, as shown in (a) of FIG. Becomes smaller and the conduction band energy difference becomes smaller. As a result, the problems as described above are suppressed and high current gain can be obtained. Also, in this configuration, the conduction band edge energy of the base layer 104 can be higher than that of the setback layer 103, and no conduction band offset occurs between them, and the cutoff frequency is not impaired.

  Next, the material which comprises the board | substrate 101 is demonstrated. It is possible to grow a GaN-based material on the substrate 101 made of SiC, and this point has been widely reported. By forming the substrate 101 from a substrate material having such a high thermal conductivity, the heat dissipation is improved more than in the case of using the InP substrate, the device temperature is reduced, and the device life can be improved and the characteristics can be improved. . When the collector layer 102 is made of SiC, the substrate material and the collector material are the same, so that high crystal quality can be easily obtained in the collector layer.

  In addition, although it is inferior in heat dissipation, it is also possible to constitute substrate 101 from materials other than SiC. For example, the substrate 101 may be made of GaN, which has lower thermal conductivity than SiC, but when the collector layer 102 is made of GaN, both are the same material, and the collector layer 102 is formed by homoepitaxial growth. It is possible to form and to obtain high crystal quality. When the collector layer 102 is made of GaN, the substrate 101 can also be made of Si or sapphire. Although these materials are inferior to SiC in terms of heat dissipation, they are substrate materials that can be obtained at low cost in terms of cost, and these substrates are applied as long as the heat dissipation does not pose a problem in device characteristics. It is also possible.

  Next, a method of manufacturing the heterojunction bipolar transistor according to the embodiment of the present invention will be described with reference to FIGS. 3A to 3H. 3A to 3H are cross-sectional views showing a state in each process for illustrating the method of manufacturing the heterojunction bipolar transistor according to the embodiment of the present invention.

  First, as shown in FIG. 3A, an emitter formation layer 205, a base formation layer 204, and a setback formation layer 203 made of a III-V compound semiconductor are sequentially formed on a growth substrate 211 (first step).

More specifically, first, a buffer layer 212 made of InP, a first etching stop layer 213 made of InGaAs, and a second etching stop made of InP on a growth substrate 211 made of, for example, InP, which is a III-V compound semiconductor. Layer 214, an emitter contact formation layer 208 made of n ⁺ -InGaAs, an emitter formation layer 205 made of n-InP, a base formation layer 204 made of p ⁺ -InGaAsSb, and a setback formation layer 203 made of n-InP sequentially Form. These may be formed by epitaxial growth by a well-known metal organic chemical vapor deposition method or molecular beam epitaxy method.

  Next, as shown in FIG. 3B, the collector formation layer 202 is formed on the substrate 101 made of SiC (second step). More specifically, a buffer formation layer 206 made of AlN, a subcollector formation layer 207 made of GaN, and a collector formation layer 202 made of n-GaN are sequentially formed on the substrate 101. These may also be formed by epitaxial growth by well-known metalorganic vapor phase epitaxy or molecular beam epitaxy.

  Next, as shown in FIG. 3C, the setback formation layer 203 and the collector formation layer 202 are pasted together, and the collector formation layer 202, the setback formation layer 203, the base formation layer 204, and the emitter formation layer 205 are formed on the substrate 101. Are stacked in this order (third step). Bonding may be performed using a well-known wafer bonding technique. For example, the bonding can be performed under relatively low temperature conditions by a known bonding (bonding) technique such as an atomic diffusion bonding method or a surface activation bonding method.

  In this example, the buffer formation layer 206, the subcollector formation layer 207, the collector formation layer 202, the setback formation layer 203, the base formation layer 204, the emitter formation layer 205, the emitter contact formation layer 208, the second on the substrate 101. The etching stop layer 214, the first etching stop layer 213, and the buffer layer 212 are stacked in this order.

  Next, after the setback formation layer 203 and the collector formation layer 202 are bonded to each other, the growth substrate 211 is removed (fourth step). For example, the growth substrate 211 may be removed by a selective etching technique using an etchant such as phosphoric acid, hydrochloric acid, sulfuric acid, or hydrogen peroxide solution.

  In the embodiment, first, the growth substrate 211 made of InP and the buffer layer 212 made of InP are etched away using hydrochloric acid or an etchant (hydrochloric acid based etchant) in which hydrochloric acid and phosphoric acid are mixed. In the process using a hydrochloric acid-based etchant, etching is stopped at the first etching stop layer 213 because InGaAs is hardly etched.

  Next, the first etching stop layer 213 made of InGaAs is etched away using an etchant (sulfuric acid based etchant) mixed with sulfuric acid and hydrogen peroxide. In the process using the sulfuric acid-based etchant, the etching is stopped at the second etching stop layer 214 because InP is hardly etched. After this, the second etching stop layer 214 is etched away using a hydrochloric acid based etchant. In the process using a hydrochloric acid-based etchant, the etching is stopped when the upper surface of the emitter contact formation layer 208 is exposed because little InGaAs is etched.

  By removing the growth substrate 211, the buffer layer 212, the first etching stop layer 213, and the second etching stop layer 214 by the selective wet etching technique described above, as shown in FIG. 3D, a buffer is formed on the substrate 101. The layer 206, the subcollector formation layer 207, the collector formation layer 202, the setback formation layer 203, the base formation layer 204, the emitter formation layer 205, and the emitter contact formation layer 208 are stacked in this order.

  After the growth substrate 211 is removed as described above, the emitter formation layer 205, the base formation layer 204, the setback formation layer 203, and the collector formation layer 202 are patterned as described later, and the collector formed on the substrate 101 is formed. A layer 102, a setback layer 103 formed on the collector layer 102, a base layer 104 formed on the setback layer 103, and an emitter layer 105 formed on the base layer 104 are formed. (Step 5). Further, the collector electrode 111 connected to the collector layer 102, the base electrode 112 connected to the base layer 104, and the emitter electrode 113 connected to the emitter layer 105 are formed (sixth step).

  First, as shown in FIG. 3E, the emitter electrode 113 is formed on the emitter contact formation layer 208. For example, first, a resist pattern in which an electrode formation region is opened is formed by a known photolithography technique. Next, Mo is deposited on the formed resist pattern by a known electron beam evaporation method to form a Mo layer, and then W is deposited by a known sputtering method to form a W layer. Next, the previously formed resist pattern is removed (lifted off). Thereby, the metal layer other than the electrode formation region is removed together with the resist pattern, and the emitter electrode 113 in which the Mo layer and the W layer are laminated is formed in the electrode formation region.

  Next, the formed emitter electrode 113 is used as a mask pattern to etch and pattern the emitter contact formation layer 208 and the emitter formation layer 205, thereby forming the emitter layer 105 and the emitter contact layer 108 as shown in FIG. 3F. For example, the emitter contact layer 108 is formed by etching the emitter contact formation layer 208 by wet etching using a sulfuric acid-based etchant. Next, the emitter formation layer 205 is etched by wet etching using a hydrochloric acid based etchant to form the emitter layer 105.

  Next, as shown in FIG. 3G, the protective layer 121 is formed, and the base electrode 112 is formed. Here, the protective layer 121 is formed so as to fill the upper surface of the base formation layer 204 in the region between the base electrode 112 and the formation region of the emitter electrode 113 (emitter layer 105, emitter contact layer).

  For example, after depositing silicon nitride by a sputtering method or the like, the protective layer 121 may be formed by etching a deposited film using a resist pattern formed by photolithography as a mask.

  Next, a resist pattern in which the electrode formation region is opened is formed by a known photolithography technique. Next, Pt is deposited on the formed resist pattern by sputtering or evaporation to form a Pt layer, then Ti is deposited to form a Ti layer, and Pt is deposited to form a Pt layer. And then deposit Au to form an Au layer. Next, the previously formed resist pattern is removed (lifted off). Thereby, each metal layer other than the electrode formation region is removed together with the resist pattern, and the base electrode 112 made of Pt / Ti / Pt / Au is formed in the electrode formation region.

  Next, the base formation layer 204, the setback formation layer 203, and the collector formation layer 202 are etched (patterned) using the emitter electrode 113 (emitter layer 105, emitter contact layer), base electrode 112, and protective layer 121 as masks. As shown in FIG. 3H, the collector layer 102, the setback layer 103, and the base layer 104 are formed. Here, dry etching may be used to pattern the collector layer 102 made of GaN.

  Next, the collector electrode 111 is formed, and the subcollector layer 107 (buffer layer 106) is formed. First, the collector electrode 111 is formed on the subcollector formation layer 207 by the same method as the base electrode 112. Then, the subcollector formation layer 207 and the buffer formation layer 206 are patterned to form the subcollector layer 107 and the buffer layer 106. By the above, the heterojunction bipolar transistor in the embodiment can be obtained.

  As described above, in the present invention, the base layer is composed of a Group III-V compound semiconductor containing Ga, As, and Sb, and the setback layer is composed of a Group III-V compound semiconductor different from the base layer. And the band gap energy between the collector layer and the base layer. As a result, according to the present invention, in the heterojunction bipolar transistor in which the collector layer is formed of the wide gap material by providing and bonding the setback layer, the characteristics due to the band gap energy difference between the collector layer and the base layer are obtained. Deterioration can be suppressed.

  The present invention is not limited to the embodiments described above, and many modifications and combinations can be made by those skilled in the art within the technical concept of the present invention. It is clear.

  DESCRIPTION OF SYMBOLS 101 ... Substrate, 102 ... Collector layer, 103 ... Setback layer, 104 ... Base layer, 105 ... Emitter layer, 106 ... Buffer layer, 107 ... Subcollector layer, 108 ... Emitter contact layer, 111 ... Collector electrode, 112 ... Base Electrode, 113 ... emitter electrode, 121 ... protective layer.

Claims (3)

Emitter-forming layer of III-V compound semiconductor, base-forming layer of III-V compound semiconductor including Ga, As, Sb, and III-V compound semiconductor on a growth substrate of III-V compound semiconductor A first step of sequentially forming a setback formation layer made of a semiconductor;
A second step of forming a collector formation layer of GaN or SiC on the substrate;
The setback formation layer and the collector formation layer are bonded to each other, and the collector formation layer, the setback formation layer, the base formation layer, and the collector formation layer are stacked in this order on the substrate. The third step,
A fourth step of removing the growth substrate after bonding the setback formation layer and the collector formation layer;
After the growth substrate is removed, the emitter formation layer, the base formation layer, the setback formation layer, and the collector formation layer are patterned to form a collector layer formed on the substrate, and the collector layer. Forming a set back layer, a base layer formed on the set back layer, and an emitter layer formed on the base layer;
A sixth step of forming a collector electrode connected to the collector layer, a base electrode connected to the base layer, and an emitter electrode connected to the emitter layer;
The setback layer is made of a group III-V compound semiconductor different from the base layer, and has a band gap energy between the collector layer and the base layer. Manufacturing method. In the method of manufacturing a heterojunction bipolar transistor according to claim 1 ,
The method of manufacturing a heterojunction bipolar transistor, wherein the set back layer is made of InP or InAlAs. In the method of manufacturing a heterojunction bipolar transistor according to claim 1 or 2 ,
A method of manufacturing a heterojunction bipolar transistor, wherein the substrate is made of any one of SiC, Si and GaN.

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