JP6348451B2 - Heterojunction bipolar transistor - Google Patents

Description

  The present invention relates to a heterojunction bipolar transistor including a collector layer made of InP.

  A heterojunction bipolar transistor (HBT) using an indium phosphide (InP) based semiconductor is a transistor excellent in high speed utilizing the high electron mobility and high electron saturation speed of an InP based material. In order to further increase the speed of the InP-based HBT having such characteristics, it is effective to shorten the charge / discharge time of the element internal capacitance by increasing the injection current of the HBT.

  On the other hand, increasing the injection current means increasing the power consumption of the HBT, and as a result, the temperature inside the HBT rises. As a result, there is a concern that the long-term reliability of the HBT may be reduced. Therefore, in order to increase the speed of the InP-based HBT, it is important to increase the amount of injected current and at the same time improve the heat dissipation of the HBT.

  In order to solve the above problem, a method of manufacturing an InP-based HBT on a heat dissipation substrate having a higher thermal conductivity than InP has been proposed (see Non-Patent Document 1). Hereinafter, this HBT will be described.

  As shown in FIG. 4, the HBT includes a heat dissipation substrate 301 and a first metal layer 302, a second metal layer 303, a third metal layer 304, and a fourth metal layer 305 formed on the heat dissipation substrate 301. Collector electrode 313, collector layer 306 made of a compound semiconductor formed on collector electrode 313, base layer 307 formed on collector layer 306, and emitter layer 308 formed on base layer 307. With. A cap layer 309 is formed on the emitter layer 308.

  An emitter electrode 311 is formed on the cap layer 309, and a base electrode 312 is formed on the base layer 307 around the emitter layer 308.

  Next, a method for manufacturing the HBT will be briefly described. First, a cap forming layer, an emitter forming layer, a base forming layer, and a collector forming layer made of a compound semiconductor are epitaxially grown in this order on an InP substrate serving as a growth substrate. For example, it may be grown by metal organic chemical vapor deposition (MOCVD). Next, a third metal layer and a fourth metal layer are formed on the collector formation layer.

  On the other hand, apart from the growth substrate, a heat dissipation substrate having a higher thermal conductivity than InP is prepared, and a first metal layer and a second metal layer are formed on the heat dissipation substrate. The heat dissipation substrate and the above-described growth substrate are bonded via the second metal layer and the third metal layer. Thereafter, the growth substrate that is no longer needed is removed, and then an emitter electrode is formed, a cap layer and an emitter layer are formed, a base electrode is formed, a base layer and a collector layer are formed, and a collector is formed from each metal layer. By forming the electrode, an HBT whose cross section is shown in FIG. 4 is obtained.

  The first metal layer is provided in order to improve the adhesion between the heat dissipation substrate and the second metal layer. The fourth metal layer is provided in order to improve the adhesion between the collector layer and the third metal layer. In the above HBT structure, the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer used as the adhesive layer when the substrates are bonded together function as the collector electrode as it is.

  According to the technique described above, the HBT element part is formed on the InP substrate because the collector electrode and the heat dissipation substrate having higher thermal conductivity than the compound semiconductor constituting the element part are formed immediately below the HBT element part. The heat dissipation is improved compared to the case where it is. In addition, since the HBT element formation layer made of a compound semiconductor is formed on the lattice-matched InP growth substrate, the crystallinity of the HBT element portion is not impaired.

  However, in the above-described HBT structure in Non-Patent Document 1, if the collector layer structure is not properly designed, the collector contact resistance may increase and the high-frequency characteristics may be deteriorated. The reason for this will be described below.

  As shown in FIG. 5, in a general HBT structure formed on an InP substrate that does not use a heat dissipation substrate, a collector electrode is provided in a subcollector layer made of a compound semiconductor doped with impurities at a high concentration. ing. In this HBT structure, since the area of the collector electrode can be designed larger than the area of the collector layer, the collector contact resistance is so small that the influence on the high frequency characteristics can be ignored.

  On the other hand, in the HBT structure in Non-Patent Document 1, the contact area between the collector layer and the collector electrode is limited to the area of the collector layer, so that the collector contact resistance may increase. In order to avoid this, it is effective to use a Schottky contact between the collector layer and the collector electrode. As an example, FIG. 6 shows a band diagram of an HBT having a base layer made of GaAsSb and a collector layer made of InP.

  As shown in FIG. 6A, the structure in which the collector electrode is in ohmic contact can be obtained by providing a region doped with impurities at a high concentration in the collector layer in contact with the collector electrode. In this case, since a spike-like potential barrier is formed on the conduction band side at the interface between the collector electrode and the collector layer, a finite collector contact resistance is generated.

  On the other hand, as shown in FIG. 6B, the Schottky contact can be obtained by not doping any impurities to the collector layer in contact with the collector electrode. In this configuration, the energy barrier as described above is not formed, and generation of collector contact resistance can be avoided in principle. Therefore, in the HBT structure in Non-Patent Document 1, it is desirable to adopt a configuration in which the collector electrode is Schottky connected to the collector layer.

  However, in the HBT structure in which the collector electrode is formed between the heat dissipation substrate and the InP collector layer, the inventors use Ti, which provides high adhesion to the InP collector layer, as a collector electrode layer in contact with the collector layer. It has been found that there is a problem in forming the InP collector layer when trying to realize key contact. Hereinafter, the above problem will be described with reference to FIG. FIG. 7 is a cross-sectional view schematically showing a state manufactured when the fourth metal layer 305 of the HBT described with reference to FIG. 4 is made of Ti.

  In this HBT, each compound semiconductor layer is formed on the metal laminated structure to be the collector electrode 313 using the substrate bonding technique described above, and then the emitter electrode 311 is formed, and the mesa of the emitter layer 308 and the cap layer 309 is formed. After the base electrode 312 is formed, mesas of the base layer 307 and the collector layer 306a are formed by wet etching.

  In the etching process for forming the collector layer 306a composed of InP, it is important that the base layer material containing As such as InGaAs or GaAsSb generally used in InP-based HBT is not etched. An etchant is used. It has been clarified by experiments by the inventors that the side wall of the collector layer 306a becomes a distorted shape with severe irregularities by the treatment using the hydrochloric acid-based etchant.

  This phenomenon is caused by the fact that Ti of the fourth metal layer 305 diffuses into the collector layer 306a composed of InP by the heat treatment in the HBT formation step, and the resulting mixed crystal layer of InP and Ti becomes a hydrochloric acid-based etchant. This is considered to inhibit etching using silicon.

  Also, when other metals such as Ni, Cr, and Pt that can be expected to have good adhesion with InP are used for the collector electrode layer in contact with the collector layer made of InP, the heat treatment (up to 400 ° C.) in the HBT formation process Non-Patent Document 2 reports that it diffuses into InP.

  From the above, when a metal that has good adhesion to the InP collector layer is used for the collector electrode in contact with the collector layer, the metal used for the collector electrode diffuses into the InP collector, and a collector layer with a good shape is obtained. There is a concern that it will not be possible.

A. Thiam et al., "InP HBT Thermal Management by Transferring to High Thermal Conductivity Silicon Substrate", IEEE Electron Device Letters, vol.35, no.10, pp.1010-1012, 2014. L. Persson et al., "Interfacial reaction studies of Cr, Ni, Ti, and Pt metallization on InP", J. Appl. Phys., Vol.80, no.6, pp.3346-3354, 1996.

  As described above, in the HBT structure in which the collector electrode is inserted between the collector layer and the substrate, the collector electrode in contact with the collector layer made of InP is used as a metal typified by Ti that can obtain good adhesion with InP. When this is used, there arises a problem that a good collector shape cannot be obtained due to the diffusion of the metal into the collector layer. Such an abnormal collector shape can be a major obstacle when a device is miniaturized in order to improve high-frequency characteristics.

  The present invention has been made to solve the above-described problems, and it is an object of the present invention to form a good collector shape even when a metal capable of obtaining good adhesion is used for a collector electrode. And

The heterojunction bipolar transistor according to the present invention includes a heat dissipation substrate having a higher thermal conductivity than InP, and a III-V group compound semiconductor in which a group V element is only As, and is formed on the heat dissipation substrate. A first collector layer, a second collector layer made of InP and formed on the first collector layer, a base layer made of a III-V compound semiconductor and formed on the second collector layer; An emitter layer made of a group III-V compound semiconductor different from the base layer and formed on the base layer, an emitter electrode formed connected to the emitter layer, and a base formed connected to the base layer comprising an electrode and a heat radiation substrate and the collector electrode formed in contact with the first collector layer is disposed between the first collector layer, the first collector layer, the thickness is in the range of 1~30nm In addition no impurity is doped.

In the heterojunction bipolar transistor, the first collector layer may be made of InGaAs or InAlGaAs .

  In the heterojunction bipolar transistor, the group III-V compound semiconductor constituting the first collector layer has an energy band structure in which the lower end of the conduction band of the first collector layer is lower than the lower end of the conduction band of the second collector layer. It is preferable that the composition be in the same or lower range than the lower end of the conduction band of the two collector layers.

  In the heterojunction bipolar transistor, the region of the collector electrode that contacts the first collector layer may be made of Ti.

  As described above, according to the present invention, an excellent effect that a good collector shape can be formed can be obtained even if a metal capable of obtaining good adhesion is used for the collector electrode.

FIG. 1 is a configuration diagram showing a configuration of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2 is an energy band diagram showing a state of band gap energy in the HBT according to the embodiment of the present invention. FIG. 3A is a configuration diagram showing a state in each step for explaining a method of manufacturing an HBT in the embodiment of the present invention. FIG. 3B is a configuration diagram showing a state in each step for explaining the method of manufacturing the HBT in the embodiment of the present invention. FIG. 3C is a configuration diagram showing a state in each step for explaining the method of manufacturing the HBT in the embodiment of the present invention. FIG. 3D is a configuration diagram showing a state in each step for explaining the method of manufacturing the HBT in the embodiment of the present invention. FIG. 3E is a configuration diagram showing a state in each step for explaining the method of manufacturing the HBT in the embodiment of the present invention. FIG. 3F is a configuration diagram showing a state in each step for explaining the method of manufacturing the HBT in the embodiment of the present invention. FIG. 3G is a configuration diagram showing a state in each step for explaining the method of manufacturing the HBT in the embodiment of the present invention. FIG. 3H is a configuration diagram showing a state in each step for explaining a method of manufacturing the HBT in the embodiment of the present invention. FIG. 4 is a configuration diagram showing the configuration of the HBT shown in Non-Patent Document 1. FIG. 5 is a configuration diagram showing a configuration of a general HBT formed on an InP substrate. FIG. 6 is an energy band diagram showing the state of band gap energy of an HBT having a base layer made of GaAsSb and a collector layer made of InP. FIG. 7 is a cross-sectional view schematically showing a state manufactured when the fourth metal layer 305 of the HBT described with reference to FIG. 4 is made of Ti.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing a configuration of a heterojunction bipolar transistor (HBT) in an embodiment of the present invention. FIG. 1 schematically shows a cross section of the HBT.

  The HBT includes a heat dissipation substrate 101, a first collector layer 102 formed on the heat dissipation substrate 101, a second collector layer 103 formed on the first collector layer 102, and a second collector layer 103. A base layer 104 formed on the base layer 104 and an emitter layer 105 formed on the base layer 104. In addition, an emitter electrode 111 connected to the emitter layer 105 via the emitter cap layer 106 and a base electrode 112 connected to the base layer 104 are provided.

  In addition, the HBT includes a collector electrode 113 disposed between the heat dissipation substrate 101 and the first collector layer 102 and formed in contact with the first collector layer 102. The collector electrode 113 is made of metal.

  The emitter cap layer 106 and the emitter layer 105 have a first mesa structure, and the base layer 104, the second collector layer 103, and the first collector layer 102 have a second mesa structure having a larger area than the first mesa structure. Has been. A base electrode 112 is disposed on the base layer 104 around the emitter layer 105 having the first mesa structure.

  Each layer is composed of a so-called InP-based III-V group compound semiconductor, and the base layer 104 and the emitter layer are composed of different compound semiconductors. In particular, the first collector layer 102 is made of a III-V group compound semiconductor in which the group V element is only As. The second collector layer 103 is made of InP.

For example, the first collector layer 102 is made of undoped InGaAs or InAlGaAs. The second collector layer 103 is made of InP (n-InP) into which an n-type impurity such as Si is introduced. The base layer 104 is made of GaAsSb (p ⁺ -GaAsSb) into which a p-type impurity is introduced at a high concentration. The emitter layer 105 is composed of InP (n-InP) into which an n-type impurity is introduced. The emitter cap layer 106 is composed of an InGaAs (n ⁺ -InGaAs) layer into which an n-type impurity is introduced at a high concentration.

  The contact region 113 a of the collector electrode 113 that contacts the first collector layer 102 is made of a metal that can provide good adhesion to the first collector layer 102. An example of such a metal is Ti.

  In FIG. 1, one element is shown on the heat dissipation board 101. However, in the area (not shown) of the heat dissipation board 101, various other elements connected by a wiring layer (not shown) are formed. Is configured.

  According to the HBT described above, the first collector layer 102 serves as a diffusion barrier for the metal constituting the collector electrode 113 such as Ti, and the metal such as Ti used for the collector electrode 113 diffuses into the second collector layer 103. Can be suppressed. Therefore, a favorable shape can be obtained even in the formation of the second collector layer 103 using a hydrochloric acid-based etchant.

  The layer thickness of the first collector layer 102 is preferably as very thin as 1 to 30 nm. A material containing As, such as InGaAs, generally has a low thermal conductivity. However, by setting the layer thickness to at least 30 nm or less, the heat dissipation due to the insertion of the first collector layer 102 made of a material having a thermal conductivity lower than that of InP. Deterioration can be minimized. Further, if the thickness of the first collector layer 102 is set to 1 nm, it can function as an etch stop layer when forming the second collector layer 103, and the second collector layer 103 in which a metal such as Ti is made of InP. It effectively suppresses the diffusion to the surface.

  The first collector layer 102 may be composed of an undoped group III-V compound semiconductor. As a result, as shown in the energy band diagram of FIG. 2, a Schottky contact having no potential spike at the lower end of the conduction band of the first collector layer 102 in the vicinity of the collector electrode 113 is obtained.

  In addition, the composition of the first collector layer 102 is first compared to the lower end of the conduction band of the second collector layer 103 in the energy band structure at the interface between the first collector layer 102 and the second collector layer 103 shown in FIG. The composition may be such that the lower end of the conduction band of the collector layer 102 is the same or lower. With this configuration, since there is no barrier in the conduction band from the second collector layer 103 side to the first collector layer 102 side, the collector resistance due to the insertion of the first collector layer 102 increases. Absent.

  As described above, according to the HBT in the embodiment, the collector contact resistance can be reduced without impairing the shape of the second collector layer 103 made of InP.

  Next, the manufacturing method of HBT in embodiment of this invention is demonstrated using FIG. 3A-FIG. 3H. FIG. 3A to FIG. 3H are configuration diagrams showing states in respective steps for explaining a method of manufacturing an HBT in the embodiment of the present invention. 3A to 3H schematically show cross sections.

First, as shown in FIG. 3A, on the growth substrate 201 made of InP, each compound semiconductor layer constituting the InP-based HBT is epitaxially grown sequentially. For example, on the growth substrate 201, an emitter cap forming layer 202 made of n ⁺ -InGaAs doped with Si at about 2 × 10 ¹⁹ cm ⁻³ and n-InP doped with about 1 × 10 ¹⁷ cm ^{−3 of} Si. Emitter forming layer 203, base forming layer 204 made of p ⁺ -GaAsSb doped with about 1 × 10 ¹⁹ cm ^{−3 of} C, and second collector formed of n-InP layer doped with about 1 × 10 ¹⁷ cm ^{−3 of} Si A layer 205 and a first collector formation layer 206 made of undoped InGaAs are sequentially grown and formed. These may be formed by depositing, for example, using metal organic vapor phase deposition or molecular beam epitaxy.

  Since each compound semiconductor layer is epitaxially grown on the growth substrate 201 made of InP in a lattice-matched state, the compound semiconductor layer is formed in a high-quality state in which generation of dislocations and defects is suppressed.

  The first collector formation layer 206 may be made of InGaAs with an In composition of 53%. With this configuration, the first collector formation layer 205 is first in the interface between the second collector formation layer 205 (second collector layer 103) and the first collector formation layer 206 (first collector layer 102). The lower end of the conduction band of the collector forming layer 206 is about 200 meV lower. As a result, an energy barrier is not generated in the conduction band from the second collector layer 103 toward the first collector layer 102, so that collector resistance is generated between the first collector layer 102 and the second collector layer 103. There is no.

  Further, the thickness of the first collector formation layer 206 may be 1 to 30 nm, for example. Since InGaAs has a thermal conductivity of about 5 W / m / K, which is lower than InP's thermal conductivity of 68 W / m / K, there is a possibility of deteriorating the heat dissipation of the manufactured HBT. On the other hand, if the thickness of the first collector formation layer 206 serving as the first collector layer 102 is in the range of 1 to 30 nm, the heat dissipation is reduced while maintaining the function of the collector electrode 113 as a diffusion barrier, as will be described later. Can be minimized.

  Next, as shown in FIG. 3B, a first collector electrode formation layer 207 is formed on the first collector formation layer 206. For example, the first collector electrode formation layer 207 may be deposited using a vacuum deposition method or a sputtering method as a stacked structure of a Ti layer 207a and an Au layer 207b from the side in contact with the first collector formation layer 206. By using Ti, good adhesion between the first collector formation layer 206 and the first collector electrode formation layer 207 can be obtained.

  By setting it as the said structure, an HBT element part does not peel from a thermal radiation board | substrate with the heat | fever and mechanical stress which generate | occur | produce in the HBT formation process mentioned later. Further, since Au has a low Young's modulus and a high thermal conductivity, it can be easily joined to a heat dissipation substrate described later without impairing the heat dissipation of the HBT. Note that the layer in contact with the first collector formation layer 206 of the first collector electrode formation layer 207 may be made of Cr, Ni, or Pt, and good adhesion can be obtained as with Ti.

  On the other hand, as shown in FIG. 3C, the second collector electrode formation layer 221 is formed on the heat dissipation substrate 101 made of, for example, Si. As described above, a Ti layer and an Au layer may be sequentially deposited from the side in contact with the heat dissipation substrate 101 by vacuum vapor deposition, sputtering, or the like. Note that the material of the heat dissipation substrate 101 preferably has an insulating property equivalent to that of semi-insulating InP in order to have higher thermal conductivity than InP and to facilitate electrical separation between HBTs. . For example, the heat dissipation substrate 101 may be made of Si, AlN, GaN, SiC, and diamond.

  Next, as illustrated in FIG. 3D, the growth substrate 201 and the heat dissipation substrate 101 are bonded together by bonding the first collector electrode formation layer 207 and the second collector electrode formation layer 221. For example, the first collector electrode forming layer 207 and the second collector electrode forming layer 221 may be bonded using a wafer bonding technique such as a surface activated bonding method or an atomic diffusion bonding method. In the embodiment, the joining surfaces of the first collector electrode forming layer 207 and the second collector electrode forming layer 221 are both made of Au and can be easily joined. In any of the bonding methods, the bonding temperature can be set to a temperature equal to or lower than the maximum process temperature (400 ° C.) of InP-based HBT. For this reason, the crystallinity degradation of the element formation layer by the temperature load which arises at a joining process, and the curvature of the board | substrate resulting from the thermal expansion coefficient difference between a growth board | substrate and a thermal radiation board | substrate can be suppressed.

  Next, the growth substrate 201 is removed. For example, the growth substrate 201 is polished and thinned using a back grinder. Next, the remaining growth substrate 201 is removed by wet etching using a hydrochloric acid-based etching solution to expose the emitter cap forming layer 202. In this wet etching, the emitter cap forming layer 202 made of InGaAs is hardly etched, so that only the growth substrate 201 can be selectively removed.

  As a result, as shown in FIG. 3E, the second collector electrode formation layer 221 and the first collector electrode formation layer 207 are stacked on the heat dissipation substrate 101, and the first collector electrode formation layer 207 is A state is obtained in which the first collector formation layer 206, the second collector formation layer 205, the base formation layer 204, the emitter formation layer 203, and the emitter cap formation layer 202 are laminated.

  Next, the emitter electrode 111 is formed on the emitter formation layer 203, and then the emitter cap formation layer 202 and the emitter formation layer 203 are patterned, and as shown in FIG. A first mesa structure is formed.

  For example, a lift-off mask having an opening is formed in the emitter electrode 111 forming portion by a known photolithography technique, and an electrode material is deposited thereon by, for example, a vacuum evaporation method. Thereafter, if the lift-off mask is removed, the emitter electrode 111 can be formed (lift-off method).

  Further, the emitter cap layer 106 is formed by etching the emitter cap forming layer 202 with a citric acid etchant using the emitter electrode 111 as a mask pattern. Next, using the emitter electrode 111 as a mask pattern, the emitter forming layer 203 is etched using a hydrochloric acid-based etchant to form the emitter layer 105. Thereafter, similarly to the formation of the emitter electrode 111, the base electrode 112 is formed on the base formation layer 204 around the emitter layer 105 having the first mesa structure by a lift-off method.

  Next, by patterning the base formation layer 204 and the second collector formation layer 205, as shown in FIG. 3G, the base layer 104 and the second collector layer 103 having the second mesa structure having a larger area than the first mesa structure are formed. Form. The base layer 104 may be formed by etching the base formation layer 204 using a citric acid-based etchant, and the second collector layer 103 may be formed by etching the second collector formation layer 205 using a hydrochloric acid-based etchant.

  Since the hydrochloric acid etchant hardly etches InGaAs, the first collector formation layer 206 functions as an etching stopper, and the second collector layer 103 can be easily formed. In addition, since the first collector formation layer 206 made of InGaAs is disposed between the first collector electrode formation layer 207 and the diffusion of metal from the first collector electrode formation layer 207 is suppressed, a favorable sidewall is obtained. A second collector layer 103 having a shape can be formed.

  Next, the first collector formation layer 206 is patterned to form the first collector layer 102 as shown in FIG. 3H. For example, the first collector formation layer 206 may be etched using a citric acid-based etchant. Even if the metal constituting the first collector electrode forming layer 207 such as Ti diffuses into the first collector forming layer 206, the etching using the citric acid-based etchant does not cause unevenness and the like, and has a good sidewall shape. One collector layer 102 can be formed.

  After the element portion is formed as described above, the first collector electrode formation layer 207 and the second collector electrode formation layer 221 are patterned by a known lithography technique and dry etching technique, as shown in FIG. A collector electrode 113 is formed. By forming the collector electrode 113, the surrounding heat dissipation substrate 101 is exposed. Since the heat dissipating substrate 101 is made of an insulating material, by forming the metal laminated structure 120 as described above, each element portion that becomes the HBT is electrically separated.

  As described above, in the present invention, the first collector layer formed of the III-V group compound semiconductor in which the group V element is only As and formed on the heat dissipation substrate, and the InP is used. A collector is constituted by a second collector layer formed on one collector layer, and a collector electrode is provided between the heat dissipation substrate and the first collector layer in contact with the first collector layer. As a result, the diffusion of the metal constituting the collector electrode is suppressed in the first collector layer, and a good collector shape can be formed even if a metal capable of obtaining good adhesion is used for the collector electrode.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, in the above description, an npn-type InP / GaAsSb-based HBT that is promising for realizing an ultra-high-speed integrated circuit has been described in detail, but the same effect is also effective for other HBTs.

  DESCRIPTION OF SYMBOLS 101 ... Radiation substrate, 102 ... 1st collector layer, 103 ... 2nd collector layer, 104 ... Base layer, 105 ... Emitter layer, 106 ... Emitter cap layer, 111 ... Emitter electrode, 112 ... Base electrode, 113 ... Collector electrode, 113a ... contact area.

Claims (4)

A heat dissipation substrate having a higher thermal conductivity than InP;
A first collector layer made of a III-V compound semiconductor in which a group V element is only As and formed on the heat dissipation substrate;
A second collector layer made of InP and formed on the first collector layer;
A base layer made of a III-V compound semiconductor and formed on the second collector layer;
An emitter layer made of a III-V compound semiconductor different from the base layer and formed on the base layer;
An emitter electrode formed connected to the emitter layer;
A base electrode formed connected to the base layer;
A collector electrode disposed between the heat dissipation substrate and the first collector layer and formed in contact with the first collector layer ;
The heterojunction bipolar transistor, wherein the first collector layer has a thickness in a range of 1 to 30 nm and is not doped with impurities . The heterojunction bipolar transistor according to claim 1, wherein
The heterojunction bipolar transistor, wherein the first collector layer is made of InGaAs or InAlGaAs. The heterojunction bipolar transistor according to claim 1 or 2 ,
The group III-V compound semiconductor constituting the first collector layer has an energy band structure in which the lower end of the conduction band of the first collector layer is lower than the lower end of the conduction band of the second collector layer. A heterojunction bipolar transistor characterized in that it has a composition that is the same as or lower than the lower end of the conduction band. The heterojunction bipolar transistor according to any one of claims 1 to 3 ,
A region of the collector electrode that contacts the first collector layer is made of Ti.

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