Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
  • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
  • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
  • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
  • H02H7/122—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. DC/AC converters
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
  • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
  • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M1/00—Details of apparatus for conversion
  • H02M1/32—Means for protecting converters other than automatic disconnection
• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
  • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
  • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
  • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
  • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
  • H02M7/483—Converters with outputs that each can have more than two voltages levels
  • H02M7/487—Neutral point clamped inverters

Definitions

• Diode midpoint clamp type three-level inverter current limiting control method and related circuit The application is submitted to the Chinese Patent Office on September 19, 2012, the application number is 201210349131.1, and the invention name is "diode midpoint clamp type three The priority of the Chinese Patent Application for Level Inverter Current Limiting Control Method and Related Circuits, the entire contents of which are incorporated herein by reference.
• the present application relates to the field of inverter current limiting technology, and in particular to a diode midpoint clamp type three-level inverter current limiting control method and related circuits. Background technique
• the inverter is used to convert DC power into AC power.
• the circuit mainly includes an inverter bridge, a control logic circuit and a filter circuit.
• FIG. 1 a schematic diagram of a main circuit of a typical diode midpoint clamp type three-level inverter is shown, which mainly includes four switch tubes: a first switch tube Q1 and a second switch tube Q2. a three-switching tube Q3, a fourth switching tube Q4, and diodes D5, D6, and each of the switching tubes is anti-parallel with a diode at both ends, as shown in Figure 1, diodes D1, D2, D3, D4;
• the switch tube is controlled to be turned on and off by four driving signals, wherein the switch tubes Q1 and Q4 are on the outer side of the bridge arm, called the outer tube (the same below), and Q2 and Q3 are on the inner side of the bridge arm, called inner Tube (the same below).
• the first controller 1 generates two SPWMs with dead zones (Sinusoidal Pulse) Width Modulation, sine pulse width modulation) drive pulse, ie PWM1 and PWM2, and output voltage positive and negative half cycle enable signal EN, when EN is low, the output voltage of the three-level inverter is in positive half cycle; when EN is When the level is high, the output voltage is in the negative half cycle; the PWM1, PWM2 and EN are generated by the second controller 2 according to the three-level inverter logic to generate four driving pulses, which are respectively Q1PWM, Q2PWM, Q3PWM, Q4PWM, respectively driving the switching tube Ql, Q2, Q3, Q4.
• the basic control strategy is: the first controller 1 generates two SPWMs with dead zones (Sinusoidal Pulse) Width Modulation, sine pulse width modulation) drive pulse, ie PWM1 and PWM2, and output voltage positive and negative half cycle enable signal EN, when EN is low, the output voltage of the three-level inverter is
• the inverter current detecting circuit 3 detects the current flowing through the switch tube in real time, and sends the detected inverter current signal Iinv to the overcurrent generating circuit 4, and when the detected inverter current is greater than a current setting value,
• the flow generating circuit generates an overcurrent signal OC and supplies it to the second controller 2, and the second controller 2 blocks the driving pulses of all the switching tubes in the inverter 5, and turns off the switching tube; when the overcurrent disappears,
• the overcurrent generating circuit 4 outputs the overcurrent signal OC to be inverted, so that the second controller 2 generates a normal driving pulse to return the switching transistor in the inverter to a normal switching state.
• FIG. 3 a schematic diagram of a driving pulse waveform of a current limiting scheme in the prior art is shown.
• the overcurrent signal OC when the overcurrent signal OC is at a high level, the inverter current is greater than the current setting value, and the access limit is entered.
• the overcurrent signal OC when the overcurrent signal OC is at a low level, it indicates that the inverter current is smaller than the current set value and is in the current limit state.
• the overcurrent OC flips, enters the current limiting logic, and delays to t2.
• the outer tubes Q1 and Q4 are closed, and the delay is to t3.
• the overcurrent signal OC is turned over, and the inner tubes Q2 and Q3 are turned on at the same time, and the delay is to t5. If the output voltage is in the positive half cycle, Q3 is turned off. If the output voltage is in the negative half cycle, Q2 is turned off. Delay to t6 and restore the four-tube drive logic.
• the two inner switch tubes (hereinafter referred to as inner tubes) Q2 and Q3 are simultaneously switched from the off state to the on state.
• the outer switch tube (hereinafter referred to as the outer tube) Q1 or Q4 will be doubled.
• the sum of the bus voltage and the additional voltage generated by the parasitic parameters of the line can easily cause the voltage stress on the outer tube to be large and cause failure.
• the embodiment of the present application provides a diode midpoint clamp type three-level inverter current limiting control method and related circuit, so as to ensure that the voltage stress of the switching tube does not exceed the standard when the current limiting current occurs, the technical solution as follows:
• An aspect of the present application provides a diode midpoint clamp type three-level inverter current limiting method, the diode midpoint clamp type three-level inverter circuit comprising at least four switching tubes connected in series in sequence
• the bridge arm the method includes:
• one of the inner switch tubes is controlled to be turned off, and the other switch tube is normally turned on;
• All of the switching transistors are controlled to be turned on or off with the control timing of the diode midpoint clamp type three-level inverter circuit.
• Another aspect of the present application further provides a diode midpoint clamp type three-level inverter circuit, comprising at least: a bridge arm and a detection control circuit formed by four switch tubes connected in series;
• the detection control circuit includes: a first controller, a second controller, an inverter current collection circuit, and an overcurrent generation detection circuit, wherein:
• the inverter current collecting circuit is configured to collect current in the switch tube and provide the current detecting circuit to the overcurrent generating circuit;
• the overcurrent occurrence detecting circuit is configured to detect whether a current in the switch tube collected by the inverter current collecting circuit exceeds a current setting value, generate a corresponding overcurrent detecting signal, and provide the second current to the second Controller
• the first controller is configured to generate at least two sinusoidal pulse width adjustment pulse SPWM pulse signals with dead time;
• the second controller is configured to drive the bridge arm when receiving an overcurrent invalid signal that is greater than a current set value by a value greater than a current set value
• One of the inner switch tubes is turned on, and after the first delay time, the other switch tube of the inner switch tube is driven to be turned on; after the second delay time, the inner switch tube is controlled.
• One of the switches is turned off, the other switch is always on, and finally all of the switches are turned on or off at normal timing.
• the diode midpoint clamp type three-level inverter current limiting control method only first turns on one of the bridge arms when the overcurrent signal is effectively turned into invalid.
• the inner switch tube of the group after a certain period of time, turns on another set of inner switch tubes in the bridge arm, and finally, restores the normal drive timing pulses of all the switch tubes.
• FIG. 1 is a schematic diagram of a main circuit of a typical diode midpoint clamp type three-level inverter in the prior art
• FIG. 2 is a schematic diagram of a control logic circuit of the circuit shown in FIG. 1;
• FIG. 3 is a schematic diagram of a drive pulse waveform of a current limiting mode corresponding to the circuit shown in FIG. 1 in the prior art;
• 4a is a schematic diagram showing voltage waveforms of driving pulses of each switching tube when a diode midpoint clamp type three-level inverter is out of current limiting according to an embodiment of the present application;
• FIG. 4b is a schematic diagram showing voltage waveforms of driving pulses of respective switching tubes when the diode midpoint clamp type three-level inverter is out of current limiting according to an embodiment of the present application;
• 5a is a schematic diagram of driving pulse waveforms of each switching tube when a diode midpoint clamp type three-level inverter is out of current limiting control according to an embodiment of the present application;
• FIG. 5b is a schematic diagram showing a driving pulse waveform of each of the switching transistors when the diode midpoint clamp type three-level inverter is out of current limiting control;
• FIG. 5c is a schematic diagram showing a driving pulse waveform of each of the switching tubes when the diode midpoint clamp type three-level inverter is out of current limiting control;
• FIG. 5d is a schematic diagram showing a driving pulse waveform of each switching tube when the diode midpoint clamp type three-level inverter is out of current limiting control
• FIG. 6a is a schematic diagram showing a driving pulse waveform of each switching tube when the diode midpoint clamp type three-level inverter is out of current limiting control
• FIG. 6b is a schematic diagram showing another driving pulse waveform of each switching tube when the diode midpoint clamp type three-level inverter is out of current limiting control;
• FIG. 6c is a schematic diagram showing another driving pulse waveform of each switching tube when the diode midpoint clamp type three-level inverter is out of current limiting control;
• Figure 6d is a schematic diagram showing another driving pulse waveform of each switching tube when the diode midpoint clamp type three-level inverter is out of current limiting control;
• FIG. 7a is a schematic diagram showing a driving pulse waveform of each switching tube when the diode midpoint clamp type three-level inverter is out of current limiting control;
• FIG. 7b is a schematic diagram showing another driving pulse waveform of each switching tube when the diode midpoint clamp type three-level inverter is out of current limiting control;
• FIG. 7c is a schematic diagram showing another driving pulse waveform of each switching tube when the diode midpoint clamp type three-level inverter is out of current limiting control;
• FIG. 7d is a schematic diagram showing another driving pulse waveform of each switching tube when the diode midpoint clamp type three-level inverter is out of current limiting control;
• FIG. 8 is a block diagram showing the structure of a diode midpoint clamp type three-level inverter circuit according to an embodiment of the present application.
• the diode midpoint clamp type three-level inverter circuit includes: The four switch tubes connected in series are the first switch tube Q1, the second switch tube Q2, the third switch tube Q3, and the fourth switch tube Q4.
• the bridge arm wherein the two inner tubes Q2 and Q3 form a series branch end with two diodes D5 and D6 connected in series, and each switch has an anti-parallel diode at both ends.
• the diode midpoint clamp type three-level inverter current limiting control method collects the current in the switch tube and determines the magnitude relationship between the current and the current set value in the collected switch tube. Thereby generating an overcurrent detection signal. Specifically, when the collected current in the switch tube is lower than the first current set value (ie, the current limit current value), an overcurrent invalid signal is generated, and the current limit control is performed. Logic, that is, when the overcurrent signal is turned from valid to inactive, only one inner tube of the bridge arm is turned on first. After a certain time, the other inner switch tube in the bridge arm is turned on. Finally, all the switches are restored. Drive timing pulses.
• the current method of the diode midpoint clamp type three-level inverter provided by the present application will be described in detail below by taking the main circuit of the diode midpoint clamp type three-level inverter shown in FIG. 1 as an example.
• FIG. 4a is a schematic diagram showing voltage waveforms of driving pulses of respective switching tubes when a diode midpoint clamp type three-level inverter is out of current limiting
• FIG. 4b shows another diode. Schematic diagram of voltage waveforms of driving pulses of each switching tube when the midpoint clamp type three-level inverter is out of current limiting;
• the positive and negative half cycle enable signals in this embodiment are the output voltage positive and negative half cycle enable signal EN.
• EN When the output voltage positive and negative half cycle enable signal EN is low level, the diode midpoint clamp type three level inverter is indicated. The output voltage is in the positive half cycle; when the output voltage is positive and negative half cycle enable signal EN is high, the table The output voltage of the bright-point diode clamp-type three-level inverter is in the negative half cycle.
• the overcurrent signal OC is at a high level, the current in the switch tube is not less than the current set value, which is a current limiting phase; when the overcurrent signal OC is at a low level, the current in the switch is less than the current set value, which is a non-current limiting phase.
• Q1PWM is the driving pulse of the first switching transistor Q1
• Q2PWM is the driving pulse of the second switching transistor Q2
• Q3PWM is the driving pulse of the third switching transistor Q3
• Q4PWM is the driving pulse of the
• the output voltage positive and negative half cycle enable signal EN is low level, that is, when the output voltage is in the positive half cycle, at this time, the second switching transistor Q2 needs to be always open, and the fourth switching transistor Q4 is normally closed, first
• the switch tube Q1 and the third switch tube Q3 are turned on in a complementary manner and ensure dead time.
• the overcurrent signal OC is switched from valid to inactive, that is, the overcurrent phenomenon disappears.
• the current limiting logic control is performed, and Q2PWM is switched from a low level to a high level to drive the second switching transistor Q2 to be turned on;
• Q3PWM changes from low level to high level, driving the third switch tube Q3 to turn on, delay to t3 time, Q3PWM turns from high level to low level to make the third switch tube Q3 turn off;
• Q3PWM changes from high level to low level.
• Q1PWM changes from low level to high level.
• the time difference between the driving pulses of Q1 and Q3 cannot meet the dead time between Q1 and Q3.
• the normal drive timing of the four switch tubes is restored after the time t4, that is, the drive pulse of the Q1 PWM in the period from t3 to t4 is cut off. close.
• the output voltage positive and negative half cycle enable signal EN is at a high level, that is, when the output voltage is in a negative half cycle, in this case, the first switch tube Q1 needs to be normally closed, and the third switch tube Q3 is normally turned on.
• the second switching transistor Q2 and the fourth switching transistor Q4 are turned on in a complementary manner and ensure dead time.
• the overcurrent signal OC is switched from valid to inactive, that is, the overcurrent phenomenon disappears.
• the current limiting logic control is performed, and the Q3PWM is switched from the low level to the high level to drive the third switching transistor Q3 to be turned on;
• the driving pulse Q2PWM of the second switching transistor Q2 is changed from a low level to a high level, driving the second switching transistor Q2 to be turned on, delaying to time t3, and Q2PWM is turned from a high level to a low level to make a second Switch tube Q2 is turned off,
• the timing at which Q2PWM transitions from a high level to a low level that is, at time t3, at which point Q4PWM transitions from the level to the high level, and between the turn-off time of Q2 and the turn-on time of Q4.
• the time difference cannot meet the dead time requirement between Q2 and Q4. Therefore, to ensure the dead time between the second switch Q2 and the fourth switch Q4, the delay is restored to t4 and the four switches are restored.
• the drive timing that is, the drive pulse of the Q4PWM in the period from t3 to t4 is cut off.
• the driving pulse Q1PWM of the first switching transistor Q1 is always at a low level, so that the fourth switching transistor Q4 is normally closed.
• the diode midpoint clamp type three-level inverter current limiting method provided by the embodiment, when the current limiting signal OC is effectively switched to inactive, only one set of the inner switch in the bridge arm is turned on first. Tube, after After a certain period of time, another set of inner switching tubes in the bridge arm is turned on, and finally, all the switching tubes are normally driven to output timing pulses. In this way, only one set of inner switch tubes is turned on, so that the outer switch tube and the unconducted inner tube share a double bus voltage, which reduces the voltage of the switch tube compared with the existing one switch tube with one double bus voltage.
• the stress ensures that the voltage stress of the switch tube does not exceed the standard when the current limit is discharged, thereby avoiding the phenomenon that the switch tube fails due to excessive voltage stress.
• pulse driving waveforms of the respective switching tubes in the case of various current limiting currents of the diode midpoint clamp type three-level inverter are respectively shown.
• the timing at which the Q3PWM changes from a high level to a low level that is, the dead time of the first switching transistor Q1 and the third switching transistor Q3 at time t3.
• the dead time of the first switching transistor Q1 and the third switching transistor Q3 can be ensured. Therefore, after the t3 time, the normal driving timing of the four switching transistors can be restored immediately to ensure the between Q1 and Q3. Dead time.
• the time when the Q3PWM changes from the high level to the low level that is, the time t3 is located in the conduction interval of the third switching transistor Q3, due to the normal pulse driving timing. Ensure that in this case, the normal drive timing of the four switches is restored immediately after t3 to ensure the dead time between Q1 and Q3.
• the time when the Q3PWM changes from the high level to the low level is also the turn-on time of the first switch Q1, that is, the turn-off time of the Q3. It coincides with the on-time of Q1.
• the time difference between the turn-off time of Q3 and the turn-on time of Q1 cannot guarantee the dead time between Q1 and Q3. Therefore, it is necessary to delay until t4 to recover four.
• the normal driving timing of the switching transistor is to cut off the pulse width of the Q 1 PWM in the period from t3 to t4, thereby ensuring the dead time between Q 1 and Q3.
• FIG. 6 is a schematic diagram showing a driving pulse waveform of each switching tube when the diode midpoint clamp type three-level inverter is out of current limiting control.
• the output voltage positive and negative half cycle enable signal EN is low, and the output current positive and negative half cycle enable signal ENI is also low, indicating that the output voltage is in the positive half cycle, and the output current is also in the positive half cycle. That is, the output current is in phase with the output voltage.
• the overcurrent signal OC is switched from valid to inactive, that is, the overcurrent phenomenon disappears.
• the current limiting logic control is performed, and Q2PWM is switched from a low level to a high level to drive the second switching transistor Q2 to be turned on;
• Q3PWM changes from low level to high level, driving the third switch tube Q3 to turn on, delay to t3 time, Q3PWM turns from high level to low level to make the third switch tube Q3 turn off;
• the path of the output current flowing through the main circuit of the diode midpoint clamp type three-level inverter shown in FIG. 1 is: LCN line-D5-Q2-L, at this time, the output point The potential at point B is clamped to the N-line potential, and Q3 and Q4 together withstand the negative bus-BUS voltage, which reduces the voltage stress on the switching tube compared to the existing current limiting method.
• the output voltage positive and negative half cycle enable signal EN is high, and the output current positive and negative half cycle enable signal ENI is also high, indicating that the output voltage is in the negative half cycle, and the output current is also in the negative half cycle. That is, the output current is in phase with the output voltage.
• the overcurrent signal oc is effectively switched to inactive, that is, the overcurrent phenomenon disappears.
• the current limiting logic control is performed, and the Q3PWM is switched from the low level to the high level to drive the third switching transistor Q3 to be turned on;
• Q2PWM changes from low level to high level, driving the second switch tube Q2 to be turned on, delaying to time t3, Q2PWM turning from high level to low level to turn off the second switch tube Q2;
• the time t3 that is, the turn-off time of Q2
• the time difference between the turn-off time of Q2 and the turn-on time of Q4 cannot satisfy the dead time requirement between Q2 and Q4, so the delay is At the time of t4, the normal driving pulse timing of the four switching tubes is restored, that is, the driving pulse of the Q4PWM in the period from t3 to t4 is cut off to ensure the dead time between Q2 and Q4.
• the path of the output current flowing through the main circuit of the diode midpoint clamp type three-level inverter shown in FIG. 1 is: N line-CL-Q3-D6-N line, at this time
• the potential at point B of the output point is clamped to the N-line potential.
• Q1 and Q2 together withstand the voltage of the positive bus +BUS, which reduces the voltage stress of the switching tube compared with the existing current limiting method.
• the output voltage positive and negative half cycle enable signal EN is low, and the output current positive and negative half cycle enable signal ENI is high, indicating that the output voltage is in the positive half cycle and the output current is in the negative half cycle;
• the overcurrent signal OC is effectively switched to inactive, that is, the overcurrent phenomenon disappears.
• the current limiting logic control is performed, and the Q3PWM is switched from the low level to the high level to drive the third switching transistor Q3 to be turned on, and the delay is delayed.
• time t2 the overcurrent signal OC is effectively switched to inactive, that is, the overcurrent phenomenon disappears.
• the current limiting logic control is performed, and the Q3PWM is switched from the low level to the high level to drive the third switching transistor Q3 to be turned on, and the delay is delayed.
• Q3PWM changes from high level to low level, turns off the third switch tube Q3, and at the same time, Q2PWM changes from low level to high level, driving the second switch tube Q2 to conduct, delay to t3 time, Restore the normal drive pulse timing of the four switch tubes;
• the path of the output current flowing through the main circuit of the diode midpoint clamp type three-level inverter shown in FIG. 1 is: N line-CL-D2-D 1 -C 1 -N Line, the potential of point B of the output point is clamped to the N line potential, and Q3 and Q4 share the voltage of the negative bus-BUS, which is in line with the existing current limiting method. Compared, the voltage stress of the switching tube is reduced. In order to ensure the dead time between Q1 and Q3, the normal drive pulse timing of the four switches is restored after the delay to t4.
• the output voltage positive and negative half cycle enable signal EN is high, and the output current positive and negative half cycle enable signal ENI is low, indicating that the output voltage is in the negative half cycle and the output current is in the positive half cycle;
• the overcurrent signal OC is effectively switched to inactive, that is, the overcurrent phenomenon disappears.
• the current limiting logic control is performed, and the Q2PWM is switched from the low level to the high level to drive the second switching transistor Q2 to be turned on.
• Q2PWM changes from high level to low level, and turns off Q2.
• Q3PWM changes from low level to high level, drives Q3 to turn on, delays to time t3, and then resumes four switch tubes. Normal drive pulse timing;
• the path of the output current flowing through the main circuit of the diode midpoint clamp type three-level inverter shown in FIG. 1 is: N line-C2-D4-D3-LCN line, at this time
• the potential at point B of the output point is clamped to the N-line potential.
• Q1 and Q2 share the voltage of the positive bus voltage + BUS. Compared with the existing current limiting method, the voltage stress of the switching tube is reduced.
• FIG. 7a is a schematic diagram showing another driving pulse waveform of each switching tube when the diode midpoint clamp type three-level inverter is out of current limiting control.
• the output voltage positive and negative half cycle enable signal EN is low, and the output current positive and negative half cycle enable signal ENI is also low, indicating that the output voltage is in the positive half cycle, and the output current is also in the positive half cycle. That is, the output current is in phase with the output voltage.
• the overcurrent signal OC is switched from valid to inactive, that is, the overcurrent phenomenon disappears.
• Flow logic control Q2PWM turns from low level to high level, drives the second switch tube Q2 to turn on; at time t2, Q3PWM changes from low level to high level, drives the third switch tube Q3 to turn on, delay to At time t3, Q3PWM changes from a high level to a low level to turn off the third switching transistor Q3;
• the time t3 that is, the turn-off time of Q3, is at the start-on time of Q1
• the time difference between the turn-off time of Q3 and the turn-on time of Q1 cannot satisfy the dead time requirement between Q1 and Q3, so the delay is At the time of t4, the normal driving pulse timing of the four switching tubes is restored, that is, the driving pulse of the Q1PWM in the period of t3 ⁇ t4 is cut off to ensure the dead time between Q1 and Q3.
• the path of the output current flowing through the main circuit of the diode midpoint clamp type three-level inverter shown in the figure is: LCN line-D5-Q2-L, at this time, output point B
• the potential of the point is clamped to the N-line potential, and Q3 and Q4 together withstand the negative bus-BUS voltage, which reduces the voltage stress on the switching tube compared with the existing current limiting method.
• the output voltage positive and negative half cycle enable signal EN is high, and the output current positive and negative half cycle enable signal ENI is also high, indicating that the output voltage is in the negative half cycle, and the output current is also in the negative half cycle. That is, the output current is in phase with the output voltage.
• the overcurrent signal OC is switched from valid to inactive, that is, the overcurrent phenomenon disappears.
• the current limiting logic control is performed, and the Q3PWM is switched from the low level to the high level to drive the third switching transistor Q3 to be turned on;
• Q2PWM changes from low level to high level, driving the second switch tube Q2 to be turned on, delaying to time t3, Q2PWM turning from high level to low level to turn off the second switch tube Q2;
• the time t3 that is, the turn-off time of Q2
• the time difference between the turn-off time of Q2 and the turn-on time of Q4 cannot satisfy the dead time requirement between Q2 and Q4, so the delay is At the time of t4, the normal driving pulse timing of the four switching tubes is restored, that is, the driving pulse of the Q4PWM in the period from t3 to t4 is cut off to ensure the dead time between Q2 and Q4.
• the path of the output current flowing through the main circuit of the diode midpoint clamp type three-level inverter shown in the figure is: N line-CL-Q3-D6-N line, at this time, Output point B point potential Clamping to the N-line potential, Q 1 and Q2 together with the positive bus + BUS voltage, compared to the existing current limiting method, reducing the voltage stress of the switching tube.
• the output voltage positive and negative half cycle enable signal EN is low, and the output current positive and negative half cycle enable signal ENI is high, indicating that the output voltage is in the positive half cycle and the output current is in the negative half cycle;
• the overcurrent signal OC is effectively switched to inactive, that is, the overcurrent phenomenon disappears.
• the current limiting logic control is performed, and the Q3PWM is switched from the low level to the high level to drive the third switching transistor Q3 to be turned on, and the delay is delayed.
• time t2 the overcurrent signal OC is effectively switched to inactive, that is, the overcurrent phenomenon disappears.
• the current limiting logic control is performed, and the Q3PWM is switched from the low level to the high level to drive the third switching transistor Q3 to be turned on, and the delay is delayed.
• Q2PWM changes from low level to high level, driving the second switch tube Q2 to be turned on, delaying to time t3;
• Q3PWM changes from high level to low level, turns off the third switch tube Q3, and then resumes the normal drive pulse timing of the four switch tubes;
• the time t3, that is, the turn-off time of Q3, is at the start-on time of Q1, that is, the time t3 coincides with the rising edge of Q1PWM, and the time difference between the turn-off time of Q3 and the turn-on time of Q1 cannot satisfy Q1 and Q3.
• the dead time requirement between the two, so the time delay to t4 will restore the normal drive pulse timing of the four switches, that is, the drive pulse of Q 1 PWM in the period of t3 ⁇ t4 is cut off to ensure the between Q 1 and Q3. Dead time.
• the path of the output current flowing through the main circuit of the diode midpoint clamp type three-level inverter shown in the figure is: N line-CL-D2-D1-C1-N line, output The potential at point B is clamped to the N-line potential, and Q3 and Q4 share the voltage of the negative bus-BUS, which reduces the voltage stress of the switching tube compared with the existing current limiting method.
• the output voltage positive and negative half cycle enable signal EN is high, and the output current positive and negative half cycle enable signal ENI is low, indicating that the output voltage is in the negative half cycle, the output current is in the positive half cycle;
• the overcurrent signal oc is turned from inactive to inactive, that is, the overcurrent phenomenon disappears.
• the current limiting logic control is performed, and the Q2PWM is switched from the low level to the high level to drive the second switching transistor Q2 to be turned on. Until time t2;
• Q3PWM changes from low level to high level, driving Q3 to turn on, delay to time t3; at time t3, Q2PWM changes from high level to level, turns off Q2, and then recovers four switch tubes Normal drive pulse timing;
• the time t3 that is, the turn-off time of Q2
• the time difference between the turn-off time of Q2 and the turn-on time of Q4 cannot satisfy the dead time requirement between Q2 and Q4, so the delay is At the time of t4, the normal driving pulse timing of the four switching tubes is restored, that is, the driving pulse of the Q4PWM in the period from t3 to t4 is cut off to ensure the dead time between Q2 and Q4.
• the path of the output current flowing through the main circuit of the diode midpoint clamp type three-level inverter shown in the figure is: N line-C2-D4-D3-LCN line, at this time, The potential at point B of the output point is clamped to the N-line potential.
• Q1 and Q2 share the voltage of the positive bus voltage + BUS.
• the present application further provides a diode midpoint clamp type three-level inverter circuit.
• FIG. 8 a schematic structural diagram of a diode midpoint clamp type three-level inverter circuit according to an embodiment of the present application is shown.
• the circuit includes at least: a bridge arm and a detection control circuit formed by four switch tubes connected in series, wherein the detection control circuit includes: a first controller 801, a second controller 802, an inverter current collecting circuit 803, and Flow generation detection circuit 804, wherein:
• the inverter current collecting circuit 803 is configured to collect current in the switch tube and provide the current to the overcurrent generating detecting circuit;
• the overcurrent occurrence detecting circuit 804 is configured to detect whether the current in the switch tube collected by the inverter current collecting circuit exceeds a current setting value, generate a corresponding overcurrent detecting signal OC, and provide the Second controller
• the first controller 801 is configured to generate two sinusoidal pulse width adjustment pulse SPWM pulse signals PWM1 and PWM2 with dead time, and a positive and negative half cycle enable signal EN, wherein the positive and negative half cycle enable signals are used to indicate The circuit outputs a positive and negative half cycle state of the electrical signal;
• the second controller 802 when receiving the overcurrent invalid signal that is greater than the current set value by the current greater than the current set value, the second controller, And driving a switch tube in the inner switch tube of the bridge arm to be turned on according to the overcurrent invalid signal and the positive and negative half cycle enable signal, and driving the inner switch tube after the first delay time
• the other switch tube is turned on, the positive and negative half cycle enable signal indicates a positive and negative half cycle state of the electrical signal output by the inverter circuit; and after a second delay time, one switch of the inner switch tube is controlled
• the tube is turned off, the other switch is always on, and then all of the switches are controlled to turn on or off at normal timing.
• the timing of the driving pulse outputted by the second controller is the same as the current limiting logic control timing of the diode clamp type three-level inverter current limiting circuit described above, and details are not described herein again.

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• 2012
  • 2012-09-19 CN CN201210349131.1A patent/CN102868291B/zh active Active
• 2013
  • 2013-08-06 WO PCT/CN2013/080873 patent/WO2014044087A1/zh not_active Ceased
  • 2013-08-06 EP EP13814817.6A patent/EP2750272B1/en not_active Not-in-force
  • 2013-08-06 IN IN342CHN2014 patent/IN2014CN00342A/en unknown
• 2014
  • 2014-03-25 US US14/224,953 patent/US9531185B2/en active Active

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