WO2014029189A1 - 一种高性能mems热电堆红外探测器结构及其制备方法 - Google Patents

一种高性能mems热电堆红外探测器结构及其制备方法 Download PDF

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Publication number
WO2014029189A1
WO2014029189A1 PCT/CN2013/000064 CN2013000064W WO2014029189A1 WO 2014029189 A1 WO2014029189 A1 WO 2014029189A1 CN 2013000064 W CN2013000064 W CN 2013000064W WO 2014029189 A1 WO2014029189 A1 WO 2014029189A1
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thermal
layer
isolation
silicon
substrate
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PCT/CN2013/000064
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English (en)
French (fr)
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毛海央
欧文
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江苏物联网研究发展中心
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Priority to US14/412,404 priority Critical patent/US9117949B2/en
Publication of WO2014029189A1 publication Critical patent/WO2014029189A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/02—Constructional details
    • G01J5/0215—Compact construction
    • G01J5/022—Monolithic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J5/00—Radiation pyrometry, e.g. infrared or optical thermometry
    • G01J5/10—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors
    • G01J5/12—Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using thermoelectric elements, e.g. thermocouples
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1446—Devices controlled by radiation in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H10N10/17—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device

Definitions

  • the invention relates to an infrared detector structure and a preparation method thereof, in particular to a high performance MEMS thermopile infrared detector structure and a preparation method thereof, in particular to a silicon germanium based high performance thermopile infrared detector structure And its preparation method belongs to the technical field of MEMS.
  • thermopile infrared detector is a typical device in the field of sensing detection. It is one of the core components of sensor detectors such as temperature sensor, rms converter, gas sensor, and thermal flowmeter. At the same time, Small-sized thermopile infrared detectors can also be constructed with infrared focal plane array (FPA) devices for infrared imaging.
  • FPA focal plane array
  • Thermopile infrared detectors have measurable constant radiation compared to infrared detectors based on other operating principles (such as pyroelectric infrared detectors and thermistor infrared detectors), no need to apply bias voltage, no need to ⁇ Waves are more suitable for obvious integrated advantages such as mobile applications and field applications.
  • MEMS thermopile infrared detectors are very important for achieving a wider range of infrared detection applications. Their civilian and military applications have broad prospects, and their commercial value and market potential are enormous. It can be said that the research and development work on MEMS thermopile infrared detectors has formed a new high-tech industry growth point in the 21st century. It is foreseeable that MEMS thermopile infrared detectors will become more widely used in many aspects of sensing detection. In particular, with the growing maturity of MEMS technology, including device design, manufacturing, packaging and testing, MEMS thermopile infrared detectors will become even more important.
  • Response rate and detection rate are two important performance indicators for describing infrared detectors, which determine the potential of infrared detectors in different fields.
  • the response rate is the ratio of the output electrical signal of the device to the incident infrared radiation power, which characterizes the sensitivity of the infrared detector in response to infrared radiation, and at the same time greatly affects the detection rate.
  • the temperature difference between the hot and cold ends of the thermocouple strip is an important parameter that reflects the device's response rate and detection rate.
  • the thermal conduction structure between the cold end and the base material and between the hot end and the infrared absorption region; considering the electrical series connection between the thermocouples, the thermal conduction structure is also It needs to have the function of electrical isolation at the same time.
  • thermopile infrared detector generally uses the substrate as a heat sink body, so that the cold end of the thermal coupler directly connects with the substrate, and the hot end and the absorption region are directly connected, because the substrate and the absorption region material may It has a certain conductivity, so the direct connection method will affect the output characteristics of the thermopile infrared detector, and ultimately affect the performance of the device.
  • thermopile infrared detectors For thermopile infrared detectors whose structure (including thermal conduction/electric isolation structure), size parameters, and thermocouple materials have been determined, the response rate and detection rate depend on the absorption efficiency of the infrared absorption region for infrared radiation. Silicon nitride film is often used as the material of the infrared absorption region in the research of infrared detectors. However, the highest infrared absorption efficiency of silicon nitride in the wavelength range of 1-12 ⁇ is only about 35%, and further, based on silicon nitride. The thermopile infrared detector of the infrared absorption layer cannot obtain a high response rate and detection rate.
  • the absorption efficiency of the infrared absorption region should be increased.
  • infrared detectors researchers have developed a variety of materials or structures that have high absorption rates and can serve as infrared absorption regions.
  • gold black has a good infrared absorption effect due to its nano-rough structure on the surface, and because of its low heat capacity, it has become a popular material in the research of infrared detectors.
  • the response rate and detection rate of the device can be correspondingly increased.
  • the preparation process of gold black involves processes such as metal evaporation and agglomeration of metal nanoparticles, the process is complicated, and its compatibility with CMOS process is also poor. Generally, it can only be fabricated after the device structure is processed. The surface of the structure. In view of this, the production of large quantities of detectors with black gold as the absorption zone is limited.
  • the 1/4 wavelength resonant structure maximizes the absorption efficiency of the infrared absorption region by utilizing the resonance effect produced by the thickness of the dielectric layer matching the 1/4 wavelength of the incident infrared light.
  • the detector with the 1/4 wavelength resonant structure as the absorption region can only sense the infrared radiation whose center wavelength is a certain value.
  • the process parameters are extremely strict when preparing a 1/4 wavelength resonant structure. If there is a slight mismatch between the thickness of the dielectric layer and the wavelength, the infrared absorption efficiency will be greatly attenuated.
  • Black silicon is a forest-like large-area nanocolumn/needle structure that was once considered a revolutionary new material in the electronics industry. Compared to conventional silicon materials, black silicon has a very high absorption efficiency for light in the near-infrared range.
  • various methods for preparing black silicon have been proposed, including high energy femtosecond laser assisted etching, metal catalyzed electrochemical etching, and plasma dry etching. For the comprehensive consideration of processing cost, process convenience and process compatibility, the method of preparing black silicon by plasma dry etching is most commonly used in conventional semiconductor processes.
  • thermopile infrared detector infrastructure including dielectric support film, thermopile, metal junction structure, etc.
  • the oc-Si or Poly-Si layer is deposited on the surface by plasma enhanced chemical vapor deposition (PECVD) technology, subjected to high energy ion implantation, followed by incomplete dry etching, and then processed into black silicon. And the position of the absorption zone is patterned, and finally the device structure is released.
  • PECVD plasma enhanced chemical vapor deposition
  • the fabrication of black silicon utilizes incomplete etching, so the controllability of the structure and size parameters of black silicon is low; and high energy ion implantation of the silicon material layer is required to introduce defects before preparing black silicon. , thus increasing the complexity of the process.
  • the method adopts the technical idea of "black silicon first, release after" after PECVD c-Si or Poly-Si layer, so it is necessary to strictly protect black silicon from damage during the structure release process.
  • black silicon still has the physical and chemical properties of silicon materials, so it is easily destroyed by corrosive gases during the subsequent XeF 2 dry release process; and because the nanostructures in black silicon have a certain height and a high density, conventional methods are used. , such as film deposition protection or glue protection, can not achieve effective protection.
  • the object of the present invention is to overcome the deficiencies in the prior art, and provide a high-performance MEMS thermopile infrared detector structure and a preparation method thereof, which are simple in structure, easy to implement, convenient for monolithic integration, high in response rate and detection rate, and CMOS process compatible, wide range of applications, safe and reliable.
  • the high performance MEMS thermopile infrared detector structure includes a substrate; the substrate is provided with a release barrier band, and the release barrier band has a thermal isolation cavity, the heat An infrared absorption region of silicon germanium is disposed directly above the isolation cavity, and the infrared absorption region of the silicon germanium is released a plurality of thermopiles are disposed on the outer side of the infrared absorption region of the silicon germanium, and a plurality of thermopiles outside the infrared absorption region of the silicon germanium are connected in series to be electrically connected together; the thermopile is formed corresponding to one end of the infrared absorption region adjacent to the silicon germanium.
  • thermopile Detecting a hot end, the thermopile forming a detection cold end corresponding to an end away from the infrared absorption region of the silicon germanium; detecting the cold end of the thermopile through the first thermal conduction isolation structure and the thermal conduction under the first thermal conduction isolation structure Connected to the substrate, the thermal conductor is located outside the thermal isolation cavity and is located between the release barrier and the substrate, and the first thermal conduction isolation structure is embedded in the release barrier; the hot end of the thermopile passes through The second thermally conductive isolation structure is in contact with the silicon germanium infrared absorption region, and the second thermal conduction isolation structure is located on the release barrier.
  • the silicon germanium infrared absorption region includes a silicon germanium structure formed by reactive ion etching of a silicon germanium material body and a corrosion release channel penetrating through the silicon germanium infrared absorption region, and the corrosion release channel is in communication with the thermal isolation cavity.
  • the thermopile includes a P-type thermocouple strip and an N-type thermocouple strip corresponding to the P-type thermocouple strip, and the N-type thermocouple strip and the P-type thermocouple strip are separated by a shielding isolation layer;
  • the thermocouple strip and the N-type thermocouple strip are electrically connected through the first connecting line at one end forming the detecting hot end, and at the end forming the detecting cold end, the P-type thermocouple strip passes through the second connecting line and the N-type in the adjacent thermocouple
  • the thermocouples are electrically connected to electrically connect the thermocouples to each other to form a thermopile.
  • the materials of the first thermal conduction isolation structure and the second thermal conduction isolation structure each include Si 3 N 4 . Electrically connected metal electrodes are disposed on the thermopile after the tantalum silicon infrared absorption region is connected in series.
  • the N-type thermal coupler is located under the P-type thermocouple strip, the N-type thermocouple strip is located on the release barrier strip, and the detection cold end of the N-type thermocouple strip is in contact with the first thermal conduction isolation structure, and passes through the A thermally conductive isolation structure is in contact with the thermal conductor; the detection hot end of the N-type thermal coupler is electrically connected to one end of the second thermal conduction isolation structure, and the other end of the second thermal conduction isolation structure is infra-red infrared The absorption zone is in contact.
  • a method for fabricating a high performance MEMS thermopile infrared detector structure comprises the following steps:
  • thermal conductor depositing a thermal conductor above the substrate contact window, and depositing a thermal conductor mask layer on the thermal conductor, the thermal conductor covering the substrate protective layer and filling the substrate contact window; d And selectively masking and etching the thermal conductor mask layer to form a thermal conductor etching window on the thermal conductor mask layer, the thermal conductor etching window penetrating the thermal conductor mask layer, and in the substrate contact window Inner side; etching the thermal conductor to the substrate protective layer by using a thermal conductor etching window to obtain a thermal conductor through hole;
  • the support layer is filled in the thermal conductor through hole and the thermal conductor etching window, and covers the thermal conductor mask layer to form a release on the substrate a barrier band structure and a dielectric support film;
  • the first thermal coupler and the second thermal coupler are disposed between the first thermal conduction isolation block and the second thermal conduction isolation block adjacent to the first thermal conduction isolation block.
  • the conductive coupler is different from the conductive doping type of the second thermal coupler, and the first coupler strip and the second coupler strip are separated by the shielding spacer layer, and one end of the first thermocouple strip is connected to the first thermal conduction isolation block. In contact with each other, the other end is in contact with the second thermal conduction isolation block;
  • thermal barrier protection layer above the second thermal coupler, the region covered by the thermal barrier protection layer comprises a second thermal coupler and a first thermal conduction isolation spacer; and an adjacent second heat Forming a silicon germanium material body between the conductive isolation spacers, wherein the silicon germanium material body is in contact with the second thermal conduction power isolation spacer;
  • thermal barrier protection layer selectively masking and etching the thermal barrier protection layer to form electrical connection vias required for connecting the first thermal coupler and the second thermal coupler;
  • One end of the second thermal conduction isolation block is electrically connected to the second thermal strip through the first connection line; at one end of the first thermal conduction isolation isolation block, the second thermal coupler passes through the second connection line and the adjacent thermocouple The first thermal coupler is electrically connected, and forms a first electrical connector on the outside of the first thermally conductive isolation structure;
  • a passivation layer on the surface of the substrate on which the first connection line, the second connection line and the first electrical connection body are formed, the passivation layer covering the silicon germanium material body, the thermal barrier protection layer, a connecting line, a second connecting line and a first electrical connector;
  • a passivation layer as a sidewall material layer of a surface roughness of the silicon germanium material body, a RIE is applied to the silicon germanium material body to form a silicon germanium infrared absorption region based on the germanium silicon structure, and a second electrical connection body is formed at the same time.
  • a release shielding layer of silicon germanium material is coated on the inner wall of the release hole.
  • the first thermal coupler is of the N conductive doping type
  • the second thermal coupler is of the P conductive doping type.
  • the material of the metal layer includes Al.
  • black silicon has high infrared absorption efficiency in a large wavelength range, the applicable wavelength range of the device is large, and the detector with the 1/4 wavelength resonant structure as the absorption region is overcome only for a single wavelength range. Insufficient.
  • the preparation process of the invention adopts the technical idea of "release first, black silicon after the line", and effectively overcomes the problem that the black silicon structure is easily damaged in the "black silicon first, release after” technique.
  • the detector obtained by the invention is designed and fabricated separately on the cold end/hot end of the thermopile, which is beneficial to further improve the performance of the device.
  • the processing of the device is fully compatible with the CMOS process, which facilitates monolithic integrated fabrication of the sensor structure and test circuit.
  • thermopile infrared detector provided by the invention has good process compatibility, easy structure realization, convenient monolithic integration, high response rate and high detection rate, and can be used in temperature sensors, gas sensors, heat fluxes. Wide range and practical applications in metering sensor assemblies and systems.
  • FIG. 15 are cross-sectional views showing the steps of a specific implementation process of the present invention, wherein
  • Figure 1 is a cross-sectional view showing a substrate protective layer formed on a substrate.
  • Figure 2 is a cross-sectional view of the present invention after forming a substrate contact window.
  • Figure 3 is a cross-sectional view showing the formation of a thermal conductor mask layer of the present invention.
  • FIG. 4 is a cross-sectional view of the present invention after forming a through hole of a heat conductor in a heat conductor.
  • Figure 5 is a cross-sectional view of the present invention after forming a release barrier strip structure.
  • Figure 6 is a cross-sectional view of the present invention after forming a thermally conductive separator layer.
  • Figure 7 is a cross-sectional view showing the first thermally conductive electrically isolated spacer and the second thermally conductive electrically isolated spacer of the present invention.
  • Figure 8 is a cross-sectional view showing the first thermal coupler and the second thermal coupler in the present invention.
  • Figure 9 is a cross-sectional view showing the deposition of a silicon germanium material in the present invention.
  • Figure 10 is a cross-sectional view showing the electrical connection through-holes of the present invention.
  • Figure 11 is a cross-sectional view showing the first connection line, the second connection line, and the first electrical connector in the present invention.
  • Figure 12 is a cross-sectional view of the present invention after depositing a passivation layer.
  • Figure 13 is a cross-sectional view of the present invention after forming a release aperture and applying a release barrier to the inner wall of the release aperture.
  • Figure 14 is a cross-sectional view of the present invention after the heat conductor is released to form a thermally isolated cavity.
  • Figure 15 is a cross-sectional view showing the silicon germanium infrared absorption region of the silicon germanium structure of the present invention.
  • Figure 16 is a scanning electron micrograph of silicon germanium according to the present invention and its infrared absorption spectrum.
  • Figure 17 is a schematic view showing the structure of the present invention.
  • the MEMS thermopile infrared detector structure of the present invention comprises a substrate 101; the substrate 101 is provided with a release barrier strip 2, and the release barrier strip 2 has a thermal isolation cavity 1403 therein, releasing the barrier
  • the belt 2 can function to block corrosion during the release of the heat conductor material to form the thermally isolating cavity 1403.
  • a silicon-silicon infrared absorption region 7 is disposed directly above the thermal isolation cavity 1403, and the silicon-silicon infrared absorption region 7 is located on the release barrier band 2; a plurality of thermopiles, silicon germanium are disposed outside the silicon-silicon infrared absorption region 7 The thermopiles on the outer side of the infrared absorption region 7 are electrically connected to each other in series; in the embodiment of the invention, the infrared absorption region 7 of the silicon germanium is rectangular, and symmetric thermopiles are arranged on both sides of the infrared absorption region 7 of silicon germanium.
  • thermo-electric stacks on both sides of the absorption zone 7 are electrically connected by being connected in series to each other through the heat-detecting structure connecting wires 8.
  • the thermopile forms a detection hot end corresponding to one end of the infrared absorption region 7 adjacent to the silicon germanium, and the thermoelectric stack forms a detection cold end corresponding to one end away from the silicon infrared absorption region 7; the detection cold end of the thermopile is electrically isolated by the first thermal conduction
  • the structure 1 and the thermal conductor 303 under the first thermally conductive isolation structure 1 are connected to the substrate 101.
  • the thermal conductor 303 is located outside the thermal isolation cavity 1403 and between the release barrier 2 and the substrate 101.
  • the first thermal conduction isolation structure 1 is embedded in the release barrier band 2; the detection hot end of the thermopile is in contact with the silicon-silicon infrared absorption region 7 through the second thermal conduction isolation structure 5, and the second thermal conduction is energized.
  • the isolation structure 5 is located on the release barrier strip 2.
  • the shape of the silicon-silicon infrared absorption region 7 may be square, rectangular, circular, tetragonal, or the like, and the silicon-silicon infrared absorption region 7 may have a desired shape.
  • the silicon germanium infrared absorbing region 7 in the embodiment of the present invention includes a silicon germanium material body 909 using a rough polysilicon (Poly-Si) surface as a side wall material supporting structure, and a silicon germanium structure formed by combining high selectivity ratio RIE. 1509 and a corrosion release channel 6 extending through the silicon-silicon infrared absorption region 7, the corrosion release channel 6 being in communication with the thermal isolation cavity 1403. Electrically connected metal electrodes 9 are disposed on the heat detecting structures on both sides of the silicon-silicon infrared absorption region 7, and the voltage detected by the heat detecting structures on both sides of the silicon-silicon infrared absorption region 7 can be outputted outward through the metal electrodes 9. The change in voltage can reflect the infrared heat absorbed by the silicon-silicon infrared absorption region 7.
  • the thermopile includes a P-type thermocouple strip 4 and an N-type thermocouple strip 3 correspondingly matched with the P-type thermocouple strip 4, and the N-type thermocouple strip 3 and the P-type thermocouple strip 4 pass through the shielding layer 808 phase isolation; one end of the P-type thermocouple strip 4 and the N-type thermocouple strip 3 forming the detecting hot end is electrically connected through the first connecting line 1109, and at the detecting cold end, the P-type thermocouple strip 4 passes through the second connecting line 1111 and The N-type thermocouple strips 3 in the adjacent thermocouples are electrically connected to electrically connect the thermocouple strips in the thermopile to each other.
  • the N-type thermal coupler 3 is located under the P-type thermal coupler 4.
  • the N-type thermal coupler 3 is located on the release barrier strip 2, and the detection cold end of the N-type thermal coupler 3 is in contact with the first thermal conduction isolation structure 1 and electrically isolated the structure 1 and the thermal conductor by the first thermal conduction 303 contact; the hot end of the N-type thermal coupler 3 is electrically connected to one end of the second thermal conduction isolation structure 5, the second thermal conduction The other end of the energization isolation structure 5 is in contact with the silicon germanium infrared absorption region 7.
  • the release barrier band 2 in FIG. 17 is equivalent to the release barrier band structure 503 in FIG. 15.
  • the first thermal conduction isolation structure 1 corresponds to the first thermal conduction isolation isolation block 705, and the second thermal conduction isolation isolation structure 2 Corresponding to the second thermal conduction energization isolation block 706.
  • thermopile infrared detector of the above structure can be realized by the following process steps.
  • the process steps are conventional methods; the reagents and materials, Unless otherwise stated, it can be obtained commercially. Specifically, including - a, providing a substrate 101, and providing a substrate protective layer 102 on the surface of the substrate 101;
  • a SiO 2 material layer is grown on the surface of the substrate 101 by dry oxygen oxidation to form a substrate protective layer 102 having a thickness of 5000 A and a dry oxidation temperature of 950 °. C, the content of oxygen is 60%; the substrate 101 is made of a conventional material, and the material of the substrate 101 is silicon.
  • the substrate protection layer 102 is selectively masked and etched to form a substrate contact window 202 over the substrate 101, the substrate contact window 202 penetrating through the substrate protection layer 102;
  • a photoresist is spin-coated on the surface of the substrate protection layer 102, and a plurality of openings of the photoresist are formed by a photolithography process at a position corresponding to the cold end of the thermal coupler.
  • the width of the opening is 16 ⁇ , each length is 35 ⁇ , and the total length is about 500 ⁇ ;
  • the substrate protective layer 102 is anisotropically etched by RIE technology, and the pattern on the photoresist is transferred onto the substrate protective layer 102 to form a substrate.
  • Contact window 202 removing the photoresist on the surface of the silicon wafer by oxygen plasma dry stripping and sulfuric acid/hydrogen peroxide wet stripping.
  • the RIE etched substrate protection layer 102 has an RF power of 300 W, a cavity pressure of 200 mTorr (mTorr), and an etching gas of CF 4 , CHF 3 , and He mixed gas, and a corresponding flow rate of 10/50/12 sccm ( Standard-state cubic centimeter per minute ).
  • the thermal conductor 303 and the thermal conductor mask layer 304 are grown on the substrate protective layer 102 on which the substrate contact window 202 has been formed by LPCVD (Low Pressure Chemical Vapor Deposition) technique, wherein the thermal conductor 303 is The material is poly-Si, the material of the thermal conductor mask layer 304 is Si0 2 , the thickness of the thermal conductor 303 is 2 ⁇ m, and the thickness of the thermal conductor mask layer 304 is 200 ⁇ . Since the thickness of the thermal conductor 303 is much thicker than the thickness of the substrate protection layer 102, the thermal conductor 303 can completely fill the substrate contact window 202, forming a thermal conductor fill structure 302 at the substrate contact window 202.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • LPCVD technology grows the heat conductor 303 when the working furnace tube is 620 ° C, the pressure is 200 mTorr, and the flow rate of Si3 ⁇ 4 is 130 sccm;
  • LPCVD technology uses TEOS (Tetraethyl Orthosilicate) when growing the thermal conductor mask layer 304
  • the source has a source temperature of 50 ° C, a furnace tube temperature of 720 ° C, a pressure of 300 mTorr, and an oxygen flow rate of 200 sccm.
  • thermal conductor mask layer 304 selectively masking and etching the thermal conductor mask layer 304 to form a thermal conductor etch window 404 on the thermal conductor mask layer 304, the thermal conductor etch window 404 penetrating the thermal conductor mask layer 304, And the inside of the substrate contact window 202; the thermal conductor 303 is etched through the thermal conductor etching window 404 to the substrate protection layer 102, to obtain a thermal conductor through hole 403;
  • a photoresist is spin-coated on the surface of the thermal conductor mask layer 304, and a closed opening is formed on the photoresist by a photolithography process, and then the photoresist is closed on the opening by RIE Si0 2 .
  • the pattern is the heat conductor through hole 403, and the formed heat conductor through hole 403 has a width of 1 ⁇ m.
  • the etching gas used in the RIE thermal conductor 303 is a mixed gas of 1 2 and He, the flow rates are 180 and 400 sccm, the RF power is 350 W, and the cavity pressure is 400 m ToiTo.
  • a support layer 505 on the thermal conductor mask layer 304 depositing a support layer 505 on the thermal conductor mask layer 304, the support layer 505 is filled in the thermal conductor through hole 403 and the thermal conductor etching window 404, and covered on the thermal conductor mask layer 304, Forming a release barrier strip structure 503 and a dielectric support film 504 over the substrate 101;
  • a growth support layer 505 is deposited by LPCVD, the support layer 505 being Si0 2 , the support layer 505
  • the thickness is 8000A, completely filling the thermal conductor through hole 403 and the thermal conductor etching window 404, forming the SiO 2 release barrier structure 503, and simultaneously forming the dielectric support film structure 504; here, releasing the barrier band structure 503 and the The release barrier strip 2 corresponds; for forming a subsequent release barrier strip 2.
  • a photoresist is spin-coated on the support layer 505, and a plurality of opening patterns of the photoresist are formed by a photolithography process at a position corresponding to a desired cold tip of the thermal coupler, the width of each of the opening patterns.
  • And lengths are 15 and 35 ⁇ respectively ; using the RIE Si0 2 technology to transfer the opening pattern on the photoresist to the support layer 505 to form a thermally conductive isolation opening 605; using oxygen plasma dry degumming and sulfuric acid / hydrogen peroxide wet method A photoresist removal method is used to remove the photoresist on the surface of the silicon wafer; subsequently, a growth thermal conduction isolation spacer layer 606 is deposited on the support layer 505 by LPCVD, and the material of the thermal conduction isolation spacer layer 606 is The thickness of the Si 3 N 4 , thermally conductive separator layer 606 is 8000 A.
  • thermally conductive isolation spacer 705 is located in the support layer 505
  • second thermal conduction isolation spacer 706 is disposed on the support layer 605.
  • the photoresist is spin-coated on the thermally conductive isolation spacer layer 606.
  • a first thermal conduction isolation spacer 705 and a second thermal conduction isolation isolation block 706 are formed, which respectively correspond to the first thermal conduction isolation isolation structure 1 and the second thermal conduction isolation isolation structure in FIG. 2, wherein the first thermal conduction isolation block 705 has a width of 20 ⁇ m and a length of 50 ⁇ m, and the second thermal conduction isolation block 706 has a width of 20 ⁇ m and a length of 50 ⁇ m .
  • RIE Si 3 N 4 has an RF power of 1 xiao, a cavity pressure of 400 mTorr, and an etching gas of CHF 3 , He, and SF 6 mixed gas, and a corresponding flow rate of 7/100/30 sccm.
  • the first thermal coupler 807 and the second thermocouple are disposed between the first thermal conduction isolation block 705 and the second thermal conduction isolation block 706 adjacent to the first thermal conduction isolation block 705.
  • the strip 809, the first thermocouple strip 807 and the second thermocouple strip 809 have different conductivity doping types, and the first thermocouple strip 807 and the second thermocouple strip 809 are separated by the shielding spacer layer 808, the first thermocouple strip One end of the 807 is in contact with the first thermal conduction isolation block 705, and the other end is in contact with the second thermal conduction isolation block 706;
  • a layer of Poly-Si having a thickness of 2000A is deposited by a LPCVD technique on the substrate 101 on which the first thermally conductive isolation structure 1 and the second thermally conductive isolation structure 2 have been implemented. And doping it with N-type doping, doping concentration is 2.5e22cm' 3 , doping energy is 80KeV; depositing a layer of shielding layer 808 and layer with thickness of 2000A by LPCVD on N-type Poly-Si Poly-Si layer of a thickness of 2000A, and the Poly-Si layer P-type dopant, doping concentration 5e22cm_ 3, doping energy of 30KeV; in Poly-Si layer P-type photoresist is spin-coated, And forming a pattern of the photoresist at a position corresponding to the N-type thermocouple strip 3 by a photolithography process; the material of the isolation spacer layer 808 is Si0 2 , and the photoresist pattern is transferred to the Poly by
  • thermocouple strip 807 is formed on the -Si layer, the Si0 2 layer and the Poly-Si layer, and the cold end of the first thermocouple strip 807 is in contact with the first thermal conduction isolation block 705;
  • the hot end 810 of the strip 807 is spanned by a half of the second thermally conductive isolation block 706;
  • the hot end 810 of the first coupler 807 is spanned across the area of the second thermally conductive isolation block 706 and
  • the coverage area of the continuous thermal protection layer 908 is matched, that is, the hot end 810 of the first thermal coupler 807 can be arbitrarily disposed across the second thermal conduction isolation isolation block 706, as long as the thermal protection layer 908 is ensured.
  • the hot end 810 is electrically isolated from the silicon germanium infrared absorbing region 7 formed subsequently, and the hot end 810 of the first thermal strip 807 is in contact with the second thermal conductive isolation block 706;
  • the method of removing the photoresist on the surface of the silicon wafer by the method of combining the degumming and the sulfuric acid/hydrogen peroxide wet-gel combination; re-coating the photoresist on the P-type Poly-Si layer again, and passing the photolithography process on the final thermocouple strip shape Forming a photoresist pattern corresponding to the position; transferring the photoresist pattern to the P-type Poly-Si layer by RIE Poly-Si technology to form a second thermocouple strip 809; finally, using an oxygen plasma dry method to remove the glue and The sulfuric acid/hydrogen peroxide wet-gel combination method is used to remove the photoresist on the surface of the silicon wafer.
  • the first thermocouple strip 807 and the second thermocouple strip 809 have a width of 5 ⁇ m, the first thermocouple strip 807 has a length of 120 ⁇ m, and the second thermocouple strip 809 has a length of 105 ⁇ m, and the first thermal conduction isolating block. Between the 705 and the adjacent second thermal conduction isolation block 706, the first thermal coupler 807 and the second thermal coupler 809 have a logarithm of 96 and are symmetrically placed along the two sides of the rectangular absorption zone.
  • the logarithm of the first thermocouple strip 807 and the second thermocouple strip 809 can be arbitrarily set according to actual needs, and is not limited to the logarithm and corresponding dimensions enumerated in the embodiments of the present invention.
  • thermocouple strip 807 formed above corresponds to the ⁇ -type thermocouple strip 3 in FIG. 17, and the second thermocouple strip 809 corresponds to the ⁇ -type thermocouple strip 4; the ⁇ -type thermocouple strip 3 and the ⁇ -type
  • the thermocouple strips 4 appear in pairs to form a thermocouple structure.
  • thermocouple is formed between the ⁇ -type thermocouple strip 3 and the ⁇ -type thermocouple strip 4, and the ⁇ -type thermocouple strip 4 is located above the ⁇ -type thermocouple strip 3, and the hot end of the ⁇ -type thermocouple strip 3 Connected to the second thermal conduction isolation structure 2, the cold end of the ⁇ -type thermal coupler 3 is connected to the substrate 101 through the first thermal conduction isolation structure 1 and the thermal conductor 303, so that the cold end of the entire thermopile is detected. In keeping with the temperature of the substrate 101, electrical insulation isolation is achieved by the first thermally conductive isolation structure 1 and the second thermally conductive isolation structure 5.
  • thermal barrier protection layer 908 above the second thermal coupler 809, the thermal barrier protection layer
  • the area covered by 908 includes a second thermal coupler 809, a first thermally conductive isolation block 705, and one half of the second thermally conductive isolation block 706; between adjacent second thermally conductive isolation blocks 706 Depositing a silicon germanium material body 909, the silicon germanium material body 909 being in contact with the second thermal conduction isolation block 706;
  • a SiO 2 layer having a thickness of 4000 A is deposited by a LPCVD technique on a substrate 101 on which a thermal detection structure has been realized; subsequently, a photoresist is spin-coated on the thermal protection layer 908, and the light is passed through
  • the engraving process forms a large-area photoresist pattern in the region where the thermal coupler is located; the photoresist pattern is transferred onto the Si0 2 layer by the RIE 0 2 technique to form a thermal strip protection layer 908, wherein the thermal strip protection layer 908
  • the first thermal conduction isolation structure 1 at the cold end of the thermal strip is completely covered, and the second thermal conduction isolation structure 2 at the hot end of the thermal strip is not completely covered by the thermal protection layer 908, and the size width of the exposed portion is
  • the thermal protection layer 908 covers half of the second thermal conduction isolation block 706, and the thermal protection layer 908 does not completely cover the second thermal isolation isolation block 706, which is mainly guaranteed.
  • the contact between the silicon material body 909 and the second thermal path electrical isolation block 706 ensures that the heat absorbed by the subsequent silicon germanium infrared absorption region 7 can be conducted to the thermocouple through the second thermal channel electrical isolation block 706, and the thermal barrier protection layer 908 covering the second thermal conduction
  • the area of the isolation block 706 can also be set as needed, as long as the heat absorbed by the silicon-silicon infrared absorption region can be transmitted to the thermocouple through the second thermal channel electrical isolation block 706; And removing the photoresist on the surface of the silicon wafer by a combination of sulfuric acid/hydrogen peroxide wet-gel removal; after that, a silicon germanium material body 909 having a thickness of 2 ⁇ m is deposited by LPCVD, and the material of the silicon germanium material body 909 is deposited.
  • the patterning of the Poly-Si layer is formed at the absorption region, and the patterned silicon germanium material body 909 is also folded across the second thermally conductive isolation structure 2 at the hot end of the thermal coupler, such as The cross-sectional area 910 is shown in the figure; the photoresist on the surface of the silicon wafer is removed by a combination of oxygen plasma dry stripping and sulfuric acid/hydrogen peroxide wet stripping.
  • the black silicon material body 909 can also be deposited and grown by a PECVD (plasma enhanced chemical vapor deposition) technique.
  • a photoresist is spin-coated on the surface of the substrate, and an opening of the photoresist pattern is formed by a photolithography process at a position corresponding to the electrical connection via 1008, and then the photoresist is applied by RIE Si0 2 technology.
  • the opening pattern is transferred to the thermal strip protection layer 908 to form an opening pattern, that is, the electrical connection via 1008 is formed; finally, the silicon wafer is removed by an oxygen plasma dry stripping method and a sulfuric acid/hydrogen peroxide wet stripping method.
  • Surface photoresist The formed electrical connection via 1008 has a structural size of 1 ⁇ > ⁇ 1 ⁇ .
  • the coupler 807 is electrically connected to the second coupler 809 at one end of the second thermal conduction isolation block 706 through the first connection line 1109; at one end of the first thermal conduction isolation block 705, the second thermocouple 809 Electrically connected to the first thermocouple strip 807 of the adjacent thermocouple through the second connecting line 1111, and the first electrical connecting body 1110 is formed outside the first thermal conductive isolation structure 705;
  • an A1 metal layer is sputtered on the substrate 101 on which the electrical connection via 1008 is formed, and the A1 metal layer is patterned at the electrical connection position and the metal electrode position by a photolithography process to form a first connection line. 1109, and the second connecting line 1111 and the first electrical connector 1110; subsequently adopting an organic cleaning method A photoresist other than the surface of the silicon wafer.
  • the patterning of A1 metal is achieved by wet etching of A1 etching solution. Phosphoric acid (concentration is 60% ⁇ 80%) in A1 etching solution: acetic acid (concentration: 0.1%): nitric acid (concentration: 0.5%): water The ratio is 16: 1: 1: 2.
  • a passivation layer 1211 on the surface of the substrate 101 on which the first connection line 1109, the second connection line 1111, and the first electrical connection body 1110 are formed, the passivation layer 1211 covering the silicon germanium material body 909, a first connection line 1109, a second connection line 1111 and a first electrical connection body 1110;
  • a SiO 2 layer having a thickness of 2000 A was deposited as a passivation layer 1211 by a PECVD technique on the substrate 101 on which the metal connection was realized.
  • PECVD deposits the passivation layer 1211 at a temperature of 270 ° C, a pressure of 250 mTorr, a Si concentration of 4.6%, a N 2 0 flow rate of 150 sccm, and a power of 103 W.
  • a photoresist is spin-coated on the passivation layer 1211, and the photoresist is subjected to a photolithography process in the device corresponding to the inside of the absorption region, the region between the thermocouple and the thermal coupler, and the closed opening.
  • a photoresist opening is formed in a large area of the enclosed area except for the thermal coupler region and the absorptive region; subsequently, the opening pattern of the photoresist is respectively performed by RIE Si0 2 , RIE Poly-Si and RIE Si0 2 techniques, respectively Transfer to a different material layer, that is, a release hole 1309 and a silicon germanium etching window 1311 are formed; in order to protect the absorption region from Poly-Si from being released by the released gas, the sidewall of the etching opening inside the absorption region is photolithographically A release shielding layer 1312 is applied, the release shielding layer 1312 is a photoresist, and the thickness of the release shielding layer 1312 is 2.5 ⁇ m, and the size of the etching release channel 6 after the release of the shielding layer 1312 is reduced.
  • the silicon germanium etch window 1311 and the release hole 1309 together form a corrosion release channel 6.
  • the heat conductor 303 in the isotropic etching device structure is etched by the XeF 2 dry etching technique, and the polysilicon of the heat conductor 303 is etched away by the etching release channel 6. And further forming a thermal isolation cavity 1403.
  • the release occlusion layer 1412 of the silicon germanium material in FIG. 14 corresponds to the release occlusion layer 1312 of FIG.
  • the rough silicon germanium material body 909 and the passivation layer 1211 covering the surface of the silicon germanium material body 909 can be used as the sidewall material layer of the surface roughness of the silicon germanium material body 909, using a RIE Poly-
  • the Si technology processes the black silicon structure 1509, and the germanium silicon structure 1509 is a needle-like or columnar structure; during the anisotropic etching process, the passivation layer 1211 on the first electrical connector 1110 is completely etched, thereby exposing the second electricity.
  • the connector 1510 finally obtains a novel MEMS thermopile infrared detector with black silicon as the material of the absorption region, and the overall structure is shown in FIG.
  • the preparation of the black silicon infrared absorption region 7 in the present invention utilizes the characteristics of a rough Poly-Si surface as a side wall support structure, combined with an anisotropic etching of a high selectivity ratio.
  • the black silicon material body 909 (the material of the black silicon material body 909 is Poly-Si) prepared by the black silicon infrared absorption region 7 in the present invention can be grown by PECVD or low pressure chemical vapor deposition (LPCVD). .
  • the second electrical connector 1510 is consistent with the first electrical connector 1110, and is consistent with the metal electrode 9 in the figure, and is used to detect the result of detecting the entire thermopile infrared detecting structure. Output.
  • thermopile infrared detector structure obtained by the manufacturing method of the embodiment of the present invention are: response rate is 249 V/W; detection rate is 2.25E8 cmHz ⁇ 1 ; thermal response time is 15.3 ms; noise The density is 35 nV/Hz 1/2 .
  • the heat absorbed by the infrared absorption region 7 of the silicon germanium absorbs the heat of the infrared rays, and the heat absorbed by the infrared absorption region 7 of the silicon germanium is conducted to the infrared absorption region of the silicon germanium through the second thermal conduction isolation structure 2.
  • the detection cold end of the thermopile is connected to the substrate 101 through the first thermal conduction isolation structure 1 and the thermal conductor 303, so that the temperature of the cold junction is consistent with the temperature of the substrate 101, and reaches The role of electrical isolation.
  • the N-type thermal coupler 3 and the P-type thermocouple strip 4 in the thermopile form a thermocouple structure, and the temperature difference between the hot end of the thermopile and the detected cold end will generate a certain potential difference at the cold end, in the thermopile.
  • a plurality of thermocouples are connected in series and outputted outward through the metal electrode 9, and the required detection process is achieved by judging the output voltage.
  • the invention adopts the silicon germanium infrared absorption region 7, and the black silicon has high infrared absorption efficiency and high performance, high detection rate and the like, thereby overcoming the detector response rate and detection of the material with Si 3 N 4 as the absorption region.
  • the rate is not high. Since the preparation of black silicon does not have very strict requirements on process parameters (such as the thickness of Si0 2 grown, the thickness of Poly-Si, the time and thickness of etching, etc.), the structure of the infrared detector based on black silicon is easier to implement, thereby overcoming the The detector with the 1/4 wavelength resonant structure as the absorption region has too high requirements for the process parameters and then the controllability of the performance parameters is poor.
  • the device has a wide applicable wavelength range, and overcomes the problem that the detector with the 1/4 wavelength resonant structure as the absorption region is only suitable for a single wavelength range. .
  • the preparation process of the invention adopts the technical idea of "release first, black silicon after the line", and effectively overcomes the problem that the black silicon structure is easily damaged in the "black silicon first, release after” technique.
  • the detector of the invention performs the design and fabrication of the thermal conduction isolation structure at the cold end/hot end of the thermopile, which is beneficial to further improve the performance of the device.
  • the device's processing is fully compatible with the CMOS process, which facilitates monolithic integrated fabrication of the sensor structure and test circuitry.
  • the novel high-performance MEMS thermopile infrared detector provided by the invention has good process compatibility, easy structure realization, convenient monolithic integration, high response rate and high detection rate, and can be used in temperature sensors, gas sensors, heat flow meters, etc. A wide range of practical applications are available in sensing probe assemblies and systems.

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Abstract

一种高性能MEMS热电堆红外探测器结构及其制备方法，红外探测器包括衬底（101）；衬底（101）上设有释放阻挡带（2），释放阻挡带（2）内具有热隔离腔体（1403），热隔离腔体（1403）的正上方设有黒硅红外吸收区（7），黒硅红外吸收区（7）位于释放阻挡带（2）上；黒硅红外吸收区（7）的外侧设有若干热电堆，黒硅红外吸收区（7）外侧的若干热电堆相互串接后电连接成一体；热电堆的探测冷端通过第一热导通电隔离结构（1）及所述第一热导通电隔离结构（1）下方的热传导体（303）与衬底（101）相连；热电堆的探测热端通过第二热导通电隔离结构（5）与黒硅红外吸收区（7）相接触，第二热导通电隔离结构（5）位于释放阻挡带（2）上。该结构简单易于实现，便于单片集成，响应率及探测率高，与CMOS工艺兼容，适用范围广，安全可靠。

Description

一种高性能 MEMS热电堆红外探测器结构及其制备方法
技术领域
本发明涉及一种红外探测器结构及其制备方法， 尤其是一种高性能 MEMS 热电堆红外探测器结构及其制备方法， 具体地说是一种基于黒硅的高性能热电 堆红外探测器结构及其制备方法， 属于 MEMS的技术领域。
背景技术
MEMS热电堆红外探测器是传感探测领域的一种典型器件， 是组成温度传 感器、 均方根转换器、 气敏传感器、 热流量计等传感探测器件的核心部件之一， 与此同时， 小尺寸热电堆红外探测器还可构建红外焦平面阵列（FPA)器件实现 红外成像。 热电堆红外探测器与基于其它工作原理的红外探测器 （如热释电型 红外探测器和热敏电阻型红外探测器等） 相比具有可测恒定辐射量、 无需加偏 置电压、 无需斩波器、 更适用于移动应用与野外应用等明显的综合优点。 因而， MEMS热电堆红外探测器对于实现更为宽广的红外探测应用具有非常重要的意 义，其民用、军用前景广阔，商业价值和市场潜力非常巨大。可以说，关于 MEMS 热电堆红外探测器的研究开发工作己形成 21世纪一个新的高技术产业增长点。 可以预见， MEMS热电堆红外探测器将在传感探测的众多方面形成更加广泛的 应用。 特别是， 随着微机电技术， 包括器件设计、 制造、 封装和测试等技术手 段的日益成熟， MEMS热电堆红外探测器将凸显更加重要的地位。
响应率和探测率是描述红外探测器的两个重要性能指标， 决定了红外探测 器在不同领域的应用潜力。 其中， 响应率是器件输出电信号与入射红外辐射功 率的比值， 表征了红外探测器响应红外辐射的灵敏度， 同时又很大程度地影响 着探测率的值。 对热电堆红外探测器而言， 热偶条热端与冷端之间的温度差是 反映器件响应率和探测率大小的一个重要参数。 为了增大温度差以提高器件的 响应率和探测率， 需要尽可能保持冷端温度与基底温度相一致， 同时热端能有 效传递红外吸收区所吸收的热量至热偶条。 为了达到这一效果， 在冷端与基底 材料之间以及热端与红外吸收区之间制作热导通结构就显得十分必要； 考虑到 热电偶之间电学串联的特点， 该热导通结构还需同时具备电学隔离的作用。 现 有的热电堆红外探测器一般将衬底作为热沉体， 使热偶条的冷端与衬底直接搭 连， 又使热端与吸收区直接搭连， 因为衬底和吸收区材料可能具有一定的导电 能力， 因而采用这种直接搭连的方法将影响热电堆红外探测器的输出特性， 最 终影响器件的性能。
对于结构（包括热导通 /电隔离结构）、尺寸参数以及热偶材料等均己确定的 热电堆红外探测器， 其响应率和探测率的值取决于红外吸收区对红外辐射的吸 收效率。 氮化硅薄膜在红外探测器的研究中常用作红外吸收区的材料， 然而氮 化硅在 1-12μιη波长范围内所能达到的最高红外吸收效率仅为 35%左右， 进而， 基于氮化硅红外吸收层的热电堆红外探测器无法获得很高的响应率和探测率。 鉴于此， 要提高探测器的响应率和探测率， 应增大红外吸收区的吸收效率。 在 对红外探测器进行研究的数十年中， 科研人员己经开发出了多种具有高吸收率 且可作为红外吸收区的材料或结构。 其中， 金黑因其表面的纳米粗糙结构而具 有很好的红外吸收效果， 又因其热容较低， 进而在红外探测器的研究中成为一 种倍受欢迎的材料。 采用金黑材料为红外吸收区时， 器件的响应率和探测率可 相应提高。 然而， 金黑的制备工艺涉及到金属蒸发和金属纳米颗粒的凝集等工 序， 过程较为复杂， 并且其与 CMOS工艺的兼容性也较差， 一般只能在器件结 构加工完成后再将其制作在结构的表面。 鉴于此， 以黑金为吸收区的探测器其 大批量的生产就受到了限制。 1/4波长谐振结构利用介质层厚度与入射红外光波 的 1/4波长相匹配时所产生的谐振效果使红外吸收区的吸收效率达到最大。 然 而， 受谐振条件的制约， 以 1/4波长谐振结构为吸收区的探测器只能敏感中心波 长为某一特定值的红外辐射。此外，制备 1/4波长谐振结构时对工艺参数的要求 极其严格苛刻， 若介质层厚度与波长之间稍有不匹配， 将造成红外吸收效率的 极大衰减。
黑硅是一种呈森林状的大面积纳米柱 /针结构， 曾被认为是电子产业界的一 种革命性新材料。 相比于传统的硅材料， 黑硅对近红外波段的光具有极高的吸 收效率。 目前已提出的制备黑硅的方法多种多样， 包括如高能量飞秒激光辅助 刻蚀、 金属催化电化学腐蚀以及等离子体干法刻蚀等。 出于加工成本、 工艺便 捷程度以及工艺兼容性等多方面的综合考虑， 用等离子体干法刻蚀技术制备黑 硅的方法在常规半导体工艺中最常使用。 已有研究人员报道将黑硅用作红外吸 收层材料来提高热电堆红外探测器件性能的方法： 在形成热电堆红外探测器的 基础结构 （包括介质支撑膜、 热电堆、 金属连接结构等） 之后， 通过等离子体 增强化学气相沉积（PECVD)技术在表面淀积生长 oc-Si或 Poly-Si层， 对其进行 高能量离子注入， 随后进行不完全干法刻蚀， 进而将其处理成黑硅并在吸收区 位置图形化， 最后进行器件结构的释放。 该方法中， 黑硅的制作利用了不完全 刻蚀， 因此黑硅的结构和尺寸参数的可控性较低； 并且在制备黑硅之前需要对 硅材料层进行高能量的离子注入以引入缺陷， 因而增加了工艺的复杂程度。 另 外， 该方法在 PECVD c -Si或 Poly-Si层之后， 采用了 "黑硅先行， 释放后行"的 技术思路， 因此在结构释放过程中需要严格保护黑硅免受破坏。 然而， 黑硅仍 具硅材料的物理、 化学性质， 因此在后续 XeF2干法释放过程中易受腐蚀气体破 坏； 又因为黑硅中纳米结构具有一定的高度且密度较大， 采用常规的方法， 如 薄膜淀积保护或涂胶保护， 均不能实现有效的保护。
发明内容
本发明的目的是克服现有技术中存在的不足， 提供一种高性能 MEMS热电 堆红外探测器结构及其制备方法， 其结构简单易于实现， 便于单片集成， 响应 率及探测率高， 与 CMOS工艺兼容， 适用范围广， 安全可靠。
按照本发明提供的技术方案， 所述高性能 MEMS热电堆红外探测器结构， 包括衬底； 所述衬底上设有释放阻挡带， 所述释放阻挡带内具有热隔离腔体， 所述热隔离腔体的正上方设有黒硅红外吸收区， 所述黒硅红外吸收区位于释放 阻挡带上； 黒硅红外吸收区的外侧设有若干热电堆， 黒硅红外吸收区外侧的若 干热电堆相互串接后电连接成一体； 所述热电堆对应邻近黒硅红外吸收区的一 端形成探测热端， 热电堆对应远离黒硅红外吸收区的一端形成探测冷端； 热电 堆的探测冷端通过第一热导通电隔离结构及所述第一热导通电隔离结构下方的 热传导体与衬底相连， 热传导体位于热隔离腔体的外部， 并位于释放阻挡带及 衬底之间， 第一热导通电隔离结构嵌置于释放阻挡带内； 热电堆的探测热端通 过第二热导通电隔离结构与黒硅红外吸收区相接触， 第二热导通电隔离结构位 于释放阻挡带上。
所述黒硅红外吸收区包括将黒硅材料体利用反应离子刻蚀形成的黒硅结构 及贯通所述黒硅红外吸收区的腐蚀释放通道， 所述腐蚀释放通道与热隔离腔体 相连通。
所述热电堆包括 P型热偶条及与所述 P型热偶条对应配合的 N型热偶条， 所述 N型热偶条与 P型热偶条通过遮挡隔离层相隔离； P型热偶条与 N型热偶 条在形成探测热端的一端通过第一连接线电连接， 且在形成探测冷端的一端， P 型热偶条通过第二连接线与相邻热电偶内的 N型热偶条电连接， 以将热电偶相 互电连接构成热电堆。
所述第一热导通电隔离结构及第二热导通电隔离结构的材料均包括 Si3N4。 所述黒硅红外吸收区外侧串接后的热电堆上设置电连接的金属电极。
所述 N型热偶条位于 P型热偶条下方， N型热偶条位于释放阻挡带上， N 型热偶条的探测冷端与第一热导通电隔离结构相接触， 并通过第一热导通电隔 离结构与热传导体相接触； N型热偶条的探测热端趴跨第二热导通电隔离结构 的一端， 第二热导通电隔离结构的另一端与黒硅红外吸收区接触。
一种高性能 MEMS热电堆红外探测器结构的制备方法,所述 MEMS热电堆 红外探测器结构的制备方法包括如下步骤：
a、 提供衬底， 并在所述衬底的表面上设置衬底保护层；
b、选择性地掩蔽和刻蚀上述衬底保护层，以在衬底上方形成衬底接触窗口， 所述衬底接触窗口贯通衬底保护层；
c、 在上述衬底接触窗口上方淀积热传导体， 并在所述热传导体上淀积热传 导体掩膜层， 所述热传导体覆盖于衬底保护层上并填充在衬底接触窗口内； d、 选择性地掩蔽和刻蚀上述热传导体掩膜层， 以在热传导体掩膜层上形成 热传导体刻蚀窗口， 所述热传导体刻蚀窗口贯通热传导体掩膜层， 并在衬底接 触窗口的内侧； 利用热传导体刻蚀窗口刻蚀热传导体直至衬底保护层， 得到热 传导体通孔；
e、 在上述热传导体掩膜层上淀积支撑层， 所述支撑层填充于热传导体通孔 及热传导体刻蚀窗口内， 并覆盖于热传导体掩膜层上， 以在衬底上方形成释放 阻挡带结构及介质支撑膜；
f、 选择性地掩蔽和刻蚀支撑层， 以在支撑层内形成热导通电隔离开口， 所 述热导通电隔离开口贯通支撑层并位于释放阻挡带结构的外侧； 在上述支撑层 上方淀积热导通电隔离体层， 所述热导通电隔离体层填充于热导通电隔离开口 内， 并覆盖于支撑层上；
g、 选择性地掩蔽和刻蚀上述热导通电隔离体层， 以在上述支撑层上形成第 一热导通电隔离块及第二热导通电隔离块， 所述第一热导通电隔离块位于支撑 层内， 第二热导通电隔离块位于支撑层上；
h、 在上述第一热导通电隔离块及与所述第一热导通电隔离块邻近的第二热 导通电隔离块间设置第一热偶条及第二热偶条， 第一热偶条与第二热偶条的导 电掺杂类型不同， 第一热偶条与第二热偶条间通过遮挡隔离层隔离， 第一热偶 条的一端与第一热导通电隔离块相接触， 另一端与第二热导通电隔离块相接触;
i、 在上述第二热偶条上方设置热偶条保护层， 所述热偶条保护层覆盖的区 域包括第二热偶条及第一热导通电隔离块； 在相邻的第二热导通电隔离块之间 形成黒硅材料体， 所述黒硅材料体与第二热导通电隔离块相接触；
j、 选择性地掩蔽和刻蚀上述热偶条保护层， 以形成用于连接第一热偶条及 第二热偶条所需的电连接通孔；
k、 在上述已制作电连接通孔的衬底上溅射金属层， 所述金属层填充在上述 电连接通孔内， 选择性地掩蔽和刻蚀上述金属层， 使得第一热偶条在第二热导 通电隔离块的一端与第二热偶条通过第一连接线电连接； 在第一热导通电隔离 块的一端， 第二热偶条通过第二连接线与邻近热电偶的第一热偶条电连接， 并 在第一热导通电隔离结构的外侧形成第一电连接体；
1、 在上述制作了第一连接线、 第二连接线和第一电连接体的衬底表面上淀 积钝化层， 所述钝化层覆盖黒硅材料体、 热偶条保护层、 第一连接线、 第二连 接线及第一电连接体；
m、选择性地掩蔽和刻蚀上述钝化层， 以在黒硅材料体上的钝化层上形成黒 硅刻蚀窗口， 利用黒硅刻蚀窗口对黒硅材料体进行刻蚀， 直至刻蚀到黒硅刻蚀 窗口正下方的热传导体， 以形成释放孔；
n 利用释放阻挡带结构释放黒硅材料体正下方的热传导体， 以得到热隔离 腔体；
0、 利用钝化层作为黒硅材料体表面粗糙结构的侧墙材料层， 对黒硅材料体 采用一次 RIE,以形成基于黒硅结构的黒硅红外吸收区，同时形成第二电连接体。
所述步骤 m和步骤 η·中， 在释放孔的内壁上涂覆黒硅材料的释放遮挡层。 所述步骤 h中， 第一热偶条为 N导电掺杂类型， 第二热偶条为 P导电掺杂 类型。
所述步骤 k中， 金属层的材料包括 Al。
本发明的优点：
1、 采用黒硅红外吸收区， 因黑硅的红外吸收效率高进而具有高响应率、 高 探测率等性能特点， 从而克服了以 Si3N4为吸收区材料的探测器响应率、探测率 不高的问题。
2、 因黑硅的制备对工艺参数（如所生长 Si〇2、 Poly-Si厚度， 刻蚀的时间及 厚度等）没有非常苛刻的要求， 因此基于黑硅的红外探测器件结构更易于实现， 从而克服了以 1/4 波长谐振结构为吸收区的探测器对工艺参数的要求过高继而 性能参数可控性差的缺陷。
3、 因黑硅在较大波长范围内都具有很高的红外吸收效率， 因此该器件的适 用波长范围大，克服了以 1/4波长谐振结构为吸收区的探测器仅适用于单一波长 范围的不足。
4、本发明的制备过程采用"释放先行，黑硅后行"的技术思路，有效克服了"黑 硅先行， 释放后行"技术方法中黑硅结构易受损的问题。
5、本发明得到的探测器在热电堆的冷端 /热端分别进行了热导通电隔离结构 的设计与制作， 有利于进一步提高器件的性能。
6、该器件的加工过程与 CMOS工艺完全兼容， 因而有利于传感器件结构和 测试电路的单片集成制造。
7、 由本发明提供的新型高性能 MEMS 热电堆红外探测器具有工艺兼容性 好， 器件结构易于实现， 便于单片集成， 响应率、 探测率高等特点， 可在温度 传感器、 气敏传感器、 热流量计等传感探测器件与系统中获得广泛和实际的应 用。
附图说明
图 1〜图 15为本发明具体实施工艺步骤剖视图， 其中
图 1为本发明在衬底上形成衬底保护层后的剖视图。
图 2为本发明形成衬底接触窗口后的剖视图。
图 3为本发明形成热传导体掩膜层后的剖视图。
图 4为本发明在热传导体内形成热传导体通孔后的剖视图。
图 5为本发明形成释放阻挡带结构后的剖视图。
图 6为本发明形成热导通电隔离体层后的剖视图。
图 7为本发明形成第一热导通电隔离块与第二热导通电隔离块后的剖视图。 图 8为本发明形成第一热偶条及第二热偶条后的剖视图。
图 9为本发明淀积形成黒硅材料体后的剖视图。
图 10为本发明形成电连接通孔后的剖视图。
图 11为本发明形成第一连接线、 第二连接线及第一电连接体后的剖视图。 图 12为本发明淀积钝化层后的剖视图。
图 13为本发明形成释放孔并在释放孔内壁涂覆释放遮挡层后的剖视图。 图 14为本发明释放热传导体形成热隔离腔体后的剖视图。
图 15为本发明形成黒硅结构的黒硅红外吸收区后的剖视图。
图 16为本发明黒硅的扫描电镜照片及其红外吸收光谱图。
图 17为本发明的结构示意图。
附图标记说明： 1-第一热导通电隔离结构、 2-释放阻挡带、 3-N型热偶条、 4-P型热偶条、 5-第二热导通电隔离结构、 6-腐蚀释放通道、 7-黒硅红外吸收区、 8-热探测结构连接线、 9-金属电极、 101-衬底、 102-衬底保护层、 202-衬底接触 窗口、 302-热传导体填充结构、 303-热传导体、 304-热传导体掩膜层、 403-热传 导体通孔、 404-热传导体刻蚀窗口、 503-释放阻挡带结构、 504-介质支撑膜、 505- 支撑层、 605-热导通电隔离开口、 606-热导通电隔离体层、 705-第一热导通电隔 离块、 706-第二热导通电隔离块、 807-第一热偶条、 808-遮挡隔离层、 809-第二 热偶条、 810-热端、 908-热偶条保护层、 909-黒硅材料体、 910-趴跨区域、 1008- 电连接通孔、 1109-第一连接线、 1110-第一电连接体、 1111-第二连接线、 1211- 钝化层、 1309-释放孔、 1311-黒硅刻蚀窗口、 1312-释放遮挡层、 1403-热隔离腔 体、 1412-黒硅材料的释放遮挡层、 1509-黒硅结构及 1510-第二电连接体。
具体实施方式
下面结合具体附图和实施例对本发明作进一步说明。
如图 17所示： 本发明的 MEMS热电堆红外探测器结构包括衬底 101 ; 所述 衬底 101上设有释放阻挡带 2， 所述释放阻挡带 2内具有热隔离腔体 1403， 释 放阻挡带 2能够在释放热传导体材料形成热隔离腔体 1403的过程中起到阻挡腐 蚀的作用。 所述热隔离腔体 1403的正上方设有黒硅红外吸收区 7， 所述黒硅红 外吸收区 7位于释放阻挡带 2上； 黒硅红外吸收区 7的外侧设有若干热电堆， 黒硅红外吸收区 7外侧的热电堆相互串接后电连接成一体； 本发明实施例中， 黒硅红外吸收区 7呈长方形， 黒硅红外吸收区 7的两侧设置对称的热电堆， 黒 硅红外吸收区 7两侧的热-电堆通过热探测结构连接线 8相互串接后电连接。 所 述热电堆对应邻近黒硅红外吸收区 7 的一端形成探测热端， 热电堆对应远离黒 硅红外吸收区 7 的一端形成探测冷端； 热电堆的探测冷端通过第一热导通电隔 离结构 1及所述第一热导通电隔离结构 1下方的热传导体 303与衬底 101相连， 热传导体 303位于热隔离腔体 1403的外部， 并位于释放阻挡带 2及衬底 101之 间， 第一热导通电隔离结构 1嵌置于释放阻挡带 2内； 热电堆的探测热端通过 第二热导通电隔离结构 5与黒硅红外吸收区 7相接触，第二热导通电隔离结构 5 位于释放阻挡带 2上。 另外， 黒硅红外吸收区 7的形状可以为正方形、 长方形、 圆形、 四角补偿形等， 黒硅红外吸收区 7可以采用所需的形状。
本发明实施例中所述黒硅红外吸收区 7包括将黒硅材料体 909利用粗糙多 晶硅 （Poly-Si) 表面可作为侧墙材料支撑结构的特性， 并结合高选择比 RIE形 成的黒硅结构 1509及贯通所述黒硅红外吸收区 7的腐蚀释放通道 6, 所述腐蚀 释放通道 6与热隔离腔体 1403相连通。 所述黒硅红外吸收区 7两侧的热探测结 构上均设置电连接的金属电极 9，通过金属电极 9能够将黒硅红外吸收区 7两侧 的热探测结构探测得到的电压向外输出， 通过电压的变化能够反映出黒硅红外 吸收区 7吸收的红外热量。
所述热电堆包括 P型热偶条 4及与所述 P型热偶条 4对应配合的 N型热偶 条 3，所述 N型热偶条 3与 P型热偶条 4通过遮挡隔离层 808相隔离； P型热偶 条 4与 N型热偶条 3形成探测热端的一端通过第一连接线 1109电连接，且在探 测冷端， P型热偶条 4通过第二连接线 1111与相邻热电偶内的 N型热偶条 3电 连接， 以将热电堆内的热偶条相互电连接成一体。
如图 15所示：本发明具体实施例中所述 N型热偶条 3位于 P型热偶条 4下 方。 N型热偶条 3位于释放阻挡带 2上， N型热偶条 3的探测冷端与第一热导 通电隔离结构 1相接触， 并通过第一热导通电隔离结构 1与热传导体 303相接 触； N型热偶条 3的探测热端趴跨第二热导通电隔离结构 5的一端， 第二热导 通电隔离结构 5的另一端与黒硅红外吸收区 7接触。 图 17中的释放阻挡带 2相 当于图 15中的释放阻挡带结构 503, 第一热导通电隔离结构 1相当于第一热导 通电隔离块 705， 第二热导通电隔离结构 2相当于第二热导通电隔离块 706。
如图 1~图 15所示：上述结构的热电堆红外探测器结构可以采用下述工艺步 骤实现， 下述实施例中， 如无特殊说明， 工艺步骤均为常规方法； 所述试剂和材 料， 如无特殊说明， 均可从商业途径获得。 具体地包括- a、 提供衬底 101， 并在所述衬底 101的表面上设置衬底保护层 102;
如图 1所示： 在衬底 101的表面通过干氧氧化的方式生长 Si02材料层， 以 形成衬底保护层 102，衬底保护层 102的厚度为 5000A,干氧氧化时温度为 950°C， 氧气的含量为 60%; 所述衬底 101采用常规的材料， 衬底 101的材料包括硅。
b、 选择性地掩蔽和刻蚀上述衬底保护层 102, 以在衬底 101上方形成衬底 接触窗口 202， 所述衬底接触窗口 202贯通衬底保护层 102;
如图 2所示： 在衬底保护层 102的表面旋涂光刻胶， 并通过光刻工艺在对 应所需形成热偶条冷端的位置形成光刻胶的多段开口图形， 开口的宽度为 16 μηι, 每段长度为 35μπι， 总长度为大约 500μιη; 利用 RIE技术对衬底保护层 102 进行各向异性刻蚀， 将光刻胶上开口的图形转移到衬底保护层 102上， 形成衬 底接触窗口 202; 利用氧等离子体干法去胶以及硫酸 /双氧水湿法去胶相结合的 方法去除硅片表面的光刻胶。其中， RIE刻蚀衬底保护层 102的 RF功率为 300W, 腔体压力为 200mTorr (毫托）， 刻蚀气体为 CF4、 CHF3、 He混合气体， 对应的 流量为 10/50/12sccm (standard-state cubic centimeter per minute )。
c、在上述衬底接触窗口 202上方淀积热传导体 303，并在所述热传导体 303 上淀积热传导体掩膜层 304，所述热传导体 303覆盖于衬底保护层 102上并填充 在衬底接触窗口 202内； '
如图 3所示，在已经形成衬底接触窗口 202的衬底保护层 102上利用 LPCVD (低压化学汽相淀积）技术生长热传导体 303和热传导体掩膜层 304， 其中， 热 传导体 303的材料为多晶硅（Poly-Si), 热传导体掩膜层 304的材料为 Si02， 热 传导体 303的厚度为 2μπι， 热传导体掩膜层 304的厚度为 200θΑ。 由于热传导 体 303的厚度较衬底保护层 102的厚度厚很多， 因此热传导体 303能完全填充 衬底接触窗口 202，形成位于衬底接触窗口 202的热传导体填充结构 302。其中， LPCVD技术生长热传导体 303时工作炉管为 620 °C， 压强为 200mTorr， Si¾的 流量为 130sccm; LPCVD技术生长热传导体掩膜层 304时采用 TEOS( (Tetraethyl Orthosilicate, 正硅酸乙酯）） 源， 源温度为 50°C , 炉管温度为 720°C， 压强为 300mTorr, 氧气流量为 200sccm。
d、选择性地掩蔽和刻蚀上述热传导体掩膜层 304，以在热传导体掩膜层 304 上形成热传导体刻蚀窗口 404，所述热传导体刻蚀窗口 404贯通热传导体掩膜层 304, 并在衬底接触窗口 202的内侧； 利用热传导体刻蚀窗口 404刻蚀热传导体 303直至衬底保护层 102， 得到热传导体通孔 403;
如图 4所示， 在热传导体掩膜层 304的表面旋涂光刻胶， 并通过光刻工艺 在光刻胶上形成封闭开口， 随后利用 RIE Si02的方法将光刻胶上封闭开口的图 形转移到热传导体掩膜层 304上， 形成位于热传导体掩膜层 304上的封闭开口 图形即热传导体刻蚀窗口 404; 利用氧等离子体干法去胶以及硫酸 /双氧水湿法 去胶相结合的方法去除硅片表面的光刻胶； 采用 RIE技术各向异性刻蚀热传导 体 303， 将热传导体掩膜层 304上的封闭开口图形转移到热传导体 303上，形成 热传导体 303 上的封闭开口图形即热传导体通孔 403， 所形成的热传导体通孔 403的宽度为 1μπι。 其中， RIE热传导体 303时采用的刻蚀气体为（ 12和 He的 混合气体， 其流量分别为 180和 400 sccm, RF功率为 350 W， 腔体压力为 400 mToiTo
e、 在上述热传导体掩膜层 304上淀积支撑层 505， 所述支撑层 505填充于 热传导体通孔 403及热传导体刻蚀窗口 404内， 并覆盖于热传导体掩膜层 304 上， 以在衬底 101上方形成释放阻挡带结构 503及介质支撑膜 504;
如图 5所示， 在已经形成热传导体通孔 403和热传导体刻蚀窗口 404的衬 底 101上， 通过 LPCVD技术淀积生长支撑层 505， 所述支撑层 505为 Si02， 支 撑层 505的厚度为 8000A,完全填充热传导体通孔 403和热传导体刻蚀窗口 404， 形成 Si02释放阻挡带结构 503， 并同时形成介质支撑膜结构 504; 此处， 释放阻 挡带结构 503与图 17中的释放阻挡带 2相对应；用于形成后续的释放阻挡带 2。
f、 选择性地掩蔽和刻蚀支撑层 505， 以在支撑层 505内形成热导通电隔离 开口 605， 所述热导通电隔离开口 605贯通支撑层 505并位于释放阻挡带结构 503的外侧； 在上述支撑层 505上方淀积热导通电隔离体层 606， 所述热导通电 隔离体层 606填充于热导通电隔离开口 605内， 并覆盖于支撑层 605上；
如图 6所示， 在支撑层 505上旋涂光刻胶， 并通过光刻工艺在对应于所需 形成热偶条冷端的位置形成光刻胶的多个开口图形， 每个开口图形的宽度和长 度分别为 15和 35μιη; 利用 RIE Si02技术将光刻胶上的开口图形转移到支撑层 505上形成热导通电隔离开口 605;利用氧等离子体干法去胶以及硫酸 /双氧水湿 法去胶相结合的方法去除硅片表面的光刻胶； 随后，通过 LPCVD技术在支撑层 505 上淀积生长热导通电隔离体层 606， 所述热导通电隔离体层 606 的材料为 Si3N4， 热导通电隔离体层 606的厚度为 8000 A。
g、 选择性地掩蔽和刻蚀上述热导通电隔离体层 606， 以在上述支撑层 505 上形成第一热导通电隔离块 705及第二热导通电隔离块 706，所述第一热导通电 隔离块 705位于支撑层 505内， 第二热导通电隔离块 706位于支撑层 605上； 如图 7所示， 在热导通电隔离体层 606上旋涂光刻胶， 并通过光刻工艺在 对应于热偶条冷端和热端的位置分别形成多个光刻胶的图形； 利用 RIE Si3N4技 术将光刻胶上的图形转移到热导通电隔离体层 606上， 形成第一热导通电隔离 块 705和第二热导通电隔离块 706, 分别对应于图 17中的第一热导通电隔离结 构 1和第二热导通电隔离结构 2，其中，第一热导通电隔离块 705的宽度为 20μιη， 长度为 50μπι， 第二热导通电隔离块 706的宽度为 20μπι， 长度为 50μιη; 最后， 利用氧等离子体干法去胶以及硫酸 /双氧水湿法去胶相结合的方法去除硅片表面 的光刻胶。其中， RIE Si3N4的 RF功率为 1蕭， 腔体压力为 400mTorr， 刻蚀气 体为 CHF3、 He、 SF6混合气体， 对应的流量为 7/100/30sccm。 h、 在上述第一热导通电隔离块 705及与所述第一热导通电隔离块 705邻近 的第二热导通电隔离块 706间设置第一热偶条 807及第二热偶条 809，第一热偶 条 807与第二热偶条 809 .的导电掺杂类型不同， 第一热偶条 807与第二热偶条 809间通过遮挡隔离层 808隔离，第一热偶条 807的一端与第一热导通电隔离块 705相接触， 另一端与第二热导通电隔离块 706相接触；
如图 8所示，在已实现第一热导通电隔离结构 1和第二热导通电隔离结构 2 的衬底 101上利用 LPCVD技术淀积生长一层厚度为 2000A的 Poly-Si层， 并对 其进行 N型掺杂， 掺杂浓度为 2.5e22cm'3， 掺杂能量为 80KeV; 在 N型 Poly-Si 上利用 LPCVD技术淀积生长一层厚度为 2000A的遮挡隔离层 808与一层厚度 为 2000A的 Poly-Si层，并对所述 Poly-Si层进行 P型掺杂，掺杂浓度为 5e22cm_3， 掺杂能量为 30KeV;在 P型 Poly-Si层上旋涂光刻胶，并通过光刻工艺在 N型热 偶条 3对应的位置形成光刻胶的图形；遮挡隔离层 808的材料为 Si02，利用 RIE Poly-Si和 RIE Si02技术将光刻胶图形转移到 Poly-Si层、 Si02层和 Poly-Si层上， 首先形成第一热偶条 807， 所述第一热偶条 807 的冷端与第一热导通电隔离块 705相接； 第一热偶条 807的热端 810趴跨半个第二热导通电隔离块 706; 第一 热偶条 807的热端 810趴跨第二热导通电隔离块 706的区域与后续热偶条保护 层 908的覆盖区域相匹配， 即第一热偶条 807的热端 810趴跨第二热导通电隔 离块 706的区域可以任意设置， 只要保证通过热偶条保护层 908实现热端 810 与后续形成的黒硅红外吸收区 7的电绝缘隔离， 且第一热偶条 807的热端 810 与第二热导通电隔离块 706相接触即可； 利用氧等离子体干法去胶以及硫酸 /双 氧水湿法去胶相结合的方法去除硅片表面的光刻胶； 再次在 P型 Poly-Si层上旋 涂光刻胶， 并通过光刻工艺在最终热偶条形貌对应位置形成光刻胶的图形； 利 用 RIE Poly-Si技术将光刻胶图形转移到 P型 Poly-Si层上，形成第二热偶条 809; 最后， 利用氧等离子体干法去胶以及硫酸 /双氧水湿法去胶相结合的方法去除硅 片表面的光刻胶。其中， 第一热偶条 807、第二热偶条 809的宽度为 5μηι， 第一 热偶条 807的长度为 120μηι， 第二热偶条 809的长度为 105μιη， 第一热导通电 隔离块 705与邻近的第二热导通电隔离块 706间设置第一热偶条 807及第二热 偶条 809的对数为 96， 并沿着长方形吸收区的两边对称放置。 本发明具体实施 时， 第一热偶条 807及第二热偶条 809的对数可以根据实际需要任意设置， 并 不局限于本发明实施例中所列举的对数及相应的尺寸。
上述形成的第一热偶条 807与图 17中的 Ν型热偶条 3相对应一致，第二热 偶条 809与 Ρ型热偶条 4相对应一致； Ν型热偶条 3与 Ρ型热偶条 4成对出现， 形成一个热电偶结构。 本发明实施例中， Ν型热偶条 3与 Ρ型热偶条 4之间形 成热电偶， Ρ型热偶条 4位于 Ν型热偶条 3的上方， Ν型热偶条 3的热端与第 二热导通电隔离结构 2相连， Ν型热偶条 3的冷端通过第一热导通电隔离结构 1 及热传导体 303与衬底 101相连， 以使得整个热电堆的探测冷端与衬底 101的 温度保持一致， 通过第一热导通电隔离结构 1及第二热导通电隔离结构 5实现 电绝缘隔离的作用。
i、 在上述第二热偶条 809上方设置热偶条保护层 908， 所述热偶条保护层 908覆盖的区域包括第二热偶条 809、 第一热导通电隔离块 705， 及第二热导通 电隔离块 706的一半； 在相邻的第二热导通电隔离块 706之间淀积黒硅材料体 909, 所述黒硅材料体 909与第二热导通电隔离块 706相接触；
如图 9所示，在已经实现热探测结构的衬底 101上利用 LPCVD技术淀积生 长厚度为 4000A的 Si02层； 随后， 在热偶条保护层 908上旋涂光刻胶， 并通过 光刻工艺在热偶条所在区域形成大面积的光刻胶图形； 利用 RIE 02技术将光 刻胶图形转移到 Si02层上， 形成热偶条保护层 908, 其中， 热偶条保护层 908 完全覆盖位于热偶条冷端的第一热导通电隔离结构 1 ,而位于热偶条热端的第二 热导通电隔离结构 2不被热偶条保护层 908完全覆盖， 露出部分的尺寸宽度为 ΙΟμπι, 本发明实施例中， 热偶条保护层 908覆盖第二热导通电隔离块 706的一 半， 热偶条保护层 908不完全覆盖第二热通道电隔离块 706， 主要是保证黒硅材 料体 909与第二热通道电隔离块 706的接触，以保证后续形成黒硅红外吸收区 7 吸收的热量通过第二热通道电隔离块 706能传导到热电偶上，热偶条保护层 908 覆盖第二热导通电隔离块 706 的面积还可以根据需要来设置， 只要能保证黒硅 红外吸收区 Ί吸收的热量通过第二热通道电隔离块 706能传导到热电偶上即可； 利用氧等离子体干法去胶以及硫酸 /双氧水湿法去胶相结合的方法去除硅片表面 的光刻胶;在此之后，通过 LPCVD技术淀积生长厚度为 2μιη的黒硅材料体 909, 所述黒硅材料体 909的材料为 Poly-Si,然后在吸收区位置形成 Poly-Si层的图形 化， 该图形化的黒硅材料体 909 同样趴跨在位于热偶条热端的第二热导通电隔 离结构 2上， 如图中的趴跨区域 910所示； 利用氧等离子体干法去胶以及硫酸 / 双氧水湿法去胶相结合的方法去除硅片表面的光刻胶。 本发明实施例中， 黑硅 材料体 909还可以采用 PECVD (等离子体增强化学气相沉积）技术淀积生长得 到。
j、 选择性地掩蔽和刻蚀上述热偶条保护层 908， 以形成用于连接第一热偶 条 807及第二热偶条 809所需的电连接通孔 1008;
如图 10所示， 在衬底表面旋涂光刻胶， 并在对应于电连接通孔 1008的位 置通过光刻工艺形成光刻胶图形的开口， 随后利用 RIE Si02技术将光刻胶上的 开口图形转移到热偶条保护层 908上形成开口图形，也即形成电连接通孔 1008; 最后， 利用氧等离子体干法去胶以及硫酸 /双氧水湿法去胶相结合的方法去除硅 片表面的光刻胶。 所形成的电连接通孔 1008的结构尺寸为 1 μηι><1μιη。
k、 在上述已制作电连接通孔 1008的衬底 101上溅射金属层， 所述金属层 填充在上述电连接通孔 1008内， 选择性地掩蔽和刻蚀上述金属层， 使得第一热 偶条 807在第二热导通电隔离块 706的一端与第二热偶条 809通过第一连接线 1109电连接； 在第一热导通电隔离块 705的一端， 第二热偶条 809通过第二连 接线 1111与邻近热电偶的第一热偶条 807电连接， 并在第一热导通电隔离结构 705的外侧形成第一电连接体 1110;
如图 11所示， 在制作了电连接通孔 1008的衬底 101上溅射 A1金属层， 并 通过光刻工艺使 A1金属层在电连接位置和金属电极位置图形化， 形成第一连接 线 1109、和第二连接线 1111及第一电连接体 1110; 随后采用有机清洗的方法去 除硅片表面的光刻胶。其中， A1金属的图形化采用 A1腐蚀液湿法腐蚀的方法实 现， A1腐蚀液中磷酸 （浓度为 60%〜80%)： 醋酸 （浓度为 0.1%): 硝酸（浓度 为 0.5%): 水的比例为 16: 1： 1： 2。
1、 在上述制作了第一连接线 1109、 第二连接线 1111和第一电连接体 1110 的衬底 101表面上淀积钝化层 1211， 所述钝化层 1211覆盖黒硅材料体 909、 第 一连接线 1109、 第二连接线 1111及第一电连接体 1110;
如图 12所示， 在实现了金属连接的衬底 101上采用 PECVD技术淀积生长 厚度为 2000 A的 Si02层作为钝化层 1211。 其中， PECVD淀积钝化层 1211时 腔体的温度为 270°C， 压力为 250 mTorr， Si 的浓度为 4.6%, N20流量为 150 sccm, 功率为 103 W。
m、 选择性地掩蔽和刻蚀上述钝化层 1211， 以在黒硅材料体 909上的钝化 层 1211上形成黒硅刻蚀窗口 1311， 利用黒硅刻蚀窗口 1311对黒硅材料体 909 进行刻蚀， 直至刻蚀到黒硅刻蚀窗口 1311正下方的热传导体 303, 以形成释放 孔 1309;
如图 13所示， 在钝化层 1211上旋涂光刻胶， 通过光刻工艺使光刻胶在器 件中对应于吸收区区域内部、 热偶条与热偶条之间的区域以及封闭开口所围面 积内除热偶条区域和吸收区区域外的大面积区域中形成光刻胶的开口； 随后， 分别利用 RIE Si02、 RIE Poly-Si和 RIE Si02技术将光刻胶的开口图形转移到不 同的材料层上， 也即形成释放孔 1309和黒硅刻蚀窗口 1311 ; 为了保护吸收区区 域的 Poly-Si不被释放气体损坏， 在吸收区区域内部的腐蚀开口侧壁通过光刻涂 覆一层释放遮挡层 1312， 所述释放遮挡层 1312为光刻胶， 释放遮挡层 1312的 厚度为 2.5μπι，进而该涂覆了释放遮挡层 1312后的腐蚀释放通道 6的尺寸縮小， 本发明实施例中，黒硅刻蚀窗口 1311及释放孔 1309—起形成了腐蚀释放通道 6。
η、 利用释放阻挡带结构 503释放黒硅材料体正下方的热传导体 303， 以得 到热隔离腔体 1403;
如图 14所示： 由于热传导体 303的材料为多晶硅， 因此采用 XeF2干法刻 蚀技术各向同性刻蚀器件结构中的热传导体 303，通过腐蚀释放通道 6将热传导 体 303的多晶硅腐蚀掉， 进而形成热隔离腔体 1403。 图 14中的黒硅材料的释放 遮挡层 1412与图 13中的释放遮挡层 1312对应一致。
o、 利用钝化层 1211作为黒硅材料体 909表面粗糙结构的侧墙材料层， 对 黒硅材料体 909采用一次 RIE, 以形成基于黒硅结构 1509的黒硅红外吸收区 7， 同时形成第二电连接体 1510。
如图 15所示， 利用粗糙的黒硅材料体 909及覆盖黒硅材料体 909表面的钝 化层 1211可作为黒硅材料体 909表面粗糙结构的侧墙材料层的特点， 采用一次 RIE Poly-Si技术加工黑硅结构 1509,黒硅结构 1509为针状或柱状结构；在各向 异性刻蚀过程中，第一电连接体 1110上的钝化层 1211被完全刻蚀，进而露出第 二电连接体 1510,最终得到以黑硅为吸收区材料的新型 MEMS热电堆红外探测 器， 总体结构示意图如图 17所示。 本发明中黑硅红外吸收区 7的制备利用了粗 糙的 Poly-Si表面可作为侧墙支撑结构的特性， 并结合高选择比的各向异性刻蚀 技术实现， 本发明中制备黑硅红外吸收区 7的黑硅材料体 909 (黑硅材料体 909 的材料为 Poly-Si) 层可以采用 PECVD或低压化学气相沉积 （LPCVD) 技术淀 禾只生长得到。
' 其中黑硅结构 1509的扫描电镜照片及其红外吸收光谱如图 16所示。 本发 明实施例中， 第二电连接体 1510与第一电连接体 1110相对应一致， 并与图 Π 中的金属电极 9相对应一致， 用于将整个热电堆红外探测结构探测的结果向外 输出。
由本发明实施例的制造方法得到的热电堆红外探测器结构， 主要性能参数 的理论计算结果为： 响应率为 249 V/W; 探测率为 2.25E8 cmHz^ 1; 热响应 时间为 15.3 ms; 噪声密度为 35 nV/Hz1/2。
如图 1~17所示： 工作时， 通过黒硅红外吸收区 7吸收红外线的热量， 黒硅 红外吸收区 7吸收的热量通过第二热导通电隔离结构 2传导到黒硅红外吸收区 7 两侧的热探测结构内， 热电堆的探测冷端通过第一热导通电隔离结构 1 及热传 导体 303与衬底 101相连， 以使得冷端温度与衬底 101的温度保持一致， 并达 到电隔离的作用。 热电堆内的 N型热偶条 3与 P型热偶条 4形成热电偶结构， 热电堆的探测热端吸收热量后与探测冷端的温度差会在冷端产生一定的电势 差， 热电堆内的多个热电偶串接后并通过金属电极 9 向外输出， 通过对输出电 压判断达到所需的检测过程。
本发明采用黒硅红外吸收区 7， 因黑硅的红外吸收效率高进而具有高响应 率、 高探测率等性能特点， 从而克服了以 Si3N4为吸收区材料的探测器响应率、 探测率不高的问题。 因黑硅的制备对工艺参数 （如所生长 Si02、 Poly-Si厚度， 刻蚀的时间及厚度等） 没有非常苛刻的要求， 因此基于黑硅的红外探测器件结 构更易于实现，从而克服了以 1/4波长谐振结构为吸收区的探测器对工艺参数的 要求过高继而性能参数可控性差的缺陷。 因黑硅在较大波长范围内都具有很高 的红外吸收效率， 因此该器件的适用波长范围大， 克服了以 1/4波长谐振结构为 吸收区的探测器仅适用于单一波长范围的不足。 本发明的制备过程采用"释放先 行， 黑硅后行"的技术思路， 有效克服了"黑硅先行， 释放后行"技术方法中黑硅 结构易受损的问题。 本发明探测器在热电堆的冷端 /热端分别进行了热导通电隔 离结构的设计与制作， 有利于进一步提高器件的性能。 该器件的加工过程与 CMOS 工艺完全兼容， 因而有利于传感器件结构和测试电路的单片集成制造。 由本发明提供的新型高性能 MEMS热电堆红外探测器具有工艺兼容性好， 器件 结构易于实现， 便于单片集成， 响应率、 探测率高等特点， 可在温度传感器、 气敏传感器、 热流量计等传感探测器件与系统中获得广泛和实际的应用。

Claims

权 利 要 求 书
一种高性能 MEMS 热电堆红外探测器结构， 包括衬底 （101 ); 其特征 是： 所述衬底 （101 ) 上设有释放阻挡带 （2), 所述释放阻挡带 （2) 内具有热 塥离腔体（1403 )， 所述热隔离腔体（1403 )的正上方设有黒硅红外吸收区（7)， 听述黒硅红外吸收区 （7)位于释放阻挡带 （2) 上； 黒硅红外吸收区 （7) 的外 则设有若干热电堆， 黒硅红外吸收区 （7) 外侧的若干热电堆相互串接后电连接 成一体； 所述热电堆对应邻近黒硅红外吸收区 （7) 的一端形成探测热端， 热电 唯对应远离黒硅红外吸收区 （7) 的一端形成探测冷端； 热电堆的探测冷端通过 第一热导通电隔离结构 （1 ) 及所述第一热导通电隔离结构 （1 ) 下方的热传导 体 （303 ) 与衬底 （101 ) 相连， 热传导体 （303 ) 位于热隔离腔体 （1403 ) 的外 部， 并位于释放阻挡带 （2) 及衬底 （101 ) 之间， 第一热导通电隔离结构 （1 ) 眹置于释放阻挡带 （2) 内； 热电堆的探测热端通过第二热导通电隔离结构 （5) 与黒硅红外吸收区 （7) 相接触， 第二热导通电隔离结构 （5 ) 位于释放阻挡带 (2) 上。
2、 根据权利要求 1所述的高性能 MEMS热电堆红外探测器结构， 其特征 是： 所述黒硅红外吸收区 （7) 包括将黒硅材料体 （909) 利用反应离子刻蚀形 成的黒硅结构 （1509) 及贯通所述黒硅红外吸收区 （7) 的腐蚀释放通道 （6)， 听述腐蚀释放通道 （6) 与热隔离腔体 （1403 ) 相连通。
3、 根据权利要求 1所述的高性能 MEMS热电堆红外探测器结构， 其特征 是： 所述热电堆包括 P型热偶条 （4)及与所述 P型热偶条 （4) 对应配合的 N 型热偶条（3 )， 所述 N型热偶条（3 )与 P型热偶条（4)通过遮挡隔离层（808) 相隔离； P型热偶条 （4) 与 N型热偶条 （3 ) 在形成探测热端的一端通过第一 连接线 （1109) 电连接， 且在形成探测冷端的一端， P型热偶条 （4) 通过第二 连接线 （1111 ) 与相邻热电偶内的 N型热偶条（3 ) 电连接， 以将热电偶相互电 连接成一体构成热电堆。
4、 根据权利要求 1所述的高性能 MEMS热电堆红外探测器结构， 其特征 是： 所述第一热导通电隔离结构 （1 ) 及第二热导通电隔离结构 （5) 的材料均 包括 Si3N4。
5、 根据权利要求 1所述的高性能 MEMS热电堆红外探测器结构， 其特征 是：所述黒硅红外吸收区（7)外侧串接后的热电堆上设置电连接的金属电极 (9)。
6、 根据权利要求 3所述的高性能 MEMS热电堆红外探测器结构， 其特征 是： 所述 N型热偶条（3)位于 P型热偶条（4) 下方， N型热偶条（3 )位于释 改阻挡带 （2) 上， N型热偶条 （3 ) 的探测冷端与第一热导通电隔离结构 （1 ) 相接触， 并通过第一热导通电隔离结构 （1 ) 与热传导体 （303 ) 相接触； N型 热偶条 （3 ) 的探测热端趴跨第二热导通电隔离结构 （5 ) 的一端， 第二热导通 电隔离结构 （5 ) 的另一端与黒硅红外吸收区 （7) 接触。
7、 一种高性能 MEMS 热电堆红外探测器结构的制备方法， 其特征是， 所 述 MEMS热电堆红外探测器结构的制备方法包括如下步骤：
(a)、提供衬底（ 101 ),并在所述衬底（ 101 )的表面上设置衬底保护层（ 102);
(b)、 选择性地掩蔽和刻蚀上述衬底保护层 （102)， 以在衬底 （101 )上方 形成衬底接触窗口 （202)， 所述衬底接触窗口 （202) 贯通衬底保护层 （102);
(c)、 在上述衬底接触窗口 （202) 上方淀积热传导体 （303 )， 并在所述热 传导体 （303 ) 上淀积热传导体掩膜层 （304)， 所述热传导体 （303 ) 覆盖于衬 底保护层 （102) 上并填充在衬底接触窗口 （202) 内；
(d)、 选择性地掩蔽和刻蚀上述热传导体掩膜层 （304)， 以在热传导体掩 膜层 （304) 上形成热传导体刻蚀窗口 （404)， 所述热传导体刻蚀窗口 （404) 贯通热传导体掩膜层 （304)， 并在衬底接触窗口 （202) 的内侧； 利用热传导体 刻蚀窗口 （404) 刻蚀热传导体 （303 ) 直至衬底保护层 （102)， 得到热传导体 通孔 （403 );
(e)、在上述热传导体掩膜层（304)上淀积支撑层（505)，所述支撑层（505) 填充于热传导体通孔 （403 ) 及热传导体刻蚀窗口 （404) 内， 并覆盖于热传导 体掩膜层 （304) 上， 以在衬底 （101 ) 上方形成释放阻挡带结构 （503)及介质 支撑膜 (504)；
(f)、 选 ^性地掩蔽和刻蚀支撑层 （505 )， 以在支撑层 （505 ) 内形成热导 通电隔离开口 （605 )， 所述热导通电隔离开口 （605 ) 贯通支撑层 （505) 并位 于释放阻挡带结构 （503 ) 的外侧； 在上述支撑层 （505 ) 上方淀积热导通电隔 离体层 （606)， 所述热导通电隔离体层 （606) 填充于热导通电隔离开口 （605) 内， 并覆盖于支撑层 （605) 上；
(g)、 选择性地掩蔽和刻蚀上述热导通电隔离体层 （606)， 以在上述支撑 层 （505 ) 上形成第一热导通电隔离块 （705 ) 及第二热导通电隔离块 （706)， 所述第一热导通电隔离块 （705 ) 位于支撑层 （505 ) 内， 第二热导通电隔离块
(706) 位于支撑层 (605) 上;
(h)、 在上述第一热导通电隔离块 （705 ) 及与所述第一热导通电隔离块 (705)邻近的第二热导通电隔离块（706) 间设置第一热偶条 （807) 及第二热 偶条 （809)， 第一热偶条 （807) 与第二热偶条 （809) 的导电掺杂类型不同， 第一热偶条 （807) 与第二热偶条 （809) 间通过遮挡隔离层 （808) 隔离， 第一 热偶条 （807) 的一端与第一热导通电隔离块 （705 ) 相接触， 另一端与第二热 导通电隔离块 （706) 相接触；
(i)、 在上述第二热偶条 （809) 上方设置热偶条保护层 （908)， 所述热偶 条保护层（908)覆盖的区域包括第二热偶条（809)及第一热导通电隔离块 (705); 在相邻的第二热导通电隔离块 （706)之间形成黒硅材料体 （909)， 所述黒硅材 料体 （909) 与第二热导通电隔离块 （706) 相接触；
(j )、选择性地掩蔽和刻蚀上述热偶条保护层（908)， 以形成用于连接第一 热偶条 （807) 及第二热偶条（809)所需的电连接通孔 （1008);
(k)、 在上述已制作电连接通孔 （1008) 的衬底 （101 )上溅射金属层， 所 述金属层填充在上述电连接通孔 （1008) 内， 选择性地掩蔽和刻蚀上述金属层， 使得第一热偶条（807)在第二热导通电隔离块（706)的一端与第二热偶条（809) 通过第一连接线 （1109) 电连接； 在第一热导通电隔离块 （705 ) 的一端， 第二 热偶条（809)通过第二连接线（1111 )与邻近热电偶的第一热偶条（807) 电连 接， 并在第一热导通电隔离结构 （705) 的外侧形成第一电连接体（1110);
(1)、 在上述制作了第一连接线 （1109)、 第二连接线 （1111 ) 和第一电连 接体（1110) 的衬底（101 )表面上淀积钝化层 （1211 ), 所述钝化层（1211 )覆 盖黒硅材料体 （909)、 第一连接线 （1109)、 第二连接线 （1111 ) 及第一电连接 体 （1110);
(m)、 选择性地掩蔽和刻蚀上述钝化层 （1211 ), 以在黒硅材料体 （909) 上的钝化层 （1211 ) 上形成黒硅刻蚀窗口 （1311 )， 利用黒硅刻蚀窗口 （1311 ) 对黒硅材料体 （909) 进行刻蚀， 直至刻蚀到黒硅刻蚀窗口 （1311 ) 正下方的热 传导体 （303 )， 以形成释放孔 （1309);
(n)、 利用释放阻挡带结构 （503 ) 释放黒硅材料体 （909) 正下方的热传 导体 （303)， 以得到热隔离腔体 （1403);
( 0)、 利用钝化层 （1211 ) 作为黒硅材料体（909) 表面粗糙结构的侧墙材 料层， 对黒硅材料体 （909) 采用一次 RIE， 以形成基于黒硅结构 （1509) 的黒 硅红外吸收区 （7)， 同时形成第二电连接体 （1510)。
8、 根据权利要求 7所述高性能 MEMS热电堆红外探测器结构的制备方法， 其特征是： 所述步骤 （m) 和步骤 （n) 中， 在释放孔 （1309) 的内壁上涂覆黒 硅材料的释放遮挡层 （1412)。
9、 根据权利要求 7所述高性能 MEMS热电堆红外探测器结构的制备方法， 其特征是： 所述步骤 （h) 中， 第一热偶条 （807) 为 N导电掺杂类型， 第二热 偶条（809) 为 P导电掺杂类型。
10、根据权利要求 7所述高性能 MEMS热电堆红外探测器结构的制备方法， 其特征是： 所述步骤 （k) 中， 金属层的材料包括 Al。
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