WO2014026304A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

Info

Publication number
WO2014026304A1
WO2014026304A1 PCT/CN2012/001375 CN2012001375W WO2014026304A1 WO 2014026304 A1 WO2014026304 A1 WO 2014026304A1 CN 2012001375 W CN2012001375 W CN 2012001375W WO 2014026304 A1 WO2014026304 A1 WO 2014026304A1
Authority
WO
WIPO (PCT)
Prior art keywords
material layer
layer
forming
high mobility
substrate
Prior art date
Application number
PCT/CN2012/001375
Other languages
English (en)
French (fr)
Inventor
马小龙
殷华湘
付作振
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US13/812,502 priority Critical patent/US20140057418A1/en
Publication of WO2014026304A1 publication Critical patent/WO2014026304A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02452—Group 14 semiconducting materials including tin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02535—Group 14 semiconducting materials including tin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02614—Transformation of metal, e.g. oxidation, nitridation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed

Definitions

  • the present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a method of fabricating a semiconductor structure having a high mobility channel region on an insulator. Background technique
  • the critical parameters of the device such as the threshold voltage
  • the advantages of reduced power consumption and increased integration promote the overall performance of the device.
  • the driving capability of the device is limited by the traditional silicon material process, the carrier mobility is low, and the device driving capability is insufficient. Therefore, high mobility channel devices have important application backgrounds in the future.
  • GeSn alloy which has high carrier mobility and can adjust the band structure of the alloy by adjusting the Sn content, making it widely used in advanced CMOS devices and optoelectronic devices.
  • a method for fabricating a high mobility material layer comprising: forming a plurality of precursors in and/or on a substrate; pulsed laser treatment to cause a plurality of precursors to react with each other to form a high migration Rate material layer.
  • the step of forming a plurality of precursors further comprises: implanting a dopant into the substrate to form a precursor in the substrate.
  • the implantation energy is 10KeV ⁇ 300KeV
  • the implantation dose is 1E15 ⁇ lE17/cm 2 .
  • the implantation dose and energy of one of the plurality of precursors are adjusted to control the composition of the high mobility material layer.
  • the step of forming a plurality of precursors further comprises: depositing a precursor on the substrate.
  • the number of pulsed laser processed pulses, the energy density, the pulse time, and the thickness of one of the plurality of precursors are adjusted to control the thickness of the high mobility material layer.
  • the method further comprises: forming a protective layer on the precursor.
  • the method of forming the protective layer includes low temperature deposition, spin coating, screen printing, and spray coating.
  • the substrate includes Si, SOL Ge, GeOI, SiGe, InP, InGaAs, GaAs, GaN, InSb.
  • the substrate has a lattice constant between 5.4 and 6.4A.
  • the substrate is a single crystal material, and the crystal orientation includes (100), (1 10), (1 1 1).
  • the precursors include: Ge, Sn, In, Ga, Si, As, P, N, Sb.
  • the high mobility material layer includes: GeSn, SiGeSn, InGeSn, GaGeSn, InGaAs
  • the present invention also provides a method of fabricating a semiconductor device using the above method for fabricating a high mobility material layer, comprising: forming a buffer layer on an insulating substrate; and using the above method for fabricating a high mobility material layer on a buffer layer Forming a first high mobility material layer; forming a second high mobility material layer on the first high mobility material layer using the high mobility material layer manufacturing method; forming in the first and second high mobility material layers
  • the trenches isolate and define the active area.
  • the first high mobility material layer and/or the second high mobility material layer comprises GeSn.
  • the step of forming a buffer layer on the insulating substrate further comprises: forming an insulating layer on the substrate; forming an insulating layer opening exposing the substrate in the insulating layer; and selectively epitaxially growing the buffer layer in the opening of the insulating layer.
  • an insulating layer is formed by thermal oxidation.
  • the buffer layer comprises SiGe
  • the substrate comprises Si
  • the step of forming the first high mobility material layer further comprises: sequentially forming a first material layer and a second material layer on the buffer layer; performing a first laser processing, irradiating the first material layer and the second material layer with a laser pulse And causing the first material layer and the second material layer to react to form a first high mobility material layer.
  • the step of forming the second high mobility material layer further comprises: sequentially forming a third material layer and a fourth material layer on the first high mobility material layer; performing a second laser processing, and irradiating the third material with the laser pulse
  • the layer and the fourth material layer are such that the third material layer and the fourth material layer react to form a second high mobility material layer.
  • first material layer and/or the third material layer comprise Ge
  • second material layer and/or the fourth material layer comprise Sn.
  • the step of forming trench isolation and defining an active region further includes: forming a photoresist pattern on the second high mobility material layer, having a photoresist opening, wherein the photoresist opening corresponds to the buffer layer; Etching the second high mobility material layer, the first high mobility material layer, and the buffer layer until the substrate is exposed to form a trench; depositing an insulating material in the trench to form trench isolation, and the second high mobility surrounded by the trench isolation The material layer, the first high mobility material layer constitutes an active region.
  • the semiconductor device manufacturing method of the present invention by adjusting the number of pulses and the energy density of the laser processing, a plurality of layers of high mobility materials are formed on the insulating substrate to be used as a channel region of the device, thereby effectively improving the device loading.
  • the mobility of the carriers further increases the device driving capability.
  • 1 to 12 are schematic cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention
  • FIG. 13 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.
  • FIG. 14 is a flow chart of a method of fabricating a high mobility material layer in accordance with an embodiment of the present invention.
  • Thin can be used to modify various device structures. These modifications are not intended to imply a spatial, order, or hierarchical relationship to the structure of the device being modified.
  • a substrate is provided.
  • the substrate may be bulk Si, SOL body Ge, GeOI, SiGe, GeSb, or other III-V or II-VI compound semiconductor substrate such as GaAs, GaN, InP, InSb, InGaAs or the like.
  • substrate 1 is preferably a bulk Si, i.e., a silicon wafer.
  • the substrate has a lattice constant between 5.4 and 6.4A.
  • the substrate is a single crystal material whose crystal orientation may be (100), (1 10), (1 1 1).
  • a precursor is formed in/on the substrate.
  • a precursor can be formed in the substrate.
  • ion implantation is performed, and a high dose of Ge and Sn are implanted into the substrate for forming GeSn.
  • a variety of precursors can be formed.
  • the implantation energy is, for example, 10 KeV to 300 KeV, and the implantation dose is, for example, 1E15 to 1E17/cm 2 .
  • these implanted ions amorphize a region of a certain thickness on the surface of the substrate to facilitate diffusion of the precursor at a later laser irradiation treatment.
  • the distance (thickness) of the amorphized region from the upper surface of the substrate is, for example, from 1 to 100 nm.
  • two precursors can be formed on the substrate.
  • the Ge layer is deposited on the surface of the substrate by PECVD, HDPCVD, MBE, ALD, etc., and has a thickness of, for example, 1 to 50 nm.
  • a metal Sn layer is deposited on the Ge layer by sputtering, MOCVD, MBE or the like, and has a thickness of, for example, 5 to 40 nm.
  • a protective layer is formed on the precursor.
  • a method such as PECVD, LPCVD, or the like is used to lower the deposition temperature to form a low temperature protective layer, that is, a low temperature deposition protective layer such as low temperature silicon oxide (LTO), and a deposition temperature of, for example, lower than 400 ° C to prevent Ge and Sn from reacting in advance at this time.
  • a low temperature deposition protective layer such as low temperature silicon oxide (LTO)
  • LTO low temperature silicon oxide
  • a deposition temperature for example, lower than 400 ° C to prevent Ge and Sn from reacting in advance at this time.
  • spin coating, screen printing, spraying, etc., using PSG, BPSG and other glass materials, or even a resin material such as photoresist to form a protective layer to avoid a little After the laser treatment is excessive and the material is damaged.
  • the protective layer can also be omitted.
  • the so-called high mobility means that the mobility of holes or electrons in the material layer is greater than the mobility of holes or electrons in the channel region of the silicon material substrate in the conventional CMOS process, and preferably, the high mobility is the mobility in Si. More than 1.5 times.
  • the high mobility layer is GeSn.
  • the number of laser-processed pulses is ml (for example, an integer from 1 to 100), the energy density is fl (for example, 100 mJ/cm 2 to lJ/cm 2 ), the laser wavelength is 157 nm to 10.6 ⁇ m, and the pulse time width is tl ( For example, lns ⁇ 10 ys ).
  • the thickness of the alloy layer can be controlled.
  • the dose and energy of one (e.g., Sn) in the implanted precursor are adjusted to adjust the composition of the alloy (e.g., GeSn), e.g., to adjust the ratio.
  • the high mobility layer may be Gel-xSnx, wherein preferably 0 ⁇ x ⁇ 0.3, and the thickness is, for example, 5 nm to 200 nm.
  • a buffer layer is formed on an insulating substrate.
  • a substrate 1 is provided, which may be bulk Si, SOL Ge, GeOI, SiGe, GeSb, or a III-V or II-VI compound semiconductor substrate, such as GaAs, GaN, InP. , InSb, etc. Further, it may be a transparent substrate such as glass, plastic or resin.
  • substrate 1 is preferably a bulk Si, i.e., a silicon wafer.
  • the substrate has a lattice constant between 5.4 and 6.4A.
  • the substrate is a single crystal material whose crystal orientation may be (100), (110), (11 1).
  • an insulating layer 2 is formed on the substrate 1.
  • the insulating layer 2 made of silicon oxide is formed by, for example, LPCVD, PECVD, HDPCVD, thermal oxidation or the like for insulating the isolation substrate to reduce substrate leakage current and/or parasitic effects.
  • the silicon oxide layer 2 is formed by thermal oxidation to improve the quality of the insulating layer 2 and to reduce defects.
  • the thickness of the insulating layer 2 depends on the isolation performance of the device, for example, 10 to 500 nm.
  • the lithography/etching of the insulating layer 2 until the exposed substrate 1 is formed in the insulating layer 2 A plurality of insulating layer openings 2A are formed.
  • the plurality of insulating layer openings 2A are shown as left and right in FIG. 3, but actually in a top view (not shown), an annular open frame at the periphery of the region corresponding to the active region of the future device, in other words, insulation
  • the area inside the layer opening 2A will be formed and defined in the future, and the area outside the opening 2A of the insulating layer corresponds to the device isolation region.
  • the width of the insulating layer opening 2A (that is, the inner and outer side spacing of the annular frame) depends on the size of the device, and is specifically determined according to the width of the active region and the need for lattice transition adjustment, for example, 50 to 1000
  • the buffer layer 3 is selectively epitaxially grown. Since the Si material of the substrate 1 is different from the silicon oxide material of the insulating layer 2, the buffer layer 3 formed by an epitaxial process such as MBE or ALD will preferably grow only in the opening 2A of the insulating layer, that is, selective epitaxial growth.
  • the lattice constant of the material of the buffer layer 3 is between the substrate 1 and the lattice constant of the high mobility material to be formed later.
  • the buffer layer 3 may be SiGe in order to control the GeSn growth crystal orientation and reduce the lattice loss between the substrate 1 and the future high mobility material channel layer.
  • Match. SiGe can be specifically determined according to the need to adjust the lattice mismatch, such as Sil-zGez, where the percentage of Ge atoms can be greater than or equal to 50%, i.e., 0.5 ⁇ ⁇ ⁇ 1.
  • a planarization process such as CMP is performed after selectively epitaxially growing the buffer layer 3 until the insulating layer 2 is exposed so that the thickness of the buffer layer 3 is the same as the thickness of the insulating layer opening 2A.
  • the first high mobility material layer is formed on the buffer layer by using the method shown in FIG. 14 to be used as a part of the channel region of the future device, and thus may also be referred to as First channel layer.
  • the high mobility refers to the mobility of holes or electrons in the material layer, and preferably, the high mobility is 1.5 times or more the mobility in Si.
  • a first material layer 4A and a second material layer 5A are sequentially deposited on the insulating layer 2 and the buffer layer 3.
  • the deposition method includes PECVD, MBE, ALD, sputtering, and the like.
  • the first high mobility material layer is GeSn
  • the first material layer 4A is amorphous Ge and has a thickness t1
  • the second material layer 5A is a metal Sn and has a thickness t2, the thickness of which is arbitrarily set according to the alloy ratio .
  • a method of PECVD, LPCVD or the like is applied on the second material layer 5A and the deposition temperature is lowered to form a low temperature protective layer, such as low temperature silicon oxide (LTO), and the deposition temperature is, for example, lower than 400 ° C to avoid Ge and Sn advance at this time.
  • a glass material such as PSG or BPSG may be spin-coated, or even a resin material such as a photoresist may be used to form a protective layer for avoiding excessive laser processing and damaging the material.
  • the laser can be well adjusted
  • the protection parameters can also be omitted.
  • the first laser processing is performed, and the first material layer 4A and the second material layer 5A are irradiated with laser pulses, so that the surface of the sample is rapidly heated to melt and react, and the same as the lining during the cooling process.
  • the number of pulses processed by the laser is ml (for example, an integer from 1 to 100)
  • the energy density is ⁇ (for example, 100 mJ/cm 2 to U/cm 2 )
  • the laser wavelength is 157 nm to 10.6 ⁇ m
  • the pulse time width is tl ( For example, lns ⁇ 10 s ).
  • the first high mobility layer 6A formed by the reaction may be Gel-xSnx, wherein preferably 0 ⁇ x ⁇ 0.1, and the thickness of the first high mobility layer 6A is, for example, 5 nm ⁇ 200nm.
  • the number of laser pulses and the energy density can be adjusted to control the Sn content in the Ge!-xSnx, it is limited by the lattice and crystal orientation of the SiGe of the underlying buffer layer 3, and the Sn content is usually not increased even if it is increased. Will be higher than 0.1, which is not sufficient for devices that require a higher mobility channel region, and therefore requires further processing of the present invention.
  • a second high mobility material layer is formed on the first high mobility material layer for use as a second portion of the future channel region, and thus is also referred to as a second channel layer.
  • the carrier mobility of the second high mobility material layer is greater than the carrier mobility of the first high mobility material layer.
  • the second high mobility material layer can be formed in the same manner. Specifically, as shown in Fig. 8, a third material layer 4B and a fourth material layer 5B are sequentially deposited on the first high mobility material layer 6A. Deposition methods include PECVD, MBE, ALD, sputtering, and the like. Wherein, if the second high mobility material layer is the same material as the first high mobility material layer, the third material layer 4B is the same material as the first material layer 4A, and the fourth material layer 5B is the same material as the second material layer 5A. .
  • the third material layer 4B is amorphous Ge and has a thickness t3
  • the second material layer 5A is metal Sn and has a thickness t4
  • the thickness of both is arbitrarily set in accordance with the alloy ratio.
  • the second high mobility material layer material may also be different from the first high mobility material layer, such as a SiGeSn alloy, a GaGeSn alloy, an InGeSn, a GeSnAs alloy, or the like, so the third material layer 4B may be Si, Ge, In. , Ga, etc., and the fourth material layer 5B may be Sn, As, or the like.
  • the same protective layer as described above can be formed on the fourth material layer 5B.
  • the second laser processing is performed, and the third material layer 4B and the fourth material layer 5B are irradiated with laser pulses, so that the surface of the sample rapidly heats up and melts, and is the same as in the cooling process. Crystallization of a high mobility material layer, resulting in a final pattern The second high mobility layer 6B shown at 10.
  • the number of pulses processed by the laser is m2 different from the above ml (for example, 10 to 200), and the energy density is f2 different from the above fl (for example, 400 mJ/cm 2 to 2 J/cm 2 ).
  • the second high mobility layer 6A formed by the reaction may be Gel -ySny , where y is greater than x above, preferably 0.1 ⁇ y ⁇ 0.3.
  • the thickness of the second high mobility layer 6B is, for example, 5 nm to 200 nm.
  • more layers may be disposed as needed, for example, a stack structure of three layers, four layers or even more layers of GeSn, or A hybrid stack structure of three or more layers of different high mobility material layers such as SiGe, GaAs, GeSn, InSb, etc., as long as the carrier mobility is gradually increased from the bottom to the top.
  • trench isolation is formed in the first and second high mobility material layers and an active region is defined.
  • a photoresist 7 is coated on the second high mobility material layer 6B, exposed/developed to form a photoresist pattern having a plurality of photoresist openings 7A, and the opening 7A is exposed second. High mobility material layer 6B.
  • the photoresist opening 7A corresponds to the position of the insulating layer opening 2A of the former, that is, constitutes a ring frame.
  • the width of the photoresist opening 7A may be equal to the width of the insulating layer opening 2A/buffer layer 3 as shown in Fig. 11, or may be preferably larger than the insulating layer opening 2A.
  • the second high mobility material layer 6B, the first high mobility material layer 6A, and the buffer layer 3 are sequentially etched by anisotropic dry etching such as plasma etching or reactive ion etching. Until the substrate 1 is exposed, a trench is formed.
  • the trench isolation 8 is formed by depositing an insulating material such as silicon oxide, silicon oxynitride, BPSG, PSG or the like in a trench by LPCVD, PECVD, HDPCVD, spin coating or the like.
  • the trench isolation 8 is of the same shape as the photoresist opening 7A and the insulating layer opening 2A, and thus has a ring-shaped frame structure, and the second high mobility material layer 6B and the first high mobility material layer 6A surrounded by the inner side serve as source and drain of the device.
  • the region and channel region, i.e., trench isolation 8, define an active region.
  • a gate stack can be formed on the active region in the trench isolation 8 by a CMOS compatible process, a source and drain region can be formed by doping implantation in the active region, and a source/drain contact layer can be formed on the source and drain regions.
  • Forming an interlayer dielectric layer on the entire device etching the interlayer dielectric layer to form a source/drain contact hole, and depositing a metal to form a source/drain contact plug and many more.
  • the semiconductor device manufacturing method of the present invention by adjusting the number of pulses and the energy density of the laser processing, a plurality of layers of high mobility materials are formed on the insulating substrate to be used as a channel region of the device, thereby effectively improving the device implantation.
  • the mobility of the carriers further increases the device driving capability.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

一种高迁移率材料层制造方法，包括：在衬底（1）中和/或上形成多种前驱物；脉冲激光处理，使得多种前驱物相互反应形成高迁移率材料层。此外还提供一种半导体器件制造方法，包括：在绝缘衬底上形成缓冲层（3）；采用上述高迁移率材料层制造方法，在缓冲层上形成第一高迁移率材料层（6A）；采用上述高迁移率材料层制造方法，在第一高迁移率材料层（6A）上形成第二高迁移率材料层（6B）；在第一和第二高迁移率材料层中形成沟槽隔离（8）并定义有源区。该半导体器件制造方法，通过调整激光处理的脉冲个数和能量密度，在绝缘衬底上分多次形成了多层高迁移率材料以用作器件沟道区，有效提高了器件载流子迁移率并进一步提高了器件驱动能力。

Description

半导体器件制造方法 优先权要求
本申请要求了 2012年 8月 16日提交的、 申请号为 201210293349.X、 发明名称为 "半导体器件制造方法" 的中国专利申请的优先权， 其全 部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体集成电路制造领域， 更具体地， 涉及一种在绝 缘体上具有高迁移率沟道区的半导体结构的制造方法。 背景技术
随着集成电路工艺持续发展， 特别是器件尺寸不断等比例缩减， 器件的各个关键参数例如阈值电压等也随之减小， 功耗减小、 集成度 提高这些优点促进了器件整体性能提高。 然而与此同时， 器件的驱动 能力却受制于传统的硅材料工艺的限制， 栽流子迁移率较低， 面临了 器件驱动能力相比而言不足的问题。 因此， 高迁移率沟道器件在未来 具有重要应用背景。
现有的高迁移率沟道器件通常是采用 Si 1 -xGex或 Si1-xCx来作为应力 源漏区向 Si的沟道区施加应力，或者直接采用这些材料作为衬底和沟道 区。 在 Si1 -xGex中引入压应变能够进一步提高空穴的迁移率， 相应地在 在 S^XCX中引入张应变能够进一步提高电子的迁移率。 然而， 这两种材 料晶格常数与 Si差别仍不够大， 能够提供的应变有限， 难以应用在需要 更高驱动能力的器件中。
一种可选的替代材料是 GeSn合金 , 该薄膜具有很高的载流子迁移 率， 并且可以通过调节 Sn的含量调节合金的能带结构， 因此广泛应用 于先进的 CMOS器件和光电子器件中。
然而传统的 GeSn合金需要用分子束外延或者 CVD， 目前仍不成熟 或者与 CMOS不兼容。 此外， 由于 Sn在 Ge中的平衡固溶度非常的低， 因此用常规的方法很难得到 Sn的含量大于 1 %的 Ge1 -xSnx。
此外， 其他高迁移率材料， 诸如 GaAs、 InSb等也存在类似问题， 难以与 Si基的 CMOS工艺兼容。 发明内容
有鉴于此， 本发明的目的在于提供一种衬底上制作高迁移率材料 层以用作沟道区的方法， 克服上述传统工艺的缺陷， 有效提高器件沟 道区载流子迁移率。
实现本发明的上述目的， 是通过提供一种高迁移率材料层制造方 法， 包括： 在衬底中和 /或上形成多种前驱物； 脉沖激光处理， 使得多 种前驱物相互反应形成高迁移率材料层。
其中， 形成多种前驱物的步骤进一步包括： 对衬底注入掺杂剂以 在衬底中形成前驱物。
其中， 注入能量为 10KeV ~ 300KeV, 注入剂量为 1E15 ~ lE17/cm2。 其中， 调整多种前驱物中的一个的注入剂量和能量， 从而控制高 迁移率材料层的成分。
其中， 形成多种前驱物的步骤进一步包括： 在衬底上沉积前驱物。 其中， 调整脉冲激光处理的脉沖个数、 能量密度、 脉沖时间以及 多种前驱物中的一个的厚度， 从而控制高迁移率材料层的厚度。
其中， 在形成多种前驱物之后还包括： 在前驱物上形成保护层。 其中， 形成保护层的方法包括低温沉积、 旋涂、 丝网印刷、 喷涂。 其中， 衬底包括 Si、 SOL Ge、 GeOI、 SiGe、 InP、 InGaAs、 GaAs、 GaN、 InSb。
其中， 衬底的晶格常数在 5.4 - 6.4A之间。
其中， 衬底是单晶材料， 晶向包括 (100)、 （1 10)、 （1 1 1)。
其中， 前驱物包括： Ge、 Sn、 In、 Ga、 Si、 As、 P、 N、 Sb。
其中， 高迁移率材料层包括： GeSn、 SiGeSn、 InGeSn、 GaGeSn、 InGaAs„
此外， 本发明还提供了一种采用上述高迁移率材料层制造方法的 半导体器件制造方法， 包括： 在绝缘衬底上形成緩沖层； 釆用上述高 迁移率材料层制造方法， 在緩沖层上形成第一高迁移率材料层； 采用 上述高迁移率材料层制造方法， 在第一高迁移率材料层上形成第二高 迁移率材料层； 在第一和第二高迁移率材料层中形成沟槽隔离并定义 有源区。
其中， 第一高迁移率材料层和 /或第二高迁移率材料层包括 GeSn。 其中， 在绝缘衬底上形成緩沖层的步骤进一步包括： 在衬底上形 成绝缘层； 在绝缘层中形成暴露衬底的绝缘层开口； 在绝缘层开口中 选择性外延生长緩沖层。
其中， 采用热氧化法形成绝缘层。
其中， 緩沖层包括 SiGe, 衬底包括 Si。
其中， 形成第一高迁移率材料层的步骤进一步包括： 在緩沖层上 依次形成第一材料层和第二材料层； 执行第一激光处理， 采用激光脉 沖照射第一材料层和第二材料层， 使得第一材料层和第二材料层反应 形成第一高迁移率材料层。
其中， 形成第二高迁移率材料层的步骤进一步包括： 在第一高迁 移率材料层上依次形成第三材料层和第四材料层； 执行第二激光处理， 釆用激光脉沖照射第三材料层和第四材料层， 使得第三材料层和第四 材料层反应形成第二高迁移率材料层。
其中， 第一材料层和 /或第三材料层包括 Ge， 第二材料层和 /或第四 材料层包括 Sn。
其中， 形成沟槽隔离并定义有源区的步骤进一步包括： 在第二高 迁移率材料层上形成光刻胶图形， 具有光刻胶开口， 其中光刻胶开口 与緩沖层相对应； 依次刻蚀第二高迁移率材料层、 第一高迁移率材料 层、 緩沖层直至暴露衬底， 形成沟槽； 在沟槽中沉积绝缘材料形成沟 槽隔离， 沟槽隔离包围的第二高迁移率材料层、 第一高迁移率材料层 构成有源区。
依照本发明的半导体器件制造方法， 通过调整激光处理的脉冲个 数和能量密度， 在绝缘衬底上分多次形成了多层高迁移率材料以用作 器件沟道区， 有效提高了器件载流子迁移率并进一步提高了器件驱动 能力。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1至图 12为根据本发明实施例的半导体器件制造方法各步骤的 剖面示意图；
图 13为根据本发明实施例的半导体器件制造方法的流程图； 以及 图 14为根据本发明实施例的高迁移率材料层的制造方法的流程 图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果。 需要指出的是， 类似的附图标记表示类似的结 构， 本申请中所用的术语 "第一" 、 "第二" 、 "上" 、 "下" 、 "厚" 、
"薄" 等等可用于修饰各种器件结构。 这些修饰除非特别说明并非暗 示所修饰器件结构的空间、 次序或层级关系。
首先， 参照图 14， 示出了制造高迁移率材料层的方法的流程。
提供衬底。 衬底可以是体 Si、 SOL 体 Ge、 GeOI 、 SiGe、 GeSb, 也可以是其他 III-V族或者 II-VI族化合物半导体衬底， 例如 GaAs、 GaN、 InP、 InSb、 InGaAs等等。 为了与现有的 CMOS工艺兼容以应用于大规 模数字集成电路制造， 衬底 1优选地为体 Si也即硅晶片。 优选地， 衬底 的晶格常数在 5.4 - 6.4A之间。 优选地， 衬底是单晶材料， 其晶向可以 是 (100)、 （1 10)、 （1 1 1)。
在衬底中 /上形成前驱物。
在本发明一个实施例中， 可以在衬底中形成前驱物。 例如执行离 子注入， 在衬底中注入高剂量的 Ge以及 Sn, 用于形成 GeSn。 此外， 对 于其他材料， 例如 InGeSn、 GaGeSn等， 可以形成多种前驱物。 注入能 量例如为 10KeV ~ 300KeV， 注入剂量例如为 1E15 ~ lE17/cm2。 在注入 前驱物的同时， 这些注入的离子使得衬底表面一定厚度的区域非晶化， 以利于稍后激光照射处理时前驱物的扩散。 非晶化区域距离衬底上表 面的距离 （厚度） 例如是 l ~ 100nm。
在本发明另一个实施例中， 可以在衬底上形成两种前驱物。 例如 先在衬底表面通过 PECVD、 HDPCVD, MBE、 ALD等方式沉积 Ge层， 其厚度例如为 1 ~ 50nm。 随后， 在 Ge层上通过溅射、 MOCVD、 MBE 等方法沉积金属 Sn层， 其厚度例如为 5 ~ 40nm。
优选地， 在前驱物上形成保护层。 例如采用 PECVD、 LPCVD等方 法并且降低沉积温度从而形成低温保护层， 也即低温沉积保护层， 例 如低温氧化硅（LTO ) ， 沉积温度例如低于 400°C以避免此时 Ge与 Sn提 前反应。 或者通过旋涂、 丝网印刷、 喷涂等方法， 采用 PSG、 BPSG等 玻璃材料， 甚至可以是光刻胶等树脂材料来形成保护层， 用于避免稍 后的激光处理过度而损坏材料。 自然， 如果能良好调整激光处理参数， 保护层也可以省略。
然后， 执行激光处理， 采用激光脉沖照射两种前驱物， 使得两种 前驱物表面快速升温融化并且相互反应， 并且在冷却的过程中以相同 于村底的晶向结晶， 最终形成合金而作为高迁移率层。 其中所谓高迁 移率指的是材料层中空穴或者电子的迁移率要大于传统 CMOS工艺中 硅材料衬底沟道区中空穴或者电子的迁移率， 并且优选地， 高迁移率 是 Si中迁移率的 1.5倍以上。 在本发明一个实施例中， 高迁移率层是 GeSn。 激光处理的脉沖个数为 ml (例如是 1 ~ 100的整数） ， 能量密度 为 fl (例如 100mJ/cm2 ~ lJ/cm2 ) , 激光波长为 157nm ~ 10.6 μ m， 脉沖 时间宽度为 tl (例如 lns ~ 10 y s ) 。 调节上迷激光脉沖参数， 可以控制 合金层的厚度。
此外， 在注入形成前驱物的过程中， 调节注入前驱物中一个 （例 如 Sn ) 的剂量和能量， 可以相应调节合金 （例如 GeSn ) 的成分， 例如 调节配比。 具体地， 高迁移率层可以是 Gel-xSnx , 其中优选地 0<x<0.3, 厚度例如是 5nm ~ 200nm。
以上参照流程图 14说明了本发明的高迁移率材料的制造方法， 以 下参流程图 13以及附图 1至 12来详细说明应用了上述高迁移率材料制 造方法来形成半导体器件的方法各个具体步骤。
参照图 13以及图 1至图 4, 在绝缘衬底上形成緩沖层。
如图 1所示，提供衬底 1 , 其可以是体 Si、 SOL体 Ge、 GeOI 、 SiGe、 GeSb , 也可以是 III-V族或者 II-VI族化合物半导体衬底， 例如 GaAs、 GaN、 InP、 InSb等等。 此外， 也可以是玻璃、 塑料、 树脂等透明基板。 为了与现有的 CMOS工艺兼容以应用于大规模数字集成电路制造，衬底 1优选地为体 Si也即硅晶片。优选地，衬底的晶格常数在 5.4 ~ 6.4A之间。 优选地， 衬底是单晶材料， 其晶向可以是 (100)、 （110)、 （11 1)。
如图 2所示， 在衬底 1上形成绝缘层 2。 例如通过 LPCVD、 PECVD、 HDPCVD, 热氧化等工艺形成氧化硅材质的绝缘层 2 , 以用于绝缘隔离 衬底从而减小衬底泄漏电流和 /或寄生效应。 优选地， 采用热氧化法来 形成氧化硅层 2， 以便提高绝缘层 2的质量、 减小缺陷。 绝缘层 2的厚度 依照器件隔离绝缘性能需要而定， 例如是 10 ~ 500nm。
如图 3所示， 光刻 /刻蚀绝缘层 2， 直至暴露村底 1， 在绝缘层 2中形 成多个绝缘层开口 2A。 该多个绝缘层开口 2A在图 3中显示为左右两个， 然而实际上在顶视图 （未示出） 中则为在对应于未来器件有源区的区 域外围的环形开口框， 换言之， 绝缘层开口 2A内侧的区域上未来将形 成并且定义有源区， 而绝缘层开口 2A外侧的区域则对应于器件隔离区。 绝缘层开口 2A的宽度 （也即环形框内外侧边间距） 依照器件尺寸需要 而定， 具体地依照有源区宽度、 晶格过渡调整的需要而确定， 例如是 50 ~ 1000亂
如图 4所示， 在绝缘层 2中的多个绝缘层开口 2A内， 选择性外延生 长緩沖层 3。 由于衬底 1的 Si材质与绝缘层 2的氧化硅材质不同， 采用 MBE、ALD等外延工艺形成的緩沖层 3将优选地仅在绝缘层开口 2A内生 长， 也即选择性外延生长。 緩沖层 3材质的晶格常数要介于衬底 1与稍 后将要形成的高迁移率材料的晶格常数之间。 例如， 当衬底 1是 Si并且 高迁移率材料是 GeSn时， 緩沖层 3可以是 SiGe， 以便控制 GeSn生长晶 向并且降低衬底 1和未来高迁移率材料沟道层之间的晶格失配。 SiGe具 体地可以依照调节晶格失配需要而确定， 例如 Sil-zGez， 其中 Ge原子百 分比可以大于等于 50 %也即 0.5<ζ<1。 优选地， 在选择性外延生长緩冲 层 3之后执行 CMP等平坦化工艺直至暴露绝缘层 2 , 以使得緩冲层 3的厚 度与绝缘层开口 2A厚度相同。
然后， 参照图 13以及图 5至图 7， 选用图 14所示的方法， 在緩冲层 上形成第一高迁移率材料层， 以用作未来器件沟道区的一部分， 因此 也可以称为第一沟道层。 其中所谓高迁移率指的是材料层中空穴或者 电子的迁移率， 并且优选地， 高迁移率是 Si中迁移率的 1.5倍以上。
如图 5所示，在绝缘层 2和緩冲层 3上依次沉积形成第一材料层 4A和 第二材料层 5A。 沉积方法包括 PECVD、 MBE、 ALD、 溅射等。 对于第 一高迁移率材料层是 GeSn而言， 第一材料层 4A是非晶 Ge并且具有厚度 tl , 第二材料层 5A是金属 Sn并且具有厚度 t2， 两者厚度依照合金配比而 任意设定。 优选地， 在第二材料层 5A上采用 PECVD、 LPCVD等方法并 且降低沉积温度从而形成低温保护层， 例如低温氧化硅 （LTO ) , 沉 积温度例如低于 400 °C以避免此时 Ge与 Sn提前反应。 或者旋涂 PSG、 BPSG等玻璃材料， 甚至可以是光刻胶等树脂材料来形成保护层， 用于 避免稍后的激光处理过度而损坏材料。 自然， 如果能良好调整激光处 理参数， 保护层也可以省略。
如图 6和图 7所示， 执行第一激光处理， 采用激光脉沖照射第一材 料层 4A和第二材料层 5A, 使得样品表面快速升温而融化反应， 并且在 冷却的过程中以相同于衬底的晶向结晶， 最终形成图 7所示的第一高迁 移率层 6A。 激光处理的脉沖个数为 ml (例如是 1 ~ 100的整数） ， 能量 密度为 Π (例如 100mJ/cm2 ~ U/cm2 ) , 激光波长为 157nm ~ 10.6 μ m, 脉冲时间宽度为 tl (例如 lns ~ 10 s )。 如果层 4A是 Ge并且层 5A是 Sn， 则反应形成的第一高迁移率层 6A可以是 Gel-xSnx ， 其中优选地 0<x<0.1 , 第一高迁移率层 6A的厚度例如是 5nm ~ 200nm。 此时， 虽然可 以调节激光脉沖的个数和能量密度来控制 Ge!-xSnx中 Sn含量， 然而受限 于其底层緩冲层 3的 SiGe的晶格和晶向， Sn含量即便提升也通常不会高 于 0.1， 这对于需要更高迁移率沟道区的器件而言是不够的， 因此需要 本发明后续的进一步处理。
接着， 参照图 13以及图 8至图 10, 在第一高迁移率材料层上形成笫 二高迁移率材料层， 用作未来沟道区的第二部分， 因此也称为第二沟 道层。 其中， 笫二高迁移率材料层的载流子迁移率大于第一高迁移率 材料层的载流子迁移率。
与图 5至图 7类似地， 可以采用相同方法形成第二高迁移率材料层。 具体地， 如图 8所示， 在第一高迁移率材料层 6A上依次沉积形成第 三材料层 4B和第四材料层 5B。 沉积方法包括 PECVD、 MBE、 ALD、 溅 射等。 其中， 如果第二高迁移率材料层与第一高迁移率材料层材质相 同， 则第三材料层 4B与第一材料层 4A材质相同， 并且第四材料层 5B与 第二材料层 5A材质相同。 例如， 第三材料层 4B是非晶 Ge并且具有厚度 t3 , 第二材料层 5A是金属 Sn并且具有厚度 t4 , 两者厚度依照合金配比而 任意设定。 此外， 第二高迁移率材料层材质也可以与第一高迁移率材 料层不同， 例如是 SiGeSn合金、 GaGeSn合金、 InGeSn、 GeSnAs合金等 等， 因此第三材料层 4B可以是 Si、 Ge、 In、 Ga等， 而第四材料层 5B可 以是 Sn、 As等。 同样优选地， 在第四材料层 5B上也可以形成与上述相 同的保护层。
如图 9和图 10所示， 执行第二激光处理， 采用激光脉冲照射第三材 料层 4B和第四材料层 5B， 使得样品表面快速升温而融化反应， 并且在 冷却的过程中以相同于第一高迁移率材料层的晶向结晶， 最终形成图 10所示的第二高迁移率层 6B。 激光处理的脉冲个数为不同于上述 ml的 m2(例如为 10 ~ 200 ) ,能量密度为不同于上述 fl的 f2(例如 400mJ/cm2 ~ 2J/cm2 ) 。 如果层 4A是 Ge并且层 5A是 Sn， 则反应形成的第二高迁移率 层 6A可以是 Gel -ySny , 其中 y要大于上述 x， 优选地 0.1<y<0.3。 第二高 迁移率层 6B的厚度例如是 5nm ~ 200nm。 此时， 由于有了第一高迁移率 层 6A作为过渡和緩沖并且改变了激光脉沖处理参数， 第二高迁移率层 6B的晶格排列更加合理， 其 Sn含量可以大幅提高， 从而有效提高了器 件驱动能力。
此外， 虽然本发明实施例中仅列举了两层高迁移率材料层叠作为 沟道区， 但是也可以依照需要设置更多层， 例如三层、 四层乃至更多 层 GeSn的堆叠结构， 或者是 SiGe、 GaAs、 GeSn、 InSb等不同高迁移率 材料层的三层以上的混杂堆叠结构， 只要能满足由下至上各层中载流 子迁移率逐渐提高的需求。
此后， 参照图 13以及图 1 1、 图 12 , 在第一和第二高迁移率材料层 中形成沟槽隔离并定义有源区。
如图 1 1所示， 在第二高迁移率材料层 6B上涂覆光刻胶 7 , 曝光 /显 影而形成了光刻胶图形， 具有多个光刻胶开口 7A， 开口 7A暴露了第二 高迁移率材料层 6B。 其中， 光刻胶开口 7A与前迷的绝缘层开口 2A位置 对应， 也即构成环形框。 光刻胶开口 7A的宽度可以如图 1 1所示与绝缘 层开口 2A/緩沖层 3宽度相等， 也可以优选地大于绝缘层开口 2A。
如图 12所示， 采用等离子体刻蚀、 反应离子刻蚀等各向异性的干 法刻蚀， 依次刻蚀第二高迁移率材料层 6B、 第一高迁移率材料层 6A、 緩沖层 3， 直至暴露衬底 1 , 而形成了沟槽。 在沟槽中通过 LPCVD、 PECVD, HDPCVD、 旋涂等方法沉积例如氧化硅、 氮氧化硅、 BPSG、 PSG等绝缘材料而形成沟槽隔离 8。 沟槽隔离 8与光刻胶开口 7A、 绝缘 层开口 2A共型， 因此具有环形框结构， 其内侧包围的第二高迁移率材 料层 6B、 第一高迁移率材料层 6A成为器件的源漏区和沟道区， 也即沟 槽隔离 8定义了有源区。
此后， 完成器件制造。 例如对于 MOSFET而言， 可以采用 CMOS 兼容工艺在沟槽隔离 8内的有源区上形成栅极堆叠、 在有源区中掺杂注 入形成源漏区、 在源漏区上形成源漏接触层、 在整个器件上形成层间 介质层、 刻蚀层间介质层形成源漏接触孔、 沉积金属形成源漏接触塞 等等。
依照本发明的半导体器件制造方法， 通过调整激光处理的脉冲个 数和能量密度， 在绝缘村底上分多次形成了多层高迁移率材料以用作 器件沟道区， 有效提高了器件栽流子迁移率并进一步提高了器件驱动 能力。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合 适的改变和等价方式。 此外， 由所公开的教导可做出许多可能适于特 定情形或材料的修改而不脱离本发明范围。 因此， 本发明的目的不在 于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例， 施例。

Claims

权 利 要 求
1. 一种高迁移率材料层制造方法， 包括：
在衬底中和 /或上形成多种前驱物；
脉沖激光处理， 使得多种前驱物相互反应形成高迁移率材料层。
2. 如权利要求 1的方法，其中，形成多种前驱物的步骤进一步包括： 对衬底注入掺杂剂以在衬底中形成前驱物。
3. 如权利要求 2的方法， 其中， 注入能量为 10KeV ~ 300KeV, 注 入剂量为 1E15 ~ lE17/cm2 0
4. 如权利要求 2的方法， 其中， 调整多种前驱物中的一个的注入剂 量和能量， 从而控制高迁移率材料层的成分。
5. 如权利要求 1的方法，其中，形成多种前驱物的步骤进一步包括： 在衬底上沉积多种前驱物。
6. 如权利要求 5的方法， 其中， 调整脉冲激光处理的脉沖个数、 能 量密度、 脉沖时间以及多种前驱物中的一个的厚度， 从而控制高迁移 率材料层的厚度。
7. 如权利要求 1的方法， 其中， 在形成多种前驱物之后还包括： 在 前驱物上形成保护层。
8. 如权利要求 7的方法， 其中， 形成保护层的方法包括低温沉积、 旋涂、 丝网印刷、 喷涂。
9. 如权利要求 1的方法， 其中，衬底包括 Si、 SOL Ge、 GeOL SiGe、 InP、 InGaAs, GaAs、 GaN、 InSb; 前驱物包括： Ge、 Sn、 In、 Ga、 Si、 As、 P、 N、 Sb; 高迁移率材料层包括： GeSn、 SiGeSn、 InGeSn, GaGeSn、 InGaASo
10. 一种半导体器件制造方法， 包括：
在绝缘衬底上形成緩沖层；
采用权利要求 1至 9任一项的方法， 在緩冲层上形成第一高迁移率 材料层；
采用权利要求 1至 9任一项的方法， 在第一高迁移率材料层上形成 第二高迁移率材料层；
在第一和第二高迁移率材料层中形成沟槽隔离并定义有源区。
1 1. 如权利要求 10的方法， 其中， 第一高迁移率材料层和 /或第二 高迁移率材料层包括 GeSn。
12. 如权利要求 10的方法， 其中， 在绝缘衬底上形成緩沖层的步骤 进一步包括：
在衬底上形成绝缘层；
在绝缘层中形成暴露衬底的绝缘层开口；
在绝缘层开口中选择性外延生长緩冲层。
13. 如权利要求 13的方法， 其中， 采用热氧化法形成绝缘层。
14. 如权利要求 10的方法， 其中， 緩沖层包括 SiGe， 衬底包括 Si。
15. 如权利要求 10的方法， 其中， 形成第一高迁移率材料层的步骤 进一步包括：
在緩沖层上依次形成第一材料层和第二材料层；
执行第一激光处理， 釆用激光脉冲照射第一材料层和第二材料层， 使得第一材料层和第二材料层反应形成第一高迁移率材料层。
16. 如权利要求 10的方法， 其中， 形成第二高迁移率材料层的步骤 进一步包括：
在第一高迁移率材料层上依次形成第三材料层和第四材料层； 执行第二激光处理， 采用激光脉沖照射第三材料层和第四材料层， 使得第三材料层和第四材料层反应形成第二高迁移率材料层。
17. 如权利要求 16或 17的方法， 其中， 第一材料层和 /或第三材料 层包括 Ge, 第二材料层和 /或第四材料层包括 Sn。
18. 如权利要求 10的方法， 其中， 形成沟槽隔离并定义有源区的步 骤进一步包括：
在第二高迁移率材料层上形成光刻胶图形， 具有光刻胶开口， 其 中光刻胶开口与緩冲层相对应；
依次刻蚀第二高迁移率材料层、 第一高迁移率材料层、 緩冲层直 至暴露衬底， 形成沟槽；
在沟槽中沉积绝缘材料形成沟槽隔离， 沟槽隔离包围的第二高迁 移率材料层、 第一高迁移率材料层构成有源区。
PCT/CN2012/001375 2012-08-16 2012-10-12 半导体器件制造方法 WO2014026304A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/812,502 US20140057418A1 (en) 2012-08-16 2012-10-12 Method for manufacturing a semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210293349.X 2012-08-16
CN201210293349.XA CN103594419B (zh) 2012-08-16 2012-08-16 半导体器件制造方法

Publications (1)

Publication Number Publication Date
WO2014026304A1 true WO2014026304A1 (zh) 2014-02-20

Family

ID=50084503

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/001375 WO2014026304A1 (zh) 2012-08-16 2012-10-12 半导体器件制造方法

Country Status (3)

Country Link
US (1) US20140057418A1 (zh)
CN (1) CN103594419B (zh)
WO (1) WO2014026304A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015129810A1 (ja) * 2014-02-27 2015-09-03 株式会社 東芝 Ｃｍｏｓイメージセンサ

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839786A (zh) * 2014-02-25 2014-06-04 清华大学 选区SiGeSn层及其形成方法
CN103839829A (zh) * 2014-02-25 2014-06-04 清华大学 具有SiGeSn沟道的鳍式场效应晶体管及其形成方法
WO2015127697A1 (en) * 2014-02-25 2015-09-03 Tsinghua University Method for forming fin field effect transistor
US9299566B2 (en) * 2014-02-25 2016-03-29 Tsinghua University Method for forming germanium-based layer
CN103839774A (zh) * 2014-02-25 2014-06-04 清华大学 SiGeSn层及其形成方法
CN103839775A (zh) * 2014-02-25 2014-06-04 清华大学 选区GeSn层及其形成方法
TWI694494B (zh) 2014-07-08 2020-05-21 美商應用材料股份有限公司 處理基板之方法及設備
CN106024717B (zh) * 2016-05-24 2019-02-19 西安电子科技大学 带隙改性Ge CMOS集成器件及其制备方法
CN107452682A (zh) * 2016-08-25 2017-12-08 西北大学 激光再晶化Ge CMOS器件及其制备方法
US10510888B2 (en) * 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
CN111584344A (zh) * 2020-05-25 2020-08-25 中国科学院半导体研究所 一种GeSn和SiGeSn合金材料及其外延方法
CN114438454A (zh) * 2022-01-26 2022-05-06 西安科技大学 一种类锗锡三元合金及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030015722A1 (en) * 2001-07-17 2003-01-23 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices for dispersing a radiant energy transmission
CN1934711A (zh) * 2004-03-12 2007-03-21 惠普开发有限公司 具有包括多成分氧化物的沟道的半导体器件
US20070215905A1 (en) * 2004-05-31 2007-09-20 Kenji Kohiro Compound Semiconductor Epitaxial Substrate and Process for Producing the Same
CN101962802A (zh) * 2010-07-14 2011-02-02 中国科学院半导体研究所 在Si衬底上分子束外延生长GeSn合金的方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3450376B2 (ja) * 1993-06-12 2003-09-22 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP3361922B2 (ja) * 1994-09-13 2003-01-07 株式会社東芝 半導体装置
US20030013319A1 (en) * 2001-07-10 2003-01-16 Motorola, Inc. Semiconductor structure with selective doping and process for fabrication
WO2005015609A2 (en) * 2003-06-13 2005-02-17 Arizona Board Of Regents, Acting For And On Behalf Of Arizona State University Sixsnyge1-x-y and related alloy heterostructures based on si, ge and sn

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030015722A1 (en) * 2001-07-17 2003-01-23 Motorola, Inc. Structure and method for fabricating semiconductor structures and devices for dispersing a radiant energy transmission
CN1934711A (zh) * 2004-03-12 2007-03-21 惠普开发有限公司 具有包括多成分氧化物的沟道的半导体器件
US20070215905A1 (en) * 2004-05-31 2007-09-20 Kenji Kohiro Compound Semiconductor Epitaxial Substrate and Process for Producing the Same
CN101962802A (zh) * 2010-07-14 2011-02-02 中国科学院半导体研究所 在Si衬底上分子束外延生长GeSn合金的方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015129810A1 (ja) * 2014-02-27 2015-09-03 株式会社 東芝 Ｃｍｏｓイメージセンサ
US10096641B2 (en) 2014-02-27 2018-10-09 Kabushiki Kaisha Toshiba CMOS image sensor

Also Published As

Publication number Publication date
CN103594419B (zh) 2018-02-13
US20140057418A1 (en) 2014-02-27
CN103594419A (zh) 2014-02-19

Similar Documents

Publication Publication Date Title
WO2014026304A1 (zh) 半导体器件制造方法
US7230264B2 (en) Semiconductor transistor having structural elements of differing materials
US8889519B2 (en) Semiconductor device and method for manufacturing the same
US8124467B2 (en) Reducing silicide resistance in silicon/germanium-containing drain/source regions of transistors
CN103594496B (zh) 半导体器件及其制造方法
WO2013121926A1 (ja) 半導体装置及びその製造方法
TWI469344B (zh) 具有包含效能增進材料成分之受應變通道區的電晶體
CN101828260A (zh) 在体半导体晶片中制造局域化绝缘体上半导体(soi)结构的方法
KR20160001583A (ko) 비평면 화합물 반도체 디바이스에 대한 채널 변형 제어
KR20080080833A (ko) 반도체 웨이퍼의 제조 방법
US20180144991A1 (en) Co-integration of tensile silicon and compressive silicon germanium
US7413939B2 (en) Method of growing a germanium epitaxial film on insulator for use in fabrication of CMOS integrated circuit
US9159830B2 (en) Field effect transistor
US7416957B2 (en) Method for forming a strained Si-channel in a MOSFET structure
WO2012094856A1 (zh) 半导体结构及其制作方法
CN105097511B (zh) 鳍式场效应晶体管及其形成方法
US20070290263A1 (en) Semiconductor device and method for manufacturing the same
TW200421476A (en) Shallow trench isolation for strained silicon processes
US20080248626A1 (en) Shallow trench isolation self-aligned to templated recrystallization boundary
KR101329352B1 (ko) 반도체 장치의 제조방법
TW201919129A (zh) 基於在沉積的非晶半導體材料基礎上形成結晶半導體材料的技術及相關的半導體裝置
TWI774853B (zh) 具有減小的橫向電場之電晶體元件
KR101714613B1 (ko) 반도체 소자 및 이의 제조 방법
CN112635314B (zh) 形成源/漏接触的方法及晶体管的制作方法
WO2016093287A1 (ja) 微細構造形成方法、半導体デバイスの製造方法、及びｃｍｏｓの形成方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13812502

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12882910

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12882910

Country of ref document: EP

Kind code of ref document: A1