WO2014015591A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2014015591A1
WO2014015591A1 PCT/CN2012/085175 CN2012085175W WO2014015591A1 WO 2014015591 A1 WO2014015591 A1 WO 2014015591A1 CN 2012085175 W CN2012085175 W CN 2012085175W WO 2014015591 A1 WO2014015591 A1 WO 2014015591A1
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Prior art keywords
pixel unit
sub
pixel
data line
array substrate
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English (en)
French (fr)
Inventor
刘莎
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US14/127,528 priority Critical patent/US9564453B2/en
Publication of WO2014015591A1 publication Critical patent/WO2014015591A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • Embodiments of the present invention relate to an array substrate and a display device having a pixel structure having a high aperture ratio while also having an easy repair feature. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • FIG. 1 is a schematic illustration of a conventional pixel structure.
  • the pixel structure includes a data line 1, a pixel unit, and a gate line 2, the data line 1 being located at one side of the pixel unit.
  • the pixel structure uses a design method of upper and lower domains in order to avoid the color shift phenomenon, and the structure inevitably has an irregular shape of the electrode in the middle portion of the pixel, and the liquid crystal alignment is disordered at the position of the pixel gap intersection region 3, which is easy.
  • a dark area that produces more areas affects the overall transmittance of the pixel structure. Summary of the invention
  • An object of the embodiments of the present invention is to provide an array substrate and a display device to overcome the defects of the pixel structure of the prior art that have a low pixel aperture ratio and affect the yield of the final product.
  • an aspect of an embodiment of the present invention provides an array substrate including a substrate and gate lines and data lines formed on the substrate, the gate lines and the data lines defining pixel units, each of the data lines being located a central portion of the corresponding pixel unit, dividing each pixel unit into a first sub-pixel unit and a second sub-pixel unit;
  • the first sub-pixel unit and the second sub-pixel unit are each connected to a thin film crystal
  • the tube is independently charged, and the thin film transistor is entirely located in a region corresponding to the gate line.
  • each data line is located at an intermediate position of the corresponding pixel unit.
  • a common electrode and a pixel electrode are formed on the array substrate, and a slit is formed on the common electrode and/or the pixel electrode;
  • the slit directions in the same sub-pixel unit are kept uniform; moreover, the slit directions in the first sub-pixel unit and the second sub-pixel unit on both sides of the same data line are symmetrical with respect to the data line.
  • a light shielding layer on the color filter substrate for shielding the data line region is disposed at a corresponding position of the pixel cell intersection region of the first sub-pixel unit and the second sub-pixel unit.
  • drain of the thin film transistor and the pixel electrode are connected by via holes.
  • the slit directions of the pixel electrodes in the first sub-pixel unit and the second sub-pixel unit form an angle, and the via holes are respectively disposed at the vacancies of the first sub-pixel unit and the second sub-pixel unit.
  • the via position is set at the bottom of the data line and is closely attached to the data line The position of the side.
  • the via position is set at the bottom of the data line and away from the data line The position on both sides.
  • a source of each of the thin film transistors is connected to two adjacent connection electrodes and a data line adjacent thereto;
  • connection electrode is formed by the same process as the source of the thin film transistor and the data line.
  • embodiments of the present invention also provide a display device including the above array substrate.
  • the embodiment of the present invention has the following advantages: the array substrate and the display device provided by the embodiments of the present invention use the data line to be disposed in the middle of the pixel unit, and are connected to two independent thin film transistors for simultaneous charging; The thin film transistor is charged, and the channel width to length ratio of each thin film transistor can be correspondingly reduced. At the same time, since the thin film transistor in the solution of the embodiment of the present invention is entirely above the gate line, the gate width of the thin film transistor is reduced, that is, reduced. The width of the grid line. therefore, With the solution provided by the embodiment of the invention, the scan line width can be greatly reduced, and the pixel aperture ratio can be improved. DRAWINGS
  • FIG. 1 is a schematic diagram of a conventional pixel structure in the prior art
  • FIG. 2 is a schematic diagram of a pixel structure according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a pixel structure according to another embodiment of the present invention.
  • FIG. 4 is a schematic view showing a cross-arrangement structure of a pixel structure according to the present invention.
  • FIG. 5 is a schematic diagram of a principle of repairing a pixel structure according to an embodiment of the present invention.
  • an embodiment of the present invention provides an array substrate including a substrate and gate lines 2 and data lines 1 formed on the substrate, wherein the gate lines 2 and the data lines 1 define a plurality of a pixel unit, the data line 1 is located in the middle of the pixel unit, for example, each data line 1 is located in the middle of the corresponding pixel unit, thereby dividing the pixel unit into the first sub-pixel unit 7 and the second sub-pixel unit 8;
  • the first sub-pixel unit 7 and the second sub-pixel unit 8 are each independently connected to a thin film transistor 6 (TFT) for independent charging, and the thin film transistor 6 is entirely located in a corresponding region of the gate line. Since the same pixel is charged by the two thin film transistors, the channel width to length ratio of each thin film transistor can be reduced correspondingly, that is, the gate width of the TFT can be reduced; and in this embodiment, the gate line is used as the TFT. With the gate electrode used, the gate width is reduced, that is, the width of the gate line can be reduced, thereby increasing the aperture ratio.
  • TFT thin film transistor 6
  • the data line 1 is located at an intermediate position of the pixel unit such that the areas of the first sub-pixel unit 7 and the second sub-pixel unit 8 are equal, ensuring that the TFT charging effect is the same.
  • the data line 1 is disposed in the middle portion of the pixel unit, and one pixel unit is equally divided into the first sub-pixel unit 7 and the second sub-pixel unit 8, and two independent TFT switches are respectively used for the first sub-pixel unit.
  • Charging with the second sub-pixel unit avoids the aperture ratio and transmittance loss caused by the intersection of the two domains in the central portion of the pixel unit in the conventional array substrate, and can effectively avoid the occurrence of color shift phenomenon, and the array of the embodiment
  • the influence of the pixel slits in the substrate is arranged together with the loss of the light-shielding layer on the data line 1 to ensure the pixel gap structure in the pixel opening region, thereby optimizing the pixel structure and reducing the pixel structure.
  • the loss of the aperture ratio ensures the uniformity of the pixel transmittance.
  • the first sub-pixel unit 7 and the second sub-pixel unit 8 in this embodiment are respectively charged by two TFTs at the same time, and when one pixel unit is divided into two parts, each part only needs to be in the prior art (for example)
  • the TFT 6) of the TFT 6 in Fig. 1 can achieve normal charging, with the gate line as the gate electrode of the TFT, so that the width of the gate line can be folded in half, thereby increasing the aperture ratio.
  • the TFT channel width-to-length ratio (W/L) in the conventional structure is 58 um/5.0 um, which is theoretically designed according to the embodiment of the present invention.
  • the width-to-length ratio (W/L) of each TFT channel can be 29um/5.0um, and the reduction of the TFT channel width can greatly reduce the line width of the scanning line, thereby greatly increasing the aperture ratio of the pixel. With 46 inches like For example, when the pixel structure is designed, the aperture ratio can be increased by 2.6%.
  • the position corresponding to the position in the prior art does not need to set the black matrix, because the pixel
  • the liquid crystal in the middle of the cell and the pixel unit is subjected to the pixel electrodes in the left and right directions.
  • the horizontal electric field formed by the two pixel electrodes is in the same direction as the rubbing direction, so that the liquid crystal does not rotate, and no light leakage occurs at the position. Ensure display quality.
  • a common electrode and a pixel electrode are formed on the array substrate, and slits are formed on the common electrode and/or the pixel electrode; the slit directions in the same sub-pixel unit are consistent; and, on both sides of the same data line
  • the slit directions in the first sub-pixel unit and the second sub-pixel unit are symmetrical with respect to the data line.
  • the common electrode is on the lower side and the pixel electrode is on the upper side (i.e., the common electrode is closer to the substrate, and the pixel electrode is closer to the liquid crystal layer) is taken as an example.
  • the common electrode is connected to the common electrode line 4 to obtain a common voltage; the pixel electrode 5 is connected to the drain of the thin film transistor through the via hole.
  • the pixel electrode 5 in the present embodiment is formed with slits, and the slits of the pixel electrodes 5 on both sides of the data line are symmetrically arranged with respect to the data line.
  • a light shielding layer disposed on the color filter substrate for shielding the data line region is disposed at a position of the pixel unit intersection region 3 (low light effect region) of the first sub-pixel unit 7 and the second sub-pixel unit 8 Optimize the pixel structure to reduce the loss of aperture ratio.
  • the drain of the TFT and the pixel electrode are connected through the via 9.
  • the slit directions of the pixel electrodes 5 in the first sub-pixel unit 7 and the second sub-pixel unit 8 form an angle, and the positions of the via holes 9 are respectively disposed at the vacancies of the first sub-pixel unit 7 and the second sub-pixel unit 8, Avoid occupying the pixel electrode area to maximize space saving.
  • the via hole 9 is disposed at the bottom of the data line and tightly Paste on both sides of the data line 1.
  • the via 9 is positioned at the bottom of the data line 1 and away from At the position on both sides of data line 1.
  • the above two structural settings optimize the pixel structure, thereby maximally saving the space occupying the pixel electrode, and minimizing the influence on the aperture ratio and the transmittance.
  • the pixel unit and the pixel unit in the pixel display area of the embodiment are not completely regularly arranged, but the pixel direction in the pixel structure is composed of two different pixels.
  • the structure is cross-distributed and expanded to avoid color shifting as a whole.
  • the TFT position in the embodiment of the present invention can achieve an easy repairing effect.
  • the source of each thin film transistor is connected to its adjacent data line through two independent connection electrodes; the connection electrode is formed by the same process as the source and the data line of the thin film transistor.
  • the gate electrode 2 is turned on, the data line 1 is input with a charging signal, and the charged signal flows through the two TFTs 6 to form a branch, and the first sub-pixel unit 7 and the second sub-pixel unit 8 are respectively independently charged, specifically
  • the first sub-pixel unit 7 completes charging by a ⁇ b ⁇ c, while the second sub-pixel unit 8 completes charging by a ⁇ e ⁇ f, and then the signal is transmitted to the pixels of the next row through d ⁇ h or g ⁇ h.
  • the second sub-pixel unit 8 When there is a data line break (DO) at "b", the second sub-pixel unit 8 is normally charged, and the first sub-pixel unit 7 completes charging by a ⁇ e ⁇ f ⁇ g ⁇ d ⁇ c, without affecting the charging of the pixel. Effect; Similarly, when the data line break (DO) occurs at the "e” on the TFT of the second sub-pixel unit, the second sub-pixel unit TFT completes charging by a ⁇ b ⁇ c ⁇ d ⁇ g ⁇ f. Since there is no vertical intersection area between the data line 1 and the gate line 2, the influence of the overlap capacitance on the line delay is greatly reduced.
  • DO data line break
  • the left and right TFTs of the signal input by the same data line 1 respectively charge the pixel structures of the first sub-pixel unit 7 and the second sub-pixel unit 8 on the left and right sides, and a data line break occurs at one of the TFTs ( When the DO line or the data line and the gate line are short-circuited (DGS), the other TFT can still be normally charged, thereby avoiding the influence of the above-mentioned defects on the picture quality.
  • DGS short-circuited
  • the array substrate provided by the embodiment of the invention uses the data line to be disposed in the middle portion of the pixel unit, and simultaneously connects two independent thin film transistors for simultaneous charging, which can greatly reduce the gate line width and increase the pixel aperture ratio, and at the same time, When there is a problem in one pixel unit area, it does not affect the normal charging of the other area, and the product picture quality is maximized.
  • the embodiment of the present invention further provides a display device, including the array substrate in the above embodiment, and the display device in the embodiment of the present invention includes, but is not limited to, a liquid crystal television, a tablet computer, a liquid crystal display or other electronic display products.
  • the array substrate in the display device provided by the embodiment of the invention uses the data line to be disposed in the middle of the pixel unit, and the two sub-pixel units are connected to two independent thin film transistors for simultaneous charging; since the same pixel is charged by two thin film transistors , correspondingly the channel width of each thin film transistor
  • the length ratio can be reduced, and since the thin film transistor in the embodiment of the present embodiment is entirely above the gate line, the gate width of the thin film transistor is reduced, that is, the width of the gate line is reduced. Therefore, with the solution provided by the embodiment of the present invention, the gate line width can be greatly reduced, and the pixel aperture ratio can be improved.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)

Abstract

提供了一种阵列基板和显示装置。该阵列基板包括基板以及形成在所述基板上的栅线（2）和数据线（1），所述栅线（2）和数据线（1）限定像素单元，每条数据线（1）位于相应的像素单元的中部，将每个像素单元分为第一子像素单元（7）和第二子像素单元（8）；第一子像素单元（7）和第二子像素单元（8）各自单独连接一个薄膜晶体管（6）进行独立充电而且薄膜晶体管（6）整体位于所述栅线（2）对应的区域。通过采用将数据线（1）设置于像素单元的中部，同时两个子像素单元（7、8）连接两个独立的小薄膜晶体管（6）开关单独进行充电，可大幅度缩小扫描线宽度，提高像素开口率。

Description

阵列基板及显示装置 技术领域
本发明的实施例涉及具有较高开口率同时还具有易修补特点的像素结构 的阵列基板及显示装置。 背景技术
在薄月莫晶体管液晶显示器 ( Thin Film Transistor Liquid Crystal Display, TFT-LCD )生产领域中， 面板的透光率是一个重要的产品指标。
随着光刻和制造技术的发展， 可生产出越来越精细的面板结构。 现有技 术中通过不断降低数据线的线宽来减小开口率的损失， 但是随着数据线线宽 的降低， 数据线断路现象出现的比率也会有所增长， 设计和制造高开口率同 时具有易于修补的像素结构， 将会有广阔的应用前景。
图 1是传统像素结构的示意图。 该像素结构包括数据线 1、 像素单元、 栅线 2, 该数据线 1位于像素单元的一侧。 现有技术中的像素结构为了避免 色偏现象而釆用上下两畴的设计方式， 该结构不可避免会在像素中间部分出 现电极形状不规则， 像素缝隙交叉区域 3位置处出现液晶排列错乱， 容易产 生较多区域的暗区， 影响像素结构的整体透过率。 发明内容
(一）要解决的技术问题
本发明实施例的目的是提供一种阵列基板及显示装置， 以克服现有技术 中像素结构的像素开口率低而导致影响最终产品良品率的缺陷。
(二）技术方案
为了实现上述目的， 本发明实施例的一方面提供一种阵列基板， 包括基 板以及形成在所述基板上的栅线和数据线，所述栅线和数据线限定像素单元， 每条数据线位于相应的像素单元的中部， 将每个像素单元分为第一子像素单 元和第二子像素单元；
所述第一子像素单元和所述第二子像素单元各自单独连接一个薄膜晶体 管进行独立充电， 以及所述薄膜晶体管整体位于所述栅线对应的区域。
进一步地， 每条数据线位于相应的像素单元的中间位置。
进一步地， 所述阵列基板上形成有公共电极和像素电极， 而且在所述公 共电极和 /或像素电极上形成有狭缝；
在同一个子像素单元中的狭缝方向保持一致； 而且， 位于同一条数据线 两侧的所述第一子像素单元和所述第二子像素单元中的狭缝方向关于数据线 对称。
进一步地， 所述滤色器基板上用于遮挡数据线区域的遮光层遮盖在第一 子像素单元和第二子像素单元的像素单元交叉区域的对应位置处。
进一步地， 所述薄膜晶体管的漏极和像素电极通过过孔连接。
进一步地， 所述第一子像素单元和所述第二子像素单元中像素电极的缝 隙方向形成夹角， 所述过孔分别设置在第一子像素单元和第二子像素单元的 空位处。
进一步地， 当所述第一子像素单元和第二子像素单元中像素电极的缝隙 方向形成的夹角开口朝向薄膜晶体管时， 所述过孔位置设置在数据线底部并 紧贴在数据线两侧的位置处。
进一步地， 当所述第一子像素单元和第二子像素单元中像素电极的缝隙 方向形成的夹角开口朝向薄膜晶体管的反方向时， 所述过孔位置设置在数据 线底部并远离数据线两侧的位置处。
进一步地， 每个所述薄膜晶体管的源极通过两个独立的连接电极和与其 相邻的数据线相连；
所述连接电极与所述薄膜晶体管的源极、 所述数据线通过相同的工艺形 成。
另一方面，本发明的实施例还提供一种显示装置， 包括上述的阵列基板。 (三）有益效果
本发明实施例具有以下优点：本发明实施例提供的阵列基板及显示装置， 釆用将数据线设置于像素单元的中部， 且连接到两个独立的薄膜晶体管同时 充电； 由于同一像素由两个薄膜晶体管进行充电， 每个薄膜晶体管的沟道宽 长比可以相应地减小， 同时由于本发明实施例的方案中的薄膜晶体管整体位 于栅线上方， 因此缩小薄膜晶体管栅极宽度， 也就是缩小栅线的宽度。 因此， 利用本发明实施例提供的方案，可大幅度缩小扫描线宽度，提高像素开口率。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中传统的像素结构示意图；
图 2为本发明实施例像素结构的示意图；
图 3为本发明另一实施例像素结构的示意图；
图 4为本发明像素结构交叉排列结构的示意图；
图 5为本发明实施例的像素结构修补原理的示意图。
其中： 1 : 数据线； 2: 栅线； 3: 交叉区域； 4: 公共电极线； 5: 像素电 极； 6: 薄膜晶体管； 7: 第一子像素单元； 8: 第二子像素单元； 9: 过孔。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
如图 2至图 4所示， 本发明实施例提供一种阵列基板， 包括基板以及形 成在所述基板上的栅线 2和数据线 1 , 所述栅线 2和数据线 1限定了若干个 像素单元， 数据线 1位于像素单元的中部， 例如每条数据线 1位于相应的像 素单元的中间位置， 从而将像素单元分为第一子像素单元 7和第二子像素单 元 8;
所述第一子像素单元 7和第二子像素单元 8各自单独连接一个薄膜晶体 管 6 ( TFT )进行独立充电， 而且薄膜晶体管 6整体位于所述栅线对应的区 域。 由于同一像素由两个薄膜晶体管进行充电， 相应地每个薄膜晶体管的沟 道宽长比可以减小， 即 TFT的栅极宽度可以减小； 而且在本实施例中， 以栅 线作为 TFT的栅电极使用， 栅极宽度减小， 也就是， 栅线宽度可以减小， 从 而提高开口率。
例如， 该数据线 1位于像素单元的中间位置， 使得第一子像素单元 7和 第二子像素单元 8的区域均等， 保证 TFT充电效果相同。
釆用将数据线 1设置于像素单元的中间部分， 将一个像素单元均等分成 第一子像素单元 7和第二子像素单元 8, 同时釆用两个独立的 TFT开关分别 对第一子像素单元和第二子像素单元进行充电， 避免了传统的阵列基板中像 素单元中心部分由于两畴的交叉引起的开口率和透过率损失， 可有效地避免 色偏现象的发生， 同时实施例的阵列基板中将像素缝隙交叉排列而产生的影 响与数据线 1上遮光层对像素开口率的损失集合在了一起， 保证了像素开口 区域中全部呈现规则的像素缝隙结构， 优化了像素结构， 降低了开口率的损 失， 同时保证了像素透过率的均匀性。
本实施例中的第一子像素单元 7和第二子像素单元 8由两个 TFT同时分 别对其进行充电， 将一个像素单元分割为两个部分时， 每一部分只需要现有 技术中 （例如图 1中的 TFT 6 )二分之一大小的 TFT就可以实现正常充电， 以栅线作为 TFT的栅电极， 使得栅线的宽度可以折半， 从而提高开口率。 具 体地， 以 46英寸像素电极所具有的 TFT宽长比为例， 传统结构中 TFT沟道 宽长比（W/L )为 58um/5.0um, 理论上若按照本发明实施例的方式设计， 每 个 TFT沟道的宽长比（ W/L )即可以实现 29um/5.0um, TFT沟道宽度缩小可 以大大减少扫描线的线宽，从而可以大幅度提高像素的开口率。以 46英寸像 素结构为例， 经计算釆用本像素结构设计时， 开口率可以提升 2.6%。
与现有技术相比， 数据线设置在像素单元中间位置时， 其现有技术中的 位置对应的位置（即， 数据线设置在每个像素单元两侧的位置）不用设置黑 矩阵， 由于像素单元与像素单元中间的液晶受到左右两个方向像素电极的作 用， 该两个像素电极形成的水平电场与摩擦方向一致， 因此液晶不会发生旋 转， 在该位置处也不会发生漏光现象， 可以确保显示品质。
阵列基板上形成有公共电极和像素电极，而且在所述公共电极和 /或像素 电极上形成有狭缝； 在同一个子像素单元中的狭缝方向保持一致； 而且， 位 于同一条数据线两侧的所述第一子像素单元和第二子像素单元中的狭缝方向 关于数据线对称。
在本实施例中， 以公共电极在下、 像素电极在上（即公共电极更靠近基 板、 像素电极更靠近液晶层） 的结构为例。 公共电极与公共电极线 4相连， 以获取公共电压； 像素电极 5通过过孔与薄膜晶体管的漏极相连。
从图 2至图 5中可以看出， 本实施例中的像素电极 5上形成有狭缝， 且 数据线两侧的像素电极 5的狭缝关于该数据线对称排布。
其中， 设置在滤色器基板上的用于遮挡数据线区域的遮光层遮盖在第一 子像素单元 7和第二子像素单元 8的像素单元交叉区域 3 (低光效区）位置 处， 从而优化像素结构， 减少开口率的损失。
其中， TFT的漏极和像素电极通过过孔 9连接。 第一子像素单元 7和第 二子像素单元 8中像素电极 5的缝隙方向形成夹角， 所述过孔 9位置分别设 置在第一子像素单元 7和第二子像素单元 8的空位处， 避免占用像素电极区 域， 最大程度的节省空间。
具体地，参考图 2, 当第一子像素单 7和第二子像素单元 8中像素电极 5 的缝隙方向形成的夹角开口朝向 TFT时，所述过孔 9位置设置在数据线底部 并紧贴在数据线 1两侧位置处。
参考图 3 , 当第一子像素单元 7和第二子像素单元 8中的像素电极 5的 缝隙方向形成的夹角开口朝向 TFT的反方向时， 过孔 9位置设置在数据线 1 底部并远离数据线 1两侧位置处。
上述两种结构设置， 优化了像素结构， 最大程度地节省了占用像素电极 的空间， 实现了对开口率和透过率影响最小化。 参考图 4, 与现有的面板显示区域不同， 本实施例的像素显示区域中的 像素单元与像素单元之间并非完全规则的重复排列， 而是将像素结构中像素 方向由两种不同的像素结构交叉分布并进行拓展,从整体上避免了色偏现象。
如图 5所示， 本发明实施例中 TFT位置可实现易修补的效果。 每个薄膜 晶体管的源极通过两个独立的连接电极和与其相邻的数据线相连； 所述连接 电极与所述薄膜晶体管的源极、 所述数据线通过相同的工艺形成。
正常情况下， 栅电极 2打开， 数据线 1输入充电信号， 该充入的信号流 经两个 TFT6形成分支， 分别对第一子像素单元 7和第二子像素单元 8进行 独立充电， 具体地， 该第一子像素单元 7通过 a→b→c完成充电， 同时第二 子像素单元 8通过 a→e→f完成充电， 随后信号通过 d→h或者 g→h传递给 下一行的像素。
当 "b" 处存在数据线断路（DO ) 时， 第二子像素单元 8正常充电， 而 第一子像素单元 7通过 a→e→f→g→d→c完成充电，不影响像素的充电效果； 同理当第二子像素单元 TFT上 "e" 处发生数据线断路（DO )时， 第二子像 素单元 TFT通过 a→b→c→d→g→f完成充电。由于数据线 1与栅线 2不存在 垂直交叉区域， 因此交叠电容对线延迟的影响大大降低。
由同一条数据线 1输入信号的左右两个 TFT, 分别对左右两侧的第一子 像素单元 7和第二子像素单元 8的像素结构进行充电， 当其中的一个 TFT处 发生数据线断路（DO )或数据线和栅线短路（DGS ) 时， 另外一个 TFT仍 然可以进行正常充电， 从而避免了上述不良对画面品质的影响。
本发明实施例提供的阵列基板， 釆用将数据线设置于像素单元的中间部 分， 同时连接两个独立薄膜晶体管进行同时充电， 可大幅度缩小栅线宽度， 提高像素开口率， 同时， 当其中一个像素单元区域出现问题时， 并不会影响 另外一个区域正常充电， 最大程度地提高产品画面品质。
另外， 本发明的实施例还提供一种显示装置， 包括上述实施例中的阵列 基板， 本发明实施例中的显示装置包括但不局限于液晶电视、 平板电脑、 液 晶显示器或其他电子显示产品。
本发明实施例提供的显示装置中的阵列基板釆用将数据线设置于像素单 元的中部， 同时两个子像素单元连接两个独立的薄膜晶体管进行同时充电； 由于同一像素由两个薄膜晶体管进行充电， 相应地每个薄膜晶体管的沟道宽 长比可以减小， 同时由于本实施例方案中的薄膜晶体管整体位于栅线上方， 因此缩小薄膜晶体管栅极宽度， 也就是缩小栅线的宽度。 因此， 利用本发明 实施例提供的方案， 可大幅度缩小栅线宽度， 提高像素开口率。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括基板以及形成在所述基板上的栅线和数据线， 所 述栅线和所述数据线限定像素单元， 其中， 每条数据线位于相应的像素单元 的中部， 将每个像素单元分为第一子像素单元和第二子像素单元；
所述第一子像素单元和所述第二子像素单元各自单独连接一个薄膜晶体 管进行独立充电， 以及所述薄膜晶体管整体位于所述栅线对应的区域。
2、如权利要求 1所述的阵列基板， 其中，每条数据线位于相应的像素单 元的中间位置。
3、如权利要求 1或 2所述的阵列基板， 其中， 所述阵列基板上形成有公 共电极和像素电极， 而且在所述公共电极和 /或像素电极上形成有狭缝； 在同一个子像素单元中的狭缝方向保持一致； 而且， 位于同一条数据线 两侧的所述第一子像素单元和所述第二子像素单元中的狭缝方向关于数据线 对称。
4、如权利要求 1至 3的任一项所述的阵列基板， 其中， 所述滤色器基板 上用于遮挡数据线区域的遮光层遮盖在第一子像素单元和第二子像素单元的 像素单元交叉区域的对应位置处。
5、如权利要求 1至 4的任一项所述的阵列基板， 其中， 所述薄膜晶体管 的漏极和像素电极通过过孔连接。
6、如权利要求 1至 5的任一项所述的阵列基板， 其中， 所述第一子像素 单元和所述第二子像素单元中像素电极的缝隙方向形成夹角， 所述过孔分别 设置在第一子像素单元和第二子像素单元的空位处。
7、如权利要求 1至 6的任一项所述的阵列基板， 其中， 当所述第一子像 素单元和所述第二子像素单元中的像素电极的缝隙方向形成的夹角开口朝向 薄膜晶体管时， 所述过孔位置设置在数据线底部并紧贴在数据线两侧的位置 处。
8、如权利要求 1至 6的任一项所述的阵列基板， 其中， 当所述第一子像 素单元和第二子像素单元中像素电极的缝隙方向形成的夹角开口朝向薄膜晶 体管的反方向时， 所述过孔位置设置在数据线底部并远离数据线两侧的位置 处。
9、如权利要求 1至 8的任一项所述的阵列基板， 其中，每个所述薄膜晶 体管的源极通过两个独立的连接电极和与其相邻的数据线相连；
所述连接电极与所述薄膜晶体管的源极、 所述数据线通过相同的工艺形 成。
10、 一种显示装置， 包括权利要求 1-9任一项所述的阵列基板。
PCT/CN2012/085175 2012-07-27 2012-11-23 阵列基板及显示装置 Ceased WO2014015591A1 (zh)

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