WO2014008684A1 - PVD制备TiN的方法 - Google Patents

PVD制备TiN的方法 Download PDF

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Publication number
WO2014008684A1
WO2014008684A1 PCT/CN2012/079176 CN2012079176W WO2014008684A1 WO 2014008684 A1 WO2014008684 A1 WO 2014008684A1 CN 2012079176 W CN2012079176 W CN 2012079176W WO 2014008684 A1 WO2014008684 A1 WO 2014008684A1
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titanium
ions
tin
wafer
increasing
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French (fr)
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付作振
殷华湘
闫江
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US13/695,191 priority Critical patent/US8802578B2/en
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/0641Nitrides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/0021Reactive sputtering or evaporation
    • C23C14/0036Reactive sputtering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/791Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/794Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising conductive materials, e.g. silicided source, drain or gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44Physical vapour deposition [PVD]

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of preparing a TiN film by PVD. Background technique
  • This technique stresses the channel by introducing various stressors such as Strained Overlayers Stress Memorization and Embedded SiGe (Embedded_SiGe, eSiGe) during device fabrication. Appropriate stress can increase the mobility of the channel carriers, thereby improving the electrical performance of the device without reducing the channel size.
  • various stressors such as Strained Overlayers Stress Memorization and Embedded SiGe (Embedded_SiGe, eSiGe) during device fabrication.
  • Embedded_SiGe, eSiGe Embedded_SiGe
  • the object of the present invention is to improve the stress by rationally optimizing the process parameters of the TiN film prepared by PVD, thereby effectively enhancing the carrier mobility in the channel region and further improving the device performance.
  • the present invention provides a method for preparing titanium nitride by PVD, comprising: causing a rare gas glow discharge to form a rare gas ion under a vacuum filled with nitrogen and a rare gas; using a nitrogen gas to planarize the wafer surface and the titanium target The surface of the table is nitrided; the rare gas ions bombard the surface of the titanium target under the acceleration of the electric field, and sputter titanium ions and titanium nitride; titanium nitride is deposited on the surface of the wafer under the action of a magnetic field to form a titanium nitride layer, while titanium ions are incident on the surface.
  • the surface of the wafer causes the titanium nitride layer to have stress; and is characterized in that the kinetic energy of the titanium ions incident on the surface of the wafer is increased, thereby increasing the amorphization ratio of the titanium nitride layer and further increasing the stress of the titanium nitride layer.
  • the step of increasing the kinetic energy of the titanium ions incident on the surface of the wafer further comprises: shortening the distance between the wafer and the titanium target.
  • the distance between the wafer and the titanium target is 190 mm to 260 mm.
  • the step of increasing the kinetic energy of the titanium ions incident on the surface of the wafer further comprises: increasing the sputtering power.
  • the sputtering power is 100w to 2000w.
  • the TiN layer has a thickness of 6 to 100 nm.
  • the stress of the titanium nitride layer is 0 to - 6. 5 GPa.
  • the method for preparing TiN by PVD according to the present invention improves the kinetic energy of Ti ions incident on the wafer by controlling the process parameters, thereby increasing the amorphization ratio of TiN and thereby increasing the stress of the TiN film.
  • FIGS. 2 to 5 schematically illustrate TiNx film stresses obtained at different target-wafer distances, power, flow rates, and thicknesses, respectively. . detailed description
  • the present invention can be used to prepare TiNx using a general (magnetron) sputtering apparatus.
  • titanium nitride titanium nitride
  • TiN titanium nitride
  • the vacuum condition is filled with a reactive gas, a nitrogen gas, and a sputtering gas, a rare gas (He, Ne, Ar, Kr, Xe, etc., preferably Ar and a larger mass of atoms to enhance the bombardment sputtering effect).
  • a reactive gas a nitrogen gas
  • a sputtering gas a rare gas (He, Ne, Ar, Kr, Xe, etc., preferably Ar and a larger mass of atoms to enhance the bombardment sputtering effect).
  • the gas pressure is constant at Smtorr during sputtering
  • the sputtering gas to glow discharge and ionize the ions of the rare gas, at which time the nitrogen causes the surface of the Ti target and the surface of the wafer (for example, a single crystal Si wafer) to be nitrided;
  • the ions accelerate the bombardment of the surface of the target Ti under the action of the electric field, and sputter the TiN atoms; under the action of the electromagnetic field, the TiN atoms fall on the wafer and deposit as TiN thin films.
  • the rare gas such as Ar bombards the surface of the Ti target and also sputters Ti ions.
  • the Ti ions continue to bombard the existing ones on the wafer.
  • the TiN film is such that the TiN film on the surface of the wafer is partially amorphized to have a certain stress.
  • the inventors obtained the core technical solution of the present invention, that is, the aging energy of Ti ions incident on the wafer is increased to increase the amorphization rate of TiN, thereby improving the stress of the TiN film. .
  • increasing the kinetic energy of Ti ions incident on the wafer can include at least the following two approaches:
  • the distance D in the prior art sputtering chamber is generally 260 mm, which is reduced to 190 mm in the method according to an embodiment of the invention. Since the distance is reduced, the electric field is greatly enhanced at the same voltage, so that Ti ions are more accelerated in the electric field, so that the amorphization rate of the TiN film deposited on the surface of the wafer is greatly improved, and the TiN film stress can be effectively improved. As shown in Fig. 2, it can be seen that in the range of 190 mm to 260 mm, as the distance D decreases, the stress of the TiN film increases remarkably, so the pitch 0 should be shortened as much as possible.
  • the sputtering power is generally 50 to 200 W, but the sputtering power is increased according to the method of the present invention, for example, 100 w to 2000 w, and preferably 800 w to 2000 w, more preferably For 1500w ⁇ 2000w.
  • the electromagnetic field increases in the same distance, and the Ti ions obtain greater kinetic energy, thereby increasing the amorphization rate of TiN, thereby improving the sputtering rate.
  • Film stress so the sputtering power should be increased as much as possible.
  • the film stress can be further increased by increasing the flow rate of nitrogen.
  • the flow rate of nitrogen in the present invention is 1. 5 ⁇ 10. 0 SCCM, more preferably 3. 0 ⁇ 10. 0 SCCM, preferably in 7. 5 ⁇ 10. 0 SCCM.
  • the thickness of the TiN film is, for example, 6 to 100 nm, and preferably 6 to 50 nm, and more preferably 6 to 10 nm.
  • the method for preparing TiN by PVD according to the present invention improves the kinetic energy of Ti ions incident on the wafer by controlling the process parameters, thereby increasing the amorphization ratio of TiN and thereby increasing the stress of the TiN film.

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  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

本发明公开了一种PVD制备TiN的方法,包括:在充有氮气和稀有气体的真空条件下,使得稀有气体辉光放电形成稀有气体离子;利用氮气将晶片表面以及Ti靶台表面氮化;稀有气体离子在电场加速下轰击Ti靶台表面,溅射出TiN以及Ti离子;TiN在磁场作用下沉积在晶片表面形成TiN层,而Ti离子入射在晶片表面而使得TiN层具有应力;其特征在于:提高Ti离子入射到晶片表面的动能,从而提高TiN层的非晶化率,进而提高TiN层的应力。依照本发明的PVD制备TiN的方法,通过控制工艺参数而提高Ti离子入射到晶片上的动能,从而提高了TiN非晶化率进而提高了TiN薄膜的应力。

Description

PVD制备 TiN的方法 本申请要求 2012年 7月 13日提交的、申请号为 201210245146. 3、发明名称为" PVD 制备 TiN的方法" 的中国专利申请的优先权, 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件制造方法,特别是涉及一种 PVD制备 TiN薄膜的方法。 背景技术
随着大规模集成电路技术的不断发展, 电路的集成度不断提高, M0SFET器件的 特征尺寸已经到了 22nm以下的技术结点。 事实上, 当进入 90nm的技术结点之后, 单 纯的通过缩小栅长以满足摩尔定律的要求已经越来越困难了。 因为随着栅长的缩短, 被用来抑制短沟道效应的沟道重掺杂引入的沟道掺杂散射、强场效应以及寄生电阻的 增加, 导致沟道载流子迁移率降低, 影响了器件电学性能的提升。 在这种背景下, 应 变工程应运而生, 它是提高沟道载流子迁移率的重要方法之一。
这种技术通过在器件制造过程中引入各种应力源, 如应变覆层 (Strained Overlayers) 应力记忆 ( Stress Memorization)^ 以及嵌入式 SiGe (Embedded_SiGe, eSiGe) , 来对沟道施加应力。 而适当的应力能够提高沟道载流子的迁移率, 进而在不 缩小沟道尺寸的前提下实现器件电学性能的提高。
从 45nm开始金属栅被引入 CMOS器件中, 并且得到了大规模应用, 而作为 SMT技 术思想的延伸, 通过金属栅向沟道引入应力的方法也随之诞生, 这种应力的引入主要 针对 nMOS器件, TiNx作为 nMOS器件的金属栅材料其应力的研究成为必要课题。
现有的 TiN薄膜制备方法, 例如蒸发、 (磁控)溅射、 PECVD等等, 通过控制工艺 参数可以获得 l〜2GPa应力的 TiNx薄膜。 然而, 随着器件尺寸持续缩减, 对于沟道 区载流子迁移率提高的需求日益增强, 上述传统的 TiNx薄膜制备方法以及工艺参数 选择难以满足进一步提高器件驱动能力的需求。 发明内容
由上所述,本发明的目的在于通过合理优化 PVD制备 TiN薄膜的工艺参数来提高 应力, 从而可以有效增强沟道区载流子迁移率, 进一步提高器件性能。 为此, 本发明提供了一种 PVD制备氮化钛的方法, 包括: 在充有氮气和稀有气体 的真空条件下, 使得稀有气体辉光放电形成稀有气体离子; 利用氮气将晶片表面以及 钛靶台表面氮化; 稀有气体离子在电场加速下轰击钛靶台表面, 溅射出钛离子以及氮 化钛; 氮化钛在磁场作用下沉积在晶片表面形成氮化钛层, 而同时钛离子入射在晶片 表面而使得氮化钛层具有应力; 其特征在于: 提高钛离子入射到晶片表面的动能, 从 而提高氮化钛层的非晶化率, 进而提高氮化钛层的应力。
其中, 提高钛离子入射到晶片表面的动能的步骤进一步包括: 缩短晶片与钛靶台 之间的距离。 其中, 晶片与钛靶台之间的距离为 190mm〜260mm。
其中, 提高钛离子入射到晶片表面的动能的步骤进一步包括: 提高溅射功率。 其 中, 溅射功率为 100w〜2000w。
进一步包括提高氮气的流量。 其中, 氮气的流量为 1. 5〜10. 0 SCCM。
进一步包括减小氮化钛层厚度。 其中, TiN层厚度为 6〜100nm。
其中, 氮化钛层的应力为 0〜- 6. 5GPa。
依照本发明的 PVD制备 TiN的方法, 通过控制工艺参数而提高 Ti离子入射到晶 片上的动能, 从而提高了 TiN非晶化率进而提高了 TiN薄膜的应力。 附图说明
以下参照附图来详细说明本发明的技术方案, 其中:
图 1示意性示出了根据本发明实施例的 TiN薄膜溅射方法的示意图; 以及 图 2〜5分别示意性示出了不同靶台 -晶片距离、功率、流量、厚度下得到的 TiNx 薄膜应力。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技 术效果, 公开了一种 PVD制备 TiNx的方法。 需要指出的是, 类似的附图标记表示类 似的结构, 本申请中所用的术语 "第一"、 "第二"、 "上"、 "下"等等可用于修饰各种 器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的 空间、 次序或层级关系。
本发明可以采用通用的 (磁控) 溅射设备来完成 TiNx的制备。 值得注意的是, 在本申请下文中, 为了简便起见, 有时将钛的氮化物 (氮化钛)简称为 TiN而省略了 N含量 x的标记, 但是并非意在将 x限定为具体的整数 1, 实质上 X可以是从 0〜4的 任意数并且不限于整数。
如图 1所示, 在充有反应气体一氮气和溅射气体一稀有气体 (He、 Ne、 Ar、 Kr、 Xe等, 优选 Ar以及更大质量的原子以增强轰击溅射效果) 的真空条件 (例如溅射时 气压恒定为 Smtorr)下, 使得溅射气体辉光放电而电离出稀有气体的离子, 此时氮气 使得 Ti靶材表面以及晶片 (例如单晶 Si晶片)表面氮化; 稀有气体离子在电场作用 下加速轰击靶材 Ti的表面, 溅射出 TiN原子; 在电磁场的作用下, TiN原子落在晶片 上, 沉积为 TiN薄膜。在此过程中, 除了 TiN原子会落在晶片上之外, Ar等稀有气体 轰击 Ti靶材表面也会溅射出 Ti离子, 该 Ti离子除了与氮气反应之外, 还持续轰击 晶片上已有的 TiN薄膜, 从而使得晶片表面的 TiN薄膜局部非晶化而具有一定应力。
本发明人根据理论分析以及多次实验数据验证, 得到了本发明的核心技术方案, 也即通过提高 Ti离子入射到晶片上的动能来提高 TiN的非晶化率,从而可以提高 TiN 薄膜的应力。
具体地, 提高 Ti离子入射到晶片上的动能至少可以包括以下两种途径:
1 ) 缩短图 1 中晶片与靶台之间的间距 D。 现有的溅射腔室中该距离 D—般是 260mm, 依照本发明实施例的方法中, 该距离缩减为 190mm。 由于距离缩减, 在相同的 电压下, 电场大大增强, 因此 Ti离子在电场中获得更高的加速, 从而晶片表面上沉 积的 TiN薄膜的非晶化率大大提高, 可以有效提高 TiN薄膜应力。 如图 2所示, 可见 在 190mm〜260mm的范围内, 随着距离 D减小, TiN薄膜的应力显著增大, 因此应该尽 可能的缩短间距0。
2) 增大溅射功率。在现有的常规溅射腔室中, 溅射功率一般是 50〜200w, 然而 依照本发明的方法提高了该溅射功率, 例如是 100w〜2000w, 并且优选地为 800w〜 2000w, 更优选地为 1500w〜2000w。 如图 3所示, 可见在 100w〜2000w的范围内, 随 着溅射功率增大, 相同距离内电磁场增强, Ti离子获得更大的动能, 从而提高了 TiN 的非晶化率, 进而提高了薄膜应力, 因此应该尽可能地增大溅射功率。
此外, 依照本发明的方法中, 可以通过增大氮气流量来进一步增大薄膜应力。 如 图 4所示, 可见随着氮气流量的增加, 薄膜应力也有显著增大。 这是因为 TiN中 N含 量增大使得薄膜本身晶格结构变化, 本征应力增大。 因此, 本发明中氮气的流量优选 1. 5〜10. 0 SCCM, 更优选地在 3. 0〜10. 0 SCCM, 最佳在 7. 5〜10. 0 SCCM。
如图 5所示,可见随着晶片上最后得到的 TiN薄膜厚度减小, TiN应力显著增大, 这是因为相同动能的 Ti离子在厚度较小的 TiN薄层中轰击得到的微细晶格裂纹可以 传播穿越的深度占总 TiN厚度的比例更大, 也即 Ti离子轰击得到的非晶化区域的占 比更加广大, 因此局部产生的应力也更大。 在本发明实施例中, TiN薄膜的厚度例如 是 6〜100nm, 并且优选地为 6〜50nm, 以及更优选地为 6〜10nm。
综合上述图 2〜图 5可见, 随着优化各种工艺参数, 可以使得制备得到的 TiN薄 膜具有的应力高达 -6. 5GPa, 例如 +1. 0〜- 6. 5GPa并优选 0〜- 6. 5GPa, 远远超过传统 PECVD、 磁控溅射工艺得到的最多 ± 2GPa的应力。
依照本发明的 PVD制备 TiN的方法, 通过控制工艺参数而提高 Ti离子入射到晶 片上的动能, 从而提高了 TiN非晶化率进而提高了 TiN薄膜的应力。
尽管已参照一个或多个示例性实施例说明本发明,本领域技术人员可以知晓无需 脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外, 由所公开的教 导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。 因此, 本发明的 目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例,而所公 开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1、 一种 PVD制备氮化钛的方法, 包括:
在充有氮气和稀有气体的真空条件下, 使得稀有气体辉光放电形成稀有气体离 子;
利用氮气将晶片表面以及钛靶台表面氮化;
稀有气体离子在电场加速下轰击钛靶台表面, 溅射出钛离子以及氮化钛; 氮化钛在磁场作用下沉积在晶片表面形成氮化钛层,而同时钛离子入射在晶片表 面而使得氮化钛层具有应力;
其特征在于:提高钛离子入射到晶片表面的动能,从而提高氮化钛层的非晶化率, 进而提高氮化钛层的应力。
2、 如权利要求 1的方法, 其中, 提高钛离子入射到晶片表面的动能的步骤进一 步包括: 缩短晶片与钛靶台之间的距离。
3、 如权利要求 2的方法, 其中, 晶片与钛靶台之间的距离为 190mm〜260mm。
4、 如权利要求 1的方法, 其中, 提高钛离子入射到晶片表面的动能的步骤进一 步包括: 提高溅射功率。
5、 如权利要求 4的方法, 其中, 溅射功率为 100w〜2000w。
6、 如权利要求 1的方法, 进一步包括提高氮气的流量。
7、 如权利要求 6的方法, 其中, 氮气的流量为 1. 5〜10. 0 SCCM。
8、 如权利要求 1的方法, 进一步包括减小氮化钛层厚度。
9、 如权利要求 8的方法, 其中, 氮化钛层厚度为 6〜100nm。
10、 如权利要求 1的方法, 其中, 氮化钛层的应力为 0〜- 6. 5GPa。
PCT/CN2012/079176 2012-07-13 2012-07-26 PVD制备TiN的方法 Ceased WO2014008684A1 (zh)

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CN106939411B (zh) * 2016-01-04 2019-01-22 中芯国际集成电路制造(上海)有限公司 氮化钛的形成方法
CN110965023A (zh) * 2019-12-25 2020-04-07 北京北方华创微电子装备有限公司 氮化钛薄膜沉积方法

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CN1896298A (zh) * 2005-07-13 2007-01-17 应用材料公司 用于大面积衬底的改进磁控管溅射系统
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WO2011117916A1 (ja) * 2010-03-24 2011-09-29 キヤノンアネルバ株式会社 電子デバイスの製造方法およびスパッタリング方法
CN102394218A (zh) * 2011-11-24 2012-03-28 上海华力微电子有限公司 氮化钛薄膜溅射方法以及半导体器件制造方法

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US20100032842A1 (en) * 2008-08-07 2010-02-11 Texas Instruments Incorporated MODULATED DEPOSITION PROCESS FOR STRESS CONTROL IN THICK TiN FILMS
WO2011117916A1 (ja) * 2010-03-24 2011-09-29 キヤノンアネルバ株式会社 電子デバイスの製造方法およびスパッタリング方法
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