WO2013157039A1

WO2013157039A1 - Path-switching electrical power amplifier

Info

Publication number: WO2013157039A1
Application number: PCT/JP2012/002665
Authority: WO
Inventors: 勝也嘉藤; 直子新田; 謙治向井; 堀口　健一; 檜枝　護重
Original assignee: 三菱電機株式会社
Priority date: 2012-04-18
Filing date: 2012-04-18
Publication date: 2013-10-24
Also published as: TW201345144A

Abstract

The drain voltage terminal (17) of a NMOS FET switch (11) is impressed with a positive DC voltage using a back gate voltage as a reference; therefore, even if the voltage amplitude of a signal amplified by an electrical power amplifier (5) on the drain side of the NMOS FET switch (11) changes over time while the NMOS FET switch (11) is in the OFF state, there is an increase in the threshold voltage (Vth) when the ON state is enabled. Accordingly, high efficiency operation up to large amounts of electrical power can be achieved without the ON state being instantaneously enabled.

Description

Path switching power amplifier

The present invention relates to an amplifier such as a high frequency power amplifier for mobile communication such as a mobile phone, and relates to a path switching power amplifier that switches a path according to output power.

As a conventional path switching power amplifier, a branching means for branching an input signal, a plurality of amplification means connected to the branching means and operating at different frequencies, and a bypass connected to the branching means and bypassing the plurality of amplification means Means, a switching means connected between the branching means and the plurality of amplifying means, and between the branching means and the bypass means, and a combined output means connected to the plurality of amplifying means and the bypass means for synthesizing and outputting the signal And a control means for controlling the switch means in accordance with the signal frequency and the output power and switching the path of the input signal (see Patent Document 1 below).

JP 2002-246848 A

Since the conventional path switching power amplifier is configured as described above, the switch means for switching the path of the input signal does not use an FET switch.
Therefore, when an FET switch is used as the switch means, the FET switch connected to the off path is instantaneously turned on by the voltage amplitude of the signal amplified by the power amplifier, and the signal component leaks to the off path, and the power The problem that efficiency is reduced due to loss cannot be solved.

The present invention has been made to solve the above-described problems, and the FET switch connected to the off path is not turned on instantaneously due to the voltage amplitude of the signal amplified by the power amplifier. An object is to obtain an efficient path switching power amplifier.

A path switching power amplifier according to the present invention connects a power amplifier that amplifies an input signal from a first node and outputs the amplified signal to a second node, and bypasses the power amplifier. A switch circuit provided in the path, the switch circuit having a source connected to the first node side and a drain connected to the second node side, and is turned on according to an on-gate bias applied to the gate And an NMOS FET switch that is turned off in response to an off-gate bias applied to the gate, and a drain voltage terminal that applies a positive DC voltage to the drain of the NMOS FET switch with reference to the back gate voltage.

According to the present invention, since a positive DC voltage is applied to the drain voltage terminal of the NMOS FET switch with reference to the back gate voltage, the power amplifier is provided on the drain side of the NMOS FET switch when the NMOS FET switch is off. Even if the voltage amplitude of the amplified signal changes with time, the threshold voltage for turning on becomes high, so that it does not turn on instantaneously. Thereby, there is an effect that high-efficiency operation is possible up to high power.

It is a block diagram which shows the path | route switching power amplifier by Embodiment 1 of this invention. It is a wave form diagram which shows the time change of the voltage between gate-drains when a positive DC voltage is applied. It is a wave form diagram which shows the time change of the voltage between gate-drains when a positive DC voltage is not applied. It is a block diagram which shows the modification of a switch circuit. It is a block diagram which shows the modification of a switch circuit. It is a block diagram which shows the modification of a switch circuit. It is a block diagram which shows the modification of a switch circuit. It is a block diagram which shows the modification of a switch circuit. It is a block diagram which shows the modification of a switch circuit. It is a block diagram which shows the modification of a switch circuit. It is a block diagram which shows the path | route switching power amplifier by Embodiment 2 of this invention.

Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
1 is a block diagram showing a path switching power amplifier according to Embodiment 1 of the present invention.
In FIG. 1, the power amplifier 5 amplifies an input signal from the node 1 via the node 2 and outputs the amplified signal to the node 4 via the node 3 and the matching circuit 6.
Here, a path from the node 1 to the node 4 through the power amplifier 5 and the matching circuit 6 is defined as a first path.

The matching circuit 7 is connected to the node 2, and the switch circuit 8 is connected between the output terminal of the matching circuit 7 and the node 3.
Here, a path from the node 1 to the node 4 via the matching circuit 7 and the switch circuit 8 is a second path.

The switch circuit 8 is provided with

capacitors

9 and 10 for cutting direct current.
An NMOS FET switch 11 having a source connected to the capacitor 9 and a drain connected to the capacitor 10 is provided.
Furthermore, a gate voltage terminal 12 for applying an on or off gate bias to the gate via the resistor 13a is provided.
Furthermore, a ground terminal 14 for connecting the ground to the back gate via the resistor 13b, a ground terminal 15 for connecting the ground to the source via the resistor 13c, and a ground terminal 16 for connecting the ground to the drain via the resistor 13d are provided. .
Further, a drain voltage terminal 17 for applying a positive DC voltage with respect to the back gate voltage (ground) to the drain via the resistor 13e is provided.
The resistors 13a to 13e are resistors having a high resistance value.

Next, the operation will be described.
A mobile terminal such as a mobile phone uses a method of changing transmission power according to the distance to the base station and the communication status, and therefore, a power amplifier for transmission is required to have a wide output power and high efficiency. ing.
In order to satisfy this requirement, there is a path switching power amplifier that switches a path related to the power amplifier according to output power.

The power amplifier shown in FIG. 1 is an amplifier whose signal path is switched, and the first path is a path from the node 1 to the node 4 via the power amplifier 5 and the matching circuit 6.
The second route is a route from the node 1 to the node 2 to the nodes 3 and 4 via the matching circuit 7 and the switch circuit 8.

When a signal passes through the first path, an off-gate bias voltage is applied to the gate voltage terminal 12 of the NMOS FET switch 11 to turn off the NMOS FET switch 11.
Further, the ground is connected to the back gate, the source, and the drain via the resistors 13b to 13d by the ground terminals 14 to 16.
In this way, by connecting the source and drain to the ground via the

resistors

13c and 13d, the source and drain can be fixed at 0V in direct current without affecting the high-frequency performance. Bias conditions can be clarified.
When the source and drain are not connected to the ground, the source and drain voltages are floating, and the bias voltage is not determined.
In addition, by connecting the back gate to the ground via the resistor 13b, the back gate can be fixed at 0V for DC and can be set open for high frequency, so that a high frequency signal leaks to the ground via the back gate. Can be prevented.
Further, a positive DC voltage is applied to the drain via the resistor 13e by the drain voltage terminal 17 with reference to the back gate voltage.

FIG. 2 shows the time change of the gate-drain voltage when a positive DC voltage is applied to the drain, and FIG. 3 shows the time change of the gate-drain voltage when no positive DC voltage is applied to the drain.
As shown in FIG. 3, when a positive DC voltage is not applied to the drain, the threshold voltage Vth at which the NMOS FET switch 11 is turned on is not relatively increased, and the NMOS FET switch 11 in the off state is powered. Due to the voltage amplitude of the signal amplified by the amplifier 5, the signal is instantaneously turned on, the signal component leaks into the off path, and the efficiency is reduced due to power loss.

On the other hand, as shown in FIG. 2, when a positive DC voltage is applied to the drain with reference to the back gate voltage, the threshold voltage Vth at which the NMOS FET switch 11 is turned on is relatively high. The NMOS FET switch 11 in the off state is not turned on by the voltage amplitude of the signal amplified by the power amplifier 5, and the signal component does not leak into the off path.
Thereby, high-efficiency operation is possible up to high power.

Further, when the first path is bypassed and the signal is allowed to pass through the second path, an on-gate bias voltage is applied to the gate voltage terminal 12 of the NMOS FET switch 11 to turn on the NMOS FET switch 11. To do.
In this case, since the signal does not pass through the power amplifier 5, it is output from the node 4 without being amplified.

In the above description, a positive DC voltage is always applied to the drain with reference to the back gate voltage.
However, only when an off-gate bias voltage is applied to the gate of the NMOS FET switch 11, a positive DC voltage may be applied to the drain with reference to the back gate voltage.
In this case, since a positive DC voltage is applied only when an off-gate bias voltage is applied, power consumption can be reduced.

Further, the relationship between the drain and source potentials in the switch circuit 8 is such that the drain-back gate potential and the source-back gate potential are set to the same value, and the drain-back gate potential and the source-back gate potential are There are two cases of setting different values.

4 and 5 show examples in which the drain-back gate potential and the source-back gate potential are set to have the same value.
The switch circuit 8a shown in FIG. 4 is different from the switch circuit 8 shown in FIG. 1 in that the

resistors

13c and 13d and the

ground terminals

15 and 16 are removed, and the source is positive with reference to the back gate voltage via the resistor 13f. A source voltage terminal 17 for applying a DC voltage is added.

The switch circuit 8b shown in FIG. 5 is different from the switch circuit 8 shown in FIG. 1 in that the

resistors

13c and 13d and the

ground terminals

15 and 16 are deleted, the source and the drain are connected, and the resistor 13g is connected in the middle. The route is added.

Examples of setting the drain-back gate potential and the source-back gate potential to have different values are shown in FIGS.
The switch circuit 8c shown in FIG. 6 is obtained by removing the resistor 13c and the ground terminal 15 from the switch circuit 8 shown in FIG.

7 is obtained by deleting the resistor 13d and the ground terminal 16 from the switch circuit 8 shown in FIG.

The switch circuit 8e shown in FIG. 8 is the same as the switch circuit 8 shown in FIG.

The switch circuit 8f shown in FIG. 9 removes the resistor 13d and the ground terminal 16 from the switch circuit 8 shown in FIG. 1, connects the source and drain, and adds a path to which the resistor 13g is connected midway. It is a thing.

The switch circuit 8g shown in FIG. 10 adds an NMOS FET switch 11a to the switch circuit 8 shown in FIG. 1, and the source of the NMOS FET switch 11 and the drain of the NMOS FET switch 11a are connected. The NMOS FET switch 11a has a gate voltage terminal 12a for applying a gate bias via a resistor 13g, a ground terminal 14a for connecting the ground to the back gate via a resistor 13h, and a ground connected to the source via a resistor 13i. A ground terminal 15a is provided.
In FIG. 10, the NMOS FET switches 11 and 11a are connected in two stages. However, a plurality of stages of three or more stages may be connected, and the NMOS FET switch 11 closest to the capacitor 10 is connected to the NMOS 10 via a resistor 13e. A drain voltage terminal 17 for applying a positive DC voltage to the drain may be provided.

The voltage applied to the drain of the NMOS FET switch must not be a voltage in which the drain-back gate voltage exceeds the withstand voltage of the NMOS FET switch.
In addition, since the battery voltage used in mobile phone terminals and the like is 3.4 to 4.2 V, the voltage that can be used in the amplifier circuit is 3.4 to 4.2 V unless there is a special circuit. .
Under the above two conditions, there are cases where only a voltage lower than a desired drain voltage can be applied to the drain of the NMOS FET switch.
In such a case, as shown in FIG. 10, a plurality of NMOS type FET switches 11 and 11a are connected in series.
Even if the drain voltage of the NMOS type FET switch 11 is lower than a desired value and the NMOS type FET switch 11 is instantaneously turned on, the NMOS type FET switch 11a can maintain the off state. Electric power leakage can be prevented.
As the number of NMOS FET switches in series increases, the leakage of power to the off path can be prevented.

The resistors 13f to 13i are resistors having a high resistance value.
The resistors 13a to 13i may be inductors.

As described above, according to the first embodiment, since a positive DC voltage is applied to the drain voltage terminal 17 of the NMOS FET switch 11 with reference to the back gate voltage, when the NMOS FET switch 11 is in the OFF state, Even if the voltage amplitude of the signal amplified by the power amplifier 5 on the drain side of the NMOS FET switch 11 changes with time, the threshold voltage Vth that is turned on is increased, so that it is not instantaneously turned on. High-efficiency operation is possible up to high power.

Embodiment 2. FIG.
FIG. 11 is a block diagram showing a path switching power amplifier according to Embodiment 2 of the present invention.
In FIG. 11, the power amplifier 25 amplifies the input signal from the node 21 and outputs the amplified signal to the node 22 via the matching circuit 26.

The switch circuit 27 is provided in a path connecting the node 22 to the node 23, and the matching circuit 29 is connected between the output terminal of the switch circuit 27 and the node 23.
Here, a path that branches from the node 21 via the power amplifier 25 and the matching circuit 26 to the node 22 and reaches the node 23 via the switch circuit 27 and the matching circuit 29 is defined as a first path.

The switch circuit 28 is provided in a path connecting the node 22 to the node 24, and the matching circuit 30 is connected between the output terminal of the switch circuit 28 and the node 24.
Here, a path that branches from the node 21 via the power amplifier 25 and the matching circuit 26 at the node 22 and reaches the node 24 via the switch circuit 28 and the matching circuit 30 is defined as a second path.

The switch circuit 28 is provided with

capacitors

9 and 10 for cutting direct current.
An NMOS FET switch 11 having a source connected to the capacitor 9 and a drain connected to the capacitor 10 is provided.
Furthermore, a gate voltage terminal 12 for applying an on or off gate bias to the gate via the resistor 13a is provided.
Furthermore, a ground terminal 14 for connecting the ground to the back gate via the resistor 13b, a ground terminal 15 for connecting the ground to the source via the resistor 13c, and a ground terminal 16 for connecting the ground to the drain via the resistor 13d are provided. .
Furthermore, a source voltage terminal 18 for applying a positive DC voltage to the source via the resistor 13f with reference to the back gate voltage (ground) is provided.
The switch circuit 27 is configured in the same manner as the switch circuit 28, but the description thereof is omitted.

Next, the operation will be described.
The power amplifier shown in FIG. 11 is an amplifier whose signal path is switched, and the first path branches from the node 21 via the power amplifier 25 and the matching circuit 26 at the node 22 to branch to the switch circuit 27 and the matching circuit 29. This is a route to the node 23 via
The second path is a path that branches from the node 21 via the power amplifier 25 and the matching circuit 26 to the node 22 and reaches the node 24 via the switch circuit 28 and the matching circuit 30.

When passing the signal of the first path and blocking the signal of the second path, an off-gate bias voltage is applied to the gate voltage terminal 12 of the NMOS type FET switch 11 of the switch circuit 28, and the NMOS type FET switch 11. Is turned off.
Further, the ground is connected to the back gate, the source, and the drain via the resistors 13b to 13d by the ground terminals 14 to 16.
Further, a positive DC voltage is applied to the source via the resistor 13f with reference to the back gate voltage by the source voltage terminal 18.

As described above, when a positive DC voltage is applied to the source with reference to the back gate voltage, the threshold voltage Vth at which the NMOS FET switch 11 is turned on is relatively high. Is not turned on by the voltage amplitude of the signal amplified by the power amplifier 25, and the signal component does not leak into the off path.
Thereby, high-efficiency operation is possible up to high power.

When passing a signal through the second path, an on-gate bias voltage is applied to the gate voltage terminal 12 of the NMOS FET switch 11 to turn on the NMOS FET switch 11.
Further, when blocking the signal of the first path and passing the signal of the second path, the NMOS FET switch 11 (not shown) of the switch circuit 27 of the first path is connected to the switch circuit 28. Control is performed in the same manner as the above control.

Note that the matching

circuits

26, 29, and 30 are not necessarily provided at the positions illustrated in FIG. 11. For example, the matching

circuits

26, 29, and 30 may be provided between the node 22 and the switch circuit 27 and between the node 22 and the switch circuit 28. .

Also in the second embodiment, the configuration shown in FIGS. 4 to 10 may be applied as the

switch circuits

27 and 28, and the same effect is obtained.
However, in the configuration shown in FIG. 5 to FIG. 10, the configuration in which the drain voltage terminal 17 for applying a positive DC voltage with the back gate voltage as a reference to the drain on the capacitor 10 side via the resistor 13 e has been described. Instead, the source voltage terminal 18 for applying a positive DC voltage with reference to the back gate voltage may be provided on the source on the capacitor 9 side via the resistor 13f.

As described above, according to the second embodiment, since the positive DC voltage is applied to the source voltage terminal 18 of the NMOS FET switch 11 with reference to the back gate voltage, when the NMOS FET switch 11 is in the OFF state, Even if the voltage amplitude of the signal amplified by the power amplifier 25 on the source side of the NMOS type FET switch 11 changes with time, the threshold voltage Vth that is turned on is increased, so that it is not instantaneously turned on. High-efficiency operation is possible up to high power.

In the present invention, within the scope of the invention, any combination of the embodiments, any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

As described above, the path switching power amplifier according to the present invention is configured to include the drain voltage terminal for applying a positive DC voltage with reference to the back gate voltage at the drain of the NMOS FET switch. Therefore, it is suitable for use in a mobile communication high-frequency power amplifier whose path is switched.

1 to 4, 21 to 24 nodes, 5,25 power amplifier, 6, 7, 26, 29, 30 matching circuit, 8, 8a to 8g, 27, 28 switch circuit, 9, 10 capacitance, 11, 11a NMOS type FET Switch, 12, 12a gate voltage terminal, 13a-13i resistor, 14, 14a, 15, 15a, 16 ground terminal, 17 drain voltage terminal, 18 source voltage terminal.

Claims

A power amplifier that amplifies the input signal from the first node and outputs it to the second node;
A switch circuit connected between the first and second nodes and provided in a path that bypasses the power amplifier;
The switch circuit is
A source is connected to the first node side and a drain is connected to the second node side. The drain is connected to the gate according to the on-gate bias applied to the gate and the off-gate bias applied to the gate. An NMOS FET switch to be turned off;
A path switching power amplifier comprising a drain voltage terminal for applying a positive DC voltage with reference to a back gate voltage to the drain of the NMOS FET switch.
The drain voltage terminal is
2. The path switching power amplifier according to claim 1, wherein a positive DC voltage is applied only when an off-gate bias is applied to the gate of the NMOS FET switch.
The switch circuit
Consists of a plurality of NMOS type FET switches whose source and drain are connected to each other,
2. The path switching power amplifier according to claim 1, wherein a drain voltage terminal to which a positive DC voltage is applied is provided to the NMOS FET switch on the second node side among the plurality of NMOS FET switches. .
A power amplifier that amplifies the input signal from the first node and outputs it to the second node;
A first switch circuit provided in a path connecting the second and third nodes;
A second switch circuit provided in a path connecting the second and fourth nodes,
The first switch circuit
A source is connected to the second node side and a drain is connected to the third node side. The drain is connected to the gate according to the on-gate bias applied to the gate and the gate is applied to the off-gate bias applied to the gate. An NMOS FET switch to be turned off;
A path switching power amplifier comprising a source voltage terminal for applying a positive DC voltage to a source of the NMOS FET switch with reference to a back gate voltage.
The source voltage terminal is
5. The path switching power amplifier according to claim 4, wherein a positive DC voltage is applied only when an off-gate bias is applied to the gate of the NMOS FET switch.
The first switch circuit
It consists of a plurality of NMOS type FET switches whose drains and sources are connected to each other,
5. The path switching power amplifier according to claim 4, wherein a source voltage terminal to which a positive DC voltage is applied is provided to the NMOS FET switch on the second node side among the plurality of NMOS FET switches. .