WO2013151998A1 - High voltage driver - Google Patents

High voltage driver Download PDF

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Publication number
WO2013151998A1
WO2013151998A1 PCT/US2013/034949 US2013034949W WO2013151998A1 WO 2013151998 A1 WO2013151998 A1 WO 2013151998A1 US 2013034949 W US2013034949 W US 2013034949W WO 2013151998 A1 WO2013151998 A1 WO 2013151998A1
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WO
WIPO (PCT)
Prior art keywords
low voltage
voltage
circuit
signal
direct current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2013/034949
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English (en)
French (fr)
Inventor
Robert J. Callanan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wolfspeed Inc
Original Assignee
Cree Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cree Inc filed Critical Cree Inc
Priority to JP2015504676A priority Critical patent/JP6465792B2/ja
Priority to DE112013001888.8T priority patent/DE112013001888B4/de
Publication of WO2013151998A1 publication Critical patent/WO2013151998A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/30—Modifications for providing a predetermined threshold before switching
    • H03K2017/307—Modifications for providing a predetermined threshold before switching circuits simulating a diode, e.g. threshold zero
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver

Definitions

  • Embodiments of the present disclosure relate to high voltage and low voltage field effect transistors, which are used in digital circuits, and specific digital circuits, such as drivers.
  • a field effect transistor is a transistor that relies on an electric field to control conductivity of a channel in a semiconductor material.
  • the channel is an active channel, majority charge carriers, electrons or holes, flow through the channel from a source of the FET to a drain of the FET.
  • Conductivity of the channel is a function of potential applied between a gate of the FET and the source.
  • an enhancement-mode only FET when a voltage between the gate and the source exceeds a threshold voltage of the FET, a low- resistance channel is established, such that the majority charge carriers can flow from the drain to the source.
  • a high-resistance channel is established, such that the majority charge carrier flow is impeded.
  • the FET When the FET is used as an electronic switch, the FET has either an ON state, in which current can flow between the source and the drain; or an OFF state, in which current is impeded from flowing between the source and the drain.
  • the FET may operate in the ON state when the voltage between the gate and the source exceeds the threshold voltage of the FET.
  • the FET Conversely, the FET may operate in the OFF state when the voltage between the gate and the source is below the threshold voltage of the FET. Therefore, if the source of the FET is coupled to ground, a voltage swing of a control signal feeding the gate of the FET must exceed the threshold voltage to ensure proper selection between the ON state and the OFF state.
  • a junction FET includes a P-N junction between the gate of the JFET and the channel of the JFET. Normally, JFETs are depletion mode only devices to prevent forward current flow though the P-N junction of the JFET.
  • a metal oxide semiconductor FET includes an oxide layer between a metal gate of the MOSFET and the channel of the MOSFET to insulate the gate from the channel. It should be noted that the term MOSFET is also commonly used to describe FETs having an oxide layer between a semiconductor gate, instead of a metal gate, of the MOSFET and the channel of the MOSFET to insulate the gate from the channel.
  • the semiconductor gate may include polysilicon.
  • MOSFET includes any FET with an oxide layer between the gate and the channel. MOSFETs may be
  • An N-type FET has a source and a drain with N- type semiconductor material
  • a P-type FET has a source and a drain with P- type semiconductor material.
  • MOSFETs may be used as electronic switches to construct logic circuits, which are commonly used in digital systems. Such logic circuits normally provide output voltage swings that are compatible with the threshold voltages of the MOSFETs used in the logic circuits. However, in some digital systems, certain MOSFETs may be used for special applications, such as high speed, high voltage, high temperature, high current, or the like. Such MOSFETs may have lower transconductance and/or higher threshold voltages than other MOSFETs in the digital system, thereby creating a voltage swing and desired gate voltage incompatibility. As such, there is need for an interface circuit, which receives an input signal having a standard voltage swing and provides an output signal having a larger voltage swing that may be used to properly drive a high gate drive voltage MOSFET.
  • Embodiments of the present disclosure relate to a circuit, which includes a high voltage driver having a low voltage input and a high voltage output.
  • the high voltage driver includes a P-type field effect transistor (PFET) and a source bias circuit.
  • the source bias circuit receives a low voltage input signal via the low voltage input and applies a direct current (DC) bias to the low voltage input signal to provide a DC biased signal.
  • the PFET has a first source, a first gate, and a first drain.
  • the first source receives the DC biased signal.
  • the first gate receives a first low voltage DC supply signal.
  • the first drain provides a high voltage output signal via the high voltage output based on the DC biased signal and the first low voltage DC supply signal.
  • the high voltage driver receives and translates the low voltage input signal to provide the high voltage output signal, such that a voltage swing of the high voltage output signal is greater than a voltage swing of the low voltage input signal.
  • the source bias circuit increases the voltage swing of the high voltage output signal beyond the voltage swing of the low voltage input signal.
  • the circuit further includes a low voltage logic driver coupled to the low voltage input.
  • the low voltage logic driver provides the low voltage input signal via the low voltage input.
  • the source bias circuit is coupled between the low voltage input and the first source.
  • the first gate is coupled to a first low voltage DC supply, which provides the first low voltage DC supply signal.
  • the first drain is coupled to the high voltage output.
  • the circuit further includes a high gate drive voltage field effect transistor (FET).
  • the high gate drive voltage FET may have a lower transconductance and/or higher threshold voltage than other FETs. As such, the high gate drive voltage FET may require a higher gate voltage than other FETs to properly transition from an OFF state to an ON state. Therefore, the greater voltage swing of the high voltage output signal may be needed for proper operation of the high gate drive voltage FET.
  • the first drain is coupled to a gate of the high gate drive voltage FET via the high voltage output.
  • the high gate drive voltage FET is a silicon carbide FET.
  • Figure 1 illustrates a circuit, which includes a high voltage driver according to one embodiment of the present disclosure.
  • Figure 2 illustrates the circuit, which further includes a low voltage logic driver and a high gate drive voltage field effect transistor according to an alternate embodiment of the circuit.
  • Figure 3 illustrates the circuit, which further includes a first low voltage DC supply according to an additional embodiment of the circuit.
  • Figure 4 illustrates the circuit, which further includes a second low voltage DC supply according to another embodiment of the circuit.
  • Figure 5 illustrates the circuit according to a further embodiment of the circuit.
  • Figure 6 illustrates the circuit according to an added embodiment of the circuit.
  • Figure 7 illustrates the circuit according to a supplementary
  • Embodiments of the present disclosure relate to a circuit, which includes a high voltage driver having a low voltage input and a high voltage output.
  • the high voltage driver includes a (P-type field effect transistor) PFET and a source bias circuit.
  • the source bias circuit receives a low voltage input signal via the low voltage input and applies a DC bias to the low voltage input signal to provide a DC biased signal.
  • the PFET has a first source, a first gate, and a first drain.
  • the first source receives the DC biased signal.
  • the first gate receives a first low voltage DC supply signal.
  • the first drain provides a high voltage output signal via the high voltage output based on the DC biased low voltage input signal and the first low voltage DC supply signal.
  • the high voltage driver receives and translates the low voltage input signal to provide the high voltage output signal, such that a voltage swing of the high voltage output signal is greater than a voltage swing of the low voltage input signal.
  • the source bias circuit increases the voltage swing of the high voltage output signal beyond the voltage swing of the low voltage input signal.
  • the circuit further includes a low voltage logic driver coupled to the low voltage input.
  • the low voltage logic driver provides the low voltage input signal via the low voltage input.
  • the source bias circuit is coupled between the low voltage input and the first source.
  • the first gate is coupled to a first low voltage DC supply, which provides the first low voltage DC supply signal.
  • the first drain is coupled to the high voltage output.
  • the circuit further includes a high gate drive voltage field effect transistor (FET).
  • the high gate drive voltage FET may have a lower transconductance and/or higher threshold voltage than other FETs. As such, the high gate drive voltage FET may require a higher gate voltage than other FETs to properly transition from an OFF state to an ON state. Therefore, the greater voltage swing of the high voltage output signal may be needed for proper operation of the high gate drive voltage FET.
  • the first drain is coupled to a gate of the high gate drive voltage FET via the high voltage output.
  • the high gate drive voltage FET is a silicon carbide FET.
  • FIG. 1 illustrates a circuit 10, which includes a high voltage driver 12 according to one embodiment of the present disclosure.
  • the high voltage driver 12 has a low voltage input LIN and a high voltage output HOUT.
  • the high voltage driver 12 includes a PFET 14 and a source bias circuit 16.
  • the PFET 14 and the source bias circuit 16 form the high voltage driver 12.
  • the PFET 14 has a first source, a first gate, and a first drain.
  • the source bias circuit 16 receives a low voltage input signal LVI via the low voltage input LIN and applies a DC bias to the low voltage input signal LVI to provide a DC biased signal DBI.
  • the first source receives the DC biased signal DBI.
  • the first gate receives a first low voltage DC supply signal DC1 .
  • the first drain provides a high voltage output signal HVO via the high voltage output HOUT based on the DC biased signal DBI and the first low voltage DC supply signal DC1 .
  • the high voltage driver 12 receives and translates the low voltage input signal LVI to provide the high voltage output signal HVO, such that a voltage swing of the high voltage output signal HVO is greater than a voltage swing of the low voltage input signal LVI.
  • the source bias circuit 16 increases the voltage swing of the high voltage output signal HVO beyond the voltage swing of the low voltage input signal LVI.
  • the voltage swing of the high voltage output signal HVO is on the order of about two times the voltage swing of the low voltage input signal LVI.
  • the voltage swing of the high voltage output signal HVO is equal to about 6 volts and the voltage swing of the low voltage input signal LVI is equal to about 3.3 volts.
  • the voltage swing of the high voltage output signal HVO is equal to about 19.4 volts and the voltage swing of the low voltage input signal LVI is equal to about 10 volts.
  • the source bias circuit 16 is coupled between the low voltage input signal LVI and the first source.
  • the first drain is coupled to the high voltage output HOUT.
  • the PFET 14 is a metal oxide semiconductor FET (MOSFET).
  • MOSFET metal oxide semiconductor FET
  • JFET junction FET
  • the PFET 14 is any type of FET.
  • the source bias circuit 16 is directly coupled between the low voltage input signal LVI and the first source, and the first drain is directly coupled to the high voltage output HOUT.
  • FIG. 2 illustrates the circuit 10 according to an alternate embodiment of the circuit 10.
  • the circuit 10 illustrated in Figure 2 is similar to the circuit 10 illustrated in Figure 1 , except the circuit 10 illustrated in Figure 2 further includes a low voltage logic driver 18 and a high gate drive voltage FET 20.
  • the low voltage logic driver 18 is coupled to the low voltage input LIN. Further, the low voltage logic driver 18 receives a driver input signal DVI and provides the low voltage input signal LVI to the high voltage driver 12 via the low voltage input LIN. As such, the low voltage input signal LVI is based on the driver input signal DVI.
  • a gate of the high gate drive voltage FET 20 is coupled to the first drain via the high voltage output HOUT.
  • the gate of the high gate drive voltage FET 20 receives the high voltage output signal HVO via the high voltage output HOUT.
  • a source of the high gate drive voltage FET 20 is coupled to a ground.
  • a drain of the high gate drive voltage FET 20 is coupled to other circuitry (not shown).
  • the low voltage logic driver 18 is directly coupled to the low voltage input LIN and the gate of the high gate drive voltage FET 20 is directly coupled to the first drain via the high voltage output HOUT.
  • the high gate drive voltage FET may have a lower transconductance and/or higher threshold voltage than other FETs. As such, the high gate drive voltage FET 20 may require a higher gate voltage than other FETs to properly transition from an OFF state to an ON state. Therefore, the greater voltage swing of the high voltage output signal HVO may be needed for proper operation of the high gate drive voltage FET 20.
  • the high gate drive voltage FET 20 may require a higher gate voltage than other FETs to properly transition from an OFF state to an ON state. Therefore, the greater voltage swing of the high voltage output signal HVO may be needed for proper operation of the high gate drive voltage FET 20.
  • the high voltage driver 12 is a high voltage logic driver, a high voltage gate driver, or both.
  • the high gate drive voltage FET 20 is a SiC FET. SiC FETs may be used in applications requiring high speed, high voltage, high temperature, high current, the like, or any combination thereof.
  • the high gate drive voltage FET 20 is an N-type FET, as illustrated in Figure 2. In an alternate embodiment of the high gate drive voltage FET 20, the high gate drive voltage FET 20 is a P- type FET. In one embodiment of the high gate drive voltage FET 20, the high gate drive voltage FET 20 is a MOSFET. In an alternate embodiment of the high gate drive voltage FET 20, the high gate drive voltage FET 20 is a JFET. In additional embodiments of the high gate drive voltage FET 20, the high gate drive voltage FET 20 is any type of FET.
  • FIG. 3 illustrates the circuit 10 according to an additional
  • the circuit 10 illustrated in Figure 3 is similar to the circuit 10 illustrated in Figure 2, except the circuit 10 illustrated in Figure 3 further includes a first low voltage DC supply 22.
  • the first low voltage DC supply 22 is coupled to the first gate and to the low voltage logic driver 18.
  • the first low voltage DC supply 22 provides the first low voltage DC supply signal DC1 .
  • the first low voltage DC supply 22 provides energy to translate the low voltage input signal LVI to provide the high voltage output signal HVO.
  • the first low voltage DC supply 22 is directly coupled to the first gate and to the low voltage logic driver 18.
  • the high voltage driver 12 further includes a first resistive element R1 coupled between the first drain and a ground.
  • the source bias circuit 16 includes a battery 24 coupled between the low voltage input LIN and the first source.
  • the battery 24 has an anode and a cathode, such that the cathode is coupled to the first source and the anode is coupled to the low voltage input LIN.
  • the cathode is positive with respect to the anode. Therefore, the battery 24 applies a DC bias to the low voltage input signal LVI, such that the DC biased signal DBI has a positive bias with respect to the low voltage input signal LVI.
  • the low voltage input signal LVI When the low voltage input signal LVI is a logic LOW, the low voltage input signal LVI may be equal to about zero volts. As such, a voltage of the DC biased signal DBI is positive and is about equal to a voltage of the battery 24. Therefore, if a difference between the voltage of the DC biased signal DBI and a voltage of the first low voltage DC supply signal DC1 is less than a threshold voltage of the PFET 14, then the PFET 14 will be in an OFF state. As a result, the first resistive element R1 will pull the high voltage output signal HVO to about zero volts, which is a logic LOW.
  • the low voltage input signal LVI is a logic HIGH
  • the low voltage input signal LVI is about equal to the voltage of the first low voltage DC supply signal DC1 .
  • the voltage of the DC biased signal DBI will be equal to the sum of the voltage of the first low voltage DC supply signal DC1 and the voltage of the battery 24. Therefore, if the difference between the voltage of the DC biased signal DBI and the voltage of the first low voltage DC supply signal DC1 is greater than the threshold voltage of the PFET 14, then the PFET 14 will be in an ON state. As a result, the PFET 14 will drive the high voltage output signal HVO to be about equal to the DC biased signal DBI, which is a logic HIGH.
  • the high voltage driver 12 translates a voltage swing of the low voltage input signal LVI, which is about equal to the voltage of the first low voltage DC supply signal DC1 , to a voltage swing of the high voltage output signal HVO, which is about equal to the sum of the voltage of the first low voltage DC supply signal DC1 and the voltage of the battery 24. Further, when the low voltage input signal LVI is a logic LOW, the high voltage output signal HVO is a logic LOW. Conversely, when the low voltage input signal LVI is a logic HIGH, the high voltage output signal HVO is a logic HIGH.
  • a maximum voltage between the first source and the first drain is less than or equal to the voltage of the first low voltage DC supply signal DC1 . In one embodiment of the circuit 10, a maximum voltage between the first gate and the first drain is less than or equal to the voltage of the first low voltage DC supply signal DC1 . In one embodiment of the circuit 10, a maximum voltage between the first source and the first gate is less than or equal to the voltage of the first low voltage DC supply signal DC1 .
  • the voltage of the battery 24 is about equal to the voltage of the first low voltage DC supply signal DC1 and the PFET 14 is an enhancement mode only FET. Therefore, the voltage swing of the high voltage output signal HVO is equal to about two times the voltage swing of the low voltage input signal LVI. Further, when the low voltage input signal LVI is a logic LOW, a voltage between the first source and the first gate is about equal to zero, which forces the PFET 14 to be in an OFF state.
  • the voltage between the first source and the first gate is about equal to the voltage of the first low voltage DC supply signal DC1 , which, if the voltage of the first low voltage DC supply signal DC1 is greater than the threshold voltage of the PFET 14, forces the PFET 14 to be in an ON state.
  • Figure 4 illustrates the circuit 10 according to another embodiment of the circuit 10.
  • the circuit 10 illustrated in Figure 4 is similar to the circuit 10 illustrated in Figure 3, except the circuit 10 illustrated in Figure 4 further includes a second low voltage DC supply 28.
  • the high voltage driver 12 further includes an N-type FET (NFET) 26 and the source bias circuit 16 includes a first capacitive element C1 and a first diode element CR1 .
  • the NFET 26 has a second source, a second gate, and a second drain.
  • the second gate is coupled to the second low voltage DC supply 28.
  • the second source is coupled to the low voltage input LIN.
  • the second drain is coupled to the high voltage output HOUT.
  • the first capacitive element C1 is coupled between the low voltage input LIN and the first source.
  • the first diode element CR1 has an anode and a cathode, such that the cathode is coupled to the first source and the anode is coupled to the first gate.
  • the NFET 26 functionally replaces the first resistive element R1 ( Figure 3), and the first capacitive element C1 and the first diode element CR1 functionally replace the battery 24 ( Figure 3).
  • the second gate is directly coupled to the second low voltage DC supply 28; the second source is directly coupled to the low voltage input LIN; the second drain is directly coupled to the high voltage output HOUT; the first capacitive element C1 is directly coupled between the low voltage input LIN and the first source; the first diode element CR1 has an anode and a cathode, such that the cathode is directly coupled to the first source and the anode is directly coupled to the first gate; or any combination thereof.
  • the first capacitive element C1 receives the low voltage input signal LVI via the low voltage input LIN.
  • the first diode element CR1 receives and rectifies the low voltage input signal LVI to feed the first capacitive element C1 .
  • the first capacitive element C1 and the first diode element CR1 provide the DC biased signal DBI based on the low voltage input signal LVI and the first low voltage DC supply signal DC1 .
  • the low voltage input signal LVI is a logic LOW
  • the low voltage input signal LVI may be equal to about zero volts.
  • the first low voltage DC supply 22 charges the first capacitive element C1 through the first diode element CR1 until a voltage across the first capacitive element C1 is equal to the voltage of the first low voltage DC supply signal DC1 minus a voltage drop across the first diode element CR1 , which may be equal to about 0.6 volts.
  • the low voltage input signal LVI transitions to a logic HIGH
  • the low voltage input signal LVI may transition to a voltage about equal to the voltage of the first low voltage DC supply signal DC1 , thereby reverse biasing the first diode element CR1 .
  • the first capacitive element C1 functions in a similar manner to the battery 24 ( Figure 3). However, to prevent discharge of the first capacitive element C1 , the first resistive element R1 ( Figure 3) is replaced with the NFET 26.
  • the second low voltage DC supply 28 provides a second low voltage DC supply signal DC2.
  • the second gate receives the second low voltage DC supply signal DC2.
  • the second source receives the low voltage input signal LVI via the low voltage input LIN.
  • the low voltage input signal LVI may be equal to about zero volts.
  • the difference between the voltage of the DC biased signal DBI and the voltage of the first low voltage DC supply signal DC1 is less than the threshold voltage of the PFET 14, then the PFET 14 will be in the OFF state.
  • the NFET 26 will be in an ON state, thereby pulling the high voltage output signal HVO to about zero volts, which is the logic LOW.
  • the PFET 14 when the low voltage input signal LVI is a logic HIGH, if the difference between the voltage of the DC biased signal DBI and the voltage of the first low voltage DC supply signal DC1 is greater than the threshold voltage of the PFET 14, then the PFET 14 will be in the ON state, thereby driving the high voltage output signal HVO to provide the logic HIGH. Further, if a difference between the voltage of the second low voltage DC supply signal DC2 and the low voltage input signal LVI is less than the threshold voltage of the NFET 26 or if the low voltage input signal LVI reverse biases the second gate/second source, then the NFET 26 will be in an OFF state. In this regard, when the PFET 14 is in the ON state, the NFET 26 is in the OFF state.
  • the NFET 26 transitions from the ON state to the OFF state before the PFET 14 transitions from the OFF state to the ON state. Further, in one embodiment of the high voltage driver 12, the PFET 14 transitions from the ON state to the OFF state before the NFET 26 transitions from the OFF state to the ON state. In one embodiment of the circuit 10, the voltage of the first low voltage DC supply signal DC1 is about equal to two times a voltage of the second low voltage DC supply signal DC2.
  • the NFET 26 is a MOSFET. In an alternate embodiment of the NFET 26, the NFET 26 is a JFET. In additional embodiments of the NFET 26, the NFET 26 is any type of FET. In one embodiment of the circuit 10, a transconductance of the high gate drive voltage FET 20 is greater than a transconductance of the NFET 26. In an exemplary embodiment of the circuit 10, the turn-on gate voltage of the high gate drive voltage FET 20 is on the order of about two times the turn-on voltage of the NFET 26. In one embodiment of the circuit 10, the turn-on voltage of the high gate drive voltage FET 20 is greater than the turn-on voltage of the PFET 14. In an exemplary embodiment of the circuit 10, the turn-on voltage of the high gate drive voltage FET 20 is on the order of about two times the turn-on voltage of the PFET 14.
  • Figure 5 illustrates the circuit 10 according to a further embodiment of the circuit 10.
  • the circuit 10 illustrated in Figure 5 is similar to the circuit 10 illustrated in Figure 4, except in the circuit 10 illustrated in Figure 5, the second low voltage DC supply 28 receives the first low voltage DC supply signal DC1 and provides the second low voltage DC supply signal DC2 based on the first low voltage DC supply signal DC1 .
  • the voltage of the first low voltage DC supply signal DC1 is about equal to two times the voltage of the second low voltage DC supply signal DC2.
  • the second low voltage DC supply 28 is a DC-DC converter, a resistor divider, a charge pump, a linear converter, a zener diode based converter, the like, or any combination thereof.
  • Figure 6 illustrates the circuit 10 according to an added embodiment of the circuit 10.
  • the circuit 10 illustrated in Figure 6 is similar to the circuit 10 illustrated in Figure 4, except in the circuit 10 illustrated in Figure 6, the second low voltage DC supply 28 is omitted and the second gate is coupled to the first low voltage DC supply 22.
  • the second gate receives the first low voltage DC supply signal DC1 .
  • the second gate is directly coupled to the first low voltage DC supply 22.
  • Figure 7 illustrates the circuit 10 according to a supplementary embodiment of the circuit 10.
  • the circuit 10 illustrated in Figure 7 is similar to the circuit 10 illustrated in Figure 4, except in the circuit 10 illustrated in Figure 7, the low voltage logic driver 18, the high gate drive voltage FET 20, the first low voltage DC supply 22, and the second low voltage DC supply 28 are provided external to the circuit 10.
  • the circuit 10 includes any or all of the high gate drive voltage FET 20, the first low voltage DC supply 22, and the second low voltage DC supply 28.
  • any or all of the high gate drive voltage FET 20, the first low voltage DC supply 22, and the second low voltage DC supply 28 are omitted.

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  • Electronic Switches (AREA)
  • Power Conversion In General (AREA)
  • Logic Circuits (AREA)
PCT/US2013/034949 2012-04-04 2013-04-02 High voltage driver Ceased WO2013151998A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015504676A JP6465792B2 (ja) 2012-04-04 2013-04-02 高電圧ドライバ
DE112013001888.8T DE112013001888B4 (de) 2012-04-04 2013-04-02 Hochspannungstreiber

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/438,927 US9344077B2 (en) 2012-04-04 2012-04-04 High voltage driver
US13/438,927 2012-04-04

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WO2013151998A1 true WO2013151998A1 (en) 2013-10-10

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JP (1) JP6465792B2 (https=)
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9660642B2 (en) * 2015-07-07 2017-05-23 Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. Expansion control circuit
US20190326900A1 (en) * 2018-04-24 2019-10-24 Infineon Technologies Ag Driver circuit for a device circuit
EP3847739A4 (en) * 2018-09-05 2022-07-06 Efficient Power Conversion Corporation GAN-BASED ADJUSTABLE POWER DRIVER CIRCUIT

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4446327A1 (de) * 1994-12-23 1996-07-04 Siemens Ag Schaltungsanordnung zum Ansteuern eines Leistungs-MOSFET
DE19655180C2 (de) * 1995-04-11 2001-05-03 Int Rectifier Corp Spannungsseitiger Schalterkreis
US20110163797A1 (en) * 2009-06-30 2011-07-07 Decicon, Inc. Power switch with reverse current blocking capability

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07249740A (ja) * 1994-03-09 1995-09-26 Mitsubishi Electric Corp 昇圧回路およびこれを利用した電圧駆動型半導体素子の駆動回路
GB9525638D0 (en) * 1995-12-15 1996-02-14 Philips Electronics Nv Matrix display devices
EP0887931A1 (en) * 1997-06-24 1998-12-30 STMicroelectronics S.r.l. Protection circuit for controlling the gate voltage of a high voltage LDMOS transistor
US6100868A (en) * 1997-09-15 2000-08-08 Silicon Image, Inc. High density column drivers for an active matrix display
DK1151638T3 (da) * 1998-12-17 2007-06-04 Biotage Ab Mikrobölgeapparat og fremgangsmåder til udförelse af kemiske reaktioner
DE19950023A1 (de) * 1999-10-09 2001-04-12 Bosch Gmbh Robert Ansteuervorrichtung für einen Schalter zum elektronischen Schalten eines Verbrauchers
GB0109971D0 (en) * 2001-04-24 2001-06-13 Harvey Geoffrey P Electronic logic driver circuit utilizing mutual induction between coupled inductors to drive capacitive loads with low power consumption
US6661276B1 (en) 2002-07-29 2003-12-09 Lovoltech Inc. MOSFET driver matching circuit for an enhancement mode JFET
US6972973B2 (en) * 2003-01-09 2005-12-06 Denso Corporation Voltage booster having noise reducing structure
JP3675457B2 (ja) * 2003-06-19 2005-07-27 セイコーエプソン株式会社 昇圧クロック生成回路及び半導体装置
TWI224869B (en) 2004-03-25 2004-12-01 Richtek Techohnology Corp Apparatus for driving depletion type junction field effect transistor
TW200642246A (en) * 2005-05-20 2006-12-01 Richtek Technology Corp DC buck/boost converter
JP2011101209A (ja) * 2009-11-06 2011-05-19 Toyota Motor Corp レベルシフタ誤動作防止回路
JP5263317B2 (ja) 2011-02-15 2013-08-14 株式会社デンソー 半導体スイッチング素子の駆動回路
JP2013013044A (ja) 2011-05-31 2013-01-17 Sanken Electric Co Ltd ゲートドライブ回路
JP5587253B2 (ja) * 2011-06-27 2014-09-10 ウィンボンド エレクトロニクス コーポレーション 昇圧回路
JP2013099123A (ja) 2011-11-01 2013-05-20 Sanken Electric Co Ltd ゲート駆動回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4446327A1 (de) * 1994-12-23 1996-07-04 Siemens Ag Schaltungsanordnung zum Ansteuern eines Leistungs-MOSFET
DE19655180C2 (de) * 1995-04-11 2001-05-03 Int Rectifier Corp Spannungsseitiger Schalterkreis
US20110163797A1 (en) * 2009-06-30 2011-07-07 Decicon, Inc. Power switch with reverse current blocking capability

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JP2015520537A (ja) 2015-07-16
US20130265084A1 (en) 2013-10-10
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JP6465792B2 (ja) 2019-02-06
DE112013001888B4 (de) 2020-08-20

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