WO2013148444A1 - Remplissage d'entités par du tungstène avec inhibition de la nucléation - Google Patents

Remplissage d'entités par du tungstène avec inhibition de la nucléation Download PDF

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Publication number
WO2013148444A1
WO2013148444A1 PCT/US2013/033174 US2013033174W WO2013148444A1 WO 2013148444 A1 WO2013148444 A1 WO 2013148444A1 US 2013033174 W US2013033174 W US 2013033174W WO 2013148444 A1 WO2013148444 A1 WO 2013148444A1
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Prior art keywords
feature
tungsten
plasma
inhibition
selectively
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PCT/US2013/033174
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English (en)
Inventor
Anand Chandrashekar
Esther JENG
Raashina Humayun
Michal Danek
Juwen Gao
Deqi Wang
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Novellus Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from US13/774,350 external-priority patent/US10256142B2/en
Application filed by Novellus Systems, Inc. filed Critical Novellus Systems, Inc.
Priority to KR1020147029798A priority Critical patent/KR102100520B1/ko
Priority to CN201380022648.2A priority patent/CN104272440B/zh
Priority to JP2015503376A priority patent/JP6195898B2/ja
Publication of WO2013148444A1 publication Critical patent/WO2013148444A1/fr

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    • H—ELECTRICITY
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/205—
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/04—Coating on selected surface areas, e.g. using masks
    • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment

Definitions

  • tungsten-containing materials using chemical vapor deposition (CVD) techniques is an integral part of many semiconductor fabrication processes. These materials may be used for horizontal interconnects, vias between adjacent metal layers, contacts between first metal layers and devices on the silicon substrate, and high aspect ratio features.
  • CVD chemical vapor deposition
  • a substrate is heated to a predetermined process temperature in a deposition chamber, and a thin layer of tungsten-containing materials that serves as a seed or nucleation layer is deposited. Thereafter, the remainder of the tungsten-containing material (the bulk layer) is deposited on the nucleation layer.
  • the tungsten- containing materials are formed by the reduction of tungsten hexafluoride (WF 6 ) with hydrogen (H 2 ). Tungsten-containing materials are deposited over an entire exposed surface area of the substrate including features and a field region.
  • Depositing tungsten-containing materials into small and, especially, high aspect ratio features may cause formation of seams and voids inside the filled features.
  • Large seams may lead to high resistance, contamination, loss of filled materials, and otherwise degrade performance of integrated circuits.
  • a seam may extend close to the field region after filling process and then open during chemical- mechanical planarization.
  • One aspect described herein is a method involving providing a substrate including a feature having one or more feature openings and a feature interior, selectively inhibiting tungsten nucleation in the feature such that there is a differential inhibition profile along a feature axis; and selectively depositing tungsten in the feature in accordance with the differential inhibition profile.
  • Methods of selectively inhibiting tungsten nucleation in the feature include exposing the feature to a direct plasma or a remote plasma.
  • the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile.
  • the plasma can contain activated species that interact with a portion the feature surface to inhibit subsequent tungsten nucleation. Examples of activated species include nitrogen, hydrogen, oxygen, and carbon activated species.
  • the plasma is nitrogen and/or hydrogen-based.
  • a tungsten layer is deposited in the feature prior to any selective inhibition of tungsten nucleation. In other embodiments, selective inhibition is performed prior to any tungsten deposition in the feature. If deposited, a tungsten layer may be deposited conformally, in some embodiments, for example by a pulsed nucleation layer (PNL) or atomic layer deposition (ALD) process. Selective deposition of tungsten in the feature can be performed by a chemical vapor deposition (CVD) process.
  • PNL pulsed nucleation layer
  • ALD atomic layer deposition
  • Selective deposition of tungsten in the feature can be performed by a chemical vapor deposition (CVD) process.
  • tungsten can be deposited in the feature to complete feature fill. According to various embodiments, this can involve non-selective deposition in the feature or one or more additional cycles of selective inhibition and selective deposition. In some embodiments, transitioning from selective to non-selective deposition involve allowing a CVD process to continue without deposition of an intervening tungsten nucleation layer. In some embodiments, a tungsten nucleation layer can be deposited on the selectively deposited tungsten, e.g., by a PNL or ALD process, prior to non-selective deposition in the feature.
  • selectively inhibiting tungsten nucleation can involve treating a tungsten (W) surface, or a barrier or liner layer, such as a tungsten nitride (WN) or titanium nitride (TiN) layer. Selective inhibition can be performed with or without simultaneous etching material in the feature. According to various embodiments, at least a constriction in the feature is selectively inhibited.
  • Another aspect of the invention relates to a method include exposing a feature to an in-situ plasma to selectively inhibit a portion of the feature.
  • the plasma can be nitrogen-based, hydrogen-based, oxygen- based, or hydrocarbon-based.
  • the plasma can contain a mixture of two or more of a nitrogen-containing, hydrogen-containing, oxygen- containing, or hydrocarbon-containing gas.
  • an unfilled or partially filled feature may be exposed to a direct plasma to thereby selectively inhibit tungsten nucleation of a portion of the feature such that there is a differential inhibition profile in the feature.
  • performing a CVD operation to thereby selectively deposit tungsten in accordance with the differential inhibition profile.
  • an apparatus includes one or more chambers configured to support a substrate; an in situ plasma generator configured to generate a plasma in one or more of the chambers; gas inlets configured to direct gas into each of the one or more chambers; and a controller having program instructions for generating a plasma such as a nitrogen- based and/or hydrogen-based plasma while applying a bias power to the substrate such that the substrate is exposed to the plasma, after exposing the substrate to the plasma, inletting a tungsten-containing precursor and a reducing agent to a chamber in which the substrate sits to deposit tungsten.
  • a plasma such as a nitrogen- based and/or hydrogen-based plasma
  • Figures 1A-1G show examples of various structures that can be filled according to the processes described herein.
  • Figures 2-4 are process flow diagrams illustrating certain operations in methods of filling features with tungsten.
  • Figures 5-7 are schematic diagrams showing features at various stages of feature fill.
  • FIGS 8-9B are schematic diagrams showing examples of apparatus suitable for practicing the methods described herein. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
  • Described herein are methods of filling features with tungsten and related systems and apparatus. Examples of application include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration with through-silicon vias (TSVs).
  • TSVs through-silicon vias
  • the methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines.
  • the methods may be used for conformal and bottom-up or inside-out fill.
  • the features can be characterized by one or more of narrow and/or re-entrant openings, constrictions within the feature, and high aspect ratios. Examples of features that can be filled are depicted in Figures 1 A- 1C.
  • Figure 1A shows an example of a cross-sectional depiction of a vertical feature 101 to be filled with tungsten.
  • the feature can include a feature hole 105 in a substrate 103.
  • the substrate may be a silicon wafer, e.g., 200-mm wafer, 300-mm wafer, 450-mm wafer, including wafers having one or more layers of material such as dielectric, conducting, or semi-conducting material deposited thereon.
  • the feature hole 105 may have an aspect ratio of at least about 2: 1, at least about 4: 1, at least about 6: 1 or higher.
  • the feature hole 105 may also have a dimension near the opening, e.g., an opening diameter or line width, of between about 10 nm to 500 nm, for example between about 25 nm to 300 nm.
  • the feature hole 105 can be referred to as an unfilled feature or simply a feature.
  • the feature, and any feature may be characterized in part by an axis 118 that extends through the length of the feature, with vertically-oriented features having vertical axes and horizontally- oriented features having horizontal axes.
  • Figure IB shows an example of a feature 101 that has a re-entrant profile.
  • a re-entrant profile is a profile that narrows from a bottom, closed end, or interior of the feature to the feature opening. According to various embodiments, the profile may narrow gradually and/or include an overhang at the feature opening.
  • Figure IB shows an example of the latter, with an under-layer 113 lining the sidewall or interior surfaces of the feature hole 105.
  • the under-layer 113 can be for example, a diffusion barrier layer, an adhesion layer, a nucleation layer, a combination of thereof, or any other applicable material.
  • the under-layer 113 forms an overhang 115 such that the under-layer 113 is thicker near the opening of the feature 101 than inside the feature 101.
  • FIG. 1C shows examples of views of various filled features having constrictions.
  • Each of the examples (a), (b) and (c) in Figure 1C includes a constriction 109 at a midpoint within the feature.
  • the constriction 109 can be, for example, between about 15 nm-20 nm wide.
  • Constrictions can cause pinch off during deposition of tungsten in the feature using conventional techniques, with deposited tungsten blocking further deposition past the constriction before that portion of the feature is filled, resulting in voids in the feature.
  • Example (b) further includes a liner/barrier overhang 115 at the feature opening. Such an overhang could also be a potential pinch-off point.
  • Example (c) includes a constriction 112 further away from the field region than the overhang 115 in example (b). As described further below, methods described herein allow void- free fill as depicted in Figure 1C.
  • Figure ID shows an example of a word line 150 in a VNAND structure 148 that includes a constriction 151.
  • the constrictions can be due to the presence of pillars in a VNAND or other structure.
  • Figure IE shows a plan view of pillars 125 in a VNAND structure, with Figure IF showing a simplified schematic of a cross-sectional depiction of the pillars 125.
  • Arrows in Figure IE represent deposition material; as pillars 125 are disposed between an area 127 and a gas inlet or other deposition source, adjacent pillars can result in constrictions that present challenges in void free fill of an area 127.
  • Figure 1G provides another example of a view horizontal feature, for example, of a VNAND or other structure including pillar constrictions 151.
  • the example in Figure 1G is open-ended, with material to be deposited able to enter laterally from two sides as indicated by the arrows.
  • 3-D structures can be characterized with the area to be filled extending along three dimensions (e.g., in the X, Y and Z-directions in the example of Figure IF), and can present more challenges for fill than filling holes or trenches that extend along one or two dimensions. For example, controlling fill of a 3-D structure can be challenging as deposition gasses may enter a feature from multiple dimensions.
  • Filling features with tungsten-containing materials may cause formation of voids and seams inside the filled features.
  • a void is region in the feature that is left unfilled.
  • a void can form, for example, when the deposited material forms a pinch point within the feature, sealing off an unfilled space within the feature preventing reactant entry and deposition.
  • tungsten in the feature may contain a seam running through the axis or middle of the via, trench, line or other feature. This is because tungsten growth can begin at the sidewall and continues until the grains meet with tungsten growing from the opposite sidewall. This seam can allow for trapping of impurities including fluorine-containing compounds such as hydrofluoric acid (HF). During chemical mechanical planarization (CMP), coring can also propagate from the seam.
  • CMP chemical mechanical planarization
  • the methods described herein can reduce or eliminate void and seam formation. The methods described herein may also address one or more of the following:
  • Void free fill can be achieved in most reentrant features using dep-etch-dep cycles as described in U.S. Patent Application No. 13/351,970, incorporated by reference herein. However, depending on the dimensions and geometry, multiple dep-etch cycles may be needed to achieve void-free fill. This can affect process stability and throughput. Embodiments described herein can provide feature fill with fewer or no dep-etch-dep cycles.
  • Figures 2-4 provide overviews of various processes of tungsten feature fill that can address the above issues, with examples of tungsten fill of various features described with reference to Figures 5-7.
  • FIG. 2 is a process flow diagram illustrating certain operations in a method of filling a feature with tungsten.
  • the method begins at a block 201 with selective inhibition of a feature.
  • Selective inhibition which may also be referred to as selective passivation, differential inhibition, or differential passivation, involves inhibiting subsequent tungsten nucleation on a portion of the feature, while not inhibiting nucleation (or inhibiting nucleation to a lesser extent) on the remainder of the feature.
  • a feature is selectively inhibited at a feature opening, while nucleation inside the feature is not inhibited.
  • Selective inhibition is described further below, and can involve, for example, selectively exposing a portion of the feature to activated species of a plasma.
  • a feature opening is selectively exposed to a plasma generated from molecular nitrogen gas.
  • a desired inhibition profile in a feature can be formed by appropriately selecting one or more of inhibition chemistry, substrate bias power, plasma power, process pressure, exposure time, and other process parameters.
  • Block 203 may involve one or more chemical vapor deposition (CVD) and/or atomic layer deposition (ALD) processes, including thermal, plasma-enhanced CVD and/or ALD processes.
  • the deposition is selective in that the tungsten preferentially grows on the lesser- and non-inhibited portions of the feature.
  • block 203 involves selectively depositing tungsten in a bottom or interior portion of the feature until a constriction is reached or passed.
  • block 205 involves a CVD process in which a tungsten-containing precursor is reduced by hydrogen to deposit tungsten. While tungsten hexafluoride (WF 6 ) is often used, the process may be performed with other tungsten precursors, including, but not limited to, tungsten hexachloride (WC1 6 ), organo-metallic precursors, and precursors that are free of fluorine such as MDNOW (methylcyclopentadienyl-dicarbonylnitrosyl-tungsten) and EDNOW
  • tungsten hexacarbonyl (W(CO) 6 ) may be used with or without a reducing agent.
  • W(CO) 6 tungsten hexacarbonyl
  • the WF 6 and H 2 or other reactants are simultaneously introduced into the reaction chamber. This produces a continuous chemical reaction of mix reactant gases that continuously forms tungsten film on the substrate surface.
  • Patent Application NoS. 12/202,126, 12/755,248 and 12/755,259 which are incorporated by reference herein in their entireties for the purposes of describing tungsten deposition processes. According to various embodiments, the methods described herein are not limited to a particular method of filling a feature but may include any appropriate deposition technique.
  • block 205 may involve continuing a CVD deposition process started at block 203. Such a CVD process may result in deposition on the inhibited portions of the feature, with nucleation occurring more slowly than on the non-inhibited portions of the feature. In some embodiments, block 205 may involve deposition of a tungsten nucleation layer over at least the inhibited portions of the feature.
  • the feature surface that is selectively inhibited can be a barrier or liner layer, such as a metal nitride layer, or it can be a layer deposited to promote nucleation of tungsten.
  • Figure 3 shows an example of a method in which a tungsten nucleation layer is deposited in the feature prior to selective inhibition. The method begins at block 301 with deposition of the thin conformal layer of tungsten in the feature. The layer can facilitate subsequent deposition of bulk tungsten-containing material thereon.
  • the nucleation layer is deposited using a PNL technique.
  • PNL broadly embodies any cyclical process of sequentially adding reactants for reaction on a semiconductor substrate, including ALD techniques.
  • PNL techniques for depositing tungsten nucleation layers are described in U.S. Patents 6,635,965; 7,589,017; 7,141,494; 7,772,114; 8,058,170 and in US Patent Application Nos. 12/755,248 and 12/755,259, which are incorporated by reference herein in their entireties for the purposes of describing tungsten deposition processes.
  • Block 301 is not limited to a particular method of tungsten nucleation layer deposition, but includes PNL, ALD, CVD, and physical vapor deposition (PVD) techniques for depositing a thin conformal layer.
  • the nucleation layer can be sufficiently thick to fully cover the feature to support high quality bulk deposition; however, because the resistivity of the nucleation layer is higher than that of the bulk layer, the thickness of the nucleation layer may be minimized to keep the total resistance as low as possible.
  • Example thicknesses of films deposited in block 301 can range from less than 10 A to 100 A.
  • Figure 4 shows an example of a method in which completing filling the feature (e.g., block 205 in Figure 2 or 3) can involve repeating selective inhibition and deposition operations.
  • the method can begin at block 201, as described above with respect to Figure 2, in which the feature is selectively inhibited, and continue at block 203 with selective deposition according to the inhibition profile. Blocks 201 and 203 are then repeated one or more times (block 401) to complete feature fill.
  • An example of filling a feature according to a method of Figure 4 is described below with reference to Figure 6.
  • selective inhibition can be used in conjunction with selective deposition.
  • Selective deposition techniques are described in U.S. Provisional Patent Application No. 61/616,377, referenced above.
  • selective inhibition can involve exposure to activated species that passivate the feature surfaces.
  • a tungsten (W) surface can be passivated by exposure to a nitrogen-based or hydrogen-based plasma.
  • inhibition can involve a chemical reaction between activated species and the feature surface to form a thin layer of a compound material such as tungsten nitride (WN) or tungsten carbide (WC).
  • WN tungsten nitride
  • WC tungsten carbide
  • inhibition can involve a surface effect such as adsorption that passivates the surface without forming a layer of a compound material.
  • Activated species may be formed by any appropriate method including by plasma generation and/or exposure to ultraviolet (UV) radiation.
  • the substrate including the feature is exposed to a plasma generated from one or more gases fed into the chamber in which the substrate sits.
  • one or more gases may be fed into a remote plasma generator, with activated species formed in the remote plasma generator fed into a chamber in which the substrate sits.
  • the plasma source can be any type of source including radio frequency (RF) plasma source or microwave source.
  • the plasma can be inductively and/or capacitively- coupled.
  • Activated species can include atomic species, radical species, and ionic species.
  • exposure to a remotely-generated plasma includes exposure to radical and atomized species, with substantially no ionic species present in the plasma such that the inhibition process is not ion-mediated.
  • ion species may be present in a remotely-generated plasma.
  • exposure to an in-situ plasma involves ion-mediated inhibition.
  • activated species are distinguished from recombined species and from the gases initially fed into a plasma generator.
  • Inhibition chemistries can be tailored to the surface that will be subsequently exposed to deposition gases.
  • W surfaces as formed for example in a method described with reference to Figure 3, exposure to nitrogen-based and/or hydrogen-based plasmas inhibits subsequent tungsten deposition on the W surfaces.
  • Other chemistries that may be used for inhibition of tungsten surfaces include oxygen-based plasmas and hydrocarbon-based plasmas. For example, molecular oxygen or methane may be introduced to a plasma generator.
  • a nitrogen-based plasma is a plasma in which the main non-inert component is nitrogen.
  • An inert component such as argon, xenon, or krypton may be used as a carrier gas.
  • no other non-inert components are present in the gas from which the plasma is generated except in trace amounts.
  • inhibition chemistries may be nitrogen-containing, hydrogen-containing, oxygen-containing, and/or carbon-containing, with one or more additional reactive species present in the plasma.
  • U.S. Patent Application No. 13/016,656, incorporated by reference herein describes passivation of a tungsten surface by exposure to nitrogen trifluoride (NF 3 ).
  • fluorocarbons such as CF 4 or C 2 F8 may be used.
  • the inhibition species are fluorine-free to prevent etching during selective inhibition.
  • UV radiation may be used in addition to or instead of plasma to provide activated species. Gases may be exposed to UV light upstream of and/or inside a reaction chamber in which the substrate sits.
  • non-plasma, non-UV, thermal inhibition processes may be used.
  • nucleation may be inhibited on liner/barrier layers surfaces such as TiN and/or WN surfaces. Any chemistry that passivates these surfaces may be used. For TiN and WN, this can include exposure to nitrogen-based or nitrogen-containing chemistries. In certain embodiments, the chemistries described above for W may also be employed for TiN, WN, or other liner layer surfaces.
  • Tuning an inhibition profile can involve appropriately controlling an inhibition chemistry, substrate bias power, plasma power, process pressure, exposure time, and other process parameters.
  • a bias can be applied to the substrate.
  • Substrate bias can, in some embodiments, significantly affect an inhibition profile, with increasing bias power resulting in active species deeper within the feature. For example, 100 W DC bias on a 300 mm substrate may result inhibition the top half of a 1500 nm deep structure, while a 700 W bias may result in inhibition of the entire structure.
  • bias power can be used to tune top- to-bottom selectivity, with decreasing bias power resulting in higher selectivity.
  • increased bias power can be used to promote top-to-bottom deposition uniformity.
  • bias power can be used in certain embodiments as the primary or only knob to tune an inhibition profile for ionic species
  • other performing selective inhibition uses other parameters in addition to or instead of bias power. These include remotely generated non-ionic plasma processes and non-plasma processes.
  • a substrate bias can be easily applied to tune selectivity in vertical but not lateral direction. Accordingly, for 3-D structures in which lateral selectivity is desired, parameters other than bias may be controlled, as described above.
  • Inhibition chemistry can also be used to tune an inhibition profile, with different ratios of active inhibiting species used.
  • nitrogen may have a stronger inhibiting effect than hydrogen; adjusting the ratio of N 2 and H 2 gas in a forming gas-based plasma can be used to tune a profile.
  • the plasma power may also be used to tune an inhibition profile, with different ratios of active species tuned by plasma power.
  • Process pressure can be used to tune a profile, as pressure can cause more recombination (deactivating active species) as well as pushing active species further into a feature.
  • Process time may also be used to tune inhibition profiles, with increasing treatment time causing inhibition deeper into a feature.
  • selective inhibition can be achieved by performing operation 203 in a mass transport limited regime.
  • the inhibition rate inside the feature is limited by amounts of and/or relative compositions of different inhibition material components (e.g., an initial inhibition species, activated inhibition species, and recombined inhibition species) that diffuse into the feature.
  • inhibition rates depend on various components' concentrations at different locations inside the feature.
  • Mass transport limiting conditions may be characterized, in part, by overall inhibition concentration variations.
  • a concentration is less inside the feature than near its opening resulting in a higher inhibition rate near the opening than inside. This in turn leads to selective inhibition near the feature opening.
  • Mass transport limiting process conditions may be achieved by supplying limited amounts of inhibition species into the processing chamber (e.g., use low inhibition gas flow rates relative to the cavity profile and dimensions), while maintaining relative high inhibition rates near the feature opening to consume some activated species as they diffuse into the feature.
  • a concentration gradient is substantial, which may be caused relatively high inhibition kinetics and relatively low inhibition supply.
  • an inhibition rate near the opening may also be mass transport limited, though this condition is not required to achieve selective inhibition.
  • selective inhibition may be influenced by relative concentrations of different inhibition species throughout the feature. These relative concentrations in turn can depend on relative dynamics of dissociation and recombination processes of the inhibition species.
  • an initial inhibition material such as molecular nitrogen
  • an in-situ plasma can be passed through a remote plasma generator and/or subjected to an in-situ plasma to generate activated species (e.g., atomic nitrogen, nitrogen ions).
  • activated species may recombine into less active recombined species (e.g., nitrogen molecules) and/or react with W, WN, TiN, or other feature surfaces along their diffusion paths.
  • different parts of the feature may be exposed to different concentrations of different inhibition materials, e.g., an initial inhibition gas, activated inhibition species, and recombined inhibition species.
  • an initial inhibition gas e.g., an initial inhibition gas
  • activated inhibition species e.g., an initial inhibition gas
  • recombined inhibition species e.g., an initial inhibition gas
  • activated species are generally more reactive than initial inhibition gases and recombined inhibition species.
  • the activated species may be less sensitive to temperature variations than the recombined species. Therefore, process conditions may be controlled in such a way that removal is predominantly attributed to activated species.
  • some species may be more reactive than others.
  • specific process conditions may result in activated species being present at higher concentrations near features' openings than inside the features.
  • activated species may be consumed (e.g., reacted with feature surface materials and/or adsorbed on the surface) and/or recombined while diffusing deeper into the features, especially in small high aspect ratio features.
  • Recombination of activated species can also occur outside of features, e.g., in the showerhead or the processing chamber, and can depends on chamber pressure. Therefore, chamber pressure may be specifically controlled to adjust concentrations of activated species at various points of the chamber and features.
  • Flow rates of the inhibition gas can depend on a size of the chamber, reaction rates, and other parameters.
  • a flow rate can be selected in such a way that more inhibition material is concentrated near the opening than inside the feature.
  • these flow rates cause mass-transport limited selective inhibition.
  • a flow rate for a 195-liter chamber per station may be between about 25 seem and 10,000 seem or, in more specific embodiments, between about 50 seem and 1,000 seem.
  • the flow rate is less than about 2,000 seem, less than about 1,000 seem, or more specifically less than about 500 seem. It should be noted that these values are presented for one individual station configured for processing a 300-mm substrate. These flow rates can be scaled up or down depending on a substrate size, a number of stations in the apparatus (e.g., quadruple for a four station apparatus), a processing chamber volume, and other factors.
  • the substrate can be heated up or cooled down before selective inhibition.
  • Various devices may be used to bring the substrate to the predetermined temperature, such as a heating or cooling element in a station (e.g., an electrical resistance heater in stalled in a pedestal or a heat transfer fluid circulated through a pedestal), infrared lamps above the substrate, igniting plasma, etc.
  • a predetermined temperature for the substrate can be selected to induce a chemical reaction between the feature surface and inhibition species and/or promote adsorption of the inhibition species, as well as to control the rate of the reaction or adsorption.
  • a temperature may be selected to have high reaction rate such that more inhibition occurs near the opening than inside the feature.
  • a temperature may be also selected to control recombination of activated species (e.g., recombination of atomic nitrogen into molecular nitrogen) and/or control which species (e.g., activated or recombined species) contribute predominantly to inhibition.
  • a substrate is maintained at less than about 300°C, or more particularly at less than about 250°C, or less than about 150°C, or even less than about 100°C.
  • a substrate is heated to between about 300°C and 450°C or, in more specific embodiments, to between about 350°C and 400°C.
  • Other temperature ranges may be used for different types of inhibition chemistries.
  • Exposure time can also be selected to cause selective inhibition. Example exposure times can range from about 10 s to 500 s, depending on desired selectivity and feature depth.
  • aspects of the invention can be used for VNAND wordline (WL) fill. While the below discussion provides a framework for various methods, the methods are not so limited and can be implemented in other applications as well, including logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3D integration (TSV).
  • WL wordline
  • TSV 3D integration
  • Figure IF provides an example of a VNAND wordline structure to be filled.
  • feature fill of these structures can present several challenges including constrictions presented by pillar placement.
  • a high feature density can cause a loading effect such that reactants are used up prior to complete fill.
  • FIG. 5 shows a sequence in which non-conformal selective inhibition is used to fill in the interior of the feature before pinch off.
  • a structure 500 is provided with a liner layer surface 502.
  • the liner layer surface 502 may be for example, TiN or WN.
  • a W nucleation layer 504 is conformally deposited on the liner layer 502.
  • a PNL process as described above can be used. Note that in some embodiments, this operation of depositing a conformal nucleation layer may be omitted.
  • the structure is exposed to an inhibition chemistry to selectively inhibit portions 506 of the structure 500.
  • the portions 508 through the pillar constrictions 151 are selectively inhibited. Inhibition can involve for example, exposure to a direct (in-situ) plasma generated from a gas such as N 2 , H 2 , forming gas, NH 3 , 0 2 , CH 4 , etc. Other methods of exposing the feature to inhibition species are described above.
  • a CVD process is performed to selectively deposit tungsten in accordance with the inhibition profile: bulk tungsten 510 is preferentially deposited on the non-inhibited portions of the nucleation layer 504, such that hard-to-fill regions behind constrictions are filled. The remainder of the feature is then filled with bulk tungsten 510.
  • the same CVD process used to selectively deposit tungsten may be used to remainder of the feature, or a different CVD process using a different chemistry or process conditions and/or performed after a nucleation layer is deposited may be used.
  • Figure 6 shows an example of a feature hole 105 including a under-layer 113, which can be, for example, a metal nitride or other barrier layer.
  • a tungsten layer 653 is conformally deposited in the feature hole 10, for example, by a PNL and/or CVD method.
  • tungsten nucleation on the under-layer 113 can be selectively inhibited prior to selective deposition of the tungsten layer 653.
  • Further deposition on the tungsten layer 653 is then selectively inhibited, forming inhibited portion 655 of the tungsten layer 653 near the feature opening.
  • Tungsten is then selectively deposited by a PNL and/or CVD method in accordance with the inhibition profile such that tungsten is preferentially deposited near the bottom and mid-section of the feature. Deposition continues, in some embodiments with one or more selective inhibition cycles, until the feature is filled.
  • the inhibition effect at the feature top can be overcome by a long enough deposition time, while in some embodiments, an additional nucleation layer deposition or other treatment may be performed to lessen or remove the passivation at the feature opening once deposition there is desired.
  • feature fill may still include formation of a seam, such as seam 657 depicted in Figure 6.
  • the feature fill may be void-free and seam-free. Even if a seam is present, it may be smaller than obtained with a conventionally filled feature, reducing the problem of coring during CMP.
  • the sequence depicted in the example of Figure 6 ends post-CMP with a relatively small void present.
  • Figure 7 depicts a sequence in which a feature 700 is filled by a method according to certain embodiments.
  • a thin conformal layer of tungsten 753 is deposited initially, followed by selective inhibition to form inhibited portions 755, layer 753 at the bottom of the feature not treated.
  • CVD deposition results in a bulk film 757 deposited on at the bottom of the feature. This is then followed by repeated cycles of selective CVD deposition and selective inhibition until the feature is filled with bulk tungsten 757.
  • nucleation on the sidewalls of the feature is inhibited except near the bottom of the feature, fill is bottom-up.
  • different parameters may be used in successive inhibitions to tune the inhibition profile appropriately as the bottom of the feature grows closer to the feature opening. For example, a bias power and/or treatment time may be decreased is successive inhibition treatments.
  • 3D VNAND features similar to the schematic depiction in Figure IF were exposed to plasmas generated from N 2 H 2 gas after deposition of an initial tungsten seed layer.
  • the substrate was biased with a DC bias, with bias power varied from 100 W to 700 W and exposure time varied between 20 s and 200 s. Longer time resulted in deeper and wider inhibition, with higher bias power resulting in deeper inhibition.
  • Table 1 shows effect of treatment time. All inhibition treatments used exposure to a direct LFRF 2000 W N 2 H 2 plasma with a DC bias of 100 W on the substrate. Table 1 : Effect of treatment time on inhibition profile
  • the inhibition effect may be overcome by certain CVD conditions, including longer CVD time and/or higher temperatures, more aggressive chemistry, etc.
  • Table 2 below shows the effect of CVD time on selective deposition.
  • Any suitable chamber may be used to implement this novel method.
  • deposition apparatuses include various systems, e.g., ALTUS and ALTUS Max, available from Novellus Systems, Inc. of San Jose, California, or any of a variety of other commercially available processing systems.
  • Figure 8 illustrates a schematic representation of an apparatus 800 for processing a partially fabricated semiconductor substrate in accordance with certain embodiments.
  • the apparatus 800 includes a chamber 818 with a pedestal 820, a shower head 814, and an in-situ plasma generator 816.
  • the apparatus 800 also includes a system controller 822 to receive input and/or supply control signals to various devices.
  • a inhibition gas and, if present, inert gases can be supplied to the remote plasma generator 806 from a source 802, which may be a storage tank.
  • a source 802 which may be a storage tank.
  • Any suitable remote plasma generator may be used for activating the etchant before introducing it into the chamber 818.
  • a Remote Plasma Cleaning (RPC) units such as ASTRON® i Type AX7670, ASTRON® e Type AX7680, ASTRON® ex Type AX7685, ASTRON® hf- s Type AX7645, all available from MKS Instruments of Andover, Massachusetts, may be used.
  • An RPC unit is typically a self-contained device generating weakly ionized plasma using the supplied etchant. Imbedded into the RPC unit a high power RF generator provides energy to the electrons in the plasma. This energy is then transferred to the neutral inhibition gas molecules leading to temperature in the order of 2000K causing thermal dissociation of these molecules.
  • An RPC unit may dissociate more than 60% of incoming molecules because of its high RF energy and special channel geometry causing the gas to adsorb most of this energy.
  • an inhibition gas is flown from the remote plasma generator 806 through a connecting line 808 into the chamber 818, where the mixture is distributed through the shower head 814.
  • an inhibition gas is flown into the chamber 818 directly completely bypassing the remote plasma generator 806 (e.g., the system 800 does not include such generator).
  • the remote plasma generator 806 may be turned off while flowing the inhibition gas into the chamber 818, for example, because activation of the inhibition gas is not needed or will be supplied by an in situ plasma generator.
  • the shower head 814 or the pedestal 820 typically may have an internal plasma generator 816 attached to it.
  • the generator 816 is a High Frequency (HF) generator capable of providing between about 0 W and 10,000 W at frequencies between about 1 MHz and 100 MHz.
  • the generator 816 is a Low Frequency (LF) generator capable of providing between about 0 W and 10,000 W at frequencies as low as about 100 KHz.
  • a HF generator may deliver between about 0 W to 5,000 W at about 13.56 MHz.
  • the RF generator 816 may generate in-situ plasma to active inhibition species.
  • the RF generator 816 can be used with the remote plasma generator 806 or not used. In certain embodiments, no plasma generator is used during deposition.
  • the chamber 818 may include a sensor 824 for sensing various process parameters, such as degree of deposition, concentrations, pressure, temperature, and others.
  • the sensor 824 may provide information on chamber conditions during the process to the system controller 822. Examples of the sensor 824 include mass flow controllers, pressure sensors, thermocouples, and others.
  • the sensor 824 may also include an infra-red detector or optical detector to monitor presence of gases in the chamber and control measures.
  • Deposition and selective inhibition operations can generate various volatile species that are evacuated from the chamber 818. Moreover, processing is performed at certain predetermined pressure levels the chamber 818. Both of these functions are achieved using a vacuum outlet 826, which may be a vacuum pump.
  • a system controller 822 is employed to control process parameters.
  • the system controller 822 typically includes one or more memory devices and one or more processors.
  • the processor may include a CPU or computer, analog and/or digital input/output connections, stepper motor controller boards, etc.
  • a user interface associated with system controller 822.
  • the user interface may include a display screen, graphical software displays of the apparatus and/or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.
  • the system controller 822 controls the substrate temperature, inhibition gas flow rate, power output of the remote plasma generator 806 and/or in situ plasma generator 816, pressure inside the chamber 818 and other process parameters.
  • the system controller 822 executes system control software including sets of instructions for controlling the timing, mixture of gases, chamber pressure, chamber temperature, and other parameters of a particular process.
  • Other computer programs stored on memory devices associated with the controller may be employed in some embodiments.
  • the computer program code for controlling the processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program.
  • the system software may be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control operation of the chamber components necessary to carry out the described processes. Examples of programs or sections of programs for this purpose include process gas control code, pressure control code, and plasma control code.
  • the controller parameters relate to process conditions such as, for example, timing of each operation, pressure inside the chamber, substrate temperature, inhibition gas flow rates, etc. These parameters are provided to the user in the form of a recipe, and may be entered utilizing the user interface. Signals for monitoring the process may be provided by analog and/or digital input connections of the system controller 822. The signals for controlling the process are output on the analog and digital output connections of the apparatus 800.
  • FIG. 9A shows an example of a multi-station apparatus 900.
  • the apparatus 900 includes a process chamber 901 and one or more cassettes 903 (e.g., Front Opening Unified Pods) for holding substrates to be processed and substrates that have completed processing.
  • the chamber 901 may have a number of stations, for example, two stations, three stations, four stations, five stations, six stations, seven stations, eight stations, ten stations, or any other number of stations. The number of stations in usually determined by a complexity of the processing operations and a number of these operations that can be performed in a shared environment.
  • Figure 9A illustrates the process chamber 901 that includes six stations, labeled 911 through 916. All stations in the multi-station apparatus 900 with a single process chamber 903 are exposed to the same pressure environment. However, each station may have a designated reactant distribution system and local plasma and heating conditions achieved by a dedicated plasma generator and pedestal, such as the ones illustrated in Figure 8.
  • a substrate to be processed is loaded from one of the cassettes 903 through a load- lock 905 into the station 911.
  • An external robot 907 may be used to transfer the substrate from the cassette 903 and into the load-lock 905.
  • there are two separate load locks 905. These are typically equipped with substrate transferring devices to move substrates from the load-lock 905 (once the pressure is equilibrated to a level corresponding to the internal environment of the process chamber 903) into the station 911 and from the station 916 back into the load- lock 905 for removal from the processing chamber 903.
  • a mechanism 909 is used to transfer substrates among the processing stations 911-916 and support some of the substrates during the process as described below.
  • one or more stations may be reserved for heating the substrate.
  • Such stations may have a heating lamp (not shown) positioned above the substrate and/or a heating pedestal supporting the substrate similar to one illustrated in Figure 8.
  • a station 911 may receive a substrate from a load-lock and be used to pre-heat the substrate before being further processed.
  • Other stations may be used for filling high aspect ratio features including deposition and selective inhibition operations.
  • the substrate is moved successively to the processing stations 912, 913, 914, 915, and 916, which may or may not be arranged sequentially.
  • the multi-station apparatus 900 can be configured such that all stations are exposed to the same pressure environment. In so doing, the substrates are transferred from the station 911 to other stations in the chamber 901 without a need for transfer ports, such as load-locks.
  • one or more stations may be used to fill features with tungsten-containing materials.
  • stations 912 may be used for an initial deposition operation
  • station 913 may be used for a corresponding selective inhibition operation.
  • stations 914 may be used for another deposition operations and station 915 may be used for another inhibition operation.
  • Section 916 may be used for the final filling operation. It should be understood that any configurations of station designations to specific processes (heating, filling, and removal) may be used.
  • any of the stations can be dedicated to one or more of PNL (or ALD) deposition, selective inhibition, and CVD deposition.
  • the method may be implemented in a single substrate chamber or a multi-station chamber processing a substrate(s) in a single processing station in batch mode (i.e., nonsequential).
  • the substrate is loaded into the chamber and positioned on the pedestal of the single processing station (whether it is an apparatus having only one processing station or an apparatus having multi-stations running in batch mode).
  • the substrate may be then heated and the deposition operation may be conducted.
  • the process conditions in the chamber may be then adjusted and the selective inhibition of the deposited layer is then performed.
  • the process may continue with one or more deposition-inhibition cycles (if performed) and with the final filling operation all performed on the same station.
  • a single station apparatus may be first used to perform only one of the operation in the new method (e.g., depositing, selective inhibition, final filling) on multiple substrates after which the substrates may be returned back to the same station or moved to a different station (e.g., of a different apparatus) to perform one or more of the remaining operations.
  • the new method e.g., depositing, selective inhibition, final filling
  • a different station e.g., of a different apparatus
  • FIG. 9B is a schematic illustration of a multi-chamber apparatus 920 that may be used in accordance with certain embodiments.
  • the apparatus 920 has three separate chambers 921, 923, and 925. Each of these chambers is illustrated with two pedestals. It should be understood that an apparatus may have any number of chambers (e.g., one, two, three, four, five, six, etc.) and each chamber may have any number of chambers (e.g., one, two, three, four, five, six, etc.).
  • Each chamber 921-525 has its own pressure environment, which is not shared between chambers.
  • Each chamber may have one or more corresponding transfer ports (e.g., load-locks).
  • the apparatus may also have a shared substrate handling robot 927 for transferring substrates between the transfer ports one or more cassettes 929.
  • separate chambers may be used for depositing tungsten containing materials and selective inhibition of these deposited materials in later operations. Separating these two operations into different chambers can help to substantially improve processing speeds by maintaining the same environmental conditions in each chamber.
  • a chamber does not need to change its environment from conditions used for deposition to conditions used for selective inhibition and back, which may involve different chemistries, different temperatures, pressures, and other process parameters. In certain embodiments, it is faster to transfer partially manufactured semiconductor substrates between two or more different chambers than changing environmental conditions of these chambers.
  • the apparatus/process described hereinabove may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility.
  • Lithographic patterning of a film typically comprises some or all of the following steps, each step enabled with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.
  • a tool such as an RF or microwave plasma resist stripper.

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Abstract

La présente invention concerne des procédés de remplissage d'entités par du tungstène, ainsi que des systèmes et un appareillage associés, faisant intervenir une inhibition de la nucléation du tungstène. Dans certains modes de réalisation, les procédés font intervenir une inhibition sélective suivant un profil d'entité. Les procédés d'inhibition sélective de la nucléation du tungstène peuvent comprendre une étape consistant à exposer l'entité à un plasma direct ou distant. Dans certains modes de réalisation, le substrat peut être polarisé pendant l'inhibition sélective. Des paramètres de processus comprenant la puissance de polarisation, le temps d'exposition, la puissance du plasma, la pression du processus et la chimie du plasma peuvent être utilisés pour affiner le profil d'inhibition. Les procédés décrits ici peuvent être utilisés pour remplir des entités verticales, telles que des traversées dans le tungstène, et des entités horizontales, telles que des lignes de mots NAND verticales (VNAND). Les procédés peuvent être utilisés aussi bien pour un remplissage conforme que pour un remplissage de bas en haut / de l'intérieur vers l'extérieur. Comme exemples d'applications, on peut citer le remplissage de contacts logiques et de mémoire, le remplissage de lignes de mots DRAM noyées, le remplissage de grilles / de lignes de mots de mémoires verticalement intégrées et l'intégration 3D avec des traversées dans le silicium (TSV).
PCT/US2013/033174 2012-03-27 2013-03-20 Remplissage d'entités par du tungstène avec inhibition de la nucléation WO2013148444A1 (fr)

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KR1020147029798A KR102100520B1 (ko) 2012-03-27 2013-03-20 핵생성 억제를 사용하는 텅스텐 피처 충진
CN201380022648.2A CN104272440B (zh) 2012-03-27 2013-03-20 用核化抑制的钨特征填充
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US201261616377P 2012-03-27 2012-03-27
US61/616,377 2012-03-27
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Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8835317B2 (en) 2009-08-04 2014-09-16 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9034768B2 (en) 2010-07-09 2015-05-19 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US9082826B2 (en) 2013-05-24 2015-07-14 Lam Research Corporation Methods and apparatuses for void-free tungsten fill in three-dimensional semiconductor features
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US9236297B2 (en) 2009-04-16 2016-01-12 Novellus Systems, Inc. Low tempature tungsten film deposition for small critical dimension contacts and interconnects
US9240347B2 (en) 2012-03-27 2016-01-19 Novellus Systems, Inc. Tungsten feature fill
JP2016046532A (ja) * 2014-08-21 2016-04-04 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ コバルトの間隙をボイドなしで充填する方法及び装置
US9548228B2 (en) 2009-08-04 2017-01-17 Lam Research Corporation Void free tungsten fill in different sized features
US9589835B2 (en) 2008-12-10 2017-03-07 Novellus Systems, Inc. Method for forming tungsten film having low resistivity, low roughness and high reflectivity
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US9748137B2 (en) 2014-08-21 2017-08-29 Lam Research Corporation Method for void-free cobalt gap fill
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
US9978610B2 (en) 2015-08-21 2018-05-22 Lam Research Corporation Pulsing RF power in etch process to enhance tungsten gapfill performance
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US10170320B2 (en) 2015-05-18 2019-01-01 Lam Research Corporation Feature fill with multi-stage nucleation inhibition
US10211099B2 (en) 2016-12-19 2019-02-19 Lam Research Corporation Chamber conditioning for remote plasma process
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US10381266B2 (en) 2012-03-27 2019-08-13 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
CN110129764A (zh) * 2014-02-26 2019-08-16 朗姆研究公司 用于沉积膜的衬底处理系统
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
JP2020128594A (ja) * 2015-02-13 2020-08-27 インテグリス・インコーポレーテッド 基材物品および装置の特性および性能を増強するためのコーティング
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US11830728B2 (en) 2021-10-13 2023-11-28 Applied Materials, Inc. Methods for seamless gap filling of dielectric material
US11972952B2 (en) 2018-12-14 2024-04-30 Lam Research Corporation Atomic layer deposition on 3D NAND structures
US11978666B2 (en) 2018-12-05 2024-05-07 Lam Research Corporation Void free low stress fill
US12077858B2 (en) 2019-08-12 2024-09-03 Lam Research Corporation Tungsten deposition

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9595466B2 (en) * 2015-03-20 2017-03-14 Applied Materials, Inc. Methods for etching via atomic layer deposition (ALD) cycles
US9828672B2 (en) 2015-03-26 2017-11-28 Lam Research Corporation Minimizing radical recombination using ALD silicon oxide surface coating with intermittent restoration plasma
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
KR102447489B1 (ko) 2015-09-02 2022-09-27 삼성전자주식회사 반도체 메모리 소자
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JP7224335B2 (ja) 2017-04-10 2023-02-17 ラム リサーチ コーポレーション モリブデンを含有する低抵抗膜
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US10760158B2 (en) 2017-12-15 2020-09-01 Lam Research Corporation Ex situ coating of chamber components for semiconductor processing
US10843618B2 (en) * 2017-12-28 2020-11-24 Lam Research Corporation Conformality modulation of metal oxide films using chemical inhibition
JP7023150B2 (ja) 2018-03-26 2022-02-21 東京エレクトロン株式会社 タングステン膜の成膜方法及び制御装置
US10727046B2 (en) * 2018-07-06 2020-07-28 Lam Research Corporation Surface modified depth controlled deposition for plasma based deposition
WO2020159882A1 (fr) 2019-01-28 2020-08-06 Lam Research Corporation Dépôt de films métalliques
CN113316836B (zh) * 2019-03-20 2024-04-09 株式会社国际电气 半导体器件的制造方法、衬底处理方法、衬底处理装置及记录介质
US11749564B2 (en) 2020-09-22 2023-09-05 Applied Materials, Inc. Techniques for void-free material depositions

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020132472A1 (en) * 2001-03-14 2002-09-19 Jusung Engineering Co., Ltd. Method for forming metal plug
US20050179141A1 (en) * 2002-05-30 2005-08-18 Yun Ju-Young Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer
US20060075966A1 (en) * 2002-01-26 2006-04-13 Applied Materials, Inc. Apparatus and method for plasma assisted deposition
US20090053893A1 (en) * 2005-01-19 2009-02-26 Amit Khandelwal Atomic layer deposition of tungsten materials
US20110233778A1 (en) * 2010-03-24 2011-09-29 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2067565C (fr) * 1992-04-29 1999-02-16 Ismail T. Emesh Methode de depot du tungstene
JPH0922896A (ja) * 1995-07-07 1997-01-21 Toshiba Corp 金属膜の選択的形成方法
KR100338941B1 (ko) * 1999-11-26 2002-05-31 박종섭 반도체소자의 컨택 형성방법
KR100399417B1 (ko) * 2001-01-08 2003-09-26 삼성전자주식회사 반도체 집적 회로의 제조 방법
US6797620B2 (en) * 2002-04-16 2004-09-28 Applied Materials, Inc. Method and apparatus for improved electroplating fill of an aperture
JP4945937B2 (ja) * 2005-07-01 2012-06-06 東京エレクトロン株式会社 タングステン膜の形成方法、成膜装置及び記憶媒体
JP4967354B2 (ja) * 2006-01-31 2012-07-04 東京エレクトロン株式会社 シード膜の成膜方法、プラズマ成膜装置及び記憶媒体
KR100757418B1 (ko) 2006-09-05 2007-09-10 삼성전자주식회사 반도체 소자 및 그 형성 방법
US20080174021A1 (en) * 2007-01-18 2008-07-24 Samsung Electronics Co., Ltd. Semiconductor devices having metal interconnections, semiconductor cluster tools used in fabrication thereof and methods of fabricating the same
KR101564473B1 (ko) * 2007-11-21 2015-10-29 램 리써치 코포레이션 텅스턴 함유층에 대한 에칭 마이크로로딩을 제어하는 방법
US8053365B2 (en) * 2007-12-21 2011-11-08 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
US9034768B2 (en) * 2010-07-09 2015-05-19 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US8119527B1 (en) * 2009-08-04 2012-02-21 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020132472A1 (en) * 2001-03-14 2002-09-19 Jusung Engineering Co., Ltd. Method for forming metal plug
US20060075966A1 (en) * 2002-01-26 2006-04-13 Applied Materials, Inc. Apparatus and method for plasma assisted deposition
US20050179141A1 (en) * 2002-05-30 2005-08-18 Yun Ju-Young Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer
US20090053893A1 (en) * 2005-01-19 2009-02-26 Amit Khandelwal Atomic layer deposition of tungsten materials
US20110233778A1 (en) * 2010-03-24 2011-09-29 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance

Cited By (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US9583385B2 (en) 2001-05-22 2017-02-28 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US9589835B2 (en) 2008-12-10 2017-03-07 Novellus Systems, Inc. Method for forming tungsten film having low resistivity, low roughness and high reflectivity
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US9236297B2 (en) 2009-04-16 2016-01-12 Novellus Systems, Inc. Low tempature tungsten film deposition for small critical dimension contacts and interconnects
US9673146B2 (en) 2009-04-16 2017-06-06 Novellus Systems, Inc. Low temperature tungsten film deposition for small critical dimension contacts and interconnects
US9653353B2 (en) 2009-08-04 2017-05-16 Novellus Systems, Inc. Tungsten feature fill
US10103058B2 (en) 2009-08-04 2018-10-16 Novellus Systems, Inc. Tungsten feature fill
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8835317B2 (en) 2009-08-04 2014-09-16 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US11075115B2 (en) 2009-08-04 2021-07-27 Novellus Systems, Inc. Tungsten feature fill
US9548228B2 (en) 2009-08-04 2017-01-17 Lam Research Corporation Void free tungsten fill in different sized features
US11410883B2 (en) 2009-08-04 2022-08-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US9034768B2 (en) 2010-07-09 2015-05-19 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US10381266B2 (en) 2012-03-27 2019-08-13 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US9240347B2 (en) 2012-03-27 2016-01-19 Novellus Systems, Inc. Tungsten feature fill
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9082826B2 (en) 2013-05-24 2015-07-14 Lam Research Corporation Methods and apparatuses for void-free tungsten fill in three-dimensional semiconductor features
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
CN110129764A (zh) * 2014-02-26 2019-08-16 朗姆研究公司 用于沉积膜的衬底处理系统
US9748137B2 (en) 2014-08-21 2017-08-29 Lam Research Corporation Method for void-free cobalt gap fill
JP2016046532A (ja) * 2014-08-21 2016-04-04 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ コバルトの間隙をボイドなしで充填する方法及び装置
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
CN110459503A (zh) * 2014-09-30 2019-11-15 朗姆研究公司 用核化抑制的特征填充
CN110459503B (zh) * 2014-09-30 2024-04-16 朗姆研究公司 一种填充衬底中的特征的方法和装置
US11901227B2 (en) 2014-09-30 2024-02-13 Lam Research Corporation Feature fill with nucleation inhibition
US10580695B2 (en) 2014-09-30 2020-03-03 Lam Research Corporation Feature fill with nucleation inhibition
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US12084778B2 (en) 2015-02-13 2024-09-10 Entegris, Inc. Coatings for enhancement of properties and performance of substrate articles and apparatus
JP2020128594A (ja) * 2015-02-13 2020-08-27 インテグリス・インコーポレーテッド 基材物品および装置の特性および性能を増強するためのコーティング
US12018382B2 (en) 2015-02-13 2024-06-25 Entegris, Inc. Coatings for enhancement of properties and performance of substrate articles and apparatus
US10170320B2 (en) 2015-05-18 2019-01-01 Lam Research Corporation Feature fill with multi-stage nucleation inhibition
US10580654B2 (en) 2015-05-18 2020-03-03 Lam Research Corporation Feature fill with multi-stage nucleation inhibition
US10916434B2 (en) 2015-05-18 2021-02-09 Lam Research Corporation Feature fill with multi-stage nucleation inhibition
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
US9978610B2 (en) 2015-08-21 2018-05-22 Lam Research Corporation Pulsing RF power in etch process to enhance tungsten gapfill performance
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
US11355345B2 (en) 2016-08-16 2022-06-07 Lam Research Corporation Method for preventing line bending during metal fill process
US10211099B2 (en) 2016-12-19 2019-02-19 Lam Research Corporation Chamber conditioning for remote plasma process
US11978666B2 (en) 2018-12-05 2024-05-07 Lam Research Corporation Void free low stress fill
US11972952B2 (en) 2018-12-14 2024-04-30 Lam Research Corporation Atomic layer deposition on 3D NAND structures
US12077858B2 (en) 2019-08-12 2024-09-03 Lam Research Corporation Tungsten deposition
US11830728B2 (en) 2021-10-13 2023-11-28 Applied Materials, Inc. Methods for seamless gap filling of dielectric material

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