WO2013108873A1 - Processeur d'image pour un endoscope - Google Patents

Processeur d'image pour un endoscope Download PDF

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Publication number
WO2013108873A1
WO2013108873A1 PCT/JP2013/050928 JP2013050928W WO2013108873A1 WO 2013108873 A1 WO2013108873 A1 WO 2013108873A1 JP 2013050928 W JP2013050928 W JP 2013050928W WO 2013108873 A1 WO2013108873 A1 WO 2013108873A1
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Prior art keywords
image processing
packet
processing unit
image
data
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PCT/JP2013/050928
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English (en)
Japanese (ja)
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滝沢　一博
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オリンパス株式会社
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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/00002—Operational features of endoscopes
    • A61B1/00004—Operational features of endoscopes characterised by electronic signal processing
    • A61B1/00009—Operational features of endoscopes characterised by electronic signal processing of image signals during a use of endoscope
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/00002—Operational features of endoscopes
    • A61B1/00011—Operational features of endoscopes characterised by signal transmission
    • A61B1/00013—Operational features of endoscopes characterised by signal transmission using optical means
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B23/00—Telescopes, e.g. binoculars; Periscopes; Instruments for viewing the inside of hollow bodies; Viewfinders; Optical aiming or sighting devices
    • G02B23/24—Instruments or systems for viewing the inside of hollow bodies, e.g. fibrescopes

Definitions

  • the present invention relates to an endoscope image processor that performs image processing on an image signal output from a solid-state imaging device.
  • the electronic endoscope performs image processing on an image signal output from the solid-state imaging device by an endoscope image processor and displays an image on a monitor.
  • functions installed in electronic devices are diversified year by year, and this tendency is the same also in an endoscope image processor.
  • this tendency is the same also in an endoscope image processor.
  • the cost of the entire apparatus will increase.
  • Patent Document 1 A method for realizing such an apparatus is described in Patent Document 1.
  • the image processing function is expanded by connecting the function expansion I / F 61 to the standard image processing unit 60 and connecting the additional image processing unit 62 to the function expansion I / F 61.
  • Image processing performed by the endoscope image processor includes various image processing such as noise reduction, color correction, color enhancement, and contour enhancement. These image processes are performed in a predetermined order, but various processing functions may be added. In order to realize more flexible expandability, it is desirable that a processing function can be added to any image processing among a plurality of image processing performed in a predetermined order. However, in Patent Document 1, only the additional image processing unit 62 can be added to the standard image processing unit 60, and the flexible extensibility as described above is not realized.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide an endoscope image processor capable of enhancing expandability related to addition of an image processing function.
  • an endoscope image processor that performs image processing on an image signal output from a solid-state imaging device of an endoscope, wherein the image processing is performed on the image signal. If the image processing unit has a second image processing unit that performs image processing on the image signal, the first image processing unit receives a packet including data of the image signal, A packet analysis unit that analyzes the packet to determine whether the destination of the packet is the first image processing unit, and the destination of the packet is determined to be the first image processing unit A data processing unit that processes data included in the packet, and a packet generation unit that includes the data processed by the data processing unit and generates a packet that designates the second image processing unit as a destination; , The packet A packet selection unit that selects and outputs one of the packets generated by the packet generation unit, the packet determined that the destination is not the first image processing unit, The second image processing unit receives a packet including data of the image signal, analyzes the packet, and determines whether the destination of the packet is the second image
  • transmission of the packet between the first image processing unit and the second image processing unit is performed by serial communication. It may be done.
  • the packet transmission between the first image processing unit and the second image processing unit is an optical transmission. May be performed.
  • the endoscope image processor according to the first aspect further includes a plurality of substrates, wherein each of the first image processing unit and the second image processing unit is the Transmission of the packet between the substrate on which the first image processing unit is disposed and the substrate on which the second image processing unit is disposed is performed by optical transmission. May be.
  • the data constituting the packet may include image data or setting parameters for image processing.
  • the packet analysis unit analyzes the input packet and determines that the destination of the packet does not exist, The inputted packet may be deleted.
  • the first image processing unit and the second image processing unit are connected in a ring shape. Even when is added, the image signal data processed by any of the image processing units can be transferred to an arbitrary image processing unit. Therefore, it is possible to improve the expandability related to the addition of the image processing function.
  • FIG. 1 is a block diagram showing a configuration of an endoscope system according to a first embodiment of the present invention.
  • FIG. 5 is a reference diagram showing a packet configuration in the first exemplary embodiment of the present invention.
  • 1 is a block diagram showing a configuration of an image processing LSI included in an endoscope system according to a first embodiment of the present invention.
  • FIG. 6 is a reference diagram illustrating another configuration of a packet according to the first embodiment of the present invention.
  • FIG. 6 is a reference diagram illustrating another configuration of a packet according to the first embodiment of the present invention.
  • FIG. 6 is a reference diagram illustrating an example of an operation using a packet in the first embodiment of the present invention.
  • FIG. 3 is a block diagram showing a configuration for explaining an operation using a packet in the first embodiment of the present invention.
  • FIG. 2 is a configuration diagram for explaining a connector mounting form included in the endoscope system according to the first embodiment of the present invention.
  • FIG. 6 is a block diagram for explaining another extension example of the image processing function in the first embodiment of the present invention.
  • FIG. 6 is a block diagram for explaining another extension example of the image processing function in the first embodiment of the present invention.
  • FIG. 6 is a block diagram illustrating a configuration of an image processor included in an endoscope system according to a second embodiment of the present invention.
  • FIG. 10 is a block diagram showing connection of an image processing LSI in a third embodiment of the present invention.
  • FIG. 10 is a block diagram showing a configuration of an image processing LSI in a third embodiment of the present invention.
  • FIG. 10 is a block diagram showing a configuration of an endoscope system according to a fourth embodiment of the present invention.
  • FIG. 10 is a block diagram showing a configuration of an endoscope system according to a fifth embodiment of the present invention.
  • FIG. 10 is a block diagram showing a configuration of an endoscope system according to a sixth embodiment of the present invention. It is a figure which shows the example of the memory space in the 1st Embodiment of this invention. It is a timing chart which shows the example of data transmission in the 1st Embodiment of this invention.
  • FIG. 1 shows a configuration of an endoscope system according to the present embodiment.
  • the endoscope system according to the present embodiment includes an endoscope scope 100 that converts optical information into a digital image signal 101, an image processor 102 that performs predetermined image processing on the digital image signal 101, and a monitor 115 that displays an image. It consists of
  • the endoscope scope 100 has a solid-state image sensor and outputs a digital image signal 101.
  • the image processor 102 includes a main substrate 103 having image processing LSIs 107 and 108 (first image processing units) that perform basic image processing, and an image processing LSI 114 (second image processing unit) that performs additional image processing.
  • an expansion board 104 having The main board 103 is provided with a connector 105, the extension board 104 is provided with a connector 106, and the main board 103 and the extension board 104 are connected via these connectors.
  • Image processing LSIs 107, 108, and 114 perform various image processing on the input digital image signal.
  • the output of the image processing LSI 107 is connected to the input of the image processing LSI 108 via the transmission path 109.
  • the output of the image processing LSI 108 is connected to the first terminal of the connector 105 via the transmission path 110.
  • the first terminal of the connector 105 is connected to the first terminal of the connector 106.
  • the first terminal of the connector 106 is connected to the input of the image processing LSI 114 via the transmission path 111.
  • the output of the image processing LSI 114 is connected to the second terminal of the connector 106 via the transmission path 112.
  • the second terminal of the connector 106 is connected to the second terminal of the connector 105 of the main board 103, and the second terminal of the connector 105 is connected to the input of the image processing LSI 107 via the transmission path 113. .
  • a monitor 115 is connected to the image processing LSI 108.
  • the monitor 115 displays an image based on the image signal 120 output from the image processing LSI 108.
  • the monitor 115 is connected to the image processing LSI 108, but the monitor 115 may be connected to the image processing LSI 107.
  • a high-speed serial communication system using, for example, LVDS (Low Voltage Differential Signaling) is applied.
  • LVDS Low Voltage Differential Signaling
  • FIG. 2 shows an example of the packet configuration.
  • an ID, an address, and data are included in a packet.
  • the ID is an identifier unique to each image processing on the endoscope system, and a unique identifier is assigned to each of the image processing modules constituting the image processing system.
  • a large functional classification is defined for each chip, and when it is not necessary to subdivide the functions in the chip, the identification target by ID is not the image processing module unit but the chip unit. It may be.
  • the address is an address of a register in the image processing LSI or an address of a memory connected to the image processing LSI.
  • the data is data such as image data constituting a digital image signal and parameters necessary for image processing.
  • the transmission path is simply a signal line, and any data can be transmitted as long as the data handling method is determined between the transmission side and the reception side.
  • address information and data information may be mixed in a predetermined bit width, or address information and data information may be sent in a time division manner. That is, since it is only necessary to determine how many bit signal lines are prepared for data transmission in the entire system, the apparatus design work becomes very simple.
  • Transmission paths 109, 110, 111, 112, 113 and connectors 105, 106 form a ring-shaped transfer path.
  • Each image processing LSI is connected in a ring shape via this transfer path, and data is transmitted from one image processing LSI to the image processing LSI adjacent to the image processing LSI in an operation like a shift register. Is done. Since data is transmitted by a transmission method such as a so-called bucket relay, data transmission between distant image processing LSIs requires some time, but data transmission in any combination can be performed without any problem.
  • the digital image signal output from the image processing LSI 107 is transmitted to the transmission path 109, the image processing The data is transferred to the image processing LSI 114 via the LSI 108, the transmission path 110, the connectors 105 and 106, and the transmission path 111, and processed by the image processing LSI 114.
  • One point on the ring-shaped transfer path can be opened and closed, and an image processing LSI with a function to be expanded later can be inserted there.
  • the image processing LSI 114 having a function to be expanded can be inserted.
  • the connector 106 is not connected, the connector 105 is short-circuited, and a ring-shaped transfer path is formed only by the configuration on the main board 103.
  • a predetermined address space must be shared by all elements connected to the bus, so that the number of addresses that can be used by each element decreases as the number of connected elements increases. This means that the possibility of function expansion is limited in the bus system, and it is further influenced by other factors. For this reason, it is not always best to apply the bus system to a device whose maximum purpose is function expansion.
  • an ID and an address are included in the packet, and the data storage location is identified by the combination of the ID and the address. Therefore, it is possible to use the same address between different IDs. For this reason, the entire predetermined address space can be used for each ID, and the selection range of addresses that can be used by each element is widened.
  • Fig. 3 shows the configuration of each image processing LSI.
  • the image processing LSI includes a packet analysis unit 200, a data processing unit 201, a packet generation unit 202, and a packet selection unit 203.
  • the packet analysis unit 200 analyzes the input signal 204 and determines whether or not the input signal 204 is a signal addressed to its own chip.
  • the ID in the packet is referred to, and this determination is performed based on the ID.
  • the packet analysis unit 200 outputs the input signal 204 as it is to the packet selection unit 203 as the packet signal 205.
  • the data included in the input signal 204 is output to the data processing unit 201, but the packet signal is not output to the packet selection unit 203.
  • the packet analysis unit 200 also has a function to check all input IDs on the system registered in advance and delete the packet (do not output it to the subsequent stage) when a packet with a nonexistent ID is detected. is doing. The function for erasing unnecessary packets is sufficient if there is only one location on the transfer path, and it is not necessary to mount it on all chips.
  • the data processing unit 201 performs predetermined image processing on the input data and outputs processing result data to the packet generation unit 202.
  • the data processing unit 201 is connected to the monitor 115, and the data processing unit 201 generates an image signal 120 from the processing result data and outputs the image signal 120 to the monitor 115.
  • the packet generation unit 202 generates a packet including the input data and molded into a predetermined packet format, and outputs the packet as a packet signal 206 to the packet selection unit 203.
  • the packet signal 206 includes an ID
  • the packet generation unit 202 determines which image processing module performs the next image processing in accordance with a predetermined image processing order, and determines the image processing module.
  • a packet signal 206 including the ID is output.
  • the packet selection unit 203 selects one of the packet signal 205 from the packet analysis unit 200 and the packet signal 206 from the packet generation unit 202, and outputs the selected signal to the next-stage image processing LSI. Basically, when the input signal 204 is a signal addressed to another chip, the packet signal 205 is selected.
  • the packet analysis unit 200 receives a signal indicating a determination result as to whether or not the input signal 204 is a signal addressed to another chip, and is input to the packet selection unit 203 together with the packet signal 205. Selects one of the packet signal 205 and the packet signal 206 based on the signal.
  • each image processing LSI is connected in a ring shape.
  • the packet is transferred to the other image processing LSI and addressed to its own chip.
  • data processing is performed, and the packet including the processed data is transferred to another image processing LSI.
  • data can be transferred from a certain image processing LSI to an arbitrary image processing LSI. Therefore, by adding the image processing LSI 114, image processing LSI 107, image processing LSI 114, and image processing LSI 108 are processed in the order, or image processing LSI 114, image processing LSI 107, and image processing LSI 108 are processed in order. In any case, desired image processing can be realized.
  • FIG. 4A and 4B show examples of other packet configurations different from the packet configuration shown in FIG.
  • FIG. 4A shows an example of a packet configuration dedicated to image data
  • FIG. 4B shows an example of a packet configuration for data transfer with an address.
  • [ID] field stores the ID.
  • the [command] field indicates the type of packet. For example, information such as “image data transfer mode” and “data transfer mode with address” is stored in the [command] field.
  • the [type] field has a role of supplementing the operation of the command.
  • Image processing in an endoscope apparatus often has a so-called pipeline operation, and input data is often processed sequentially.
  • a process for temporarily storing data in the storage means is unnecessary, and therefore there is no [address] field in the format (FIG. 4A) for transferring image data that can be processed by the pipeline operation.
  • the data transfer destination is also uniquely determined. In this case, the “ID” field may be omitted.
  • FIG. 5 shows an example of an operation using a packet in which “Write” is stored in the [Type] field.
  • FIG. 5 shows an example in which packets 220, 221 and 222 are sequentially transmitted from the image processing LSI on the transmission side to the image processing LSI on the reception side. No data is stored in the packet 220, an arbitrary ID is stored in the [ID] field, “data transfer mode with address” is stored in the [Command] field, and “Write” is stored in the [Type] field. ",” 2 "is stored in the [burst] field, and an arbitrary address is stored in the [address] field. Packets 221 and 222 are packets in which only data is stored.
  • the data processing unit 201 determines from the [command] field of the packet 220 that it is “data transfer with address”, and then determines that the operation is “Write” from the [type] field. know. Further, the data processing unit 201 knows that the data for writing is transmitted over the subsequent two cycles from the [burst] field. When the packets 221 and 222 are received, the data processing unit 201 writes the data stored in these packets in the position indicated by the address stored in the [address] field of the packet 220.
  • a memory 212 is connected to the image processing LSI 211.
  • the image processing LSI 210 can access the memory 212 connected to the image processing LSI 211 using the packet in FIG. 4B.
  • the ID of the memory 212 is stored in the [ID] field of the packet 220, and the address of the memory 212 is stored in the [address] field of the packet 220.
  • This ID is actually the ID of the “port” of the memory controller that controls the memory.
  • FIG. 16 shows an example of a memory map of the memory 212. In FIG. 16, the memory space is divided into three spaces of ports A, B, and C, and data stored in these ports is determined. When accessing the memory, ID numbers corresponding to these ports are designated.
  • FIG. 17 shows the transfer timing of image data and image processing parameters in the present embodiment.
  • the data is transferred by the same transfer path (transmission paths 109, 110, 111, 112, 113 in FIG. 1) regardless of the type of data. Transmission is realized. Therefore, in order to increase the data transmission efficiency, it is necessary to reduce transfer timing contention.
  • control is performed so that image processing parameters are transferred during an invalid period (blanking period) of image data. By controlling in this way, arbitration of data output to the transfer path is simplified.
  • the vertical synchronization signal is drawn independently, but in actuality, the synchronization signal is embedded in the packet and transferred.
  • the mounting form of the connectors 105 and 106 will be described.
  • the extension board 104 may be unnecessary.
  • a ring-shaped transfer path needs to be formed. Therefore, when the extension board 104 is not connected, it is necessary to short-circuit the first terminal and the second terminal of the connector 105 by some means.
  • FIG. 7 shows an example of a configuration in which the first terminal and the second terminal of the connector 105 are short-circuited.
  • FIG. 7 shows the main board 103 as viewed from the side.
  • a short circuit 300 is fitted to the connector 105.
  • the first terminal of the connector 105 connected to the transmission path 110 is connected to the terminal 301 of the short circuit 300
  • the second terminal of the connector 105 connected to the transmission path 113 is connected to the terminal 302 of the short circuit 300.
  • the terminal 301 and the terminal 302 that need to be short-circuited are short-circuited inside the short-circuit device 300.
  • a ring-shaped transfer path can be formed only by the main substrate 103.
  • FIG. 8 shows an example in which connectors 400 and 401 with switches are mounted on the main board 103.
  • the connectors with switches 400 and 401 are normally closed by a spring-like mechanism, but when an external contact is connected, the spring is pushed down and the connection is switched to the external contact side.
  • a ring-shaped transfer path is formed in the main board 103 when the extension board 104 is not connected, but a ring-shaped transfer path including the extension board 104 is formed when the extension board 104 is connected.
  • FIG. 9 shows an example in which the extension function is directly mounted on the main board 103 without connecting the extension board 104.
  • a ring-shaped transmission line is normally formed by the resistor 500 (resistance value is 0 ⁇ ).
  • resistor 500 resistance value is 0 ⁇ .
  • the image processing LSIs are connected in a ring shape, and the image processing LSI can be added to at least one point of the ring-shaped transfer path.
  • each image processing LSI can perform image processing in an arbitrary order. For this reason, the addition of a desired image processing function can be realized, and the expandability related to the addition of the image processing function can be improved.
  • serial transmission for data transmission between image processing LSIs
  • the number of physical signals can be reduced compared to parallel transmission.
  • transmitting data as a low-voltage differential signal such as LVDS (Low Voltage Differential Differential), it is possible to increase the signal transmission speed.
  • LVDS Low Voltage Differential Differential
  • FIG. 10 shows the configuration of the image processor according to the present embodiment.
  • the image processor according to the present embodiment includes a main board 103 and expansion boards 600 and 601.
  • the main substrate 103 includes image processing LSIs 107 and 108
  • the expansion substrate 600 includes an image processing LSI 116
  • the expansion substrate 601 includes an image processing LSI 117.
  • the extension boards 600 and 601 are created based on the same standard.
  • the main board 103 and the extension boards 600 and 601 are connected by optical transmission cables 602, 603, and 604, not by connectors.
  • data transmission using the transmission path 605 on the main board 103 may be optical transmission.
  • Optical transmission has higher transmission capability than electric signal transmission, and more data can be transmitted.
  • the expansion boards 600 and 601 are created based on the same standard, but the functions of the image processing LSI mounted on them are naturally different. However, if a device such as an FPGA (Field Programmable Gate Array) that can change the internal logic is used for the image processing LSI, only one type of substrate may be created.
  • FPGA Field Programmable Gate Array
  • optical transmission has higher transfer capability than electrical signal transmission, in addition to data transmission between boards, data transmission between image processing LSIs on the same board is made optical transmission, which further reduces the number of signals. The transfer capability can be improved.
  • FIG. 11 shows the connection of the image processing LSI in this embodiment.
  • Transmission lines 705, 706, and 707 are added in addition to the transmission lines that connect two adjacent image processing LSIs among the five image processing LSIs 700, 701, 702, 703, and 704.
  • the transmission path 705 connects the image processing LSIs 703 and 700
  • the transmission path 706 connects the image processing LSIs 704 and 701
  • the transmission path 707 connects the image processing LSIs 702 and 704.
  • FIG. 12 shows the configuration of each image processing LSI.
  • the image processing LSI includes a packet analysis unit 230, a data processing unit 232, packet generation units 233 and 234, and packet selection units 235 and 236.
  • the image processing LSI of this embodiment supports input and output of two systems of digital image signals.
  • One of the two systems of digital image signals is input to the packet analysis unit 230 as an input signal 237 from one transmission path on the input side, and the other of the two systems of digital image signals is input signal 238 from the other transmission path on the input side. Is input to the packet analysis unit 230.
  • one of the two digital image signals is output from the packet selection unit 235 to one transmission line on the output side, and the other of the two digital image signals is output from the packet selection unit 236 to the other transmission line on the output side. Is done.
  • the packet analysis unit 230 analyzes the input signals 237 and 238 and determines whether or not the input signals 237 and 238 are signals addressed to the own chip.
  • the packet analysis unit 230 outputs the input signals 237 and 238 as they are to the packet selection unit 235 as the packet signal 239 or outputs them to the packet selection unit 236 as the packet signal 240. Further, when the input signals 237 and 238 are signals addressed to the own chip, the packet analysis unit 230 outputs the data included in the input signals 237 and 238 to the data processing unit 232.
  • the packet analysis units 230 and 231 detect this information from the packets of the input signals 237 and 238, notify the data processing unit 232, and based on this information, send packets to one of the packet selection unit 235 and the packet selection unit 236. Output a signal.
  • the data processing unit 232 performs predetermined image processing on the input data, and outputs the processing result data to the packet generation unit 233 or the packet generation unit 234.
  • the packet generation units 233 and 234 serving as data output destinations are determined based on the information related to the transfer path notified from the packet analysis unit 230.
  • the packet generation unit 233 generates a packet including the input data and molded into a predetermined packet format, and outputs the packet as a packet signal 241 to the packet selection unit 235.
  • the packet selection unit 235 selects one of the packet signal 239 from the packet analysis unit 230 and the packet signal 241 from the packet generation unit 233, and is connected to the one transmission line on the output side. Output to a multistage image processing LSI.
  • the packet generation unit 234 generates a packet including the input data and molded into a predetermined packet format, and outputs the packet as a packet signal 242 to the packet selection unit 236.
  • the packet selection unit 236 selects one of the packet signal 240 from the packet analysis unit 230 and the packet signal 242 from the packet generation unit 234, and is connected to the other transmission path on the output side. Output to a multistage image processing LSI.
  • each image processing LSI is connected by a ring-shaped transfer path, but this transfer path does not have to be one system. It is also possible to provide a plurality of transfer paths as in this embodiment.
  • the image processing LSI When the image processing LSI is implemented with a logic device such as an FPGA whose internal structure can be changed, the logic device does not include any data transfer during the process of changing the circuit configuration of these logic devices. It cannot be processed.
  • a logic device such as an FPGA whose internal structure can be changed
  • the logic device does not include any data transfer during the process of changing the circuit configuration of these logic devices. It cannot be processed.
  • FIG. 13 shows the configuration of the endoscope system according to the present embodiment.
  • the endoscope system according to the present embodiment includes an endoscope scope 800 that converts optical information into a digital image signal, an image processor 801 that performs predetermined image processing on the digital image signal, and a monitor 806 that displays a 3D image. It is configured.
  • the endoscope scope 800 includes two imaging elements 802 and 803 inside, and a stereoscopic image can be configured in combination with the subsequent 3D processing.
  • the image sensor 802 generates an image signal for the left eye image
  • the image sensor 803 generates an image signal for the right eye image.
  • the image processor 801 includes a substrate 809 having an image processing LSI 804 and a connector 807, and a substrate 810 having an image processing LSI 805 and a connector 808.
  • the substrate 809 corresponds to the main substrate 103 of the first embodiment
  • the substrate 810 corresponds to the expansion substrate 104 of the first embodiment.
  • High-accuracy assembly technology is required to acquire 3D images, but it is very difficult to perform high-accuracy processing with equipment that requires space saving, such as an endoscope scope. Therefore, it is considered that it is necessary to correct variations in processing accuracy by subsequent signal processing. To that end, it is necessary to significantly improve the performance of the image processing circuit.
  • the image processing LSI 804 is in charge of signal processing for the left eye image and the image processing LSI 805 is in charge of signal processing for the right eye image, even if the performance of the image processing LSI is close to the limit, 3D Image processing corresponding to the image becomes possible.
  • a dedicated monitor compatible with 3D is required to display a 3D image, but the image processing LSI 805 may perform processing for inputting an appropriate image signal to the dedicated monitor.
  • Distribution of the left and right image signals from the endoscope scope 800 may be performed by the endoscope scope 800, or an IF conversion FPGA is provided between the endoscope scope 800 and the image processing LSI 804. You may make it perform. If the image processing LSI 804 itself is realized by an FPGA, the image processing LSI 804 may distribute the left and right image signals.
  • FIG. 14 shows the configuration of the endoscope system according to the present embodiment.
  • the endoscope system according to the present embodiment includes an endoscope scope 811 that converts optical information into a digital image signal, an image processor 812 that performs predetermined image processing on the digital image signal, and monitors 813 and 814 that display images. It consists of
  • the image processor 812 includes a substrate 819 having an image processing LSI 815 and a connector 817, and a substrate 820 having an image processing LSI 816 and a connector 818.
  • the substrate 819 corresponds to the main substrate 103 of the first embodiment
  • the substrate 820 corresponds to the expansion substrate 104 of the first embodiment.
  • the image processing LSI 815 basically displays an image by outputting an image signal to the monitor 813.
  • the image processing LSI 815 has a larger number of pixels than the number of pixels of the monitor 813.
  • a system for outputting an image to the monitor 814 can be added.
  • the image processing LSI 816 enlarges the image size of the image signal to a size corresponding to the screen of the monitor 814, and outputs the image signal to the monitor 814. Therefore, even if the multi-pixel monitor becomes mainstream, the image display can be maintained.
  • the display means has been described with respect to the increase in the number of pixels.
  • the processing capability of the image processing LSI 815 may be insufficient due to the increase in the number of pixels. In this case, the shortage of processing capability can be resolved by using the image processing LSI 816 together.
  • FIG. 15 shows the configuration of the endoscope system according to the present embodiment.
  • the endoscope system according to the present embodiment includes an endoscope scope 821 that converts optical information into a digital image signal, an image processor 822 that performs predetermined image processing on the digital image signal, and recording devices 823 and 824 that record images. It consists of and.
  • the image processor 822 includes a substrate 829 having an image processing LSI 825 and a connector 827, and a substrate 830 having an image processing LSI 826 and a connector 828.
  • the substrate 829 corresponds to the main substrate 103 of the first embodiment
  • the substrate 830 corresponds to the expansion substrate 104 of the first embodiment.
  • the image processing LSI 825 outputs an image signal to the recording device 823 to record an image, but apart from this system, the recording device 824 corresponding to a standard different from the recording device 823.
  • a system for outputting an image signal can be added to.
  • the image processing LSI 826 converts the format of the image signal into a recording format corresponding to the recording device 824, and outputs the converted image signal.
  • Image data recording has been switched from analog to digital, but there are various standards for digital systems, and it is thought that new standards will be established in the future. This embodiment makes it possible to flexibly cope with new standards.
  • the second image processing unit when the second image processing unit is added, since the first image processing unit and the second image processing unit are connected in a ring shape, the second image processing unit is located at which position. Even when added, the image signal data processed by any of the image processing units can be transferred to an arbitrary image processing unit. Therefore, it is possible to improve the expandability related to the addition of the image processing function.
  • Memory 300 ... Short circuit 301, 302 ... Terminal 400, 401 ... Connector with switch 500 ... Resistor 602, 603, 604 ... Optical transmission cable 802, 803 ..Image sensors 809, 810, 819, 820, 829, 830 ... Substrate 823, 824 ... Recording device

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Abstract

Selon l'invention, chaque LSI de traitement d'image est connecté de façon annulaire. Dans des cas où un paquet adressé à une autre puce est entré, le paquet est transféré à une autre LSI de traitement d'image. Dans des cas où un paquet adressé à la puce elle-même est entré, les données sont traitées et le paquet comprenant les données traitées est transféré à une autre LSI de traitement d'image. Par la connexion d'un autre connecteur à un connecteur, des LSI de traitement d'image présentant une fonction d'extension souhaitée peuvent être introduits.
PCT/JP2013/050928 2012-01-18 2013-01-18 Processeur d'image pour un endoscope WO2013108873A1 (fr)

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WO2016174902A1 (fr) * 2015-04-30 2016-11-03 ソニー・オリンパスメディカルソリューションズ株式会社 Dispositif de relais et dispositif médical
JP2020145578A (ja) * 2019-03-06 2020-09-10 キヤノン株式会社 信号処理回路、画像読み取り装置、画像形成装置及び信号処理方法

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