WO2013108873A1 - Image processor for endoscope - Google Patents

Image processor for endoscope Download PDF

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Publication number
WO2013108873A1
WO2013108873A1 PCT/JP2013/050928 JP2013050928W WO2013108873A1 WO 2013108873 A1 WO2013108873 A1 WO 2013108873A1 JP 2013050928 W JP2013050928 W JP 2013050928W WO 2013108873 A1 WO2013108873 A1 WO 2013108873A1
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Prior art keywords
image processing
packet
processing unit
image
data
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PCT/JP2013/050928
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French (fr)
Japanese (ja)
Inventor
滝沢　一博
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オリンパス株式会社
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Publication of WO2013108873A1 publication Critical patent/WO2013108873A1/en

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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/00002—Operational features of endoscopes
    • A61B1/00004—Operational features of endoscopes characterised by electronic signal processing
    • A61B1/00009—Operational features of endoscopes characterised by electronic signal processing of image signals during a use of endoscope
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B1/00—Instruments for performing medical examinations of the interior of cavities or tubes of the body by visual or photographical inspection, e.g. endoscopes; Illuminating arrangements therefor
    • A61B1/00002—Operational features of endoscopes
    • A61B1/00011—Operational features of endoscopes characterised by signal transmission
    • A61B1/00013—Operational features of endoscopes characterised by signal transmission using optical means
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B23/00—Telescopes, e.g. binoculars; Periscopes; Instruments for viewing the inside of hollow bodies; Viewfinders; Optical aiming or sighting devices
    • G02B23/24—Instruments or systems for viewing the inside of hollow bodies, e.g. fibrescopes

Definitions

  • the present invention relates to an endoscope image processor that performs image processing on an image signal output from a solid-state imaging device.
  • the electronic endoscope performs image processing on an image signal output from the solid-state imaging device by an endoscope image processor and displays an image on a monitor.
  • functions installed in electronic devices are diversified year by year, and this tendency is the same also in an endoscope image processor.
  • this tendency is the same also in an endoscope image processor.
  • the cost of the entire apparatus will increase.
  • Patent Document 1 A method for realizing such an apparatus is described in Patent Document 1.
  • the image processing function is expanded by connecting the function expansion I / F 61 to the standard image processing unit 60 and connecting the additional image processing unit 62 to the function expansion I / F 61.
  • Image processing performed by the endoscope image processor includes various image processing such as noise reduction, color correction, color enhancement, and contour enhancement. These image processes are performed in a predetermined order, but various processing functions may be added. In order to realize more flexible expandability, it is desirable that a processing function can be added to any image processing among a plurality of image processing performed in a predetermined order. However, in Patent Document 1, only the additional image processing unit 62 can be added to the standard image processing unit 60, and the flexible extensibility as described above is not realized.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide an endoscope image processor capable of enhancing expandability related to addition of an image processing function.
  • an endoscope image processor that performs image processing on an image signal output from a solid-state imaging device of an endoscope, wherein the image processing is performed on the image signal. If the image processing unit has a second image processing unit that performs image processing on the image signal, the first image processing unit receives a packet including data of the image signal, A packet analysis unit that analyzes the packet to determine whether the destination of the packet is the first image processing unit, and the destination of the packet is determined to be the first image processing unit A data processing unit that processes data included in the packet, and a packet generation unit that includes the data processed by the data processing unit and generates a packet that designates the second image processing unit as a destination; , The packet A packet selection unit that selects and outputs one of the packets generated by the packet generation unit, the packet determined that the destination is not the first image processing unit, The second image processing unit receives a packet including data of the image signal, analyzes the packet, and determines whether the destination of the packet is the second image
  • transmission of the packet between the first image processing unit and the second image processing unit is performed by serial communication. It may be done.
  • the packet transmission between the first image processing unit and the second image processing unit is an optical transmission. May be performed.
  • the endoscope image processor according to the first aspect further includes a plurality of substrates, wherein each of the first image processing unit and the second image processing unit is the Transmission of the packet between the substrate on which the first image processing unit is disposed and the substrate on which the second image processing unit is disposed is performed by optical transmission. May be.
  • the data constituting the packet may include image data or setting parameters for image processing.
  • the packet analysis unit analyzes the input packet and determines that the destination of the packet does not exist, The inputted packet may be deleted.
  • the first image processing unit and the second image processing unit are connected in a ring shape. Even when is added, the image signal data processed by any of the image processing units can be transferred to an arbitrary image processing unit. Therefore, it is possible to improve the expandability related to the addition of the image processing function.
  • FIG. 1 is a block diagram showing a configuration of an endoscope system according to a first embodiment of the present invention.
  • FIG. 5 is a reference diagram showing a packet configuration in the first exemplary embodiment of the present invention.
  • 1 is a block diagram showing a configuration of an image processing LSI included in an endoscope system according to a first embodiment of the present invention.
  • FIG. 6 is a reference diagram illustrating another configuration of a packet according to the first embodiment of the present invention.
  • FIG. 6 is a reference diagram illustrating another configuration of a packet according to the first embodiment of the present invention.
  • FIG. 6 is a reference diagram illustrating an example of an operation using a packet in the first embodiment of the present invention.
  • FIG. 3 is a block diagram showing a configuration for explaining an operation using a packet in the first embodiment of the present invention.
  • FIG. 2 is a configuration diagram for explaining a connector mounting form included in the endoscope system according to the first embodiment of the present invention.
  • FIG. 6 is a block diagram for explaining another extension example of the image processing function in the first embodiment of the present invention.
  • FIG. 6 is a block diagram for explaining another extension example of the image processing function in the first embodiment of the present invention.
  • FIG. 6 is a block diagram illustrating a configuration of an image processor included in an endoscope system according to a second embodiment of the present invention.
  • FIG. 10 is a block diagram showing connection of an image processing LSI in a third embodiment of the present invention.
  • FIG. 10 is a block diagram showing a configuration of an image processing LSI in a third embodiment of the present invention.
  • FIG. 10 is a block diagram showing a configuration of an endoscope system according to a fourth embodiment of the present invention.
  • FIG. 10 is a block diagram showing a configuration of an endoscope system according to a fifth embodiment of the present invention.
  • FIG. 10 is a block diagram showing a configuration of an endoscope system according to a sixth embodiment of the present invention. It is a figure which shows the example of the memory space in the 1st Embodiment of this invention. It is a timing chart which shows the example of data transmission in the 1st Embodiment of this invention.
  • FIG. 1 shows a configuration of an endoscope system according to the present embodiment.
  • the endoscope system according to the present embodiment includes an endoscope scope 100 that converts optical information into a digital image signal 101, an image processor 102 that performs predetermined image processing on the digital image signal 101, and a monitor 115 that displays an image. It consists of
  • the endoscope scope 100 has a solid-state image sensor and outputs a digital image signal 101.
  • the image processor 102 includes a main substrate 103 having image processing LSIs 107 and 108 (first image processing units) that perform basic image processing, and an image processing LSI 114 (second image processing unit) that performs additional image processing.
  • an expansion board 104 having The main board 103 is provided with a connector 105, the extension board 104 is provided with a connector 106, and the main board 103 and the extension board 104 are connected via these connectors.
  • Image processing LSIs 107, 108, and 114 perform various image processing on the input digital image signal.
  • the output of the image processing LSI 107 is connected to the input of the image processing LSI 108 via the transmission path 109.
  • the output of the image processing LSI 108 is connected to the first terminal of the connector 105 via the transmission path 110.
  • the first terminal of the connector 105 is connected to the first terminal of the connector 106.
  • the first terminal of the connector 106 is connected to the input of the image processing LSI 114 via the transmission path 111.
  • the output of the image processing LSI 114 is connected to the second terminal of the connector 106 via the transmission path 112.
  • the second terminal of the connector 106 is connected to the second terminal of the connector 105 of the main board 103, and the second terminal of the connector 105 is connected to the input of the image processing LSI 107 via the transmission path 113. .
  • a monitor 115 is connected to the image processing LSI 108.
  • the monitor 115 displays an image based on the image signal 120 output from the image processing LSI 108.
  • the monitor 115 is connected to the image processing LSI 108, but the monitor 115 may be connected to the image processing LSI 107.
  • a high-speed serial communication system using, for example, LVDS (Low Voltage Differential Signaling) is applied.
  • LVDS Low Voltage Differential Signaling
  • FIG. 2 shows an example of the packet configuration.
  • an ID, an address, and data are included in a packet.
  • the ID is an identifier unique to each image processing on the endoscope system, and a unique identifier is assigned to each of the image processing modules constituting the image processing system.
  • a large functional classification is defined for each chip, and when it is not necessary to subdivide the functions in the chip, the identification target by ID is not the image processing module unit but the chip unit. It may be.
  • the address is an address of a register in the image processing LSI or an address of a memory connected to the image processing LSI.
  • the data is data such as image data constituting a digital image signal and parameters necessary for image processing.
  • the transmission path is simply a signal line, and any data can be transmitted as long as the data handling method is determined between the transmission side and the reception side.
  • address information and data information may be mixed in a predetermined bit width, or address information and data information may be sent in a time division manner. That is, since it is only necessary to determine how many bit signal lines are prepared for data transmission in the entire system, the apparatus design work becomes very simple.
  • Transmission paths 109, 110, 111, 112, 113 and connectors 105, 106 form a ring-shaped transfer path.
  • Each image processing LSI is connected in a ring shape via this transfer path, and data is transmitted from one image processing LSI to the image processing LSI adjacent to the image processing LSI in an operation like a shift register. Is done. Since data is transmitted by a transmission method such as a so-called bucket relay, data transmission between distant image processing LSIs requires some time, but data transmission in any combination can be performed without any problem.
  • the digital image signal output from the image processing LSI 107 is transmitted to the transmission path 109, the image processing The data is transferred to the image processing LSI 114 via the LSI 108, the transmission path 110, the connectors 105 and 106, and the transmission path 111, and processed by the image processing LSI 114.
  • One point on the ring-shaped transfer path can be opened and closed, and an image processing LSI with a function to be expanded later can be inserted there.
  • the image processing LSI 114 having a function to be expanded can be inserted.
  • the connector 106 is not connected, the connector 105 is short-circuited, and a ring-shaped transfer path is formed only by the configuration on the main board 103.
  • a predetermined address space must be shared by all elements connected to the bus, so that the number of addresses that can be used by each element decreases as the number of connected elements increases. This means that the possibility of function expansion is limited in the bus system, and it is further influenced by other factors. For this reason, it is not always best to apply the bus system to a device whose maximum purpose is function expansion.
  • an ID and an address are included in the packet, and the data storage location is identified by the combination of the ID and the address. Therefore, it is possible to use the same address between different IDs. For this reason, the entire predetermined address space can be used for each ID, and the selection range of addresses that can be used by each element is widened.
  • Fig. 3 shows the configuration of each image processing LSI.
  • the image processing LSI includes a packet analysis unit 200, a data processing unit 201, a packet generation unit 202, and a packet selection unit 203.
  • the packet analysis unit 200 analyzes the input signal 204 and determines whether or not the input signal 204 is a signal addressed to its own chip.
  • the ID in the packet is referred to, and this determination is performed based on the ID.
  • the packet analysis unit 200 outputs the input signal 204 as it is to the packet selection unit 203 as the packet signal 205.
  • the data included in the input signal 204 is output to the data processing unit 201, but the packet signal is not output to the packet selection unit 203.
  • the packet analysis unit 200 also has a function to check all input IDs on the system registered in advance and delete the packet (do not output it to the subsequent stage) when a packet with a nonexistent ID is detected. is doing. The function for erasing unnecessary packets is sufficient if there is only one location on the transfer path, and it is not necessary to mount it on all chips.
  • the data processing unit 201 performs predetermined image processing on the input data and outputs processing result data to the packet generation unit 202.
  • the data processing unit 201 is connected to the monitor 115, and the data processing unit 201 generates an image signal 120 from the processing result data and outputs the image signal 120 to the monitor 115.
  • the packet generation unit 202 generates a packet including the input data and molded into a predetermined packet format, and outputs the packet as a packet signal 206 to the packet selection unit 203.
  • the packet signal 206 includes an ID
  • the packet generation unit 202 determines which image processing module performs the next image processing in accordance with a predetermined image processing order, and determines the image processing module.
  • a packet signal 206 including the ID is output.
  • the packet selection unit 203 selects one of the packet signal 205 from the packet analysis unit 200 and the packet signal 206 from the packet generation unit 202, and outputs the selected signal to the next-stage image processing LSI. Basically, when the input signal 204 is a signal addressed to another chip, the packet signal 205 is selected.
  • the packet analysis unit 200 receives a signal indicating a determination result as to whether or not the input signal 204 is a signal addressed to another chip, and is input to the packet selection unit 203 together with the packet signal 205. Selects one of the packet signal 205 and the packet signal 206 based on the signal.
  • each image processing LSI is connected in a ring shape.
  • the packet is transferred to the other image processing LSI and addressed to its own chip.
  • data processing is performed, and the packet including the processed data is transferred to another image processing LSI.
  • data can be transferred from a certain image processing LSI to an arbitrary image processing LSI. Therefore, by adding the image processing LSI 114, image processing LSI 107, image processing LSI 114, and image processing LSI 108 are processed in the order, or image processing LSI 114, image processing LSI 107, and image processing LSI 108 are processed in order. In any case, desired image processing can be realized.
  • FIG. 4A and 4B show examples of other packet configurations different from the packet configuration shown in FIG.
  • FIG. 4A shows an example of a packet configuration dedicated to image data
  • FIG. 4B shows an example of a packet configuration for data transfer with an address.
  • [ID] field stores the ID.
  • the [command] field indicates the type of packet. For example, information such as “image data transfer mode” and “data transfer mode with address” is stored in the [command] field.
  • the [type] field has a role of supplementing the operation of the command.
  • Image processing in an endoscope apparatus often has a so-called pipeline operation, and input data is often processed sequentially.
  • a process for temporarily storing data in the storage means is unnecessary, and therefore there is no [address] field in the format (FIG. 4A) for transferring image data that can be processed by the pipeline operation.
  • the data transfer destination is also uniquely determined. In this case, the “ID” field may be omitted.
  • FIG. 5 shows an example of an operation using a packet in which “Write” is stored in the [Type] field.
  • FIG. 5 shows an example in which packets 220, 221 and 222 are sequentially transmitted from the image processing LSI on the transmission side to the image processing LSI on the reception side. No data is stored in the packet 220, an arbitrary ID is stored in the [ID] field, “data transfer mode with address” is stored in the [Command] field, and “Write” is stored in the [Type] field. ",” 2 "is stored in the [burst] field, and an arbitrary address is stored in the [address] field. Packets 221 and 222 are packets in which only data is stored.
  • the data processing unit 201 determines from the [command] field of the packet 220 that it is “data transfer with address”, and then determines that the operation is “Write” from the [type] field. know. Further, the data processing unit 201 knows that the data for writing is transmitted over the subsequent two cycles from the [burst] field. When the packets 221 and 222 are received, the data processing unit 201 writes the data stored in these packets in the position indicated by the address stored in the [address] field of the packet 220.
  • a memory 212 is connected to the image processing LSI 211.
  • the image processing LSI 210 can access the memory 212 connected to the image processing LSI 211 using the packet in FIG. 4B.
  • the ID of the memory 212 is stored in the [ID] field of the packet 220, and the address of the memory 212 is stored in the [address] field of the packet 220.
  • This ID is actually the ID of the “port” of the memory controller that controls the memory.
  • FIG. 16 shows an example of a memory map of the memory 212. In FIG. 16, the memory space is divided into three spaces of ports A, B, and C, and data stored in these ports is determined. When accessing the memory, ID numbers corresponding to these ports are designated.
  • FIG. 17 shows the transfer timing of image data and image processing parameters in the present embodiment.
  • the data is transferred by the same transfer path (transmission paths 109, 110, 111, 112, 113 in FIG. 1) regardless of the type of data. Transmission is realized. Therefore, in order to increase the data transmission efficiency, it is necessary to reduce transfer timing contention.
  • control is performed so that image processing parameters are transferred during an invalid period (blanking period) of image data. By controlling in this way, arbitration of data output to the transfer path is simplified.
  • the vertical synchronization signal is drawn independently, but in actuality, the synchronization signal is embedded in the packet and transferred.
  • the mounting form of the connectors 105 and 106 will be described.
  • the extension board 104 may be unnecessary.
  • a ring-shaped transfer path needs to be formed. Therefore, when the extension board 104 is not connected, it is necessary to short-circuit the first terminal and the second terminal of the connector 105 by some means.
  • FIG. 7 shows an example of a configuration in which the first terminal and the second terminal of the connector 105 are short-circuited.
  • FIG. 7 shows the main board 103 as viewed from the side.
  • a short circuit 300 is fitted to the connector 105.
  • the first terminal of the connector 105 connected to the transmission path 110 is connected to the terminal 301 of the short circuit 300
  • the second terminal of the connector 105 connected to the transmission path 113 is connected to the terminal 302 of the short circuit 300.
  • the terminal 301 and the terminal 302 that need to be short-circuited are short-circuited inside the short-circuit device 300.
  • a ring-shaped transfer path can be formed only by the main substrate 103.
  • FIG. 8 shows an example in which connectors 400 and 401 with switches are mounted on the main board 103.
  • the connectors with switches 400 and 401 are normally closed by a spring-like mechanism, but when an external contact is connected, the spring is pushed down and the connection is switched to the external contact side.
  • a ring-shaped transfer path is formed in the main board 103 when the extension board 104 is not connected, but a ring-shaped transfer path including the extension board 104 is formed when the extension board 104 is connected.
  • FIG. 9 shows an example in which the extension function is directly mounted on the main board 103 without connecting the extension board 104.
  • a ring-shaped transmission line is normally formed by the resistor 500 (resistance value is 0 ⁇ ).
  • resistor 500 resistance value is 0 ⁇ .
  • the image processing LSIs are connected in a ring shape, and the image processing LSI can be added to at least one point of the ring-shaped transfer path.
  • each image processing LSI can perform image processing in an arbitrary order. For this reason, the addition of a desired image processing function can be realized, and the expandability related to the addition of the image processing function can be improved.
  • serial transmission for data transmission between image processing LSIs
  • the number of physical signals can be reduced compared to parallel transmission.
  • transmitting data as a low-voltage differential signal such as LVDS (Low Voltage Differential Differential), it is possible to increase the signal transmission speed.
  • LVDS Low Voltage Differential Differential
  • FIG. 10 shows the configuration of the image processor according to the present embodiment.
  • the image processor according to the present embodiment includes a main board 103 and expansion boards 600 and 601.
  • the main substrate 103 includes image processing LSIs 107 and 108
  • the expansion substrate 600 includes an image processing LSI 116
  • the expansion substrate 601 includes an image processing LSI 117.
  • the extension boards 600 and 601 are created based on the same standard.
  • the main board 103 and the extension boards 600 and 601 are connected by optical transmission cables 602, 603, and 604, not by connectors.
  • data transmission using the transmission path 605 on the main board 103 may be optical transmission.
  • Optical transmission has higher transmission capability than electric signal transmission, and more data can be transmitted.
  • the expansion boards 600 and 601 are created based on the same standard, but the functions of the image processing LSI mounted on them are naturally different. However, if a device such as an FPGA (Field Programmable Gate Array) that can change the internal logic is used for the image processing LSI, only one type of substrate may be created.
  • FPGA Field Programmable Gate Array
  • optical transmission has higher transfer capability than electrical signal transmission, in addition to data transmission between boards, data transmission between image processing LSIs on the same board is made optical transmission, which further reduces the number of signals. The transfer capability can be improved.
  • FIG. 11 shows the connection of the image processing LSI in this embodiment.
  • Transmission lines 705, 706, and 707 are added in addition to the transmission lines that connect two adjacent image processing LSIs among the five image processing LSIs 700, 701, 702, 703, and 704.
  • the transmission path 705 connects the image processing LSIs 703 and 700
  • the transmission path 706 connects the image processing LSIs 704 and 701
  • the transmission path 707 connects the image processing LSIs 702 and 704.
  • FIG. 12 shows the configuration of each image processing LSI.
  • the image processing LSI includes a packet analysis unit 230, a data processing unit 232, packet generation units 233 and 234, and packet selection units 235 and 236.
  • the image processing LSI of this embodiment supports input and output of two systems of digital image signals.
  • One of the two systems of digital image signals is input to the packet analysis unit 230 as an input signal 237 from one transmission path on the input side, and the other of the two systems of digital image signals is input signal 238 from the other transmission path on the input side. Is input to the packet analysis unit 230.
  • one of the two digital image signals is output from the packet selection unit 235 to one transmission line on the output side, and the other of the two digital image signals is output from the packet selection unit 236 to the other transmission line on the output side. Is done.
  • the packet analysis unit 230 analyzes the input signals 237 and 238 and determines whether or not the input signals 237 and 238 are signals addressed to the own chip.
  • the packet analysis unit 230 outputs the input signals 237 and 238 as they are to the packet selection unit 235 as the packet signal 239 or outputs them to the packet selection unit 236 as the packet signal 240. Further, when the input signals 237 and 238 are signals addressed to the own chip, the packet analysis unit 230 outputs the data included in the input signals 237 and 238 to the data processing unit 232.
  • the packet analysis units 230 and 231 detect this information from the packets of the input signals 237 and 238, notify the data processing unit 232, and based on this information, send packets to one of the packet selection unit 235 and the packet selection unit 236. Output a signal.
  • the data processing unit 232 performs predetermined image processing on the input data, and outputs the processing result data to the packet generation unit 233 or the packet generation unit 234.
  • the packet generation units 233 and 234 serving as data output destinations are determined based on the information related to the transfer path notified from the packet analysis unit 230.
  • the packet generation unit 233 generates a packet including the input data and molded into a predetermined packet format, and outputs the packet as a packet signal 241 to the packet selection unit 235.
  • the packet selection unit 235 selects one of the packet signal 239 from the packet analysis unit 230 and the packet signal 241 from the packet generation unit 233, and is connected to the one transmission line on the output side. Output to a multistage image processing LSI.
  • the packet generation unit 234 generates a packet including the input data and molded into a predetermined packet format, and outputs the packet as a packet signal 242 to the packet selection unit 236.
  • the packet selection unit 236 selects one of the packet signal 240 from the packet analysis unit 230 and the packet signal 242 from the packet generation unit 234, and is connected to the other transmission path on the output side. Output to a multistage image processing LSI.
  • each image processing LSI is connected by a ring-shaped transfer path, but this transfer path does not have to be one system. It is also possible to provide a plurality of transfer paths as in this embodiment.
  • the image processing LSI When the image processing LSI is implemented with a logic device such as an FPGA whose internal structure can be changed, the logic device does not include any data transfer during the process of changing the circuit configuration of these logic devices. It cannot be processed.
  • a logic device such as an FPGA whose internal structure can be changed
  • the logic device does not include any data transfer during the process of changing the circuit configuration of these logic devices. It cannot be processed.
  • FIG. 13 shows the configuration of the endoscope system according to the present embodiment.
  • the endoscope system according to the present embodiment includes an endoscope scope 800 that converts optical information into a digital image signal, an image processor 801 that performs predetermined image processing on the digital image signal, and a monitor 806 that displays a 3D image. It is configured.
  • the endoscope scope 800 includes two imaging elements 802 and 803 inside, and a stereoscopic image can be configured in combination with the subsequent 3D processing.
  • the image sensor 802 generates an image signal for the left eye image
  • the image sensor 803 generates an image signal for the right eye image.
  • the image processor 801 includes a substrate 809 having an image processing LSI 804 and a connector 807, and a substrate 810 having an image processing LSI 805 and a connector 808.
  • the substrate 809 corresponds to the main substrate 103 of the first embodiment
  • the substrate 810 corresponds to the expansion substrate 104 of the first embodiment.
  • High-accuracy assembly technology is required to acquire 3D images, but it is very difficult to perform high-accuracy processing with equipment that requires space saving, such as an endoscope scope. Therefore, it is considered that it is necessary to correct variations in processing accuracy by subsequent signal processing. To that end, it is necessary to significantly improve the performance of the image processing circuit.
  • the image processing LSI 804 is in charge of signal processing for the left eye image and the image processing LSI 805 is in charge of signal processing for the right eye image, even if the performance of the image processing LSI is close to the limit, 3D Image processing corresponding to the image becomes possible.
  • a dedicated monitor compatible with 3D is required to display a 3D image, but the image processing LSI 805 may perform processing for inputting an appropriate image signal to the dedicated monitor.
  • Distribution of the left and right image signals from the endoscope scope 800 may be performed by the endoscope scope 800, or an IF conversion FPGA is provided between the endoscope scope 800 and the image processing LSI 804. You may make it perform. If the image processing LSI 804 itself is realized by an FPGA, the image processing LSI 804 may distribute the left and right image signals.
  • FIG. 14 shows the configuration of the endoscope system according to the present embodiment.
  • the endoscope system according to the present embodiment includes an endoscope scope 811 that converts optical information into a digital image signal, an image processor 812 that performs predetermined image processing on the digital image signal, and monitors 813 and 814 that display images. It consists of
  • the image processor 812 includes a substrate 819 having an image processing LSI 815 and a connector 817, and a substrate 820 having an image processing LSI 816 and a connector 818.
  • the substrate 819 corresponds to the main substrate 103 of the first embodiment
  • the substrate 820 corresponds to the expansion substrate 104 of the first embodiment.
  • the image processing LSI 815 basically displays an image by outputting an image signal to the monitor 813.
  • the image processing LSI 815 has a larger number of pixels than the number of pixels of the monitor 813.
  • a system for outputting an image to the monitor 814 can be added.
  • the image processing LSI 816 enlarges the image size of the image signal to a size corresponding to the screen of the monitor 814, and outputs the image signal to the monitor 814. Therefore, even if the multi-pixel monitor becomes mainstream, the image display can be maintained.
  • the display means has been described with respect to the increase in the number of pixels.
  • the processing capability of the image processing LSI 815 may be insufficient due to the increase in the number of pixels. In this case, the shortage of processing capability can be resolved by using the image processing LSI 816 together.
  • FIG. 15 shows the configuration of the endoscope system according to the present embodiment.
  • the endoscope system according to the present embodiment includes an endoscope scope 821 that converts optical information into a digital image signal, an image processor 822 that performs predetermined image processing on the digital image signal, and recording devices 823 and 824 that record images. It consists of and.
  • the image processor 822 includes a substrate 829 having an image processing LSI 825 and a connector 827, and a substrate 830 having an image processing LSI 826 and a connector 828.
  • the substrate 829 corresponds to the main substrate 103 of the first embodiment
  • the substrate 830 corresponds to the expansion substrate 104 of the first embodiment.
  • the image processing LSI 825 outputs an image signal to the recording device 823 to record an image, but apart from this system, the recording device 824 corresponding to a standard different from the recording device 823.
  • a system for outputting an image signal can be added to.
  • the image processing LSI 826 converts the format of the image signal into a recording format corresponding to the recording device 824, and outputs the converted image signal.
  • Image data recording has been switched from analog to digital, but there are various standards for digital systems, and it is thought that new standards will be established in the future. This embodiment makes it possible to flexibly cope with new standards.
  • the second image processing unit when the second image processing unit is added, since the first image processing unit and the second image processing unit are connected in a ring shape, the second image processing unit is located at which position. Even when added, the image signal data processed by any of the image processing units can be transferred to an arbitrary image processing unit. Therefore, it is possible to improve the expandability related to the addition of the image processing function.
  • Memory 300 ... Short circuit 301, 302 ... Terminal 400, 401 ... Connector with switch 500 ... Resistor 602, 603, 604 ... Optical transmission cable 802, 803 ..Image sensors 809, 810, 819, 820, 829, 830 ... Substrate 823, 824 ... Recording device

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Abstract

Each image processing LSI is connected in a ring. In cases when a packet addressed to another chip is inputted, the packet is transferred to another image processing LSI. In cases when a packet addressed to the chip itself is inputted, data is processed and the packet including the processed data is transferred to another image processing LSI. By connecting another connector to a connector, image processing LSIs having a desired function can be inserted.

Description

内視鏡用画像プロセッサEndoscopic image processor
　本発明は、固体撮像素子から出力された画像信号に画像処理を施す内視鏡用画像プロセッサに関する。
　本願は、２０１２年０１月１８日に、日本に出願された特願２０１２－００８０９３号に基づき優先権を主張し、その内容をここに援用する。 The present invention relates to an endoscope image processor that performs image processing on an image signal output from a solid-state imaging device.
This application claims priority based on Japanese Patent Application No. 2012-008093 filed in Japan on January 18, 2012, the contents of which are incorporated herein by reference.
　医療分野において、電子内視鏡による検査が広く行われている。電子内視鏡は、固体撮像素子から出力される画像信号に対して、内視鏡用画像プロセッサにより画像処理を施してモニタに画像を表示する。電子機器に搭載される機能が年々多様化する傾向があるが、その傾向は内視鏡用画像プロセッサにおいても同様である。しかし、製品に求められる全ての機能を搭載すると、装置全体のコストアップにつながってしまう。 In the medical field, inspection using an electronic endoscope is widely performed. The electronic endoscope performs image processing on an image signal output from the solid-state imaging device by an endoscope image processor and displays an image on a monitor. There is a tendency that functions installed in electronic devices are diversified year by year, and this tendency is the same also in an endoscope image processor. However, if all the functions required for the product are installed, the cost of the entire apparatus will increase.
　また、医療機器の発売までに種々の認証を取得しなければならないため、製品の発売サイクルが長期化する傾向がある。そのため、新製品を発売することによりその時代のニーズに逐次応えていくことは非常に難しい。そこで、多くの製品に共通で使用可能な、標準的な機能のみが実装され、その他の機能に関しては後から追加できる拡張性を有する構造の装置が求められている。 Also, since various certifications must be obtained before the medical device is released, the product release cycle tends to be prolonged. For this reason, it is very difficult to respond to the needs of the times by launching new products. Therefore, there is a demand for an apparatus having an expandable structure in which only standard functions that can be commonly used in many products are mounted and other functions can be added later.
　そのような装置を実現する方法が特許文献1に記載されている。特許文献1では、標準画像処理部60に機能拡張用I/F61を接続し、機能拡張用I/F61に増設画像処理部62を接続することで、画像処理機能の拡張が実現されている。 A method for realizing such an apparatus is described in Patent Document 1. In Patent Document 1, the image processing function is expanded by connecting the function expansion I / F 61 to the standard image processing unit 60 and connecting the additional image processing unit 62 to the function expansion I / F 61.

日本国特開２００９－２７３８２４号公報Japanese Unexamined Patent Publication No. 2009-273824

　内視鏡用画像プロセッサが行う画像処理には、ノイズ軽減、色補正、色強調、輪郭強調等の様々な画像処理がある。これらの画像処理は所定の順番で実施されるが、様々な処理機能の追加が発生する可能性がある。より柔軟な拡張性を実現するためには、所定の順番で実施される複数の画像処理のうちの任意の画像処理に対して処理機能を追加できることが望ましい。しかし、特許文献1では、標準画像処理部60に対して増設画像処理部62を追加できるだけであり、上記のような柔軟な拡張性は実現されていない。
Image processing performed by the endoscope image processor includes various image processing such as noise reduction, color correction, color enhancement, and contour enhancement. These image processes are performed in a predetermined order, but various processing functions may be added. In order to realize more flexible expandability, it is desirable that a processing function can be added to any image processing among a plurality of image processing performed in a predetermined order. However, in Patent Document 1, only the additional image processing unit 62 can be added to the standard image processing unit 60, and the flexible extensibility as described above is not realized.

　本発明は、上述した課題に鑑みてなされたものであって、画像処理機能の追加に係る拡張性を高めることができる内視鏡用画像プロセッサを提供することを目的とする。
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an endoscope image processor capable of enhancing expandability related to addition of an image processing function.

　本発明の第１の態様によれば、内視鏡の固体撮像素子から出力された画像信号に画像処理を施す内視鏡用画像プロセッサであって、前記画像信号に対して画像処理を行う第1の画像処理部を有し、前記画像信号に対して画像処理を行う第2の画像処理部を備える場合、前記第1の画像処理部は、前記画像信号のデータを含むパケットが入力され、前記パケットを解析して前記パケットの宛先が前記第1の画像処理部であるか否かを判定するパケット解析部と、前記パケットの前記宛先が前記第1の画像処理部であると判定された場合に、前記パケットに含まれるデータを処理するデータ処理部と、前記データ処理部によって処理されたデータを含むとともに、前記第2の画像処理部を宛先に指定するパケットを生成するパケット生成部と、前記パケットの前記宛先が前記第1の画像処理部でないと判定された前記パケット、および、前記パケット生成部によって生成された前記パケットのいずれか一方を選択して出力するパケット選択部と、を有し、前記第2の画像処理部は、前記画像信号のデータを含むパケットが入力され、前記パケットを解析して前記パケットの宛先が前記第2の画像処理部であるか否かを判定するパケット解析部と、前記パケットの前記宛先が前記第2の画像処理部であると判定された場合に、前記パケットに含まれるデータを処理するデータ処理部と、前記データ処理部によって処理されたデータを含むとともに、前記第1の画像処理部を宛先に指定するパケットを生成するパケット生成部と、前記パケットの前記宛先が前記第2の画像処理部でないと判定された前記パケット、および、前記パケット生成部によって生成された前記パケットのいずれか一方を選択して出力するパケット選択部と、を有し、前記第2の画像処理部が追加された場合に、前記第1の画像処理部および前記第2の画像処理部はリング状に接続される。
According to the first aspect of the present invention, there is provided an endoscope image processor that performs image processing on an image signal output from a solid-state imaging device of an endoscope, wherein the image processing is performed on the image signal. If the image processing unit has a second image processing unit that performs image processing on the image signal, the first image processing unit receives a packet including data of the image signal, A packet analysis unit that analyzes the packet to determine whether the destination of the packet is the first image processing unit, and the destination of the packet is determined to be the first image processing unit A data processing unit that processes data included in the packet, and a packet generation unit that includes the data processed by the data processing unit and generates a packet that designates the second image processing unit as a destination; , The packet A packet selection unit that selects and outputs one of the packets generated by the packet generation unit, the packet determined that the destination is not the first image processing unit, The second image processing unit receives a packet including data of the image signal, analyzes the packet, and determines whether the destination of the packet is the second image processing unit A data processing unit that processes data included in the packet when the destination of the packet is determined to be the second image processing unit, and data processed by the data processing unit A packet generation unit that generates a packet designating the first image processing unit as a destination, and the packet that is determined that the destination of the packet is not the second image processing unit. And a packet selection unit that selects and outputs any one of the packets generated by the packet generation unit, and when the second image processing unit is added, the first The image processing unit and the second image processing unit are connected in a ring shape.

　本発明の第２態様によれば、上記第１態様の内視鏡用画像プロセッサにおいて、前記第1の画像処理部と前記第2の画像処理部の間の前記パケットの伝送は、シリアル通信により行われてもよい。
According to the second aspect of the present invention, in the endoscope image processor according to the first aspect, transmission of the packet between the first image processing unit and the second image processing unit is performed by serial communication. It may be done.

　本発明の第３態様によれば、上記第１態様の内視鏡用画像プロセッサにおいて、前記第1の画像処理部と前記第2の画像処理部との間の前記パケットの伝送は、光伝送により行われてもよい。
According to a third aspect of the present invention, in the endoscope image processor according to the first aspect, the packet transmission between the first image processing unit and the second image processing unit is an optical transmission. May be performed.

　本発明の第４態様によれば、上記第１態様の内視鏡用画像プロセッサにおいて、複数の基板をさらに有し、前記第1の画像処理部および前記第2の画像処理部のそれぞれは前記複数の基板のいずれかに配置され、前記第1の画像処理部が配置された基板と前記第2の画像処理部が配置された基板との間の前記パケットの伝送は、光伝送により行われてもよい。　
According to the fourth aspect of the present invention, the endoscope image processor according to the first aspect further includes a plurality of substrates, wherein each of the first image processing unit and the second image processing unit is the Transmission of the packet between the substrate on which the first image processing unit is disposed and the substrate on which the second image processing unit is disposed is performed by optical transmission. May be.
　本発明の第５態様によれば、上記第１態様の内視鏡用画像プロセッサにおいて、前記パケットを構成するデータは、画像データ、あるいは画像処理用の設定パラメータを含んでいてもよい。 According to the fifth aspect of the present invention, in the endoscope image processor according to the first aspect, the data constituting the packet may include image data or setting parameters for image processing.
　本発明の第６態様によれば、上記第１態様の内視鏡用画像プロセッサにおいて、前記パケット解析部は、入力された前記パケットを解析し、前記パケットの宛先が存在しないと判断した場合、入力された前記パケットを消去してもよい。
According to the sixth aspect of the present invention, in the endoscope image processor according to the first aspect, when the packet analysis unit analyzes the input packet and determines that the destination of the packet does not exist, The inputted packet may be deleted.

　上記各態様よれば、第2の画像処理部が追加された場合に、第１の画像処理部および第2の画像処理部がリング状に接続されるため、どの位置に第2の画像処理部が追加された場合でも、いずれかの画像処理部で処理された画像信号のデータを任意の画像処理部に転送することが可能となる。したがって、画像処理機能の追加に係る拡張性を高めることができる。
According to each aspect described above, when the second image processing unit is added, the first image processing unit and the second image processing unit are connected in a ring shape. Even when is added, the image signal data processed by any of the image processing units can be transferred to an arbitrary image processing unit. Therefore, it is possible to improve the expandability related to the addition of the image processing function.
本発明の第1の実施形態による内視鏡システムの構成を示すブロック図である。1 is a block diagram showing a configuration of an endoscope system according to a first embodiment of the present invention. 本発明の第1の実施形態におけるパケットの構成を示す参考図である。FIG. 5 is a reference diagram showing a packet configuration in the first exemplary embodiment of the present invention. 本発明の第1の実施形態による内視鏡システムが有する画像処理LSIの構成を示すブロック図である。1 is a block diagram showing a configuration of an image processing LSI included in an endoscope system according to a first embodiment of the present invention. 本発明の第1の実施形態におけるパケットの他の構成を示す参考図である。FIG. 6 is a reference diagram illustrating another configuration of a packet according to the first embodiment of the present invention. 本発明の第1の実施形態におけるパケットの他の構成を示す参考図である。FIG. 6 is a reference diagram illustrating another configuration of a packet according to the first embodiment of the present invention. 本発明の第1の実施形態におけるパケットを用いた動作の例を示す参考図である。FIG. 6 is a reference diagram illustrating an example of an operation using a packet in the first embodiment of the present invention. 本発明の第1の実施形態におけるパケットを用いた動作を説明するための構成を示すブロック図である。FIG. 3 is a block diagram showing a configuration for explaining an operation using a packet in the first embodiment of the present invention. 本発明の第1の実施形態による内視鏡システムが有するコネクタの実装形態を説明するための構成図である。FIG. 2 is a configuration diagram for explaining a connector mounting form included in the endoscope system according to the first embodiment of the present invention. 本発明の第1の実施形態における画像処理機能の他の拡張例を説明するためのブロック図である。FIG. 6 is a block diagram for explaining another extension example of the image processing function in the first embodiment of the present invention. 本発明の第1の実施形態における画像処理機能の他の拡張例を説明するためのブロック図である。FIG. 6 is a block diagram for explaining another extension example of the image processing function in the first embodiment of the present invention. 本発明の第2の実施形態による内視鏡システムが有する画像プロセッサの構成を示すブロック図である。FIG. 6 is a block diagram illustrating a configuration of an image processor included in an endoscope system according to a second embodiment of the present invention. 本発明の第3の実施形態における画像処理LSIの接続を示すブロック図である。FIG. 10 is a block diagram showing connection of an image processing LSI in a third embodiment of the present invention. 本発明の第3の実施形態における画像処理LSIの構成を示すブロック図である。FIG. 10 is a block diagram showing a configuration of an image processing LSI in a third embodiment of the present invention. 本発明の第4の実施形態による内視鏡システムの構成を示すブロック図である。FIG. 10 is a block diagram showing a configuration of an endoscope system according to a fourth embodiment of the present invention. 本発明の第5の実施形態による内視鏡システムの構成を示すブロック図である。FIG. 10 is a block diagram showing a configuration of an endoscope system according to a fifth embodiment of the present invention. 本発明の第6の実施形態による内視鏡システムの構成を示すブロック図である。FIG. 10 is a block diagram showing a configuration of an endoscope system according to a sixth embodiment of the present invention. 本発明の第１の実施形態におけるメモリ空間の例を示す図である。It is a figure which shows the example of the memory space in the 1st Embodiment of this invention. 本発明の第１の実施形態におけるデータ伝送例を示すタイミングチャートである。It is a timing chart which shows the example of data transmission in the 1st Embodiment of this invention.
　以下、図面を参照し、本発明の実施形態を説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
　（第1の実施形態）
　まず、本発明の第1の実施形態を説明する。図1は、本実施形態による内視鏡システムの構成を示している。本実施形態による内視鏡システムは、光学情報をデジタル画像信号101に変換する内視鏡スコープ100と、デジタル画像信号101に所定の画像処理を施す画像プロセッサ102と、画像を表示するモニタ115とで構成されている。 (First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 shows a configuration of an endoscope system according to the present embodiment. The endoscope system according to the present embodiment includes an endoscope scope 100 that converts optical information into a digital image signal 101, an image processor 102 that performs predetermined image processing on the digital image signal 101, and a monitor 115 that displays an image. It consists of
　内視鏡スコープ100は固体撮像素子を有しており、デジタル画像信号101を出力する。画像プロセッサ102は、基本的な画像処理を行う画像処理LSI107，108（第1の画像処理部）を有するメイン基板103と、付加的な画像処理を行う画像処理LSI114（第2の画像処理部）を有する拡張基板104とで構成されている。メイン基板103にはコネクタ105が設けられ、拡張基板104にはコネクタ106が設けられ、メイン基板103と拡張基板104とはこれらのコネクタを介して接続されている。 The endoscope scope 100 has a solid-state image sensor and outputs a digital image signal 101. The image processor 102 includes a main substrate 103 having image processing LSIs 107 and 108 (first image processing units) that perform basic image processing, and an image processing LSI 114 (second image processing unit) that performs additional image processing. And an expansion board 104 having The main board 103 is provided with a connector 105, the extension board 104 is provided with a connector 106, and the main board 103 and the extension board 104 are connected via these connectors.
　画像処理LSI107，108，114は、入力されたデジタル画像信号に対して各種の画像処理を行う。画像処理LSI107の出力は、伝送路109を介して画像処理LSI108の入力に接続されている。画像処理LSI108の出力は、伝送路110を介してコネクタ105の第1の端子に接続されている。コネクタ105の第1の端子はコネクタ106の第1の端子と接続されている。コネクタ106の第1の端子は、伝送路111を介して画像処理LSI114の入力に接続されている。画像処理LSI114の出力は、伝送路112を介してコネクタ106の第2の端子に接続されている。コネクタ106の第2の端子はメイン基板103のコネクタ105の第2の端子に接続されており、コネクタ105の第2の端子は、伝送路113を介して画像処理LSI107の入力に接続されている。 Image processing LSIs 107, 108, and 114 perform various image processing on the input digital image signal. The output of the image processing LSI 107 is connected to the input of the image processing LSI 108 via the transmission path 109. The output of the image processing LSI 108 is connected to the first terminal of the connector 105 via the transmission path 110. The first terminal of the connector 105 is connected to the first terminal of the connector 106. The first terminal of the connector 106 is connected to the input of the image processing LSI 114 via the transmission path 111. The output of the image processing LSI 114 is connected to the second terminal of the connector 106 via the transmission path 112. The second terminal of the connector 106 is connected to the second terminal of the connector 105 of the main board 103, and the second terminal of the connector 105 is connected to the input of the image processing LSI 107 via the transmission path 113. .
　画像処理LSI108にはモニタ115が接続されている。モニタ115は、画像処理LSI108から出力された画像信号120に基づいて画像を表示する。図1では画像処理LSI108にモニタ115が接続されているが、画像処理LSI107にモニタ115が接続されていてもよい。 A monitor 115 is connected to the image processing LSI 108. The monitor 115 displays an image based on the image signal 120 output from the image processing LSI 108. In FIG. 1, the monitor 115 is connected to the image processing LSI 108, but the monitor 115 may be connected to the image processing LSI 107.
　伝送路109，110，111，112，113には、例えばLVDS(Low Voltage Differential Signaling)を用いるような高速なシリアル通信方式が適用されている。 For the transmission paths 109, 110, 111, 112, and 113, a high-speed serial communication system using, for example, LVDS (Low Voltage Differential Signaling) is applied.
　これらの伝送路上に流れる信号はパケット化されている。図2はパケット構成の一例を示している。
　本実施形態では、ID、アドレス、データがパケットに内包されている。IDは、内視鏡システム上の各画像処理に固有の識別子であり、画像処理システムを構成するすべての画像処理モジュールに、それぞれ固有の識別子が付与されている。複数チップにより画像処理システムを構成する場合において、大きな機能分類がチップごとに規定されており、チップ内の機能を細分化する必要がない場合、IDによる識別対象を画像処理モジュール単位ではなくチップ単位にしてもよい。
　アドレスは、画像処理LSI内のレジスタのアドレスや、画像処理LSIに接続されるメモリのアドレスである。データは、デジタル画像信号を構成する画像データや、画像処理に必要なパラメータ等のデータである。 Signals flowing on these transmission lines are packetized. FIG. 2 shows an example of the packet configuration.
In this embodiment, an ID, an address, and data are included in a packet. The ID is an identifier unique to each image processing on the endoscope system, and a unique identifier is assigned to each of the image processing modules constituting the image processing system. When configuring an image processing system with multiple chips, a large functional classification is defined for each chip, and when it is not necessary to subdivide the functions in the chip, the identification target by ID is not the image processing module unit but the chip unit. It may be.
The address is an address of a register in the image processing LSI or an address of a memory connected to the image processing LSI. The data is data such as image data constituting a digital image signal and parameters necessary for image processing.
　パケット通信において、伝送路は単なる信号線であり、送信側と受信側との間でデータの扱い方さえ決まっていればどのようなデータを伝送させても問題ない。例えば、図２に示すように、所定のビット幅の中にアドレス情報とデータ情報を混在させてもよいし、アドレス情報とデータ情報を時分割で送出してもよい。すなわち、システム全体として、データ伝送に何ビットの信号線を用意するかという点だけを決めておけばよいため、装置設計の作業が非常に簡単になる。 In packet communication, the transmission path is simply a signal line, and any data can be transmitted as long as the data handling method is determined between the transmission side and the reception side. For example, as shown in FIG. 2, address information and data information may be mixed in a predetermined bit width, or address information and data information may be sent in a time division manner. That is, since it is only necessary to determine how many bit signal lines are prepared for data transmission in the entire system, the apparatus design work becomes very simple.
　伝送路109，110，111，112，113とコネクタ105，106はリング状の転送路を形成している。各画像処理LSIは、この転送路を介してリング状に接続されており、ある画像処理LSIから、その画像処理LSIに隣接する画像処理LSIに対して、シフトレジスタのような動作でデータが伝送される。所謂バケツリレーのような伝送方式でデータが伝送されるため、離れた画像処理LSI間のデータ伝送には若干時間が必要となるが、あらゆる組み合わせでのデータ伝送を問題なく行うことができる。例えば、所定の画像処理の順番に従って画像処理LSI107で画像処理が行われた後、画像処理LSI114で画像処理が行われる場合、画像処理LSI107から出力されたデジタル画像信号は、伝送路109、画像処理LSI108、伝送路110、コネクタ105，106、伝送路111をそれぞれ経由して、画像処理LSI114に転送され、画像処理LSI114によって処理される。 Transmission paths 109, 110, 111, 112, 113 and connectors 105, 106 form a ring-shaped transfer path. Each image processing LSI is connected in a ring shape via this transfer path, and data is transmitted from one image processing LSI to the image processing LSI adjacent to the image processing LSI in an operation like a shift register. Is done. Since data is transmitted by a transmission method such as a so-called bucket relay, data transmission between distant image processing LSIs requires some time, but data transmission in any combination can be performed without any problem. For example, when image processing is performed by the image processing LSI 107 after image processing is performed by the image processing LSI 107 according to a predetermined image processing order, the digital image signal output from the image processing LSI 107 is transmitted to the transmission path 109, the image processing The data is transferred to the image processing LSI 114 via the LSI 108, the transmission path 110, the connectors 105 and 106, and the transmission path 111, and processed by the image processing LSI 114.
　リング状の転送路における一点は開閉可能になっており、そこに後から拡張したい機能を有する画像処理LSIを挿入できる。本実施形態では、コネクタ105にコネクタ106を接続することにより、拡張したい機能を有する画像処理LSI114を挿入することができる。後述するように、コネクタ106を接続しない場合、コネクタ105が短絡され、メイン基板103上の構成のみでリング状の転送路が形成される。 一 One point on the ring-shaped transfer path can be opened and closed, and an image processing LSI with a function to be expanded later can be inserted there. In this embodiment, by connecting the connector 106 to the connector 105, the image processing LSI 114 having a function to be expanded can be inserted. As will be described later, when the connector 106 is not connected, the connector 105 is short-circuited, and a ring-shaped transfer path is formed only by the configuration on the main board 103.
　一般的なバス方式のように、全ての画像処理LSIが同じ伝送路を経由してデータ伝送を行う場合、ある時点において伝送路を使用できるのは1つの画像処理LSIのみである。よって、システム上の画像処理LSIの総数が増えるほど、データ伝送を待たされる画像処理LSIの数が増えることになり、拡張性の観点では問題がある。 When all image processing LSIs perform data transmission via the same transmission path as in a general bus system, only one image processing LSI can use the transmission path at a certain time. Therefore, as the total number of image processing LSIs on the system increases, the number of image processing LSIs waiting for data transmission increases, which is problematic in terms of expandability.
　本実施形態では、画像処理LSIの総数が増えてもデータの伝送能力はあまり低下しない。また、転送路中の任意の画像処理LSIから他の任意の画像処理LSIへのデータ伝送が可能であるため、新機能を追加する場合は任意の一点（本実施形態ではコネクタ105の位置）に挿入するだけでよく、基板の作製が容易になる。 In this embodiment, even if the total number of image processing LSIs increases, the data transmission capability does not decrease much. In addition, since data transmission from any image processing LSI in the transfer path to any other image processing LSI is possible, when adding a new function, at any one point (position of the connector 105 in this embodiment) It is only necessary to insert them, and the production of the substrate becomes easy.
　また、バス方式の場合、所定のアドレス空間を、そのバスに接続されるすべての要素で共有しなければならないので、接続される要素が増えるほど、各要素が利用可能なアドレスは少なくなる。これは、バス方式では機能拡張の可能性に限界があり、さらに他の要素の影響を受けることを意味している。このため、機能拡張を最大の目的とする装置にバス方式を適用することは必ずしも最良ではない。 Also, in the case of the bus system, a predetermined address space must be shared by all elements connected to the bus, so that the number of addresses that can be used by each element decreases as the number of connected elements increases. This means that the possibility of function expansion is limited in the bus system, and it is further influenced by other factors. For this reason, it is not always best to apply the bus system to a device whose maximum purpose is function expansion.
　本実施形態では、パケットにIDとアドレスが含まれており、IDとアドレスの組合せによりデータの格納場所が識別されるので、異なるID間で同一のアドレスを使用することが可能である。このため、ID毎に所定のアドレス空間の全体を使用することが可能となり、各要素が利用可能なアドレスの選択幅が広くなる。 In this embodiment, an ID and an address are included in the packet, and the data storage location is identified by the combination of the ID and the address. Therefore, it is possible to use the same address between different IDs. For this reason, the entire predetermined address space can be used for each ID, and the selection range of addresses that can be used by each element is widened.
　図3は各画像処理LSIの構成を示している。画像処理LSIは、パケット解析部200、データ処理部201、パケット生成部202、パケット選択部203で構成されている。 Fig. 3 shows the configuration of each image processing LSI. The image processing LSI includes a packet analysis unit 200, a data processing unit 201, a packet generation unit 202, and a packet selection unit 203.
　パケット解析部200は、入力信号204を解析し、入力信号204が自チップ宛の信号であるか否かを判定する。本実施形態ではパケット内のIDを参照し、IDに基づいて、この判定を行う。IDに「一斉同報」を示す固有IDを設定することで、全てのチップに同じデータを一斉に送信することも可能である。パケット解析部200は、入力信号204が他チップ宛の信号であった場合には、入力信号204をそのままパケット選択部203にパケット信号205として出力する。入力信号204が自チップ宛の信号であった場合には、データ処理部201に対して入力信号204に含まれるデータを出力するが、パケット選択部203にはパケット信号を出力しない。これにより、データの回収（消去）が適切に行われ、転送が完了したデータが延々と転送路を巡回しつづける状況を回避する。
　本実施の形態では、転送効率を上げるため、転送元と転送先との間での事前のネゴシエーションを省略している（後述の”Read”動作を除く）。よって、転送先が存在しないデータが誤って送出されてしまう可能性があり、その場合には受信されないデータが転送路を巡回しつづけてしまう。パケット解析部200は、事前に登録されているシステム上のすべてのIDと入力パケットを照合し、存在しないIDのパケットが検出されると、そのパケットを消去（後段に出力しない）する機能も有している。
　不要なパケットを消去する機能は、転送路上に一箇所だけ存在すれば十分であり、すべてのチップに実装する必要はない。 The packet analysis unit 200 analyzes the input signal 204 and determines whether or not the input signal 204 is a signal addressed to its own chip. In this embodiment, the ID in the packet is referred to, and this determination is performed based on the ID. By setting a unique ID indicating “broadcast” to the ID, it is possible to transmit the same data to all chips simultaneously. When the input signal 204 is a signal addressed to another chip, the packet analysis unit 200 outputs the input signal 204 as it is to the packet selection unit 203 as the packet signal 205. When the input signal 204 is a signal addressed to its own chip, the data included in the input signal 204 is output to the data processing unit 201, but the packet signal is not output to the packet selection unit 203. This avoids a situation in which data is properly collected (erased) and data that has been transferred continues to cycle around the transfer path.
In this embodiment, in order to increase transfer efficiency, prior negotiation between the transfer source and the transfer destination is omitted (except for a “Read” operation described later). Therefore, there is a possibility that data for which there is no transfer destination may be erroneously sent, and in this case, data that is not received continues to circulate through the transfer path. The packet analysis unit 200 also has a function to check all input IDs on the system registered in advance and delete the packet (do not output it to the subsequent stage) when a packet with a nonexistent ID is detected. is doing.
The function for erasing unnecessary packets is sufficient if there is only one location on the transfer path, and it is not necessary to mount it on all chips.
　データ処理部201は、入力されたデータに対して所定の画像処理を行い、処理結果のデータをパケット生成部202に出力する。画像処理LSI108においては、データ処理部201はモニタ115に接続されており、データ処理部201は処理結果のデータから画像信号120を生成し、モニタ115に出力する。 The data processing unit 201 performs predetermined image processing on the input data and outputs processing result data to the packet generation unit 202. In the image processing LSI 108, the data processing unit 201 is connected to the monitor 115, and the data processing unit 201 generates an image signal 120 from the processing result data and outputs the image signal 120 to the monitor 115.
　パケット生成部202は、入力されたデータを含むとともに所定のパケットフォーマットに成型されたパケットを生成し、パケット信号206としてパケット選択部203に出力する。パケット信号206にはIDが含まれるが、パケット生成部202は、予め定められた画像処理の順番に従って、次に画像処理を行う画像処理モジュールがどれであるのかを判断し、その画像処理モジュールのIDを含むパケット信号206を出力する。 The packet generation unit 202 generates a packet including the input data and molded into a predetermined packet format, and outputs the packet as a packet signal 206 to the packet selection unit 203. Although the packet signal 206 includes an ID, the packet generation unit 202 determines which image processing module performs the next image processing in accordance with a predetermined image processing order, and determines the image processing module. A packet signal 206 including the ID is output.
　パケット選択部203は、パケット解析部200からのパケット信号205と、パケット生成部202からのパケット信号206とのうちのいずれか一方を選択して次段の画像処理LSIに出力する。基本的には、入力信号204が他のチップ宛の信号であった場合にはパケット信号205を選択する。図示していないが、パケット解析部200からは、入力信号204が他チップ宛の信号であるか否かの判定結果を示す信号がパケット信号205とともにパケット選択部203に入力され、パケット選択部203はその信号に基づいて、パケット信号205とパケット信号206のうちのいずれか一方を選択する。 The packet selection unit 203 selects one of the packet signal 205 from the packet analysis unit 200 and the packet signal 206 from the packet generation unit 202, and outputs the selected signal to the next-stage image processing LSI. Basically, when the input signal 204 is a signal addressed to another chip, the packet signal 205 is selected. Although not shown, the packet analysis unit 200 receives a signal indicating a determination result as to whether or not the input signal 204 is a signal addressed to another chip, and is input to the packet selection unit 203 together with the packet signal 205. Selects one of the packet signal 205 and the packet signal 206 based on the signal.
　上記のように本実施形態では、各画像処理LSIは、リング状に接続されており、他チップ宛のパケットが入力された場合にはそのパケットを他の画像処理LSIに転送し、自チップ宛のパケットが入力された場合にはデータ処理を行い、処理後のデータを含むパケットを他の画像処理LSIに転送する。これにより、ある画像処理LSIから任意の画像処理LSIに対してデータを転送することができる。したがって、画像処理LSI114を追加することにより、画像処理LSI107、画像処理LSI114、画像処理LSI108の順番で画像処理を行う場合や、画像処理LSI114、画像処理LSI107、画像処理LSI108の順番で画像処理を行う場合のいずれについても、所望の画像処理を実現することができる。 As described above, in this embodiment, each image processing LSI is connected in a ring shape. When a packet addressed to another chip is input, the packet is transferred to the other image processing LSI and addressed to its own chip. When the packet is input, data processing is performed, and the packet including the processed data is transferred to another image processing LSI. Thereby, data can be transferred from a certain image processing LSI to an arbitrary image processing LSI. Therefore, by adding the image processing LSI 114, image processing LSI 107, image processing LSI 114, and image processing LSI 108 are processed in the order, or image processing LSI 114, image processing LSI 107, and image processing LSI 108 are processed in order. In any case, desired image processing can be realized.
　次に、本実施形態におけるパケット転送のバリエーションに関して説明する。図4A及び図4Bは、図2に示したパケット構成とは異なる他のパケット構成の一例を示している。図4Aは、画像データ専用のパケット構成の一例を示し、図4Bはアドレス付きデータ転送のパケット構成の一例を示している。 Next, variations of packet transfer in this embodiment will be described. 4A and 4B show examples of other packet configurations different from the packet configuration shown in FIG. FIG. 4A shows an example of a packet configuration dedicated to image data, and FIG. 4B shows an example of a packet configuration for data transfer with an address.
　[ID]フィールドにはIDが格納されている。[コマンド]フィールドはパケットの種別を示しており、例えば“画像データ転送モード”や“アドレス付きデータ転送モード”といった情報が[コマンド]フィールドに格納されている。[タイプ]フィールドは、コマンドの動作を補足する役割を有する。 [ID] field stores the ID. The [command] field indicates the type of packet. For example, information such as “image data transfer mode” and “data transfer mode with address” is stored in the [command] field. The [type] field has a role of supplementing the operation of the command.
　図4Aの [タイプ]フィールドには、画面のスタート位置やラインのスタート位置といった付帯情報が格納される。図4Bの[タイプ]フィールドには、“Read”、“Write”、“Read Back”といった情報が格納される。“Read”は、[アドレス]フィールドに格納されている情報が示すアドレスからデータを読み出してパケットに格納することを示している。“Write”は、パケットに格納されているデータを、[アドレス]フィールドに格納されている情報が示すアドレスに格納することを示している。“Read Back”は、“Read”が格納されているパケットに対する応答パケットに格納される情報であり、読み出されたデータが後続のパケットに格納されていることを示す。[バースト]フィールドには、このパケット以降にデータのみのパケットが何個連続で伝送されるのかを示す情報が格納される。[アドレス]フィールドには、チップ内のレジスタやメモリのアドレスを示す情報が格納される。 In the [Type] field of FIG. 4A, additional information such as the start position of the screen and the start position of the line is stored. Information such as “Read”, “Write”, and “Read Back” is stored in the [Type] field of FIG. 4B. “Read” indicates that data is read from the address indicated by the information stored in the [address] field and stored in the packet. “Write” indicates that the data stored in the packet is stored at the address indicated by the information stored in the [address] field. “Read Back” is information stored in a response packet to a packet in which “Read” is stored, and indicates that the read data is stored in a subsequent packet. In the [burst] field, information indicating how many consecutive data-only packets are transmitted after this packet is stored. In the [address] field, information indicating the addresses of registers and memories in the chip is stored.
　内視鏡装置における画像処理は、所謂パイプライン的な動作が多く、入力されるデータを順次処理することが多い。そのような場合、記憶手段にデータを一旦格納するような処理は不要であるため、パイプライン動作で処理可能な画像データを転送するためのフォーマット（図4A）では[アドレス]フィールドが存在しない。また、データ転送先も一義的に決まる場合も多く、その場合には「ID」フィールドを省略してもよい。 Image processing in an endoscope apparatus often has a so-called pipeline operation, and input data is often processed sequentially. In such a case, a process for temporarily storing data in the storage means is unnecessary, and therefore there is no [address] field in the format (FIG. 4A) for transferring image data that can be processed by the pipeline operation. In many cases, the data transfer destination is also uniquely determined. In this case, the “ID” field may be omitted.
　図5は、[タイプ]フィールドに“Write”が格納されたパケットを用いた動作の例を示している。図5は、送信側の画像処理LSIから受信側の画像処理LSIにパケット220、221、222が順次送出される例である。パケット220にはデータが格納されておらず、[ID]フィールドには任意のIDが格納され、[コマンド]フィールドには“アドレス付きデータ転送モード”が格納され、[タイプ]フィールドには“Write”が格納され、[バースト]フィールドには“2”が格納され、[アドレス]フィールドには任意のアドレスが格納されている。パケット221、222はデータのみが格納されたパケットである。 FIG. 5 shows an example of an operation using a packet in which “Write” is stored in the [Type] field. FIG. 5 shows an example in which packets 220, 221 and 222 are sequentially transmitted from the image processing LSI on the transmission side to the image processing LSI on the reception side. No data is stored in the packet 220, an arbitrary ID is stored in the [ID] field, “data transfer mode with address” is stored in the [Command] field, and “Write” is stored in the [Type] field. "," 2 "is stored in the [burst] field, and an arbitrary address is stored in the [address] field. Packets 221 and 222 are packets in which only data is stored.
　受信側の画像処理LSIにおいて、データ処理部201は、パケット220の[コマンド]フィールドから“アドレス付きデータ転送”であることを判別し、続いて[タイプ]フィールドから“Write”動作であることを知る。さらに、データ処理部201は、[バースト]フィールドから、以降の2サイクル間にわたって書き込み用のデータが送出されることを知る。パケット221、222を受信すると、データ処理部201はそれらのパケットに格納されているデータを、パケット220の[アドレス]フィールドに格納されているアドレスが示す位置に書き込む。 In the image processing LSI on the receiving side, the data processing unit 201 determines from the [command] field of the packet 220 that it is “data transfer with address”, and then determines that the operation is “Write” from the [type] field. know. Further, the data processing unit 201 knows that the data for writing is transmitted over the subsequent two cycles from the [burst] field. When the packets 221 and 222 are received, the data processing unit 201 writes the data stored in these packets in the position indicated by the address stored in the [address] field of the packet 220.
　図6では、画像処理LSI211にメモリ212が接続されている。画像処理LSI210は、図4Bのパケットを使用して、画像処理LSI211に接続されたメモリ212にアクセスできる。この場合、図5に示したパケットの例では、パケット220の[ID]フィールドにメモリ212のIDが格納され、パケット220の[アドレス]フィールドにメモリ212のアドレスが格納される。このIDは、実際にはメモリを制御するメモリコントローラの“ポート”のIDである。図16にメモリ212のメモリマップの例を示す。図16では、メモリ空間はポートＡ、Ｂ、Ｃの３つの空間に分割されており、これらのポートには格納されるデータが決められている。メモリにアクセスする際には、これらのポートに対応するID番号を指定する。 In FIG. 6, a memory 212 is connected to the image processing LSI 211. The image processing LSI 210 can access the memory 212 connected to the image processing LSI 211 using the packet in FIG. 4B. In this case, in the example of the packet shown in FIG. 5, the ID of the memory 212 is stored in the [ID] field of the packet 220, and the address of the memory 212 is stored in the [address] field of the packet 220. This ID is actually the ID of the “port” of the memory controller that controls the memory. FIG. 16 shows an example of a memory map of the memory 212. In FIG. 16, the memory space is divided into three spaces of ports A, B, and C, and data stored in these ports is determined. When accessing the memory, ID numbers corresponding to these ports are designated.
　次に、データ転送のタイミングについて説明する。
　図17に、本実施の形態における画像データと画像処理パラメータとの転送タイミングを示す。本実施形態では、すべてのデータがパケットに変換されて転送されているため、データの種別によらずに同一の転送路（図１中の伝送路109、110、111、112、113）によりデータ伝送が実現されている。そのため、データ伝送効率を高めるためには、転送タイミングの競合を減らさなければならない。本実施の形態では、画像データの無効期間（ブランキング期間）に画像処理パラメータを転送するように制御している。このように制御することで、転送路に出力するデータのアービトレーションが簡単になる。また、処理パラメータと処理対象画像フレームとの対応も明確になるため、不適切な画像処理が行われることが回避できる。
　なお、図17では垂直同期信号を独立して描画しているが、実際には同期信号はパケット内に埋め込まれて転送される。 Next, data transfer timing will be described.
FIG. 17 shows the transfer timing of image data and image processing parameters in the present embodiment. In this embodiment, since all data is converted into packets and transferred, the data is transferred by the same transfer path ( transmission paths 109, 110, 111, 112, 113 in FIG. 1) regardless of the type of data. Transmission is realized. Therefore, in order to increase the data transmission efficiency, it is necessary to reduce transfer timing contention. In the present embodiment, control is performed so that image processing parameters are transferred during an invalid period (blanking period) of image data. By controlling in this way, arbitration of data output to the transfer path is simplified. In addition, since the correspondence between the processing parameter and the processing target image frame becomes clear, inappropriate image processing can be avoided.
In FIG. 17, the vertical synchronization signal is drawn independently, but in actuality, the synchronization signal is embedded in the packet and transferred.
　次に、コネクタ105、106の実装形態に関して説明する。廉価機種においては基本的な機能のみで十分であり、その場合には拡張基板104が不要となる可能性がある。しかし、本実施形態においては、リング状の転送路が形成されている必要がある。よって、拡張基板104が接続されない場合には、何らかの手段によりコネクタ105の第1の端子と第2の端子とを短絡する必要がある。 Next, the mounting form of the connectors 105 and 106 will be described. In a low-priced model, only basic functions are sufficient, and in that case, the extension board 104 may be unnecessary. However, in the present embodiment, a ring-shaped transfer path needs to be formed. Therefore, when the extension board 104 is not connected, it is necessary to short-circuit the first terminal and the second terminal of the connector 105 by some means.
　図7は、コネクタ105の第1の端子と第2の端子とを短絡する構成の一例を示す。図7は、メイン基板103を横から見た状態を示している。コネクタ105に対して短絡器300が嵌合される。伝送路110に接続されたコネクタ105の第1の端子は短絡器300の端子301に接続され、伝送路113に接続されたコネクタ105の第2の端子は短絡器300の端子302に接続される。短絡が必要な端子301と端子302とは短絡器300内部で短絡されている。コネクタ105に短絡器300を嵌合させることでメイン基板103のみでリング状の転送路を形成することができる。 FIG. 7 shows an example of a configuration in which the first terminal and the second terminal of the connector 105 are short-circuited. FIG. 7 shows the main board 103 as viewed from the side. A short circuit 300 is fitted to the connector 105. The first terminal of the connector 105 connected to the transmission path 110 is connected to the terminal 301 of the short circuit 300, and the second terminal of the connector 105 connected to the transmission path 113 is connected to the terminal 302 of the short circuit 300. . The terminal 301 and the terminal 302 that need to be short-circuited are short-circuited inside the short-circuit device 300. By fitting the short-circuit device 300 to the connector 105, a ring-shaped transfer path can be formed only by the main substrate 103.
　次に、画像処理機能を拡張する他の例を説明する。図8は、メイン基板103にスイッチ付きコネクタ400、401を搭載した例を示している。スイッチ付きコネクタ400、401は、ばねのような機構により通常時は閉状態であるが、外部接点が接続されるとばねが押し下げられ、外部接点側に接続が切りかわる。これにより、拡張基板104が未接続の状態ではメイン基板103内でリング状の転送路が形成されているが、拡張基板104が接続されたときには拡張基板104を含むリング状の転送路が形成される。 Next, another example of extending the image processing function will be described. FIG. 8 shows an example in which connectors 400 and 401 with switches are mounted on the main board 103. The connectors with switches 400 and 401 are normally closed by a spring-like mechanism, but when an external contact is connected, the spring is pushed down and the connection is switched to the external contact side. As a result, a ring-shaped transfer path is formed in the main board 103 when the extension board 104 is not connected, but a ring-shaped transfer path including the extension board 104 is formed when the extension board 104 is connected. The
　図9は、拡張基板104を接続せずに、メイン基板103上に直接拡張機能を実装する例である。抵抗器500（抵抗値は0Ω）により通常時はリング状の伝送路が形成されている。機能を拡張する際には、未実装領域501に新たな画像処理LSIを実装し、この抵抗器500を削除すればよい。 FIG. 9 shows an example in which the extension function is directly mounted on the main board 103 without connecting the extension board 104. A ring-shaped transmission line is normally formed by the resistor 500 (resistance value is 0Ω). When expanding the function, a new image processing LSI may be mounted in the unmounted area 501 and the resistor 500 may be deleted.
　上述したように、本実施形態によれば、画像処理LSIをリング状に接続するとともに、リング状の転送路の少なくとも1点に画像処理LSIを追加できるようにし、各画像処理LSIから任意の画像処理LSIにデータを転送できるようにすることによって、各画像処理LSIが任意の順番で画像処理を行うことが可能となる。このため、所望の画像処理機能の追加を実現することができ、画像処理機能の追加に係る拡張性を高めることができる。 As described above, according to the present embodiment, the image processing LSIs are connected in a ring shape, and the image processing LSI can be added to at least one point of the ring-shaped transfer path. By enabling data to be transferred to the processing LSI, each image processing LSI can perform image processing in an arbitrary order. For this reason, the addition of a desired image processing function can be realized, and the expandability related to the addition of the image processing function can be improved.
　また、画像処理LSI間のデータ伝送をシリアル伝送にすることによって、パラレル伝送と比較して、物理的な信号本数を削減することができる。さらに、LVDS（Low Voltage Differential Signaling）のような低電圧の差動信号としてデータを伝送することで、信号伝送の高速化も可能になる。 Also, by using serial transmission for data transmission between image processing LSIs, the number of physical signals can be reduced compared to parallel transmission. Furthermore, by transmitting data as a low-voltage differential signal such as LVDS (Low Voltage Differential Differential), it is possible to increase the signal transmission speed.
　（第2の実施形態）
　次に、本発明の第2の実施形態を説明する。図10は、本実施形態による画像プロセッサの構成を示している。本実施形態による画像プロセッサは、メイン基板103と、拡張基板600、601とで構成されている。メイン基板103は画像処理LSI107、108を有し、拡張基板600は画像処理LSI116を有し、拡張基板601は画像処理LSI117を有する。拡張基板600、601は、同一の規格に基づいて作成されている。メイン基板103、拡張基板600、601のそれぞれの基板は、コネクタではなく光伝送ケーブル602、603、604により接続されている。 (Second embodiment)
Next, a second embodiment of the present invention will be described. FIG. 10 shows the configuration of the image processor according to the present embodiment. The image processor according to the present embodiment includes a main board 103 and expansion boards 600 and 601. The main substrate 103 includes image processing LSIs 107 and 108, the expansion substrate 600 includes an image processing LSI 116, and the expansion substrate 601 includes an image processing LSI 117. The extension boards 600 and 601 are created based on the same standard. The main board 103 and the extension boards 600 and 601 are connected by optical transmission cables 602, 603, and 604, not by connectors.
　本実施形態の拡張基板を任意に組み合わせることで、より効果的な機能拡張を実現することができる。また、基板間の接続をケーブルにすることにより、接続の自由度が向上し、同様な構造を持つ拡張基板を複数枚接続することができる。 よ り More effective function expansion can be realized by arbitrarily combining the expansion boards of the present embodiment. In addition, by using a cable for connection between the substrates, the degree of freedom of connection is improved, and a plurality of extension substrates having a similar structure can be connected.
　さらに、メイン基板103上の伝送路605を使用したデータ伝送を光伝送にしてもよい。光伝送は電気信号による伝送よりも伝送能力が高く、より多くのデータを伝送することができる。 Furthermore, data transmission using the transmission path 605 on the main board 103 may be optical transmission. Optical transmission has higher transmission capability than electric signal transmission, and more data can be transmitted.
　拡張基板600、601は同一の規格に基づいて作成されているが、これらに搭載されている画像処理LSIの機能は当然異なる。しかし、画像処理LSIに、内部論理を変更可能なFPGA(Field Programmable Gate Array)のようなデバイスを使用すれば、作成する基板は一種類でよい。 The expansion boards 600 and 601 are created based on the same standard, but the functions of the image processing LSI mounted on them are naturally different. However, if a device such as an FPGA (Field Programmable Gate Array) that can change the internal logic is used for the image processing LSI, only one type of substrate may be created.
　内視鏡装置では、被験者の体内に挿入される回路部分とその他の電気回路部分との間に電気的な絶縁が確保されていなくてはならない。内視鏡スコープが接続される基板と、商用電源が供給される基板との間を光伝送ケーブルで接続することで、電気的な絶縁を容易に得ることができる。したがって、医療機器に必須の電気安全性を容易に得ることができる。光伝送は電気信号による伝送よりもさらに転送能力が高いため、基板間のデータ伝送に加えて、同一基板上の画像処理LSI間のデータ伝送を光伝送にすることによって、さらなる信号数の削減と転送能力向上を実現することができる。 In an endoscopic device, electrical insulation must be ensured between a circuit portion inserted into the body of a subject and other electrical circuit portions. Electrical insulation can be easily obtained by connecting the substrate to which the endoscope scope is connected and the substrate to which commercial power is supplied with an optical transmission cable. Therefore, it is possible to easily obtain the electrical safety essential for the medical device. Since optical transmission has higher transfer capability than electrical signal transmission, in addition to data transmission between boards, data transmission between image processing LSIs on the same board is made optical transmission, which further reduces the number of signals. The transfer capability can be improved.
　（第3の実施形態）
　次に、本発明の第3の実施形態を説明する。図11は、本実施形態における画像処理LSIの接続を示している。5つの画像処理LSI700、701、702、703、704のうち隣接する2つの画像処理LSIを接続する伝送路のほかに、伝送路705、706、707が追加されている。伝送路705は画像処理LSI703、700を接続し、伝送路706は画像処理LSI704、701を接続し、伝送路707は画像処理LSI702、704を接続する。これにより、隣接する画像処理LSIとの間の伝送路だけでなく、2つ隣りの画像処理LSIとの間の伝送路も確保される。 (Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 11 shows the connection of the image processing LSI in this embodiment. Transmission lines 705, 706, and 707 are added in addition to the transmission lines that connect two adjacent image processing LSIs among the five image processing LSIs 700, 701, 702, 703, and 704. The transmission path 705 connects the image processing LSIs 703 and 700, the transmission path 706 connects the image processing LSIs 704 and 701, and the transmission path 707 connects the image processing LSIs 702 and 704. Thereby, not only a transmission path between adjacent image processing LSIs but also a transmission path between two adjacent image processing LSIs is secured.
　図12は、各画像処理LSIの構成を示している。画像処理LSIは、パケット解析部230、データ処理部232、パケット生成部233、234、パケット選択部235、236で構成されている。 FIG. 12 shows the configuration of each image processing LSI. The image processing LSI includes a packet analysis unit 230, a data processing unit 232, packet generation units 233 and 234, and packet selection units 235 and 236.
　本実施形態の画像処理LSIは2系統のデジタル画像信号の入力および出力に対応している。2系統のデジタル画像信号の一方は、入力側の一方の伝送路から入力信号237としてパケット解析部230に入力され、2系統のデジタル画像信号の他方は入力側の他方の伝送路から入力信号238としてパケット解析部230に入力される。また、2系統のデジタル画像信号の一方はパケット選択部235から出力側の一方の伝送路に出力され、2系統のデジタル画像信号の他方はパケット選択部236から出力側の他方の伝送路に出力される。 The image processing LSI of this embodiment supports input and output of two systems of digital image signals. One of the two systems of digital image signals is input to the packet analysis unit 230 as an input signal 237 from one transmission path on the input side, and the other of the two systems of digital image signals is input signal 238 from the other transmission path on the input side. Is input to the packet analysis unit 230. Also, one of the two digital image signals is output from the packet selection unit 235 to one transmission line on the output side, and the other of the two digital image signals is output from the packet selection unit 236 to the other transmission line on the output side. Is done.
　パケット解析部230は、入力信号237、238を解析し、入力信号237、238が自チップ宛の信号であるか否かを判定する。パケット解析部230は、入力信号237、238をそのままパケット選択部235にパケット信号239として出力するか、パケット選択部236にパケット信号240として出力する。また、パケット解析部230は、入力信号237、238が自チップ宛の信号であった場合には、データ処理部232に対して、入力信号237、238に含まれるデータを出力する。 The packet analysis unit 230 analyzes the input signals 237 and 238 and determines whether or not the input signals 237 and 238 are signals addressed to the own chip. The packet analysis unit 230 outputs the input signals 237 and 238 as they are to the packet selection unit 235 as the packet signal 239 or outputs them to the packet selection unit 236 as the packet signal 240. Further, when the input signals 237 and 238 are signals addressed to the own chip, the packet analysis unit 230 outputs the data included in the input signals 237 and 238 to the data processing unit 232.
　入力信号237、238のパケットの例えば[コマンド]フィールドには、転送経路に関する情報が格納されている。パケット解析部230、231は、入力信号237、238のパケットからこの情報を検出し、データ処理部232に通知するとともに、この情報に基づいて、パケット選択部235とパケット選択部236の一方にパケット信号を出力する。 In the [command] field of the packets of the input signals 237 and 238, information related to the transfer path is stored. The packet analysis units 230 and 231 detect this information from the packets of the input signals 237 and 238, notify the data processing unit 232, and based on this information, send packets to one of the packet selection unit 235 and the packet selection unit 236. Output a signal.
　データ処理部232は、入力されたデータに対して所定の画像処理を行い、処理結果のデータをパケット生成部233またはパケット生成部234に出力する。データの出力先となるパケット生成部233、234は、パケット解析部230から通知された、転送経路に関する情報に基づいて決定される。 The data processing unit 232 performs predetermined image processing on the input data, and outputs the processing result data to the packet generation unit 233 or the packet generation unit 234. The packet generation units 233 and 234 serving as data output destinations are determined based on the information related to the transfer path notified from the packet analysis unit 230.
　パケット生成部233は、入力されたデータを含むとともに所定のパケットフォーマットに成型されたパケットを生成し、パケット信号241としてパケット選択部235に出力する。パケット選択部235は、パケット解析部230からのパケット信号239と、パケット生成部233からのパケット信号241とのうちのいずれか一方を選択して、出力側の一方の伝送路に接続された次段の画像処理LSIに出力する。 The packet generation unit 233 generates a packet including the input data and molded into a predetermined packet format, and outputs the packet as a packet signal 241 to the packet selection unit 235. The packet selection unit 235 selects one of the packet signal 239 from the packet analysis unit 230 and the packet signal 241 from the packet generation unit 233, and is connected to the one transmission line on the output side. Output to a multistage image processing LSI.
　パケット生成部234は、入力されたデータを含むとともに所定のパケットフォーマットに成型されたパケットを生成し、パケット信号242としてパケット選択部236に出力する。パケット選択部236は、パケット解析部230からのパケット信号240と、パケット生成部234からのパケット信号242とのうちのいずれか一方を選択して、出力側の他方の伝送路に接続された次段の画像処理LSIに出力する。 The packet generation unit 234 generates a packet including the input data and molded into a predetermined packet format, and outputs the packet as a packet signal 242 to the packet selection unit 236. The packet selection unit 236 selects one of the packet signal 240 from the packet analysis unit 230 and the packet signal 242 from the packet generation unit 234, and is connected to the other transmission path on the output side. Output to a multistage image processing LSI.
　上記の構成により、画像処理LSIで処理されたデジタル画像信号を2系統の伝送路のうちのいずれか一方に出力し、所望の画像処理LSIにデータを転送することができる。 With the above configuration, it is possible to output a digital image signal processed by the image processing LSI to one of the two transmission paths and transfer the data to a desired image processing LSI.
　本実施形態による画像プロセッサでは、各画像処理LSIがリング状の転送路で接続されていることが重要であるが、この転送路は1系統である必要がない。本実施形態のように、複数の転送路を設けることも可能である。 In the image processor according to the present embodiment, it is important that each image processing LSI is connected by a ring-shaped transfer path, but this transfer path does not have to be one system. It is also possible to provide a plurality of transfer paths as in this embodiment.
　画像処理LSIが、内部構造を変更可能なFPGA等の論理デバイスで実現されている場合、これらの論理デバイスの回路構成を変更する処理を行っている間は、その論理デバイスではデータ転送を含むいかなる処理も行えない。本実施形態のように画像処理LSIを接続することで、任意の画像処理LSIが処理不能な状態であっても、その画像処理LSIを迂回してデータを転送することが可能となるので、データ転送を止めてしまうことを回避することができる。 When the image processing LSI is implemented with a logic device such as an FPGA whose internal structure can be changed, the logic device does not include any data transfer during the process of changing the circuit configuration of these logic devices. It cannot be processed. By connecting an image processing LSI as in this embodiment, even if any image processing LSI cannot be processed, it is possible to transfer data bypassing the image processing LSI. It is possible to avoid stopping the transfer.
　（第4の実施形態）
　次に、本発明の第4の実施形態を説明する。図13は、本実施形態による内視鏡システムの構成を示している。本実施形態による内視鏡システムは、光学情報をデジタル画像信号に変換する内視鏡スコープ800と、デジタル画像信号に所定の画像処理を施す画像プロセッサ801と、3D画像を表示するモニタ806とで構成されている。 (Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. FIG. 13 shows the configuration of the endoscope system according to the present embodiment. The endoscope system according to the present embodiment includes an endoscope scope 800 that converts optical information into a digital image signal, an image processor 801 that performs predetermined image processing on the digital image signal, and a monitor 806 that displays a 3D image. It is configured.
　本実施形態では、内視鏡スコープ800は内部に2つの撮像素子802、803を有しており、後段の３D処理との組み合わせで立体画像が構成できる。例えば、撮像素子802は左目画像用の画像信号を生成し、撮像素子803は右目画像用の画像信号を生成する。画像プロセッサ801は、画像処理LSI804とコネクタ807とを有する基板809と、画像処理LSI805とコネクタ808とを有する基板810とで構成されている。基板809が第1の実施形態のメイン基板103に対応し、基板810が第1の実施形態の拡張基板104に対応する。 In the present embodiment, the endoscope scope 800 includes two imaging elements 802 and 803 inside, and a stereoscopic image can be configured in combination with the subsequent 3D processing. For example, the image sensor 802 generates an image signal for the left eye image, and the image sensor 803 generates an image signal for the right eye image. The image processor 801 includes a substrate 809 having an image processing LSI 804 and a connector 807, and a substrate 810 having an image processing LSI 805 and a connector 808. The substrate 809 corresponds to the main substrate 103 of the first embodiment, and the substrate 810 corresponds to the expansion substrate 104 of the first embodiment.
　3D画像を取得するには、高精度な組み付け技術が必要であるが、内視鏡スコープのような省スペースが必須である機器で高精度な加工を施すのは非常に困難である。よって、加工精度のばらつきを後段の信号処理で補正する必要が生じると考えられるが、そのためには、画像処理回路の大幅な性能向上が必要となる。そこで、例えば画像処理LSI804が左目画像用の信号処理を担当し、画像処理LSI805が右目画像用の信号処理を担当すれば、たとえ画像処理LSIの性能が限界に近い状態であったとしても、3D画像に対応した画像処理が可能になる。また、3D画像の表示には、3Dに対応した専用モニタが必要であるが、専用モニタに適切な画像信号を入力するための処理も画像処理LSI805が行えばよい。 ∙ High-accuracy assembly technology is required to acquire 3D images, but it is very difficult to perform high-accuracy processing with equipment that requires space saving, such as an endoscope scope. Therefore, it is considered that it is necessary to correct variations in processing accuracy by subsequent signal processing. To that end, it is necessary to significantly improve the performance of the image processing circuit. Thus, for example, if the image processing LSI 804 is in charge of signal processing for the left eye image and the image processing LSI 805 is in charge of signal processing for the right eye image, even if the performance of the image processing LSI is close to the limit, 3D Image processing corresponding to the image becomes possible. In addition, a dedicated monitor compatible with 3D is required to display a 3D image, but the image processing LSI 805 may perform processing for inputting an appropriate image signal to the dedicated monitor.
　内視鏡スコープ800からの左右の画像信号の分配は、内視鏡スコープ800が行ってもよいし、内視鏡スコープ800と画像処理LSI804の間にIF変換用のFPGAを設け、そのFPGAが行うようにしてもよい。画像処理LSI804自体がFPGAで実現されているのであれば、画像処理LSI804が左右の画像信号の分配を行ってもよい。 Distribution of the left and right image signals from the endoscope scope 800 may be performed by the endoscope scope 800, or an IF conversion FPGA is provided between the endoscope scope 800 and the image processing LSI 804. You may make it perform. If the image processing LSI 804 itself is realized by an FPGA, the image processing LSI 804 may distribute the left and right image signals.
　（第5の実施形態）
　次に、本発明の第5の実施形態を説明する。図14は、本実施形態による内視鏡システムの構成を示している。本実施形態による内視鏡システムは、光学情報をデジタル画像信号に変換する内視鏡スコープ811と、デジタル画像信号に所定の画像処理を施す画像プロセッサ812と、画像を表示するモニタ813、814とで構成されている。画像プロセッサ812は、画像処理LSI815とコネクタ817とを有する基板819と、画像処理LSI816とコネクタ818とを有する基板820とで構成されている。基板819が第1の実施形態のメイン基板103に対応し、基板820が第1の実施形態の拡張基板104に対応する。 (Fifth embodiment)
Next, a fifth embodiment of the present invention will be described. FIG. 14 shows the configuration of the endoscope system according to the present embodiment. The endoscope system according to the present embodiment includes an endoscope scope 811 that converts optical information into a digital image signal, an image processor 812 that performs predetermined image processing on the digital image signal, and monitors 813 and 814 that display images. It consists of The image processor 812 includes a substrate 819 having an image processing LSI 815 and a connector 817, and a substrate 820 having an image processing LSI 816 and a connector 818. The substrate 819 corresponds to the main substrate 103 of the first embodiment, and the substrate 820 corresponds to the expansion substrate 104 of the first embodiment.
　本実施形態では、基本的に画像処理LSI815がモニタ813に対して画像信号を出力することで画像の表示を行っているが、この系とは別に、モニタ813の画素数よりも多い画素数のモニタ814に対して画像を出力する系を追加できる。昨今、モニタの高精細化が進んでいるが、この傾向は今後も継続すると考えられる。画像処理LSI816は、画像信号の画像サイズを、モニタ814の画面に対応したサイズに拡大して画像信号をモニタ814に出力する。よって、多画素モニタが主流になっても、画像表示を維持することができる。 In this embodiment, the image processing LSI 815 basically displays an image by outputting an image signal to the monitor 813. However, apart from this system, the image processing LSI 815 has a larger number of pixels than the number of pixels of the monitor 813. A system for outputting an image to the monitor 814 can be added. In recent years, the resolution of monitors has been increasing, but this trend is expected to continue. The image processing LSI 816 enlarges the image size of the image signal to a size corresponding to the screen of the monitor 814, and outputs the image signal to the monitor 814. Therefore, even if the multi-pixel monitor becomes mainstream, the image display can be maintained.
　本実施形態では、表示手段の多画素化に関して述べたが、その傾向は内視鏡スコープを構成する撮像素子に関しても同様である。高画素化により、画像処理LSI815の処理能力が不足する可能性があるが、その場合に画像処理LSI816を併用することで処理能力不足を解消することができる。 In the present embodiment, the display means has been described with respect to the increase in the number of pixels. The processing capability of the image processing LSI 815 may be insufficient due to the increase in the number of pixels. In this case, the shortage of processing capability can be resolved by using the image processing LSI 816 together.
　（第6の実施形態）
　次に、本発明の第6の実施形態を説明する。図15は、本実施形態による内視鏡システムの構成を示している。本実施形態による内視鏡システムは、光学情報をデジタル画像信号に変換する内視鏡スコープ821と、デジタル画像信号に所定の画像処理を施す画像プロセッサ822と、画像を記録する記録装置823、824とで構成されている。画像プロセッサ822は、画像処理LSI825とコネクタ827とを有する基板829と、画像処理LSI826とコネクタ828とを有する基板830とで構成されている。基板829が第1の実施形態のメイン基板103に対応し、基板830が第1の実施形態の拡張基板104に対応する。 (Sixth embodiment)
Next, a sixth embodiment of the present invention will be described. FIG. 15 shows the configuration of the endoscope system according to the present embodiment. The endoscope system according to the present embodiment includes an endoscope scope 821 that converts optical information into a digital image signal, an image processor 822 that performs predetermined image processing on the digital image signal, and recording devices 823 and 824 that record images. It consists of and. The image processor 822 includes a substrate 829 having an image processing LSI 825 and a connector 827, and a substrate 830 having an image processing LSI 826 and a connector 828. The substrate 829 corresponds to the main substrate 103 of the first embodiment, and the substrate 830 corresponds to the expansion substrate 104 of the first embodiment.
　本実施形態では、画像処理LSI825が記録装置823に対して画像信号を出力することで画像の記録を行っているが、この系統とは別に、記録装置823とは異なる規格に対応した記録装置824に対して画像信号を出力する系を追加できる。画像処理LSI826は、画像信号のフォーマットを、記録装置824が対応する記録フォーマットに変換して、変換後の画像信号を出力する。 In this embodiment, the image processing LSI 825 outputs an image signal to the recording device 823 to record an image, but apart from this system, the recording device 824 corresponding to a standard different from the recording device 823. A system for outputting an image signal can be added to. The image processing LSI 826 converts the format of the image signal into a recording format corresponding to the recording device 824, and outputs the converted image signal.
　画像データの記録は、アナログからデジタルに切り替わってきているが、デジタル方式には種々の規格があり、今後も新たな規格が制定されると考えられる。本実施形態により、新しい規格に対しても柔軟に対応していくことが可能になる。 Image data recording has been switched from analog to digital, but there are various standards for digital systems, and it is thought that new standards will be established in the future. This embodiment makes it possible to flexibly cope with new standards.
　以上、図面を参照して本発明の実施形態について詳述してきたが、具体的な構成は上記の実施形態に限らず、本発明の要旨を逸脱しない範囲の設計変更等も含まれる。 As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the above-described embodiments, and includes design changes and the like without departing from the gist of the present invention.
　上記によれば、第2の画像処理部が追加された場合に、第１の画像処理部および第2の画像処理部がリング状に接続されるため、どの位置に第2の画像処理部が追加された場合でも、いずれかの画像処理部で処理された画像信号のデータを任意の画像処理部に転送することが可能となる。したがって、画像処理機能の追加に係る拡張性を高めることができる。 According to the above, when the second image processing unit is added, since the first image processing unit and the second image processing unit are connected in a ring shape, the second image processing unit is located at which position. Even when added, the image signal data processed by any of the image processing units can be transferred to an arbitrary image processing unit. Therefore, it is possible to improve the expandability related to the addition of the image processing function.
　100，800，811，821・・・内視鏡スコープ
　102，801，812，822・・・画像プロセッサ（内視鏡用画像プロセッサ）
　103・・・メイン基板
　104，600，601・・・拡張基板
　105，106，807，808，817，818，827，828・・・コネクタ
　107，108，114，116，117，210，211，700，701，702，703，704，804，805，815，816，825，826・・・画像処理LSI
　115，806，813，814・・・モニタ
　200，230・・・パケット解析部
　201，232・・・データ処理部
　202，233，234・・・パケット生成部
　203，235，236・・・パケット選択部
　212・・・メモリ、300・・・短絡器
　301，302・・・端子
　400，401・・・スイッチ付きコネクタ
　500・・・抵抗器
　602，603，604・・・光伝送ケーブル
　802，803・・・撮像素子
　809，810，819，820，829，830・・・基板
　823，824・・・記録装置 100, 800, 811, 821 ... Endoscope scope 102, 801, 812, 822 ... Image processor (image processor for endoscope)
103 ... Main board 104, 600, 601 ... Expansion board 105, 106, 807, 808, 817, 818, 827, 828 ... Connector 107, 108, 114, 116, 117, 210, 211, 700 , 701,702,703,704,804,805,815,816,825,826 ... Image processing LSI
115,806,813,814 ... monitor 200,230 ... packet analysis unit 201,232 ... data processing unit 202,233,234 ... packet generation unit 203,235,236 ... packet selection Section 212 ... Memory, 300 ... Short circuit 301, 302 ... Terminal 400, 401 ... Connector with switch 500 ... Resistor 602, 603, 604 ... Optical transmission cable 802, 803 .. Image sensors 809, 810, 819, 820, 829, 830 ... Substrate 823, 824 ... Recording device

Claims (6)

  1. 　内視鏡の固体撮像素子から出力された画像信号に画像処理を施す内視鏡用画像プロセッサであって、
    　前記画像信号に対して画像処理を行う第1の画像処理部を有し、前記画像信号に対して画像処理を行う第2の画像処理部を備える場合、
    　前記第1の画像処理部は、
    　前記画像信号のデータを含むパケットが入力され、前記パケットを解析して前記パケットの宛先が前記第1の画像処理部であるか否かを判定するパケット解析部と、
    　前記パケットの前記宛先が前記第1の画像処理部であると判定された場合に、前記パケットに含まれるデータを処理するデータ処理部と、
    　前記データ処理部によって処理されたデータを含むとともに、前記第2の画像処理部を宛先に指定するパケットを生成するパケット生成部と、
    　前記パケットの前記宛先が前記第1の画像処理部でないと判定された前記パケット、および、前記パケット生成部によって生成された前記パケットのいずれか一方を選択して出力するパケット選択部と、
    　を有し、
    　前記第2の画像処理部は、
    　前記画像信号のデータを含むパケットが入力され、前記パケットを解析して前記パケットの宛先が前記第2の画像処理部であるか否かを判定するパケット解析部と、
    　前記パケットの前記宛先が前記第2の画像処理部であると判定された場合に、前記パケットに含まれるデータを処理するデータ処理部と、
    　前記データ処理部によって処理されたデータを含むとともに、前記第1の画像処理部を宛先に指定するパケットを生成するパケット生成部と、
    　前記パケットの前記宛先が前記第2の画像処理部でないと判定された前記パケット、および、前記パケット生成部によって生成された前記パケットのいずれか一方を選択して出力するパケット選択部と、
    　を有し、
    　前記第2の画像処理部が追加された場合に、前記第1の画像処理部および前記第2の画像処理部はリング状に接続される
    　内視鏡用画像プロセッサ。     An image processor for an endoscope that performs image processing on an image signal output from a solid-state imaging device of an endoscope,
    When having a first image processing unit that performs image processing on the image signal, and a second image processing unit that performs image processing on the image signal,
    The first image processing unit
    A packet analysis unit that receives data including the image signal data and analyzes the packet to determine whether the destination of the packet is the first image processing unit;
    A data processing unit that processes data included in the packet when it is determined that the destination of the packet is the first image processing unit;
    A packet generation unit that includes data processed by the data processing unit and generates a packet that specifies the second image processing unit as a destination;
    The packet that is determined that the destination of the packet is not the first image processing unit, and a packet selection unit that selects and outputs one of the packets generated by the packet generation unit;
    Have
    The second image processing unit
    A packet analysis unit that receives data including the image signal data, analyzes the packet, and determines whether the destination of the packet is the second image processing unit;
    A data processing unit that processes data included in the packet when it is determined that the destination of the packet is the second image processing unit;
    A packet generation unit that includes data processed by the data processing unit and generates a packet that specifies the first image processing unit as a destination;
    The packet that is determined that the destination of the packet is not the second image processing unit, and a packet selection unit that selects and outputs one of the packets generated by the packet generation unit;
    Have
    An endoscope image processor, wherein when the second image processing unit is added, the first image processing unit and the second image processing unit are connected in a ring shape.
  2. 　前記第1の画像処理部と前記第2の画像処理部との間の前記パケットの伝送は、シリアル通信により行われる
    請求項1に記載の内視鏡用画像プロセッサ。     2. The endoscope image processor according to claim 1, wherein transmission of the packet between the first image processing unit and the second image processing unit is performed by serial communication.
  3. 　前記第1の画像処理部と前記第2の画像処理部との間の前記パケットの伝送は、光伝送により行われる
    請求項1に記載の内視鏡用画像プロセッサ。     2. The endoscope image processor according to claim 1, wherein transmission of the packet between the first image processing unit and the second image processing unit is performed by optical transmission.
  4. 　複数の基板をさらに有し、
    　前記第1の画像処理部および前記第2の画像処理部のそれぞれは前記複数の基板のいずれかに配置され、
    　前記第1の画像処理部が配置された基板と前記第2の画像処理部が配置された基板との間の前記パケットの伝送は、光伝送により行われる
    請求項1に記載の内視鏡用画像プロセッサ。     A plurality of substrates;
    Each of the first image processing unit and the second image processing unit is disposed on any of the plurality of substrates,
    2. The endoscope for an endoscope according to claim 1, wherein transmission of the packet between the substrate on which the first image processing unit is disposed and the substrate on which the second image processing unit is disposed is performed by optical transmission. Image processor.
  5. 　前記パケットを構成するデータは、画像データ、あるいは画像処理用の設定パラメータを含む
    請求項１に記載の内視鏡用画像プロセッサ。     The endoscope image processor according to claim 1, wherein the data constituting the packet includes image data or setting parameters for image processing.
  6. 　前記パケット解析部は、入力された前記パケットを解析し、前記パケットの前記宛先が存在しないと判断した場合、入力された前記パケットを消去する
    請求項１に記載の内視鏡用画像プロセッサ。     The endoscope image processor according to claim 1, wherein the packet analysis unit analyzes the input packet and deletes the input packet when it is determined that the destination of the packet does not exist.
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