JP2001166889A - Printer and data communication method in printer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printer capable of performing two-way communications without increasing the number of input/output ports. SOLUTION: This printer is provided with three circuit modules M1, M2, M3 connected in the shape of ring and transmits packets in a single direction among the circuit modules. The circuit module M1 transmits and receives data, for example, with a host computer, the circuit module M2 performs, for example, an image processing and the circuit module M3 controls, for example printer mechanism. Since the packets are transmitted only in a single direction, data transfer rate is increased and pseudo two-way communications are enabled. In addition, data are transmitted only in a single direction, the number of input/ output ports is reduced. Furthermore, since packet communication is performed among the respective modules, desired data is surely transmitted to the desired module.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer incorporating a plurality of circuit modules, and more particularly to a technique for performing high-speed data communication between circuit modules.

[0002]

2. Description of the Related Art A printer control circuit for controlling a printer is usually composed of a plurality of circuit modules. For example, FIG. 9 shows a conventional example of a printer control circuit including an IF module 11 for transmitting and receiving signals to and from a host computer, an image processing module 12 for performing image processing, and a mechanical control module 13 for controlling a mechanical part of the printer. Is shown. These modules are separate CPUs
And ASICs, and are usually configured on separate boards.

Each module has an input / output port, and sends and receives signals to and from adjacent modules. For example, in the case of FIG. 9, signals are transmitted and received between the IF module 11 and the image processing module 12, and signals are transmitted and received between the image processing module 12 and the mechanical control module 13.

[0004]

As shown in FIG. 9, when data is transmitted / received in two directions between two adjacent input / output ports, the input / output ports of the input / output ports are compared with the case where data is transmitted in one direction. Although the number can be reduced, there is a problem that the data transmission speed is reduced.

Further, when data transmission and reception are performed by connecting a plurality of circuit modules to a bidirectional bus, it takes time until communication preparation is completed, and a protocol for controlling the bus becomes troublesome. However, there is a problem that data cannot be transmitted quickly.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a printer capable of performing high-speed data communication without increasing the number of input / output ports and a data communication method in the printer. Is to provide.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a printer according to the first aspect of the present invention is provided with three or more circuit modules connected in a ring and capable of transmitting data in one direction. The three or more circuit modules each include a data channel unit for transmitting and receiving print data;
It has a control channel unit for transmitting and receiving print control data and a connector for transmitting and receiving the print data and the print control data to and from another circuit module, and transmits and receives at least the print control data in the form of packets.

According to the first aspect of the present invention, since three or more circuit modules inside the printer are connected in a ring and data is transmitted in one direction, the number of input / output ports is increased without increasing the number of input / output ports.
High-speed transmission becomes possible.

According to the second aspect of the present invention, a broadcast packet is transmitted from the master circuit module to allocate one of the three or more circuit modules to the master circuit module and the other to the slave circuit module. , Can control all slave circuit modules.

According to the third aspect of the present invention, the master circuit module determines the logical address of each slave circuit module based on the identification information transmitted by each slave circuit module, and notifies each slave circuit module of the logical address. The module can easily communicate with other circuit modules using this logical address.

According to the fourth aspect of the present invention, when the logical address information transmitted by the master circuit module returns to itself, all the slave circuit modules determine that the logical address information has been received and transmit the communication permission signal by broadcast. Thus, the procedure up to the start of communication can be simplified.

According to the fifth aspect of the present invention, before starting communication, the transmission source circuit module receives the communication preparation completion signal or the communication disable signal from the transmission destination circuit module, so that a communication error can be prevented beforehand. .

In the present invention, when both the communication preparation completion signal and the communication disable signal are received, it is determined that communication is impossible, so that the communication is performed even if the communication preparation of the destination is not completed. No more problems.

According to the seventh aspect of the invention, when neither the communication preparation completion signal nor the communication disable signal is received, the communication apparatus is set on standby, so that the communication can be reliably performed even if the communication speed is slightly reduced.

According to the present invention, the data channel section and the control channel section are selected by the address lines in the transfer bus, so that the print data and the print control data can be transmitted on the same transfer bus. , The number of buses can be reduced.

According to the ninth aspect of the present invention, the circuit module of the transmission source and the circuit module of the transmission destination operate asynchronously, so that processing for synchronization is not required, and the circuit configuration can be simplified.

According to the tenth aspect of the present invention, in the packet,
Since the logical address information and the command information of the transmission destination and the transmission source are included, a desired command can be reliably delivered to a desired transmission destination.

An invention according to claim 11 is a data communication method in a printer comprising three or more circuit modules connected in a ring and capable of transmitting data in one direction, wherein said three or more circuit modules are provided. Respectively transmit and receive print data via a data channel unit connected to a connector, transmit and receive print control data via a control channel unit connected to the connector, and transmit at least the print control data in the form of packets. To send and receive.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a printer according to the present invention will be specifically described with reference to the drawings.

FIG. 1 is a schematic structural view of the inside of a printer according to the present invention. The printer of FIG. 1 includes three circuit modules M1, M2, and M3, and these circuit boards M1
M3 is connected in a ring shape and data transmission is performed only in one direction.

The circuit module M1 performs data transmission with, for example, a host computer, and the circuit module M2 performs image processing on, for example, print data sent from the host computer to generate print data. The circuit module M3 controls, for example, a printer mechanism.

Each of the circuit modules M1, M2, M3 has a data channel 1 for transmitting data, a control channel 2 for transmitting control information, and a connector 3 for inputting and outputting data and control information.

A transfer bus 4 is connected between adjacent connectors 3. The bus width of the transfer bus 4 can be selected from, for example, 8 bits, 16 bits, and 32 bits. The transfer bus 4 is provided with one address line. By the logic of the address line, data for the data channel 1 and data for the control channel 2 can be distinguished.

Asynchronous communication is performed between the circuit modules. Therefore, the system clock of the source circuit module and the system clock of the destination circuit module may be asynchronous with each other.

The communication speed is adjusted to the system clock having the lower frequency among the system clocks of the circuit modules of the transmission source and the transmission destination. Further, two clocks of the system clock are required to transfer one packet of data. Therefore, if the system clocks of the source and destination circuit modules are both 40 MHz, the transfer rate is 20 MHz.

In the data channel 1 of FIG. 1, print data is transferred. The control channel 2 transfers control information such as a printer control command, a printer maintenance command, and a communication control command.

Even if the destination circuit module cannot receive the print data of the source circuit module for some reason, it is possible to switch to the control channel 2 and continue the command communication without interrupting the communication. .

The priority of the command flowing through the control channel 2 is set higher than that of the print data flowing through the data channel 1. Therefore, when both the print data to the data channel 1 and the command to the control channel 2 exist, the transmission source circuit module gives priority to the command to the control channel 2 and transmits the command.

The signals transmitted via the transfer bus 4 include:
A signal transmitted from the circuit module of the transmission source to the circuit module of the transmission destination and a signal transmitted from the circuit module of the transmission destination to the circuit module of the transmission source are included.

The signals to the destination include an address signal ADxx designating a destination address and a transmission data signal DATA
xx and a strobe signal STBxx for notifying data transmission. In addition, among the signals to the transmission source, an acknowledge signal (communication preparation completion signal) ACKxx for notifying that data reception preparation is completed, and a nack signal (communication for notifying that data reception preparation is not completed). Impossible signal) NACK
xx exists.

As shown in FIG. 1, each circuit module includes:
Since the connection is made in a ring shape, the packet can be sent to all circuit modules even if the packet is transmitted in one direction. The transmitted packet makes a circuit between each circuit module and returns to the original circuit module. As a result, the transmission source circuit module recognizes that the packet has been transmitted to all the other circuit modules. In this case, in order to avoid transmitting the same packet many times, it is desirable that the source packet discard the packet that has returned to itself.

Each circuit module may simply deliver the packet, or may process the received packet and transmit it to the next circuit module. In the latter case, for example, the circuit module M1 transmits a packet including a printer command to the circuit module M2, and the circuit module M2 interprets the command in the packet to convert the command into dot information, and converts the packet including the dot information into a packet. The signal is transmitted to the circuit module M3. The circuit module M3 controls the ink ejected from the print head of the printer based on the dot information included in the packet.

As described above, by arranging each circuit module in accordance with the processing order of the printer, the processing result of each circuit module can be transmitted in the form of a packet to the circuit module which performs the next processing, and the printing processing can be performed efficiently. it can.

Various forms can be applied to the form of the transfer bus between the circuit modules, and a general-purpose bus such as a PCI bus or a dedicated bus may be used.
Alternatively, a USB terminal or an IEEE1394 terminal may be used as the connector 3 to transmit and receive data conforming to the USB and IEEE1394 standards.

In the case of this embodiment, since data flows only in one direction, the configuration of the input / output ports can be simplified and the data transmission speed can be improved. That is, when transmitting and receiving data in both directions, a bidirectional buffer must be provided, which complicates the configuration, and the time required for data switching control limits the data transmission speed. However, if data transmission is performed in one direction as in the present embodiment, data transmission can be performed at high speed as much as control of data switching is unnecessary.

To further improve the data transmission speed, the connection order of the circuit modules may be determined according to the amount of data transmitted and received between the circuit modules. For example, when the circuit module M1 is an IF circuit module, the circuit module M2 is an image processing circuit module, and the circuit module M3 is a mechanical control circuit module, the data transmission amount from the circuit module M1 to the circuit module M2 and the circuit module M2 from the circuit module M2 While the amount of data transmitted to M3 is large, the amount of data transmitted from circuit module M2 to circuit module M1 and the amount of data transmitted from circuit module M3 to circuit module M2 are small.

Therefore, as shown in FIG. 1, if the circuit modules M1, M2, and M3 are connected in this order, data can be transmitted most efficiently, and the average data transmission speed can be improved.

FIG. 2 is a timing waveform diagram of each part in the circuit module. FIG. 2A is a timing waveform diagram when the address signal ADxx changes, and FIG. 2B is a timing waveform diagram when the address signal ADxx does not change. It is a timing waveform diagram.

As shown in FIG. 2A, the transmission source circuit module transmits the address signal ADxx and the data signal DATAxx to the transmission destination circuit module while the acknowledge signal ACKxx is at the low level, Signal STBxx
To a high level. After the strobe signal STBxx goes high, when the reception preparation is completed, the circuit module at the transmission destination sets the acknowledge signal ACKxx high.

When the address signal ADxx does not change, as shown in FIG. 2 (b), the circuit module of the transmission source operates while the acknowledge signal ACKxx is at the low level.
The address signal ADxx and the data signal DATAxx are transmitted to the transmission source circuit module, and the strobe signal STBxx is set to a high level.

On the other hand, FIG. 3 is a timing waveform chart when the transmission source circuit module cannot receive data for some reason. In this case, the destination circuit module is
When the transmission source circuit module sets the strobe signal STBxx to the high level, the nack signal NACKxx is set to the high level (time t1 in FIG. 3). As a result, the source circuit module recognizes that the destination circuit module cannot receive data.

In this case, the source circuit module must hold data to the destination until the next output opportunity. The source circuit module may retransmit the same data by specifying the same address as the circuit module that could not be transmitted, or retransmit the same data by specifying another address corresponding to another circuit module. Is also good.

FIG. 4 is a timing waveform diagram when the circuit module of the transmission destination does not return the acknowledge signal ACKxx or the acknowledgment signal NACKxx. For example, when the circuit module of the transmission destination is in a sleep state, neither the acknowledge signal ACKxx nor the NACK signal NACKxx may be returned to the circuit module of the transmission source. In such a case, the transmission source circuit module continues to hold the strobe signal STBxx at a high level as shown in FIG.

FIG. 5 is a timing waveform chart when the transmission source circuit module simultaneously receives the acknowledge signal ACKxx and the acknowledgment signal NACKxx. In such a case,
The transmission source circuit module gives priority to the NACK signal NACKxx, and determines that the transmission destination circuit module has failed to receive data.

Next, the format of data transmitted via the control channel 2 will be described. As described above, in the present embodiment, a packet is transmitted to the control channel 2.

FIG. 6 is a flowchart showing a control procedure of the acknowledge signal ACKxx and the acknowledgment signal NACKxx shown in FIGS. First, the circuit module of the transmission source determines whether or not only the acknowledge signal ACKxx has been received (step S1). If only ACKxx is received, it is determined that the communication preparation of the transmission destination is completed, and data transmission to the transmission destination is performed (step S2).

If the determination in step S1 is NO, it is determined whether only the NACK signal NACKxx has been received (step S3). If only NACKxx is received, it is determined that the transmission destination cannot communicate, and processing for interrupting data transmission to the transmission destination is performed (step S4).

If the determination in step S3 is NO, it is determined whether the acknowledgment signal ACKxx and the acknowledgment signal NACKxx have been received simultaneously (step S5). This judgment is YE
If S, it is determined that the transmission destination cannot communicate, and step S
4 is performed.

If the determination in step S5 is NO, it is determined that neither the acknowledge signal ACKxx nor the acknowledgment signal NACKxx has been received, and a standby process is performed (step S5).
6).

FIG. 7 shows the data structure of a packet. As shown in the drawing, the packet is transmitted to the destination address area 2.
1, a source address area 22, and a data length area 23
And a command area 24.

The destination address area 21 is an area indicating the logical address of the circuit module of the packet destination.
This area 21 is further divided into a broadcast logical address area for specifying all circuit modules and an individual logical address area for specifying the logical address of a specific circuit module.

The source address area 22 is an area indicating the logical address of the circuit module of the packet source.
The data length area 23 is an area indicating the data length (unit byte) of the command area, and an arbitrary command is stored in this area.

When transmitting a command to another circuit module, each circuit module needs to detect whether or not the destination circuit module is actually mounted on the data communication device. Further, when a circuit module at the transmission destination is mounted, it is necessary to detect the logical address of the circuit module at the transmission destination and its own logical address as the transmission source.

For this reason, the present data communication device checks the actually mounted circuit module when the power is turned on,
The logical addresses of these circuit modules are confirmed.

The communication method between the circuit modules is roughly divided into broadcast command communication and peer communication.
There are two, to-peer command communication. The types of commands to be communicated are mainly printer control commands, printer maintenance commands, and communication control commands between circuit modules.

FIG. 8 is a flowchart showing a data communication procedure. In order to perform data communication between circuit modules, it is necessary to determine a circuit module to be a master (hereinafter, referred to as a master circuit module). Therefore, immediately after the power of the data communication device is turned on, the state of the dip switch and the like is checked to detect a circuit module to be a master (step S11). Note that all circuit modules other than the master are handled as slaves (hereinafter, referred to as slave circuit modules).

Next, the master circuit module transmits a broadcast packet (step S12).
The slave circuit module receiving this packet transmits its own ID number to the master circuit module (step S13).

When receiving the ID numbers from all the slave circuit modules, the master circuit module assigns a logical address to each slave circuit module (step S14).

Next, the master circuit module broadcasts a logical address list in which all logical addresses assigned to each slave circuit module are recorded as a packet (step S15).

Each slave circuit module receives this packet, recognizes the logical address assigned to itself and the logical addresses of all other circuit modules,
These pieces of information are stored in the module (step S1).
6).

The master circuit module performs step S1
When the packet transmitted in step 4 returns, it recognizes that this packet has been transmitted to all slave circuit modules, and broadcasts a communication permission packet for permitting packet communication to each slave circuit module (step S17). .

Upon receiving this packet, the slave circuit module performs communication as required (step S1).
8).

In the above-described embodiment, an example in which the present invention is applied to a circuit module of a printer has been described. However, the present invention can be widely applied to purposes other than a printer.
In FIG. 1, three circuit modules M1, M2, M
Although an example in which 3 is connected in a ring shape has been described, the number of circuit modules connected in a ring shape is not particularly limited.

In the above-described embodiment, an example in which a packet is transmitted via the control channel 2 has been described, but a packet may be transmitted also on the data channel 1.

[0065]

As described in detail above, according to the present invention, three or more circuit modules inside a printer are connected in a ring shape to transmit packets only in one direction.
High-speed data transmission can be performed between circuit modules without increasing the number of input / output ports. Further, since the transmitted packet passes through all the circuit modules, the packet can be delivered not only to a specific circuit module but also to a plurality of circuit modules.

Further, if the connection order of each circuit module is set in consideration of the amount of data transmission between each circuit module, data can be transmitted efficiently.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a data communication device according to the present invention.

2A is a timing waveform chart when an address signal ADxx changes, and FIG. 2B is a timing waveform chart when an address signal ADxx does not change.

FIG. 3 is a timing waveform chart when a transmission source circuit module cannot receive data for some reason.

FIG. 4 is a diagram showing an acknowledge signal AC when a transmission destination circuit module is used.
FIG. 11 is a timing waveform chart when neither Kxx nor a NACKxx is returned.

FIG. 5 is a diagram showing an acknowledge signal AC when a circuit module of a transmission source is used.
FIG. 6 is a timing waveform chart when Kxx and a NACK signal NACKxx are received at the same time.

FIG. 6 is a flowchart showing a control procedure of the acknowledge signal ACKxx and the acknowledgment signal NACKxx shown in FIGS. 2 to 5;

FIG. 7 is a diagram showing a data configuration of a packet.

FIG. 8 is a flowchart showing a data communication procedure.

FIG. 9 is a diagram showing a conventional example of a printer control circuit.

[Explanation of symbols]

 M1, M2, M3 module 11 IF module 12 Image processing module 13 Mechanical module

Claims (11)

[Claims] 1. A printer comprising three or more circuit modules connected in a ring and capable of transmitting data in one direction, wherein each of the three or more circuit modules transmits and receives print data. And a control channel unit for transmitting and receiving print control data, and a connector for transmitting and receiving the print data and the print control data to and from another circuit module, and at least transmitting and receiving the print control data in the form of a packet. A printer characterized in that: 2. One of the three or more circuit modules is assigned to a master circuit module, and all others are assigned to slave circuit modules. The master circuit module is assigned to all other slave circuit modules. The printer according to claim 1, wherein the printer transmits a broadcast packet to the slave circuit module to identify the slave circuit module that can communicate. 3. The slave circuit module includes: identification information transmitting means for transmitting identification information for identifying itself to the master circuit module; and self-logical address information transmitted from the master circuit module and another slave circuit. Address storage means for storing logical address information of the module, and wherein the master circuit module is configured to store the logical address information for each of the slave circuit modules based on the identification information transmitted from all of the slave circuit modules. 3. The printer according to claim 2, further comprising address setting means for assigning a logical address, and address transmitting means for broadcasting the assigned logical address to all of the slave circuit modules. 4. The master circuit module has permission signal transmission means for broadcasting a communication permission signal to all of the slave circuit modules when the data broadcast transmitted by the address transmission means returns to itself. 4. The printer according to claim 3, wherein each of the slave circuit modules performs communication with another circuit module as needed upon receiving the communication permission signal. 5. 5. A circuit module of a transmission destination which has received a notification signal indicating that data communication is to be performed from a circuit module of a transmission source, when the communication preparation is completed, sends a communication preparation completion signal to the circuit module of the transmission source. 5. A communication status notifying means for returning a communication failure signal to the circuit module of the transmission source when communication is impossible.
Printer according to. 6. The transmission source circuit module, when receiving both the communication preparation completion signal and the communication disable signal from the transmission destination circuit module, determines that communication is not possible, and determines that the transmission is not possible. 6. The printer according to claim 5, further comprising communication interruption means for interrupting communication with the previous circuit module. 7. The communication source circuit module, when receiving neither the communication preparation completion signal nor the communication disable signal from the transmission destination circuit module, transmits the communication preparation completion signal and the communication preparation signal. 7. The printer according to claim 5, further comprising a standby unit that waits until one of the disable signal is received. 8. A transfer bus connected to the connector in the source circuit module and the connector in the destination circuit module has an address for selecting the data channel unit and the control channel unit. The printer according to any one of claims 1 to 7, wherein a line is provided. 9. The circuit module of the transmission source and the circuit module of the transmission destination operate asynchronously, and when there is a difference between the operation frequencies of the system clocks of the two circuit modules, the circuit modules are synchronized with the slower system clock. The printer according to any one of claims 1 to 8, wherein data communication is performed by performing the data communication. 10. The packet includes logical address information of a destination circuit module, logical address information of a source circuit module, information indicating a data length of print control data, and command information corresponding to the print control data. The printer according to any one of claims 1 to 9, comprising: 11. A data communication method in a printer comprising three or more circuit modules connected in a ring and capable of transmitting data in one direction, wherein the three or more circuit modules each have a connector. Transmitting and receiving print data via a connected data channel unit, transmitting and receiving print control data via a control channel unit connected to the connector, and transmitting and receiving at least the print control data in a packet form. Data communication method.