WO2013108301A1 - 薄膜トランジスタ - Google Patents
薄膜トランジスタ Download PDFInfo
- Publication number
- WO2013108301A1 WO2013108301A1 PCT/JP2012/003978 JP2012003978W WO2013108301A1 WO 2013108301 A1 WO2013108301 A1 WO 2013108301A1 JP 2012003978 W JP2012003978 W JP 2012003978W WO 2013108301 A1 WO2013108301 A1 WO 2013108301A1
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- WIPO (PCT)
- Prior art keywords
- thin film
- film transistor
- oxide semiconductor
- electrode
- semiconductor layer
- Prior art date
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- 239000010409 thin film Substances 0.000 title claims abstract description 50
- 239000010408 film Substances 0.000 claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 7
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- 229910052725 zinc Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 34
- 238000000034 method Methods 0.000 description 19
- 238000004519 manufacturing process Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 235000006408 oxalic acid Nutrition 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/124—Insulating layers formed between TFT elements and OLED elements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
Definitions
- the present invention relates to a thin film transistor used in a liquid crystal display device or an organic EL display device.
- a thin film transistor including an oxide semiconductor film has a channel etching stopper structure in order to suppress damage to the oxide semiconductor when a source electrode and a drain electrode are formed.
- a SiO 2 thin film is used for the channel etching stopper in order to prevent the oxide semiconductor from changing characteristics due to the reducing gas when the channel etching stopper is formed.
- the present invention includes a gate electrode formed on a substrate, a gate insulating film formed so as to cover the gate electrode, an oxide semiconductor layer formed on the gate insulating film, and an end portion of the oxide semiconductor layer.
- a source electrode and a drain electrode which are formed so as to cover; and a passivation film which is formed so as to cover the source and drain electrodes and the oxide semiconductor layer.
- the passivation film is made of an insulating film material that can attenuate light having a wavelength of 450 nm or less.
- FIG. 1 is a perspective view of an EL display device according to an embodiment.
- FIG. 2 is a perspective view illustrating an example of a pixel bank of an EL display device according to an embodiment.
- FIG. 3 is an electric circuit diagram showing a circuit configuration of a pixel circuit of a thin film transistor in one embodiment.
- FIG. 4 is a schematic cross-sectional view showing a thin film transistor in one embodiment.
- FIG. 5A is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor in one embodiment.
- FIG. 5B is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor in one embodiment.
- FIG. 5C is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor in one embodiment.
- FIG. 5A is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor in one embodiment.
- FIG. 5B is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor in one embodiment.
- FIG. 5D is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor in one embodiment.
- FIG. 5E is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor in one embodiment.
- FIG. 5F is a schematic cross-sectional view for illustrating the method for manufacturing the thin film transistor in one embodiment.
- FIG. 5G is a schematic cross-sectional view for explaining the method for manufacturing the thin film transistor in one embodiment.
- FIG. 1 is a perspective view of an EL display device according to an embodiment
- FIG. 2 is a perspective view illustrating an example of a pixel bank of the EL display device according to the embodiment
- FIG. 3 is a circuit of a pixel circuit of a thin film transistor according to the embodiment. It is a figure which shows a structure.
- the EL display device is a thin film transistor array device 1 in which a plurality of thin film transistors 10 or thin film transistors 11 are arranged from the lower layer, an anode 2 as a lower electrode, and a light emitting layer made of an organic material. It is constituted by a laminated structure of a light emitting part composed of an EL layer 3 and a cathode 4 which is a transparent upper electrode. The light emission part is controlled to emit light by the thin film transistor array device 1.
- the light emitting part has a configuration in which an EL layer 3 is disposed between an anode 2 and a cathode 4 which are a pair of electrodes.
- a hole transport layer is laminated between the anode 2 and the EL layer 3, and an electron transport layer is laminated between the EL layer 3 and the transparent cathode 4.
- the thin film transistor array device 1 has a plurality of pixels 5 arranged in a matrix.
- the thin film transistor array device 1 includes a plurality of gate wirings 7 arranged in a row, a plurality of signal wirings arranged in a row so as to intersect the gate wirings 7, and a parallel to the source wiring 8. And a plurality of power supply wires 9 (not shown in FIG. 1).
- the gate wiring 7 connects the gate electrode 10g of the thin film transistor 10 operating as a switching element included in each pixel circuit 6 for each row.
- the source wiring 8 connects the source electrodes 10 s of the thin film transistors 10 that operate as switching elements included in each of the pixel circuits 6 for each column.
- the power supply wiring 9 connects the drain electrode 11d of the thin film transistor 11 operating as a driving element included in each of the pixel circuits 6 for each column.
- each pixel 5 of the EL display device is configured by sub-pixels 5R, 5G, and 5B of three colors (red, green, and blue), and these sub-pixels 5R, 5G, and 5B are displayed on the display surface. It is formed so as to be arranged in a matrix on the top (hereinafter referred to as a sub-pixel column).
- the sub-pixels 5R, 5G, and 5B are separated from each other by the bank 5a.
- the bank 5a is formed such that a ridge extending in parallel with the gate wiring 7 and a ridge extending in parallel with the source wiring 8 intersect each other.
- subpixels 5R, 5G, and 5B are formed in a portion surrounded by the protrusions (that is, an opening of the bank 5a).
- the anode 2 is formed for each of the sub-pixels 5R, 5G, and 5B on the interlayer insulating film on the thin film transistor array device 1 and in the opening of the bank 5a.
- the EL layer 3 is formed for each of the sub-pixels 5R, 5G, and 5B on the anode 2 and in the opening of the bank 5a.
- the transparent cathode 4 is continuously formed on the plurality of EL layers 3 and the banks 5a so as to cover all the subpixels 5R, 5G, and 5B.
- a pixel circuit 6 is formed for each of the sub-pixels 5R, 5G, and 5B.
- Each of the sub-pixels 5R, 5G, and 5B and the corresponding pixel circuit 6 are electrically connected by a contact hole and a relay electrode that will be described later.
- the subpixels 5R, 5G, and 5B have the same configuration except that the emission color of the EL layer 3 is different. Therefore, in the following description, the sub-pixels 5R, 5G, and 5B are all referred to as pixels 5 without being distinguished.
- the pixel circuit 6 includes a thin film transistor 10 that operates as a switch element, a thin film transistor 11 that operates as a drive element, and a capacitor 12 that stores data to be displayed in the corresponding pixel.
- the thin film transistor 10 includes a gate electrode 10g connected to the gate wiring 7, a source electrode 10s connected to the source wiring 8, a drain electrode 10d connected to the gate electrode 11g of the capacitor 12 and the thin film transistor 11, and a semiconductor film (FIG. Not shown).
- the thin film transistor 10 stores the voltage value applied to the source wiring 8 in the capacitor 12 as display data.
- the thin film transistor 11 includes a gate electrode 11g connected to the drain electrode 10d of the thin film transistor 10, a drain electrode 11d connected to the power supply wiring 9 and the capacitor 12, a source electrode 11s connected to the anode 2, and a semiconductor film (not shown). Z).
- the thin film transistor 11 supplies a current corresponding to the voltage value held by the capacitor 12 from the power supply wiring 9 to the anode 2 through the source electrode 11s. That is, the EL display device having the above configuration employs an active matrix system in which display control is performed for each pixel 5 located at the intersection of the gate line 7 and the source line 8.
- FIG. 4 is a schematic cross-sectional view showing a thin film transistor according to an embodiment.
- a gate electrode 22 is formed on a substrate 21, and a gate insulating film 23 is formed so as to cover the gate electrode 22.
- An oxide semiconductor layer 24 is formed in an island shape over the gate insulating film 23.
- a source electrode 25s and a drain electrode 25d are formed so as to cover the end portion of the oxide semiconductor layer 24.
- a passivation film 26 is formed on the source electrode 25s, the drain electrode 25d, and the oxide semiconductor layer 24 to insulate them from the electrode of the light emitting layer formed as an upper layer so as to cover them.
- a contact hole is formed in the passivation film 26 and is electrically connected to the electrode of the upper light emitting layer through the contact hole.
- a glass substrate is used as the substrate 21.
- a resin substrate for example, a metal such as Ti, Mo, W, Al, or Au, or a conductive oxide such as ITO (indium tin oxide) can be used.
- a metal such as Ti, Mo, W, Al, or Au
- a conductive oxide such as ITO (indium tin oxide)
- an alloy such as MoW can also be used.
- a metal laminate having good adhesion to the oxide for example, a metal sandwiching Ti, Al, Au, or the like can be used as the electrode.
- an oxide thin film such as a silicon oxide film or a hafnium oxide film, a nitride film such as a silicon nitride film, a single layer film or a laminated film of a silicon oxynitride film, or the like is used.
- an oxide semiconductor containing In, Zn, and Ga is used for the oxide semiconductor layer 24, but it is more preferable if it is amorphous.
- a method for forming the oxide semiconductor layer 24 a DC sputtering method, a high frequency sputtering method, a plasma CVD method, a pulse laser deposition method, an ink jet printing method, or the like can be used.
- the film thickness is preferably 10 nm to 150 nm. When the film thickness is less than 10 nm, pinholes are likely to occur, and when the film thickness is more than 150 nm, there is a problem that the leakage current at the time of turning off the transistor characteristics and the subthreshold swing value (S value) increase. .
- a metal such as Ti, Mo, W, Al, Au, or a conductive oxide such as ITO can be used.
- a metal laminate having good adhesion to the oxide for example, a metal sandwiching Ti, Al, Au, or the like can be used as the electrode.
- a resin-coated photosensitive insulating film material including silsesioxene, acrylic, and siloxane that can attenuate light having a wavelength of 450 nm or less is used as the passivation film 26 . Accordingly, a structure in which light having a wavelength of 450 nm or less is not irradiated on the channel portion of the oxide semiconductor layer 24 can be obtained. It was confirmed by experiments that the photosensitive insulating material should have a light transmittance of 20% or less for light having a wavelength of 450 nm or less.
- the passivation film 26 can be processed by photolithography, and a processing process such as a dry etching method or a wet etching method is not necessary, so that the cost can be reduced. It becomes.
- the passivation film 26 may be a laminated film of the photosensitive insulating material and the inorganic insulating material.
- silicon oxide, aluminum oxide, titanium oxide, or the like is used as the inorganic insulating material.
- CVD, sputtering, ALD, or the like is used for film formation.
- a gate electrode 22 is processed into a desired gate shape on a substrate 21, and then a gate insulating film 23 is formed so as to cover the gate electrode 22. After that, the oxide semiconductor layer 24 is formed over the gate insulating film 23.
- a resist mask 27 is formed on the oxide semiconductor layer 24.
- the oxide semiconductor layer 24 is patterned as shown in FIG. 5C.
- a wet etching method is used for processing the oxide semiconductor layer 24.
- an acid mixed solution such as phosphoric acid, nitric acid, and acetic acid, oxalic acid, hydrochloric acid, and the like are used.
- the resist mask 27 is removed.
- a wet etching process using a resist stripping solution, a dry etching process using O 2 plasma, or the like is used.
- a resist mask 28 is formed.
- the electrode layer 25 is patterned using the resist mask 28 to process the source electrode 25s and the drain electrode 25d, and then the resist mask 28 is removed.
- a wet etching method is used for processing the source electrode 25s and the drain electrode 25d.
- the oxide semiconductor layer 24 is heat-treated at 150 to 450 ° C. for 0.5 to 1200 minutes. By performing the heat treatment, the contact resistance value with the source electrode 25s and the drain electrode 25d can be reduced, and the characteristics of the oxide semiconductor layer 24 can be stabilized.
- a passivation film 26 is formed. As described above, contact holes are formed in the passivation film 26 in order to form electrical contacts with the source electrode 25 s and the drain electrode 25 d and electrical contact with the gate electrode 22.
- the contact hole can be formed by photolithography using a photosensitive material for the passivation film 26.
- a resin-coated photosensitive insulating film material that can attenuate light having a wavelength of 450 nm or less is used as the passivation film 26 on the oxide semiconductor layer 24. Accordingly, a structure in which light having a wavelength of 450 nm or less is not irradiated on the channel portion of the oxide semiconductor layer 24 can be formed, and the thin film transistor 10 or the thin film transistor 11 using an oxide semiconductor that does not generate photoconduction can be formed. Become. Accordingly, it is possible to provide the thin film transistor 10 or the thin film transistor 11 having desired transistor characteristics while suppressing variation in characteristics.
- the present invention is useful for stabilizing characteristics of a thin film transistor using an oxide semiconductor.
Abstract
Description
10d ドレイン電極
10g ゲート電極
10s ソース電極
11 薄膜トランジスタ
11d ドレイン電極
11g ゲート電極
11s ソース電極
21 基板
22 ゲート電極
23 ゲート絶縁膜
24 酸化物半導体層
25d ドレイン電極
25s ソース電極
26 パッシベーション膜
Claims (2)
- 基板上に形成したゲート電極と、このゲート電極を覆うように形成したゲート絶縁膜と、このゲート絶縁膜上に形成した酸化物半導体層と、この酸化物半導体層の端部を覆うように形成したソース電極及びドレイン電極と、前記ソース電極及びドレイン電極と前記酸化物半導体層上にこれらを覆うように形成したパッシベーション膜とを有する薄膜トランジスタであって、前記パッシベーション膜は、450nm以下の波長の光を減衰させることが可能な絶縁膜材料により構成した薄膜トランジスタ。
- 前記酸化物半導体層は、In、Zn及びGaを含む酸化物半導体により構成した請求項1に記載の薄膜トランジスタ。
Priority Applications (3)
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KR1020137026886A KR20130133289A (ko) | 2012-01-20 | 2012-06-19 | 박막 트랜지스터 |
CN201280018902.7A CN103493187A (zh) | 2012-01-20 | 2012-06-19 | 薄膜晶体管 |
US13/973,694 US20130334526A1 (en) | 2012-01-20 | 2013-08-22 | Thin film transistor |
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US13/973,694 Continuation US20130334526A1 (en) | 2012-01-20 | 2013-08-22 | Thin film transistor |
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US (1) | US20130334526A1 (ja) |
JP (1) | JPWO2013108301A1 (ja) |
KR (1) | KR20130133289A (ja) |
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KR20150091265A (ko) * | 2014-01-31 | 2015-08-10 | 고쿠리츠다이가쿠호징 나라 센탄카가쿠기쥬츠 다이가쿠인 다이가쿠 | 보호막을 구비한 박막 트랜지스터 기판 및 이의 제조 방법 |
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KR102408938B1 (ko) * | 2015-07-17 | 2022-06-14 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 |
KR102475504B1 (ko) * | 2015-08-20 | 2022-12-09 | 엘지디스플레이 주식회사 | 투명표시패널 및 이를 포함하는 투명표시장치 |
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JP2010251735A (ja) * | 2009-03-27 | 2010-11-04 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
JP2012009839A (ja) * | 2010-05-21 | 2012-01-12 | Semiconductor Energy Lab Co Ltd | 記憶装置、半導体装置 |
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JP2003031817A (ja) * | 2002-05-17 | 2003-01-31 | Sanyo Electric Co Ltd | コンタクト構造の形成方法 |
KR20070008099A (ko) * | 2005-07-13 | 2007-01-17 | 삼성전자주식회사 | 표시기판, 이를 포함하는 액정표시패널 및 이의 제조방법 |
KR101476817B1 (ko) * | 2009-07-03 | 2014-12-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 트랜지스터를 갖는 표시 장치 및 그 제작 방법 |
JP5685855B2 (ja) * | 2009-09-08 | 2015-03-18 | 株式会社リコー | 表示装置および表示装置の製造方法 |
JP2011222767A (ja) * | 2010-04-09 | 2011-11-04 | Sony Corp | 薄膜トランジスタならびに表示装置および電子機器 |
WO2011148538A1 (ja) * | 2010-05-24 | 2011-12-01 | シャープ株式会社 | 表示パネル及び薄膜トランジスタ基板 |
US8710497B2 (en) * | 2011-12-08 | 2014-04-29 | LG Dispay Co., Ltd | Array substrate including thin film transistor and method of fabricating the same |
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2012
- 2012-06-19 JP JP2013535188A patent/JPWO2013108301A1/ja active Pending
- 2012-06-19 CN CN201280018902.7A patent/CN103493187A/zh active Pending
- 2012-06-19 WO PCT/JP2012/003978 patent/WO2013108301A1/ja active Application Filing
- 2012-06-19 KR KR1020137026886A patent/KR20130133289A/ko not_active Application Discontinuation
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2013
- 2013-08-22 US US13/973,694 patent/US20130334526A1/en not_active Abandoned
Patent Citations (2)
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JP2010251735A (ja) * | 2009-03-27 | 2010-11-04 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
JP2012009839A (ja) * | 2010-05-21 | 2012-01-12 | Semiconductor Energy Lab Co Ltd | 記憶装置、半導体装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150091265A (ko) * | 2014-01-31 | 2015-08-10 | 고쿠리츠다이가쿠호징 나라 센탄카가쿠기쥬츠 다이가쿠인 다이가쿠 | 보호막을 구비한 박막 트랜지스터 기판 및 이의 제조 방법 |
JP2015146332A (ja) * | 2014-01-31 | 2015-08-13 | 国立大学法人 奈良先端科学技術大学院大学 | 保護膜を具備する薄膜トランジスタ基板およびその製造方法 |
TWI626511B (zh) * | 2014-01-31 | 2018-06-11 | National University Corporation NARA Institute of Science and Technology | 具備保護膜之薄膜電晶體基板的製造方法 |
KR102302306B1 (ko) | 2014-01-31 | 2021-09-17 | 고쿠리츠다이가쿠호징 나라 센탄카가쿠기쥬츠 다이가쿠인 다이가쿠 | 보호막을 구비한 박막 트랜지스터 기판 및 이의 제조 방법 |
Also Published As
Publication number | Publication date |
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CN103493187A (zh) | 2014-01-01 |
JPWO2013108301A1 (ja) | 2015-05-11 |
US20130334526A1 (en) | 2013-12-19 |
KR20130133289A (ko) | 2013-12-06 |
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