Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
  • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/12—Replacement control
  • G06F12/121—Replacement control using replacement algorithms
  • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0893—Caches characterised by their organisation or structure
  • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
  • G06F2212/26—Using a specific storage system architecture
  • G06F2212/261—Storage comprising a plurality of storage devices
  • G06F2212/262—Storage comprising a plurality of storage devices configured as RAID
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
  • G06F2212/31—Providing disk cache in a specific location of a storage system
  • G06F2212/312—In storage controller
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
  • G06F2212/46—Caching storage objects of specific type in disk cache
  • G06F2212/462—Track or segment

Definitions

• the present invention relates to a computer program product, system, and method for populating a first stride of tracks from a first cache to write to a second stride in a second cache.
• a cache management system buffers tracks in a storage device recently accessed as a result of read and write operations in a faster access storage device, such as memory, than the storage device storing the requested tracks. Subsequent read requests to tracks in the faster access cache memory are returned at a faster rate than returning the requested tracks from the slower access storage, thus reducing read latency.
• the cache management system may also return complete to a write request when the modified track directed to the storage device is written to the cache memory and before the modified track is written out to the storage device, such as a hard disk drive.
• the write latency to the storage device is typically significantly longer than the latency to write to a cache memory. Thus, using cache also reduces write latency.
• a cache management system may maintain a linked list having one entry for each track stored in the cache, which may comprise write data buffered in cache before writing to the storage device or read data.
• LRU Least Recently Used
• MRU Most Recently Used
• a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system.
• a first stride is formed including the determined tracks to demote.
• FIG. 2 illustrates an embodiment of first cache management information.
• FIG. 3 illustrates an embodiment of second cache management information.
• FIG. 6 illustrates an embodiment of stride information.
• FIG. 7 illustrates an embodiment of a second cache RAID configuration.
• FIG. 9 illustrates an embodiment of operations to demote unmodified non-sequential tracks from the first cache to promote to the second cache.
• FIG. 12 illustrates an embodiment of operations to free space in the second cache.
• a plurality of hosts 2a, 2b...2n may submit Input/Output (I/O) requests to a storage controller 4 over a network 6 to access data at volumes 8 (e.g., Logical Unit Numbers, Logical Devices, Logical Subsystems, etc.) in a storage 10.
• the storage controller 4 includes a processor complex 12, including one or more processors with single or multiple cores, a first cache 14 and a second cache 18. The first 14 and second 18 caches cache data transferred between the hosts 2a, 2b...2n and the storage 10.
• management information 28 to manage read (unmodified) and write (modified) tracks in the first cache 14 and the second cache 18.
• the storage manager 22 and cache manager 24 are shown in FIG. 1 as program code loaded into the memory 20 and executed by the processor complex 12. Alternatively, some or all of the functions may be implemented in hardware devices in the storage controller 4, such as in Application Specific Integrated Circuits (ASICs).
• ASICs Application Specific Integrated Circuits
• the second cache 18 may store tracks in a log structured array (LSA) 32, where tracks are written in a sequential order as received, thus providing a temporal ordering of the tracks written to the second cache 18.
• LSA log structured array
• later versions of tracks already present in the LSA are written at the end of the LSA 32.
• the second cache 18 may store data in formats other than in an LSA.
• the memory 20 further includes second cache RAID configuration information 34 providing information on a RAID configuration used to determine how to form a stride of tracks to store in the second cache 18.
• the second cache 18 may be comprised of a plurality of storage devices, such as separate solid state storage devices (SSDs), such that the strides formed of tracks from the first cache 14 are striped across the separate storage devices forming the second cache 18, such as flash memories.
• the second cache 18 may comprise a single storage device, such as one flash memory, such that the tracks are grouped in strides as defined by the second cache RAID configuration 34, but the tracks are written as strides to a single device, such as one flash memory, implementing the second cache 18.
• the tracks of strides configured for the second cache RAID configuration 34 may be written to the LSA 32 in the second cache 18 device.
• the second cache RAID configuration 34 may specify different RAID levels, e.g., levels 5, 10, etc.
• the memory 20 further includes storage RAID configuration information 36 providing information on a RAID configuration used to determine how to write tracks from the first cache 14 or second cache 18, if the second cache 18 should store modified data, to the storage system 10, where the tracks in the destaged stride are striped across the storage devices, such as disk drives, in the storage system 10.
• the first cache 14 may be part of the memory 20 or implemented in a separate memory device, such as a DRAM.
• the network 6 may comprise a Storage Area Network (SAN), a Local Area Network (LAN), a Wide Area Network (WAN), the Internet, and Intranet, etc.
• FIG. 2 illustrates an embodiment of the first cache management information 26 including a track index 50 providing an index of tracks in the first cache 14 to control blocks in a control block directory 52; an unmodified sequential LRU list 54 providing a temporal ordering of unmodified sequential tracks in the first cache 14; a modified LRU list 56 providing a temporal ordering of modified sequential and non-sequential tracks in the first cache 14; an unmodified non-sequential LRU list 58 providing a temporal ordering of unmodified non-sequential tracks in the first cache 14; and stride information 60 providing information on strides formed of unmodified non-sequential tracks in the first cache 14 to write to the second cache 18 as a full stride write.
• a track index 50 providing an index of tracks in the first cache 14 to control blocks in a control block directory 52
• an unmodified sequential LRU list 54 providing a temporal ordering of unmodified sequential tracks in the first cache 14
• a modified LRU list 56 providing a temporal ordering of modified sequential and non-
• the cache manager 24 may designate that destaged tracks as an unmodified non-sequential track in the first cache 14 and add indication of the newly designated unmodified track to the unmodified non-sequential LRU list 58, from where it is eligible to be promoted to the second cache 14.
• the state of the destaged modified track may be changed by updating the first cache control block 104 to indicate the destaged modified nonsequential track as unmodified in field 106.
• unmodified non-sequential tracks in the first cache 14 may comprise read data or modified non-sequential tracks that were destaged to the storage 10 according to the modified LRU list 56.
• destaged modified tracks that become unmodified tracks in the LRU list 58 may be promoted to the second cache 14 to be available for subsequent read requests.
• the second cache 14 comprises a read only cache to cache unmodified non-sequential tracks.
• All the LRU lists 54, 56, 58, and 74 may include the track IDs of tracks in the first cache 14 and the second cache 18 ordered according to when the identified track was last accessed.
• the LRU lists 54, 56, 58, and 74 have a most recently used (MRU) end indicating a most recently accessed track and a LRU end indicating a least recently used or accessed track.
• the track IDs of tracks added to the caches 14 and 18 are added to the MRU end of the LRU list and tracks demoted from the caches 14 and 18 are accessed from the LRU end.
• the track indexes 50 and 70 may comprise a scatter index table (SIT).
• Non-sequential tracks may comprise Online Line Transaction Processing (OLTP) tracks, which often comprise small block writes that are not fully random and have some locality of reference, i.e., have a probability of being repeatedly accessed.
• OTP Online Line Transaction Processing
• FIG. 4 illustrates an embodiment of a first cache control block 100 entry in the control block directory 52, including a control block identifier (ID) 102, a first cache location 104 of the physical location of the track in the first cache 14, information 106 indicating whether the track is modified or unmodified, information 108 indicating whether the track is a sequential or non-sequential access, and information 110 indicating a demote status for the track, such as no demotion, ready to demote, and demote complete.
• ID control block identifier
• first cache location 104 of the physical location of the track in the first cache 14
• information 106 indicating whether the track is modified or unmodified
• information 108 indicating whether the track is a sequential or non-sequential access
• information 110 indicating a demote status for the track, such as no demotion, ready to demote, and demote complete.
• FIG. 5 illustrates an embodiment of a second cache control block 120 entry in the second cache control block directory 72, including a control block identifier (ID) 122; an LSA location 124 where the track is located in the LSA 32; modified/unmodified info 126 indicating whether the track is modified or unmodified; and valid/invalid flag 128 indicating whether the track is valid or invalid.
• ID control block identifier
• LSA location 124 where the track is located in the LSA 32
• modified/unmodified info 126 indicating whether the track is modified or unmodified
• valid/invalid flag 128 indicating whether the track is valid or invalid.
• a track in the second cache 18 is indicated as invalid if the track is updated in the first cache 14 or if the track is demoted from the second cache 18.
• the cache manager 24 may designate that destaged tracks as an unmodified non-sequential track in the first cache 14 and add indication of the newly designated unmodified track to the unmodified non-sequential LRU list 58, from where it is eligible to be promoted to the second cache 14.
• the state of the destaged modified track may be changed by updating the first cache control block 100 to indicate the destaged modified nonsequential track as unmodified in field 106.
• unmodified non-sequential tracks in the first cache 14 may comprise read data or modified non-sequential tracks that were destaged to the storage 10 according to the modified LRU list 56.
• destaged modified tracks that become unmodified tracks in the LRU list 58 may be promoted to the second cache 14 to be available for subsequent read requests.
• the second cache 14 comprises a read only cache to cache unmodified non-sequential tracks.
• FIG. 6 illustrates an instance 130 of the stride information 60, 78 for one stride to be formed in the second cache 18, including a stride identifier (ID) 132, tracks 134 of the storage 10 included in the stride 132, and an occupancy 136 indicating a number of valid tracks in the stride of the total number of tracks, where the tracks in the stride that are not valid are eligible for garbage collection operations.
• ID stride identifier
• FIG. 7 illustrates an embodiment of the second cache RAID configuration 34 that is maintained to determine how to form strides of tracks in the second cache 18 from the tracks in the first cache 14.
• a RAID level 140 indicates the RAID configuration to use, e.g., RAID 1, RAID 5, RAID 6, RAID 10, etc., a number of data disks (m) 142 storing tracks of user data, and a number of parity disks (p) 144 storing parity calculated from the data disks 142, where p can be one or more, indicating the number of disks for storing the calculated parity blocks.
• An unmodified parity optional flag 148 indicates whether parity should be calculated for unmodified non-sequential tracks in the first cache 14 being promoted to the second cache 18.
• This optional flag 148 allows for only including unmodified nonsequential tracks in a stride to fill the stride with only unmodified non-sequential tracks.
• the stride of unmodified non-sequential tracks in the first cache 14 may be indicated in an LSA 32, where the tracks of the stride are striped across m plus p storage devices forming the second cache 18.
• the second cache 18 may comprise fewer than n devices.
• FIG. 8 illustrates an embodiment of the storage RAID configuration 36 that is maintained to determine how to form strides of modified tracks in the second cache 18 to stripe across the disks of the storage 10.
• a RAID level 150 indicates the RAID configuration to use, a number of data disks (m) 152 storing tracks of user data, and a number of parity disks (p) 154 storing parity calculated from the data disks 152, where p can be one or more, indicating the number of disks for storing the calculated parity blocks.
• the stride of tracks from the second cache 18 may be striped across disks in the storage system 10.
• FIG. 9 illustrates an embodiment of operations performed by the cache manager 24 to demote unmodified non-sequential tracks from the first cache 14 to promote to the second cache 18, where the unmodified non-sequential tracks may be selected from the LRU end of the unmodified non-sequential LRU list 58 when space is needed.
• the demote status 110 (FIG. 4) of the unmodified non-sequential tracks selected to demote is set (at block 202) to "ready".
• the cache manager 24 uses (at block 204) the second cache RAID configuration information 34 to form a first stride of tracks from the first cache 114 to promote to a stride in the second cache 18.
• forming the first stride of tracks may comprise forming a stride for a RAID configuration based on a RAID configuration defined 34 for the second cache as having n devices including m devices for storing tracks of data and at least one parity device p to store parity data calculated from the tracks of data for the m devices.
• the first stride of tracks may be striped across n solid state storage devices without parity to form the second stride in embodiments where the second cache comprises at least n solid state storage devices.
• the cache manager 24 processes (at block 206) the unmodified non- sequential LRU 58 list to determine a number of unmodified non-sequential tracks having a demote status 110 of ready in their control blocks 100. If the cache manager 24 determines (at block 208) that the number of unmodified non-sequential tracks is sufficient to form a stride, then the cache manager 24 populates (at block 210) the first stride of unmodified non-sequential tracks having a demote status 110 of ready. In one embodiment, the first stride may be populated starting from the LRU end of the unmodified non-sequential LRU list 58 and use enough tracks for the data disks in stride.
• the cache manager 24 calculates (at block 212) parity for the unmodified non-sequential tracks included in the stride and includes parity data (for the p parity disks) in the stride. If (at block 208) there are not sufficient unmodified non- sequential tracks in the first cache 14 to fill the first stride, then control ends until there are a sufficient number of unmodified non-sequential tracks having the demote ready status available to populate the first stride.
• the cache manager 14 determines (at block 214) a free second stride in the second cache 18 in which to include the tracks from the first stride.
• the tracks from the first stride are written or striped (at block 216) as a full stride write to the second stride across the devices forming the second cache 18.
• the cache manager 14 indicates (at block 218) the occupancy 136 of the stride information 130 for the second stride as full.
• the cache manager 24 updates (at block 220) the demote status 110 for the unmodified non- sequential tracks included in the stride as demote "complete".
• FIG. 9 Although the operations of FIG. 9 are described as demoting unmodified nonsequential tracks from the first cache 14 to promote to the second cache 18, in alternative embodiments, the operations may apply to demoting different types of tracks, such as modified, sequential, etc. [0047] With the described embodiments, the unmodified tracks from the first cache 14 are gathered and written as a stride to the second cache 18 so that one Input/Output (I/O) operation is used to transfer multiple tracks.
• I/O Input/Output
• the track to add is a modified nonsequential track and if (at block 264) a copy of the track to add is in the second cache 18, as determined from the second cache track index 70, then the copy of the track in the second cache 18 is invalidated (at block 266), such as by setting the valid/invalid flag 128 in the cache control block 120 for the track in the second cache 18 to invalid. If (at block 306) the track to add is unmodified sequential, control ends.
• FIG. 11 illustrates an embodiment of operations performed by the cache manager 24 to add tracks from the first stride from the first cache 14 to the second stride in the second cache 18.
• the cache manager 24 creates (at block 302) stride information 130 (FIG. 6) for the second stride indicating the tracks 134 from the first stride being added and indicating the occupancy 136 as full. For each track in the first stride being added, a loop of operations is performed at blocks 304 through 318.
• the cache manager 24 adds (at block 302) indication, such as the track ID, of the track being promoted to the LSA 32 in the second cache 18.
• the cache manager 24 updates (at block 310) the cache control block 120 for the track indicating the location 124 in the LSA 32, that the data is unmodified 126, and that and that the track is valid 128. If (at block 308) the track is not already in the second cache 18, then the cache manager 24 creates (at block 312) a control block 120 (FIG. 5) for the track to add indicating the track location 124 in the LSA 32 and whether the track is
• modified/unmodified 126 An entry is added (at block 314) to the second cache track index 70 having the track ID of the promoted track and an index to the created cache control block 120 in the control block directory 72 for the second cache 18. From block 310 or 316, the cache manager 24 indicates (at block 316) the promoted track at the MRU end of the unmodified LRU list 74, such as by adding the track ID to the MRU end.
• the unmodified tracks in the second cache 18 may comprise read tracks added to the first cache 14 or modified tracks destaged from the first cache 14. Further, the tracks selected by the cache manager 24 for demotion from the second cache 18 may be from different strides formed in the second cache 18. Further, strides in the second cache may include both valid and invalid tracks, where tracks are invalidated by demoting from the second cache 18 or by the track being updated in the first cache 18.
• the cache manager 24 uses different track demotion algorithms to determine tracks to demote from the first cache 14 and the second cache 18 by using separate LRU lists 58 and 74 for the first 14 and second 18 caches 18, respectively, to determine the tracks to demote.
• the algorithms used to select tracks for demotion in the first 14 and second 18 caches may consider characteristics of the tracks in the first 14 and second 18 caches to determine tracks to demote first.
• the cache manager 24 determines (at block 374) an available stride having zero occupancy 136 and determines (at block 376) at least two strides that are partially full, i.e., having valid and invalid tracks, whose valid tracks can fit into the free stride.
• the cache manager 24 combines (at block 378) the valid tracks from the determined at least two partially full strides into the determined available stride.
• the cache manager 24 indicates (at block 380) the at least two strides from which the tracks merged as having zero occupancy 136, so they are available to receive tracks from strides from the first cache 14.
• the cache manager 24 determines (at block 460) any of the requested tracks in the storage 10, from the second cache track index 70, not in the first 14 and the second 18 caches. The cache manager 24 then promotes (at block 462) any of the determined tracks in the second cache 18 and the storage 10 to the first cache 14. The cache manager 24 uses (at block 464) the first cache track index 50 to retrieve the requested tracks from the first cache 14 to return to the read request. The entries for the retrieved tracks are moved (at block 466) to the MRU end of the LRU list 54, 56, 58 including entries for the retrieved tracks.
• the cache manager 24 retrieves requested tracks from a highest level cache 14, then second cache 18 first before going to the storage 10, because the caches 14 and 18 would have the most recent modified version of a requested track.
• the most recent version is first found in the first cache 14, then the second cache 18 if not in the first cache 14 and then the storage 10 if not in either cache 14, 18.
• Described embodiments provide techniques to group tracks in a first cache in strides defined according to a RAID configuration for the second cache, so that tracks in the first cache can be grouped in strides to a second cache.
• the tracks cached in the second cache may then be grouped into strides, defined according to a RAID configuration for the storage, and then written to the storage system.
• Described embodiments provide techniques for promoting tracks from a first cache in strides so that the tracks may be written as full stride writes to strides in the second cache to improve the efficiency of cache promotion operations.
• the described embodiments allow full stride writes to be used to promote demoted tracks in the first cache to the second cache in order to conserve resources by promoting an entire stride to the second cache as a single I/O operation.
• tracks are being promoted from the first cache 14 to the second cache 18 as strides, tracks are demoted from the second cache 18 on a track-by-track basis according to a cache demotion algorithm, such as an LRU algorithm.
• a cache demotion algorithm such as an LRU algorithm.
• aspects of the embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit,” "module” or “system.”
• aspects of the embodiments may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
• the computer readable medium may be a computer readable signal medium or a computer readable storage medium.
• a computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.
• a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof.
• a computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device [0061]
• Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, PvF, etc., or any suitable combination of the foregoing.
• the computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
• Devices that are in communication with each other need not be in continuous communication with each other, unless expressly specified otherwise.
• devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.

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