IN2014CN04679A - - Google Patents

Info

Publication number
IN2014CN04679A
IN2014CN04679A IN4679CHN2014A IN2014CN04679A IN 2014CN04679 A IN2014CN04679 A IN 2014CN04679A IN 4679CHN2014 A IN4679CHN2014 A IN 4679CHN2014A IN 2014CN04679 A IN2014CN04679 A IN 2014CN04679A
Authority
IN
India
Prior art keywords
cache
tracks
stride
demote
determination
Prior art date
Application number
Other languages
English (en)
Inventor
Lokesh Mohan Gupta
Matthew Joseph Kalos
Michael Thomas Benhase
Karl Allen Nielsen
Kevin John Ash
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IN2014CN04679A publication Critical patent/IN2014CN04679A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/26—Using a specific storage system architecture
    • G06F2212/261—Storage comprising a plurality of storage devices
    • G06F2212/262—Storage comprising a plurality of storage devices configured as RAID
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31—Providing disk cache in a specific location of a storage system
    • G06F2212/312—In storage controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/46—Caching storage objects of specific type in disk cache
    • G06F2212/462—Track or segment

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IN4679CHN2014 2012-01-17 2012-12-10 IN2014CN04679A (enExample)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/352,230 US8966178B2 (en) 2012-01-17 2012-01-17 Populating a first stride of tracks from a first cache to write to a second stride in a second cache
PCT/IB2012/057140 WO2013108097A1 (en) 2012-01-17 2012-12-10 Populating a first stride of tracks from a first cache to write to a second stride in a second cache

Publications (1)

Publication Number Publication Date
IN2014CN04679A true IN2014CN04679A (enExample) 2015-09-18

Family

ID=48780809

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4679CHN2014 IN2014CN04679A (enExample) 2012-01-17 2012-12-10

Country Status (7)

Country Link
US (2) US8966178B2 (enExample)
EP (1) EP2805241B1 (enExample)
JP (1) JP5908118B2 (enExample)
KR (1) KR101572401B1 (enExample)
CN (1) CN104040508B (enExample)
IN (1) IN2014CN04679A (enExample)
WO (1) WO2013108097A1 (enExample)

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US10033810B2 (en) 2015-12-03 2018-07-24 International Business Machines Corporation Recovery point objective via dynamic usage of bind segments in a global mirror environment
US10956322B2 (en) 2016-06-02 2021-03-23 International Business Machines Corporation Storage drive dependent track removal in a cache for storage
CN106293543B (zh) * 2016-08-25 2019-03-12 中国科学院计算技术研究所 一种基于捎带回收的瓦记录raid写顺序化方法及装置
US10691566B2 (en) 2017-07-27 2020-06-23 International Business Machines Corporation Using a track format code in a cache control block for a track in a cache to process read and write requests to the track in the cache
US12135655B2 (en) 2017-07-27 2024-11-05 International Business Machines Corporation Saving track metadata format information for tracks demoted from cache for use when the demoted track is later staged into cache
US10417139B2 (en) 2017-08-18 2019-09-17 International Business Machines Corporation Cache management based on types of I/O operations
US11294812B2 (en) * 2020-08-04 2022-04-05 International Business Machines Corporation Obtaining cache resources for expected writes to tracks in a write set after the cache resources were released for the tracks in the write set
CN112015674B (zh) * 2020-08-27 2023-05-30 平安科技（深圳）有限公司 基于多层级的缓存资源访问方法、装置和计算机设备

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Also Published As

Publication number Publication date
JP2015509242A (ja) 2015-03-26
CN104040508B (zh) 2017-03-29
EP2805241A1 (en) 2014-11-26
JP5908118B2 (ja) 2016-04-26
US20130185494A1 (en) 2013-07-18
KR101572401B1 (ko) 2015-11-26
US8966178B2 (en) 2015-02-24
EP2805241A4 (en) 2015-07-08
US20130185478A1 (en) 2013-07-18
KR20140106516A (ko) 2014-09-03
EP2805241B1 (en) 2019-01-23
US8959279B2 (en) 2015-02-17
WO2013108097A1 (en) 2013-07-25
CN104040508A (zh) 2014-09-10

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