WO2013086908A1 - 一种otp存储单元及其制作方法 - Google Patents

一种otp存储单元及其制作方法 Download PDF

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Publication number
WO2013086908A1
WO2013086908A1 PCT/CN2012/083975 CN2012083975W WO2013086908A1 WO 2013086908 A1 WO2013086908 A1 WO 2013086908A1 CN 2012083975 W CN2012083975 W CN 2012083975W WO 2013086908 A1 WO2013086908 A1 WO 2013086908A1
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gate
dielectric layer
sidewall
otp memory
silicon nitride
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French (fr)
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蔡建祥
许宗能
杜鹏
周玮
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/697—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having trapping at multiple separated sites, e.g. multi-particles trapping sites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/36—Gate programmed, e.g. different gate material or no gate
    • H10B20/367—Gate dielectric programmed, e.g. different thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

Definitions

  • the present invention relates to a device structure of a memory and related fabrication processes, and more particularly to a one-time programmable (OTP, one time)
  • OTP one-time programmable
  • OTP memory has been widely used in recent years due to its low cost and compatibility with logic processes.
  • OTP memory is usually composed of an OTP memory cell array and a matching peripheral circuit.
  • the existing OTP memory cell is generally composed of a coupling capacitor (or NMOS strobe) plus a floating gate transistor (NMOS transistor), which can pass heat.
  • Electron injection (HCI, hot Carrier) is programmed to store electrons on the polysilicon floating gate, and then use the magnitude of the threshold voltage to determine whether there is electron injection on the floating gate, thereby characterizing 0 or 1 in one cell.
  • the technical problem to be solved by the present invention is to provide a novel OTP memory unit and a manufacturing method thereof.
  • the OTP memory unit has a small occupied area, a simple manufacturing method, and a low cost.
  • An OTP storage unit comprising:
  • a silicon nitride sidewall structure located around the gate
  • the silicon nitride sidewall structure is used for storing electrons.
  • the semiconductor substrate is a single crystal silicon substrate.
  • the material of the gate dielectric layer is silicon oxide or other high dielectric constant material.
  • the material of the gate is polysilicon.
  • the material of the sidewall dielectric layer is silicon oxide.
  • the silicon nitride sidewall structure has a thickness of 500-1000 nm.
  • the sidewall dielectric layer has a thickness of 50 to 100 nm.
  • a method for manufacturing an OTP storage unit includes the following steps:
  • Step 1 forming a gate dielectric layer on the semiconductor substrate, and forming a gate material layer on the gate dielectric layer;
  • Step 2 patterning the gate material layer to form a gate
  • Step 3 forming a sidewall dielectric layer on a sidewall of the gate
  • Step 4 depositing silicon nitride on the gate formed with the sidewall dielectric layer on the sidewall, so that the silicon nitride completely encapsulates the gate and the sidewall dielectric layer;
  • Step 5 removing excess silicon nitride by an etching process, and forming a silicon nitride sidewall structure around the gate of the sidewall formed with the sidewall dielectric layer;
  • Step 6 Form a source and a drain on both sides of the gate.
  • the semiconductor substrate is a single crystal silicon substrate; and the gate material layer is a polysilicon layer.
  • the gate material layer is patterned to form a gate using photolithography and etching processes.
  • the patterning operation of step 2 is performed, and after the step 6 is completed, the protective layer is removed to expose the gate for subsequent processing. Electrode connection.
  • a high temperature oxide layer is deposited on the surface of the gate material layer as the protective layer.
  • a sidewall dielectric layer is formed on the sidewall of the gate by thermal oxidation.
  • step 6 ion implantation is used to form a source and a drain in a semiconductor substrate which is not covered by the silicon nitride spacer structure on both sides of the gate.
  • the OTP memory cell of the present invention is different from the conventional floating gate OTP.
  • the hot electrons are not stored in the floating gate, but the sidewall dielectric structure is used to capture and store the electrons by adding a sidewall dielectric layer between the gate and the sidewall structure. . Therefore, the OTP memory cell of the present invention requires only one transistor structure, and data storage and reading can be realized without an additional strobe or coupling capacitor.
  • the memory structure has a small footprint compared to the conventional floating gate OTP. It is beneficial to increase the storage density of the memory, and the manufacturing method of the structure is compatible with the standard logic process, the process is simple, and the manufacturing cost can be greatly saved.
  • FIG. 1 is a schematic structural diagram of an OTP storage unit according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic diagram of a principle of an OTP storage unit according to Embodiment 1 of the present invention.
  • FIG. 3 is an I-V characteristic curve of an OTP memory unit according to Embodiment 1 of the present invention.
  • 4a-4h are schematic diagrams showing a manufacturing process of an OTP storage unit according to Embodiment 2 of the present invention.
  • the inventor of the present invention deeply studied the structure and principle of the OTP memory, and designed an OTP with small occupied area, simple structure and low production cost. Storage unit.
  • the OTP memory cell includes: a semiconductor substrate 100; a gate dielectric layer 101 on the semiconductor substrate 100; a gate 102 on the gate dielectric layer 101; a surrounding silicon nitride sidewall structure 104; a sidewall dielectric layer 103 between the gate 102 and the silicon nitride sidewall structure 104; and a source 105 and a drain on both sides of the gate 102 Pole 106.
  • the semiconductor substrate 100 may be a common single crystal silicon substrate; the gate dielectric layer 101 may be a conventional dielectric material, such as silicon oxide. In other embodiments, the gate dielectric layer 101 may also be A high dielectric constant material such as SrTiO 3 , HfO 2 or ZrO 2 ; the material of the gate electrode 102 may preferably be polysilicon; the material of the sidewall dielectric layer 103 may preferably be silicon oxide.
  • the thickness of the silicon nitride sidewall structure 104 may be 500-1000 nm, which is determined according to the specific needs of the device, and serves as a memory unit for storing a core portion of the charge.
  • the sidewall dielectric layer 103 has a relatively thin thickness and may be 50-100 nm, which functions to isolate the silicon nitride sidewall structure from the gate. It should be noted that the dimensions and preferred materials mentioned in this embodiment are merely illustrative. In practical applications, the selection of device dimensions and materials should not be limited thereto.
  • the OTP memory cell can store electrons in the silicon nitride sidewall structure 104 by means of hot electron injection or the like due to the isolation of the sidewall dielectric layer 103, thereby realizing device programming.
  • the silicon nitride material used in the sidewall structure is due to the large number of electron traps in the silicon nitride.
  • the electron mobility in the silicon nitride is extremely low, and the hot electrons are easily trapped by the electron traps in the silicon nitride after being injected into the sidewall structure. Thereby, the hot electron capture efficiency of the OTP memory cell can be improved.
  • the source S and the substrate B are grounded, the drain D is connected to a high voltage (eg, 3-3.6V), and the gate G is connected to a high voltage (eg, 3- 3.6V); at this time, the channel is turned on, and electrons avalanche breakdown occurs in the depletion region near the drain D, so that high-energy hot electrons are injected into the sidewall structure, and silicon nitride captures these electrons to realize data storage. Since the threshold voltage of the device changes after trapping electrons in the sidewall structure, the magnitude of the threshold voltage can be used to determine whether or not electrons are injected into the sidewall structure, thereby characterizing 0 or 1 in one cell.
  • a high voltage eg, 3-3.6V
  • the gate G is connected to a high voltage (eg, 3- 3.6V)
  • the source S and the substrate B are grounded, the drain D is connected to a low voltage (eg, 1-1.8V), and the gate G is connected to a low voltage (eg, 1-1.8V), and is read. Data can be read by taking the threshold voltage.
  • I-V when the storage unit is reading information, I-V
  • the characteristic curve exhibits different output currents due to the presence or absence of stored electrons in the silicon nitride sidewall structure near the drain.
  • the curve (such as a dotted line) is significantly different from the absence of electrons (such as a solid line). In this way, different unit information is stored.
  • the high voltage mentioned in the write data in the present embodiment and the low voltage mentioned in the read data are only exemplified. In practical applications, the range of the operating voltage should not be limited to this, and only needs to be read.
  • the gate and drain access voltages at the time of data are lower than the gate and drain access voltages at the time of writing data.
  • the OTP memory cell can be fabricated as follows:
  • Step 1 as shown in FIG. 4a, a conventional single crystal silicon substrate is provided as the semiconductor substrate 200, and then a gate dielectric layer 201 is formed on the surface of the single crystal silicon substrate.
  • a gate oxide layer can be formed by thermal oxidation.
  • other dielectric materials may be formed by using a deposition method or the like as the gate dielectric layer 201, such as a high dielectric constant material such as SrTiO 3 , HfO 2 or ZrO 2 ; then a gate material is formed on the gate dielectric layer 201.
  • Layer 202 such as a polysilicon layer, is deposited as the gate material layer 202.
  • a protective layer 203 is formed on the surface of the gate material layer 202, for example, a high temperature oxide layer (HTO) is deposited; then, as shown in FIG. 4c, The gate material layer 202 is patterned using photolithography and etching processes to form a gate.
  • the protective layer 203 is used to protect the gate material from subsequent processes.
  • Step 3 silicon oxide is formed as a sidewall dielectric layer 204 on the sidewall of the gate by thermal oxidation.
  • the thickness of the sidewall dielectric layer 204 is preferably 50-100 nm.
  • Step 4 As shown in FIG. 4e, silicon nitride 205 is deposited on the gate of the sidewall formed with the sidewall dielectric layer 204, so that the silicon nitride 205 completely encapsulates the gate and sidewall dielectric layers 204.
  • Step 5 As shown in FIG. 4f, the excess silicon nitride 205 is removed by an etching process, and a silicon nitride sidewall structure 206 is formed around the gate of the sidewall formed with the sidewall dielectric layer 204.
  • the thickness of the silicon nitride sidewall structure 206 is preferably 500-1000 nm.
  • the removal of excess silicon nitride 205 can be reversed by a dry etching process, and the reverse etching process does not require a mask.
  • the result of the reverse etching is that most of the silicon oxide 205 is etched away, only at the gate. A portion of the silicon oxide 205 remains around the sidewalls, and the remaining silicon oxide 205 is the silicon nitride sidewall structure 206.
  • a source 207 and a drain 208 are formed on both sides of the gate.
  • the source 207 and the drain 208 are formed in the semiconductor substrate 200 not covered by the silicon nitride sidewall structure 206 on both sides of the gate by ion implantation.
  • the source-drain light doping (LDD) is not performed in the process of fabricating the memory cell, which can improve the injection efficiency of the hot electrons.
  • the protective layer 203 is removed to expose the gate for subsequent electrode connections.
  • a person skilled in the art can fabricate a memory cell array composed of the OTP memory cells and a peripheral circuit matched thereto, thereby forming a complete OTP memory.
  • Applying the OTP memory to the system integrated chip or the micro processing chip can improve the flexibility of the system coding and can greatly save the manufacturing cost.

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Abstract

一种一次可编程（OTP）存储单元及其制作方法。该OTP存储单元，包括：半导体衬底；位于所述半导体衬底上的栅介质层；位于所述栅介质层上的栅极（G）；位于所述栅极周围的氮化硅侧墙结构；位于所述栅极与所述氮化硅侧墙结构之间的侧壁介质层；以及位于所述栅极两侧的源极（S）和漏极（D）。该OTP存储单元热电子不是储存在浮栅中，利用侧墙结构来俘获并存储电子，因此不需要额外的选通管或耦合电容即可实现数据的存储与读取，相对于传统的浮栅OTP而言，占用面积小，有利于提高存储器的存储密度，并且其制作方法与标准逻辑制程相兼容，工艺简单，可以极大的节省制造成本。

Description

一种OTP存储单元及其制作方法
【技术领域】
本发明涉及存储器的器件结构及相关制作工艺，尤其涉及一种一次可编程（OTP，one time programmable）存储器的存储单元结构及其制作方法，属于半导体器件制造领域。
【背景技术】
目前比较流行的系统集成芯片或微处理芯片，都需要一个存储器来储存系统代码，由于逻辑和常规存储器的制作流程差异很大，比较传统的方式是在逻辑制程中引入只读存储器（ROM）。但是只读存储器的制作在晶圆流片的过程中就需要定义，一定程度上制约了系统编码的灵活性。针对只读存储器的这一缺点，可以通过电路板分别把逻辑芯片和存储器芯片封装在一起，这样的话系统代码可以通过存储器芯片内容的改变而改变。但是这样的方式因为需要两块或者以上的芯片，制造成本会相当的高，封装的成本也会很高，而且芯片的面积也很大，同时，由于信号需要通过电路板来传递，很容易受到杂讯干扰。
一种一次可编程（OTP）存储器，由于其成本较低且与逻辑制程相兼容，近年来得到了广泛的应用。通过在集成电路芯片中加入OTP存储器来替代传统的ROM只读存储器，可以极大的提高芯片系统代码的灵活性。也就是说，当晶圆流片结束后，可以通过编码的形式将代码写入OTP存储器，这样可以针对不同的客户和产品实现无差别化，即可以针对不同的客户提供不同的代码以实现不同的功能。OTP存储器通常由OTP存储单元阵列和与之相匹配的外围电路组成，现有的OTP存储单元一般由一个耦合电容（或NMOS选通管）加一个浮栅晶体管（NMOS晶体管）构成，可以通过热电子注入（HCI，hot carrier injection）等方法对其编程，使电子储存于多晶硅浮栅上，然后利用阈值电压的大小来判断浮栅上有无注入电子，由此在一个单元表征出0或1。
然而，这种现有的OTP存储单元对应每一个浮栅晶体管都需要一个耦合电容，电容耦合部分通常面积较大，极大的占用了存储器的面积，并且其制造工艺也是比较复杂的。
【发明内容】
本发明要解决的技术问题在于提供一种新型的OTP存储单元及其制作方法，该OTP存储单元占用面积小，制作方法较简单，成本较低。
为了解决上述技术问题，本发明采用如下技术方案：
一种OTP存储单元，包括：
半导体衬底；
位于所述半导体衬底上的栅介质层；
位于所述栅介质层上的栅极；
位于所述栅极周围的氮化硅侧墙结构；
位于所述栅极与所述氮化硅侧墙结构之间的侧壁介质层；
以及位于所述栅极两侧的源极和漏极；
其中，所述氮化硅侧墙结构用于存储电子。
作为本发明的优选方案，所述半导体衬底为单晶硅衬底。
作为本发明的优选方案，所述栅介质层的材料为氧化硅或其他高介电常数材料。
作为本发明的优选方案，所述栅极的材料为多晶硅。
作为本发明的优选方案，所述侧壁介质层的材料为氧化硅。
作为本发明的优选方案，所述氮化硅侧墙结构的厚度为500-1000nm。
作为本发明的优选方案，所述侧壁介质层的厚度为50-100nm。
一种OTP存储单元的制作方法，包括以下步骤：
步骤一、在半导体衬底上形成一层栅介质层，再在所述栅介质层上形成一层栅极材料层；
步骤二、将所述栅极材料层图形化，形成栅极；
步骤三、在所述栅极的侧壁形成侧壁介质层；
步骤四、在侧壁形成有侧壁介质层的栅极上沉积氮化硅，使氮化硅将栅极和侧壁介质层完全包裹；
步骤五、利用刻蚀工艺去除多余的氮化硅，在侧壁形成有侧壁介质层的栅极周围形成氮化硅侧墙结构；
步骤六、在所述栅极两侧形成源极和漏极。
作为本发明的优选方案，步骤一中，所述半导体衬底为单晶硅衬底；所述栅极材料层为多晶硅层。
作为本发明的优选方案，步骤二中，利用光刻和刻蚀工艺将所述栅极材料层图形化形成栅极。
作为本发明的优选方案，先在所述栅极材料层表面形成保护层后，再进行步骤二的图形化操作，直到完成步骤六之后再去除所述保护层，露出栅极，以便进行后续的电极连接。
进一步优选的，在所述栅极材料层表面沉积高温氧化层（HTO）作为所述保护层。
作为本发明的优选方案，步骤三中，利用热氧化法在所述栅极侧壁形成侧壁介质层。
作为本发明的优选方案，步骤六中，采用离子注入在所述栅极两侧未被氮化硅侧墙结构覆盖的半导体衬底内形成源极和漏极。
本发明的有益效果在于：
本发明的OTP存储单元与传统的浮栅OTP不同，热电子不是存储在浮栅中，而是通过在栅极与侧墙结构之间增设侧壁介质层，利用侧墙结构来俘获并存储电子。因此，本发明的OTP存储单元仅需要一个晶体管结构，不需要额外的选通管或耦合电容即可实现数据的存储与读取，该存储结构相对于传统的浮栅OTP而言，占用面积小，有利于提高存储器的存储密度，并且该结构的制作方法与标准逻辑制程相兼容，工艺简单，可以极大的节省制造成本。
【附图说明】
图1为本发明实施例一中OTP存储单元的结构示意图；
图2为本发明实施例一中OTP存储单元的原理示意图；
图3为本发明实施例一中OTP存储单元的I-V特性曲线；
图4a-4h为本发明实施例二中 OTP存储单元的制作流程示意图。
【具体实施方式】
下面结合附图进一步说明本发明的优选实施方式，为了示出的方便附图并未按照比例绘制。
本发明的发明人为了提高OTP存储器密度，简化制备工艺，降低生产成本，对OTP存储器的结构和原理进行了深入地研究，设计出了一种占用面积小、结构简单、制作成本较低的OTP存储单元。
实施例一
如图1所示，该OTP存储单元包括：半导体衬底100；位于所述半导体衬底100上的栅介质层101；位于所述栅介质层101上的栅极102；位于所述栅极102周围的氮化硅侧墙结构104；位于所述栅极102与所述氮化硅侧墙结构104之间的侧壁介质层103；以及位于所述栅极102两侧的源极105和漏极106。
本实施例中，半导体衬底100可以优选常见的单晶硅衬底；所述栅介质层101可以选用常规的介电材料，例如氧化硅，其他实施例中所述栅介质层101还可以为SrTiO3、HfO2或ZrO2等高介电常数材料；所述栅极102的材料可以优选为多晶硅；所述侧壁介质层103的材料可以优选为氧化硅。所述氮化硅侧墙结构104的厚度可以为500-1000nm，该厚度根据对器件的具体需要而定，作为存储单元用于存储电荷的核心部位。所述侧壁介质层103的厚度较薄，可以为50-100nm，起到隔离氮化硅侧墙结构与栅极的作用。需要说明的是，本实施例中提及的尺寸和优选材料仅作为示例性说明，在实际应用中，对器件尺寸和材料的选用应不仅限于此。
该OTP存储单元由于侧壁介质层103的隔离作用，可以通过热电子注入等方法在氮化硅侧墙结构104中存储电子，从而实现器件编程。这里侧墙结构选用氮化硅材料是由于氮化硅中具有大量的电子陷阱，电子在氮化硅中迁移率极低，热电子注入侧墙结构后容易被氮化硅中的电子陷阱捕获，从而可提高OTP存储单元的热电子捕获效率。
如图2所示，当对该OTP存储单元写入数据时，源极S和衬底B接地，漏极D接高电压（如3-3.6V），栅极G接高电压（如3-3.6V）；此时沟道导通，电子在漏极D附近的耗尽区发生雪崩击穿，使高能量热电子注入到侧墙结构中，氮化硅捕获这些电子从而实现数据的存储。由于侧墙结构中俘获电子后器件的阈值电压会发生变化，因此可以利用阈值电压的大小来判断侧墙结构中有无注入电子，由此在一个单元表征出0或1。当对该OTP存储单元读取数据时，源极S和衬底B接地，漏极D接低电压（如1-1.8V），栅极G接低电压（如1-1.8V），通过读取阈值电压即可读出数据。如图3所示，存储单元被读取信息的时候，I-V 特性曲线由于靠近漏极的氮化硅侧墙结构存储电子的有无而呈现不同的输出电流，当单元存储电子的时候，曲线（如虚线）会与没有电子（如实线）呈现显著的不同，以此来存储不同的单元信息。需要说明的是，本实施例中写入数据提及的高电压和读出数据提及的低电压仅作为示例性说明，在实际应用中，对操作电压的范围应不仅限于此，只需读数据时的栅极、漏极接入电压低于写入数据时的栅极、漏极接入电压即可。
实施例二
参阅图4a-4h，这种OTP存储单元可以采用如下的方法制作：
步骤一、如图4a所示，提供常用的单晶硅衬底作为半导体衬底200，然后在该单晶硅衬底表面形成一层栅介质层201，例如可采用热氧化法形成栅氧层，当然也可以采用沉积等方法形成其他介电材料作为栅介质层201，如SrTiO3、HfO2或ZrO2等高介电常数材料；然后在所述栅介质层201上形成一层栅极材料层202，例如沉积多晶硅层作为所述栅极材料层202。
步骤二、如图4b所示，本实施例优选地，先在所述栅极材料层202表面形成保护层203，例如，沉积一层高温氧化层（HTO）；然后，如图4c所示，利用光刻和刻蚀工艺将所述栅极材料层202图形化，形成栅极。该保护层203用于保护栅极材料，避免后续工艺对其造成影响。
步骤三、如图4d所示，利用热氧化法在所述栅极侧壁形成氧化硅作为侧壁介质层204。所述侧壁介质层204的厚度优选为50-100nm。
步骤四、如图4e所示，在侧壁形成有侧壁介质层204的栅极上沉积氮化硅205，使氮化硅205将栅极和侧壁介质层204完全包裹。
步骤五、如图4f所示，利用刻蚀工艺去除多余的氮化硅205，在侧壁形成有侧壁介质层204的栅极周围形成氮化硅侧墙结构206。所述氮化硅侧墙结构206的厚度优选为500-1000nm。其中，去除多余的氮化硅205可以利用干法刻蚀工艺进行反刻，反刻过程不需要掩膜，反刻的结果是刻蚀掉了绝大部分的氧化硅205，只在栅极的侧壁周围保留了一部分氧化硅205，所保留下来的氧化硅205即为氮化硅侧墙结构206。
步骤六、如图4g所示，在所述栅极两侧形成源极207和漏极208。本实施例中，采用离子注入在所述栅极两侧未被氮化硅侧墙结构206覆盖的半导体衬底200内形成源极207和漏极208。需要注意的是该存储单元制作的过程中并没有进行源漏轻掺杂（LDD），这样可以提高热电子的注入效率。
最后，如图4h所示，去除所述保护层203，露出栅极，以便进行后续的电极连接。
本领域技术人员根据上述方法，可以制作出由该OTP存储单元组成的存储单元阵列，以及与之相匹配的外围电路，由此可形成完整的OTP存储器。将该OTP存储器应用于系统集成芯片或微处理芯片中可以提高系统编码的灵活性，并可极大的节省制造成本。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
上述实施例仅列示性说明本发明的原理及功效，而非用于限制本发明。任何熟悉此项技术的人员均可在不违背本发明的精神及范围下，对上述实施例进行修改。因此，本发明的权利保护范围，应如权利要求书所列。

Claims (14)

  1. 一种OTP存储单元，其特征在于，包括：
    半导体衬底；
    位于所述半导体衬底上的栅介质层；
    位于所述栅介质层上的栅极；
    位于所述栅极周围的氮化硅侧墙结构；
    位于所述栅极与所述氮化硅侧墙结构之间的侧壁介质层；
    以及位于所述栅极两侧的源极和漏极；
    其中，所述氮化硅侧墙结构用于存储电子。
  2. 根据权利要求1所述的OTP存储单元，其特征在于：所述半导体衬底为单晶硅衬底。
  3. 根据权利要求1所述的OTP存储单元，其特征在于：所述栅介质层的材料为氧化硅或高介电常数材料。
  4. 根据权利要求1所述的OTP存储单元，其特征在于：所述栅极的材料为多晶硅。
  5. 根据权利要求1所述的OTP存储单元，其特征在于：所述侧壁介质层的材料为氧化硅。
  6. 根据权利要求1所述的OTP存储单元，其特征在于：所述氮化硅侧墙结构的厚度为500-1000nm。
  7. 根据权利要求1所述的OTP存储单元，其特征在于：所述侧壁介质层的厚度为50-100nm。
  8. 一种OTP存储单元的制作方法，其特征在于，包括以下步骤：
    步骤一、在半导体衬底上形成一层栅介质层，再在所述栅介质层上形成一层栅极材料层；
    步骤二、将所述栅极材料层图形化，形成栅极；
    步骤三、在所述栅极的侧壁形成侧壁介质层；
    步骤四、在侧壁形成有侧壁介质层的栅极上沉积氮化硅，使氮化硅将栅极和侧壁介质层完全包裹；
    步骤五、利用刻蚀工艺去除多余的氮化硅，在侧壁形成有侧壁介质层的栅极周围形成氮化硅侧墙结构；
    步骤六、在所述栅极两侧形成源极和漏极。
  9. 根据权利要求8所述的OTP存储单元的制作方法，其特征在于：步骤一中，所述半导体衬底为单晶硅衬底；所述栅极材料层为多晶硅层。
  10. 根据权利要求8所述的OTP存储单元的制作方法，其特征在于：步骤二中，利用光刻和刻蚀工艺将所述栅极材料层图形化形成栅极。
  11. 根据权利要求8所述的OTP存储单元的制作方法，其特征在于：先在所述栅极材料层表面形成保护层后，再进行步骤二的图形化操作，直到完成步骤六之后再去除所述保护层，露出栅极，以便进行后续的电极连接。
  12. 根据权利要求11所述的OTP存储单元的制作方法，其特征在于：在所述栅极材料层表面沉积高温氧化层作为所述保护层。
  13. 根据权利要求8所述的OTP存储单元的制作方法，其特征在于：步骤三中，利用热氧化法在所述栅极侧壁形成侧壁介质层。
  14. 根据权利要求8所述的OTP存储单元的制作方法，其特征在于：步骤六中，采用离子注入在所述栅极两侧未被氮化硅侧墙结构覆盖的半导体衬底内形成源极和漏极。
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