WO2013080520A1 - Dispositif d'affichage - Google Patents

Dispositif d'affichage Download PDF

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Publication number
WO2013080520A1
WO2013080520A1 PCT/JP2012/007598 JP2012007598W WO2013080520A1 WO 2013080520 A1 WO2013080520 A1 WO 2013080520A1 JP 2012007598 W JP2012007598 W JP 2012007598W WO 2013080520 A1 WO2013080520 A1 WO 2013080520A1
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WIPO (PCT)
Prior art keywords
wiring
lead
display
display device
pixels
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PCT/JP2012/007598
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English (en)
Japanese (ja)
Inventor
慎司 貞光
孝司 上野
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シャープ株式会社
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Publication of WO2013080520A1 publication Critical patent/WO2013080520A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to a display device that performs multi-color display, and in particular, in a display device having a so-called two-layer wiring structure, a reduction in display quality due to variation in effective voltage applied by pixel electrodes between sub-pixels of the same color. It is about measures.
  • red (R), green (G), and blue (B) sub-pixels constituting each pixel are arranged in a scanning direction, so-called.
  • R red
  • G green
  • B blue
  • the number of gate wirings formed in the display area is three times that of normal driving, and correspondingly, each gate wiring is located around the display area and is not displayed.
  • the number of gate lead-out wirings that are routed over the frame region, which is a region, and lead out to the signal input terminal region provided on one end thereof also increases.
  • Patent Document 1 discloses that a plurality of gate lead-out lines are formed using a metal film for forming a gate line and a metal film for forming a source line, and adjacent gate lead-out lines are gate lines and source lines.
  • a two-layer wiring structure formed so as to be positioned above and below an insulating film interposed therebetween is disclosed.
  • the gate lead-out wiring has a lower lead-out wiring formed from a metal film for forming a gate wiring and an upper-layer lead wiring formed from a metal film for forming a source wiring. Alternatingly arranged.
  • the effective voltage applied to the liquid crystal layer between the sub-pixels of the same color varies.
  • a striped pattern is easily visible along the gate wiring, and the display quality is degraded. Resulting in.
  • the present invention has been made in view of such a point, and an object of the present invention is to suppress variation in effective voltage applied by pixel electrodes between sub-pixels of the same color while realizing a narrow frame structure. This is to improve the display quality.
  • each lead-out wiring electrically connected to a thin film transistor (hereinafter referred to as a TFT) included in a sub-pixel of the same color is provided with a common By forming it from a conductive film, it is configured to be unified by the lower layer lead wiring or the upper layer lead wiring.
  • a TFT thin film transistor
  • the present invention is directed to a display device that performs multi-color display, and has the following solutions.
  • the first invention is the above display device, A base substrate; A display area provided on the base substrate; A frame area provided around the display area; A signal input terminal region provided on one end of the frame region; A plurality of first display lines provided in the display area so as to extend in parallel to each other; A plurality of second display wirings provided in the display area so as to extend in parallel to each other in a direction intersecting with the first display wirings; An insulating film interposed between each of the first display wirings and each of the second display wirings to insulate the two wirings; Thin film transistors connected to the first display wiring and the second display wiring that are provided at the intersections of the first display wirings and the second display wirings and that form the corresponding intersections.
  • the display area includes a plurality of pixels each having a plurality of color sub-pixels each having the thin film transistor and the pixel electrode.
  • Each of the first display wirings is connected to a thin film transistor included in a sub-pixel of the same color
  • the plurality of first lead wires include a lower lead wire covered with the insulating film and an upper lead wire provided on the insulating film,
  • One of the lower lead wiring and the upper lead wiring is formed from the same film as the first display wiring, and the other is formed from the same film as the second display wiring and is a contact hole formed in the insulating film.
  • the first display wiring connected to the thin film transistor included in the sub-pixels of the same color is characterized in that the first display wiring is unified and electrically connected to the lower layer leading wiring or the upper layer leading wiring.
  • a plurality of first lead-out wires for leading each first display wire provided in the display region to a terminal region on the frame region are a lower lead-out wire covered with an insulating film, and an insulating film It has a two-layer wiring structure including an upper layer lead wiring provided above. According to this two-layer wiring structure, it is possible to reduce the pitch between the first extraction wirings at the location where the lower layer extraction wiring and the upper layer extraction wiring are adjacent to each other, thereby reducing the width of the frame region. . Further, due to being formed of separate conductive films, the line width and film thickness of the lower layer lead wire and the upper layer lead wire become non-uniform, and the first display wire is interposed between these two lead wires.
  • the lower layer lead line and the upper layer lead line are separated for each color of the sub-pixel for controlling the drive through the electrically connected TFT.
  • a second invention is the display device of the first invention, wherein The lower layer lead wires and the upper layer lead wires constituting the first lead wires are alternately arranged without overlapping each other in a plan view.
  • the lower layer wiring and the upper layer wiring are alternately arranged in a plan view.
  • the lower layer lead wiring and the upper layer lead wiring are arranged so as to overlap each other. An increase in power consumption due to a decrease in display quality due to signal delay and an increase in impedance can be suppressed.
  • a third invention is the display device of the second invention, wherein The plurality of pixels are arranged in a matrix, and each pixel includes four sub-pixels arranged along the second display wiring.
  • each pixel arranged in a matrix is composed of sub-pixels of four colors arranged along the second display wiring. According to such a pixel configuration, it is possible to realize the display device according to the first invention with a simple configuration in which the above-described alternate wiring structure is simply applied.
  • a fourth invention is the display device according to any one of the first to third inventions,
  • the terminal region is provided at an end of the base substrate located on an extension of the second display wiring;
  • the plurality of first lead wires constitutes a first wire group drawn from one side of the display region and a second wire group drawn from the other side of the display region. To do.
  • a so-called double-side lead-out wiring structure in which the first lead-out wiring is drawn from both sides of the display area is provided.
  • the display area can be reduced even if the frame is narrower than the case where a so-called single-side lead-out wiring structure in which all the first lead-out wirings are drawn from only one side of the display area is adopted. It becomes easy to arrange at the center position. Thereby, it becomes possible to employ
  • the fifth invention is the display device of the fourth invention,
  • the first wiring group is composed of an odd number of first lead wiring groups,
  • the second wiring group includes an even number of the second lead wiring groups.
  • the first wiring group and the second wiring group are composed of the same number of first lead wiring groups. According to such a lead-out configuration of the first lead-out wiring, it is possible to narrow the width of both frame area portions where the first wiring group and the second wiring group are provided in a balanced manner.
  • a sixth invention is the display device according to any one of the first to fifth inventions, Each of the first display wirings is a gate wiring, Each of the second display wirings is a source wiring.
  • each first display wiring is a gate wiring
  • each gate wiring is connected to a TFT of a sub-pixel of the same color to perform a triple scan driving.
  • the total number of gate wirings and source wirings is reduced, and the number of gate driver circuits having a relatively simple circuit configuration is increased while the number of source driver circuits having a complicated circuit configuration compared to the gate driver circuit is increased.
  • COG Chip On Glass
  • a driver IC Integrated Circuit
  • a seventh invention is the display device according to any one of the first to sixth inventions, A thin film transistor substrate having a base substrate provided with each of the first display wiring, each second display wiring, an insulating film, each thin film transistor, each pixel electrode, each first extraction wiring, and each second extraction wiring; A counter substrate disposed to face the thin film transistor substrate; And a liquid crystal layer provided between the thin film transistor substrate and the counter substrate.
  • the display device according to the present invention is a liquid crystal display device.
  • the liquid crystal display device a variation in effective voltage applied to the liquid crystal layer between sub-pixels of the same color while realizing a narrow frame structure. It is possible to improve the display quality while suppressing the above.
  • a display region in which pixels each having a first color sub-pixel and a second color sub-pixel are arranged, and a frame region around the display region, and the frame region includes a terminal region. Intended for display devices including
  • the eighth invention is the above display device, A base substrate provided with the terminal region; A pixel electrode provided on the base substrate corresponding to a sub-pixel included in the display area; A thin film transistor electrically connected to the pixel electrode; One wiring for electrically connecting the thin film transistors corresponding to the sub-pixels of the same color among the thin film transistors, Another wiring provided to intersect the one wiring in a plan view and electrically connect the thin film transistor; An insulating film interposed between the one wiring and the other wiring; A lead wire drawn from the one wire to the terminal region; Including a thin film transistor substrate, The lead-out wiring electrically connects the first lead-out wiring led out from one wiring electrically connecting the thin film transistors corresponding to the first color sub-pixels and the thin film transistor corresponding to the second color sub-pixels.
  • the first lead wiring is formed of the same conductive film as the one wiring
  • the second lead wiring is formed of the same conductive film as the other wiring and is electrically connected to the one wiring through a contact hole formed in the insulating film.
  • a ninth invention is the display device of the eighth invention,
  • the pixel further includes a third color sub-pixel,
  • the lead-out wiring includes a third lead-out wiring led out from one wiring that electrically connects the thin film transistors corresponding to the sub-pixels of the third color,
  • the third lead wiring is formed of the same conductive film as the one wiring.
  • the tenth invention is the display device of the ninth invention,
  • the pixel further includes a fourth color sub-pixel,
  • the lead-out wiring includes a fourth lead-out wiring led out from one wiring that electrically connects the thin film transistors corresponding to the sub-pixels of the fourth color,
  • the fourth lead-out wiring is formed of the same conductive film as the other wiring and is electrically connected to the one wiring through a contact hole formed in the insulating film.
  • the eleventh invention is the display device of the tenth invention.
  • the first to fourth color sub-pixels are red, green, blue and yellow sub-pixels.
  • the twelfth invention is the display device of the eighth invention,
  • the pixel further includes a third color sub-pixel,
  • the lead-out wiring includes a third lead-out wiring led out from one wiring that electrically connects the thin film transistors corresponding to the sub-pixels of the third color,
  • the third lead wiring is formed of the same conductive film as the other wiring and is electrically connected to the one wiring through a contact hole formed in the insulating film.
  • the respective extraction wirings electrically connected to the TFTs of the sub-pixels of the same color are formed from a common conductive film, thereby being unified by the lower layer extraction wiring or the upper layer extraction wiring.
  • FIG. 1 is a plan view schematically showing the configuration of the liquid crystal display device according to the first embodiment.
  • 2 is a cross-sectional view showing a cross-sectional structure taken along the line II-II in FIG.
  • FIG. 3 is an enlarged plan view showing the arrangement of pixels and sub-pixels in the display area according to the first embodiment.
  • FIG. 4 is a plan view showing a lead-out configuration of the display wiring of the TFT substrate according to the first embodiment.
  • FIG. 5 is an equivalent circuit diagram illustrating a configuration of one subpixel in the first embodiment.
  • FIG. 6 is a cross-sectional view showing a cross-sectional structure of the TFT.
  • FIG. 7 is an enlarged plan view showing a part of the main configuration of the TFT substrate according to the first embodiment.
  • FIG. 8 is a cross-sectional view showing a cross-sectional structure taken along line VIII-VIII in FIG.
  • FIG. 9 is a cross-sectional view showing a connection structure between the gate wiring and the upper lead wiring.
  • FIG. 10 is a plan view schematically showing the connection relationship between the sub-pixels of each color according to the first embodiment and the gate lead-out wiring that drives them.
  • FIG. 11 is a plan view schematically showing a state in which monochromatic halftone display is performed in the first embodiment.
  • FIG. 12 is a plan view schematically showing a configuration for drawing display wiring on the TFT substrate according to the second embodiment.
  • FIG. 13 is a plan view schematically showing a connection relationship between sub-pixels of respective colors according to the second embodiment and gate lead-out wirings for driving them.
  • FIG. 14 is a plan view schematically showing a state in which monochromatic halftone display is performed in the second embodiment.
  • FIG. 15 is an enlarged plan view showing the arrangement of pixels and sub-pixels in the display area according to the third embodiment.
  • FIG. 16 is a plan view showing a configuration for drawing display wiring of the TFT substrate according to the third embodiment.
  • FIG. 17 is a plan view schematically showing the connection relationship between the sub-pixels of each color according to the third embodiment and the gate lead-out wiring that drives them.
  • FIG. 18 is a plan view schematically showing a state in which monochromatic halftone display is performed in the third embodiment.
  • Embodiment 1 of the Invention In the first embodiment, a liquid crystal display device S that performs full-color display will be described as an example of a display device according to the present invention.
  • FIG. 1 shows a schematic configuration of the liquid crystal display device S of the present embodiment.
  • 2 is a cross-sectional view showing a cross-sectional structure taken along the line II-II in FIG.
  • the liquid crystal display device S includes a liquid crystal display panel 10, a driver IC chip 50 for driving the liquid crystal display panel 10, and an image to be displayed on the driver IC chip 50.
  • a wiring board 60 such as an FPC (Flexible Printed Circuit) for inputting display signals including data corresponding to the external circuit (not shown), and a driver IC chip 50 and wiring on one end side of the liquid crystal display panel 10. It has a COG structure on which a substrate 60 is mounted.
  • FPC Flexible Printed Circuit
  • the liquid crystal display panel 10 is a display element that generates a display image by driving the driver IC chip 50 in accordance with a display signal input via the wiring board 60, and is configured to be capable of triple scan driving.
  • the liquid crystal display panel 10 includes a TFT substrate 11 and a counter substrate 12 that are arranged so as to face each other, a frame-shaped sealing material 13 that bonds the outer peripheral edges of the substrates 11 and 12, and the TFT substrate 11 A liquid crystal layer 14 surrounded and sealed by a sealing material 13 is provided between the counter substrate 12 and the counter substrate 12.
  • the liquid crystal display panel 10 has a rectangular display area D for displaying an image in an area where the TFT substrate 11 and the counter substrate 12 overlap and inside the sealing material 13, that is, in an area where the liquid crystal layer 14 is provided. ing. Further, the liquid crystal display panel 10 has a frame region F having a rectangular frame shape that is a non-display region around the display region D. On one side of the frame region F (lower side in FIG. 1 and left side in FIG. 2), a signal input terminal region 11a is provided in which the TFT substrate 11 protrudes from the counter substrate 12 and is exposed to the outside.
  • the driver IC chip 50 is mounted near the display area D in the terminal area 11a. Further, the wiring board 60 is mounted at a position outside the driver IC chip 50 in the terminal region 11a. The driver IC chip 50 and the wiring board 60 are connected to the terminal region 11a via a connecting material such as ACF (Anisotropic Conductive Film).
  • ACF Anagonal Conductive Film
  • the TFT substrate 11 and the counter substrate 12 are formed in a rectangular shape, for example, and as shown in FIG. 2, alignment films 15 and 16 are provided on the inner surfaces facing each other, and polarizing plates 17 and 18 are provided on the outer surfaces. Are provided.
  • the liquid crystal layer 14 is made of a nematic liquid crystal material having electro-optical characteristics.
  • FIG. 3 shows an enlarged plan view of the pixel configuration in the display area D.
  • a plurality of pixels P which is the minimum unit of an image, are arranged in a matrix.
  • Each of these pixels P is composed of sub-pixels p1 of four colors of red (R, second color), green (G, fourth color), blue (B, first color), and white (W, third color).
  • These four sub-pixels p1 (R), p1 (G), p1 (B), and p1 (W) are striped in a juxtaposed manner along the scanning direction (Y-axis direction) in the same order for all the pixels P. It is installed side by side.
  • sub-pixels p1 of the same color are aligned in the horizontal direction (X-axis direction) in FIG. 3 to form a sub-pixel row for each color, and the vertical direction (Y-axis direction) in FIG.
  • a plurality of four-color sub-pixel rows are periodically arranged.
  • FIG. 4 is a plan view showing a lead-out configuration of the display wirings 21 and 23 on the TFT substrate 11.
  • FIG. 5 is an equivalent circuit diagram showing a configuration of one subpixel p1.
  • FIG. 6 is a cross-sectional view showing a cross-sectional structure of the TFT 24.
  • FIG. 7 is an enlarged plan view showing the main configuration of the TFT substrate 11.
  • 8 is a cross-sectional view showing a cross-sectional structure taken along line VIII-VIII in FIG.
  • FIG. 9 is a cross-sectional view showing a connection structure between the gate wiring 21 and the upper layer extraction wiring 31B.
  • the TFT substrate 11 includes an insulating substrate 20 such as a glass substrate as a base substrate, as shown in FIG.
  • a plurality of gate wirings (one wiring) 21 as first display wirings are provided so as to extend in parallel to each other in the horizontal direction (X-axis direction) in FIG. It has been.
  • Each of these gate wirings 21 is covered with a gate insulating film 22 described later.
  • a plurality of source wirings as second display wirings extend in parallel with each other in the vertical direction (Y-axis direction) in FIG. (Other wiring) 23 is provided.
  • Each gate wiring 21 and each source wiring 23 are insulated by interposing a gate insulating film 22 between these wirings 21 and 23.
  • the gate wiring 21 and the source wiring 23 are formed in a lattice shape so as to partition each sub-pixel p1 as a whole.
  • each subpixel p1 is provided with a TFT 24 and a pixel electrode 30 connected thereto.
  • the TFT 24 is provided at each intersection of each gate line 21 and each source line 23 and is connected to the corresponding gate line 21 and source line 23 that form the intersection.
  • the TFT 24 is a bottom gate type TFT, and includes a gate electrode 25 provided on the insulating substrate 20, and a gate insulating film 22 provided so as to cover the gate electrode 25.
  • a semiconductor layer 26 provided so as to straddle the gate electrode 25 via the gate insulating film 22, and a source electrode 27 and a drain electrode 28 which are partly overlapped with the semiconductor layer 26 and are connected to be separated from each other. And is covered with an interlayer insulating film 29.
  • the gate electrode 25 is connected to the gate wiring 21.
  • the source electrode 27 is connected to the source wiring 23.
  • the pixel electrode 30 is provided on the interlayer insulating film 29 and is connected to the drain electrode 28 through a contact hole formed in the interlayer insulating film 29 (not shown).
  • a stray capacitance C ′ shown in FIG. 5 is formed between the pixel electrode 30 and the gate wiring 21.
  • the TFTs 24 are connected to the same gate wiring 21 separately for each sub-pixel row composed of sub-pixels p1 of the same color aligned in the horizontal direction (X-axis direction) in FIG.
  • Each TFT 24 is connected to the same source wiring 23 separately for each pixel column composed of a plurality of pixels P aligned in the vertical direction (Y-axis direction) in FIG.
  • a plurality of gate lead wires 31 as first lead wires connected to the gate wires 21 and drawn from the display region D side to the terminal region 11a side are provided.
  • a plurality of source lead lines 35 are provided as second lead lines connected to the source lines 23 and led from the display area D side to the terminal area 11 a side.
  • Terminals (not shown) for connection to the driver IC chip 50 are formed along the edge of the TFT substrate 1 at the leading ends of the gate lead-out lines 31 and the source lead-out lines 35.
  • the plurality of gate lead-out lines 31 are alternately drawn out on one side and the other side of the display area D to constitute a double-side lead-out wiring structure.
  • Each gate lead-out line 31 connected to the odd-numbered gate lines 21 from the upper side of the display area D is drawn from one side (left side in FIG. 4) of the display area D to form a first wiring group 32.
  • each gate lead-out line 31 connected to the even-numbered gate lines 21 from the upper side of the display area D is drawn out from the other side (right side in FIG. 4) of the display area D to form the second wiring group 33.
  • the display area D is arranged at the center position of the outer shape of the TFT substrate 1 as compared with the case where a single-side lead-out wiring structure in which all the gate lead-out wirings 31 are drawn from only one side of the display area D is adopted. can do.
  • the first wiring group 32 and the second wiring group 33 are composed of the same number of groups of gate lead-out wirings 31, the widths of both frame regions B provided with these can be narrowed in a balanced manner. .
  • the first wiring group 32 and the second wiring group 33 include a lower lead wiring (first lead wiring, third lead wiring) 31A covered with the gate insulating film 22, a gate,
  • the upper layer lead wiring (second lead wiring, fourth lead wiring) 31B provided on the insulating film 22.
  • the lower layer lead wiring 31A and the upper layer lead wiring 31B are three-dimensionally arranged via the gate insulating film 22 to form a two-layer wiring structure.
  • the lower layer lead wiring 31A and the upper layer lead wiring 31B are alternately arranged without overlapping each other in a plan view to constitute an alternate wiring structure.
  • this alternate wiring structure has an adverse effect on the capacitance formed between the two lead wires 31A and 31B. It is possible to suppress an increase in power consumption due to a decrease in display quality and an increase in impedance due to the delay of the delay.
  • the lower lead line 31 ⁇ / b> A is formed of the same metal film as the gate line 21 and is formed integrally with the gate line 21.
  • the upper lead line 31B is formed of the same metal film as the source line 23 and is connected to one end of the gate line 21 through a contact hole 22a formed in the gate insulating film 22 as shown in FIG. ing.
  • the upper lead line 31B is covered with an interlayer insulating film 29.
  • FIG. 10 shows a schematic plan view of the connection relationship between the sub-pixels p1 of each color and the gate lead-out wiring 31 that drives them in the present embodiment.
  • “GL” is drawn on the lead side of the subpixel row having the TFT 24 to which the lower layer lead-out wiring 31A is electrically connected, and the subpixel row having the TFT 24 to which the upper layer lead-out wiring 31B is electrically connected.
  • “SL” is attached to the drawer side. This also applies to FIGS. 11, 13, 14, 16, and 17 referred to later.
  • the lower lead wiring 31A and the upper lead wiring 31B are formed separately for each color of the sub-pixel p1 having the TFT 24 electrically connected through the gate wiring 21.
  • an upper layer extraction wiring 31B (SL) is electrically connected to the TFT 24 included in the red (R) and green (G) subpixels p1.
  • the lower lead wiring 31A (GL) is electrically connected to the TFT 24 of the blue (G) and white (W) subpixels p1. Accordingly, it is possible to suppress variations in effective voltage applied to the liquid crystal layer 14 by the pixel electrode 30 between the sub-pixels p1 of the same color while realizing a narrow frame structure.
  • the plurality of gate lead-out wirings 31 have a two-layer wiring structure including a lower-layer lead-out wiring 31A covered with the gate insulating film 22 and an upper-layer lead-out wiring 31B provided on the gate insulating film 22. Therefore, the pitch between the lower layer lead-out line 31A and the upper layer lead-out line 31B can be narrowed, whereby the width of the frame region F can be narrowed.
  • the lower lead wiring 31A and the upper lead wiring 31B are formed of separate metal films, so that the line widths and film thicknesses of both the lead wirings 31A and 31B become non-uniform.
  • the lower layer wiring 31A and the upper layer wiring 31B are electrically connected.
  • the subpixels p1 whose driving is controlled via the TFTs 24 are formed separately for each color, so that the potential fluctuation width when the gate wiring 21 is turned off between the pixel electrodes 30 in the subpixels p1 of the same color is formed. It can suppress that a difference arises.
  • a black matrix provided in a lattice shape so as to correspond to the gate wiring 21 and the source wiring 23 on an insulating substrate such as a glass substrate as a base substrate, and the black matrix
  • a red layer, a green layer, a blue layer and a transparent layer provided so as to be periodically arranged corresponding to the subpixels p1 (R), p1 (G), p1 (B), and p1 (W) of each color between the lattices.
  • a plurality of color filters composed of layers, a common electrode 51 provided so as to cover the black matrix and each color filter, and facing the group of the pixel electrodes 30, and a photo spacer provided in a column shape on the common electrode 51 And.
  • the light transmittance in the liquid crystal layer 14 is changed by changing the alignment state of the liquid crystal molecules according to the magnitude of the voltage applied to the liquid crystal layer 14 in the four-color sub-pixels p1 of each pixel P.
  • An image is displayed by adjusting and synthesizing the light transmitted through the four color filters of the red layer, the green layer, the blue layer, and the transparent layer.
  • each gate lead-out wiring 31 electrically connected to the TFT 24 included in the subpixel p1 of the same color is formed from the same metal film, and the lower lead-out wiring 31A or the upper layer Since the lead wiring 31B is unified, the narrow frame structure is realized, and the display quality is improved by suppressing the variation in the effective voltage applied to the liquid crystal layer 14 by the pixel electrode 30 between the sub-pixels p1 of the same color. Can be improved.
  • FIG. 11 is a schematic plan view showing a state in which monochromatic halftone display is performed on the liquid crystal display device S in the present embodiment.
  • FIG. 12 is a plan view showing a lead-out configuration of the gate wiring 21 of the TFT substrate 11 in the second embodiment.
  • the liquid crystal display device S is configured in the same manner as in the first embodiment except that the drawing configuration of the gate wiring 21 of the TFT substrate 11 is different from that in the first embodiment. Only the substrate 11 will be described, and the same components will be left to the description of the first embodiment based on FIGS. 1 to 11, and the detailed description thereof will be omitted.
  • the gate lead-out wiring 31 forms a double-side lead-out wiring structure.
  • each gate lead-out wiring 31 is connected to one side of the display area D (see FIG. 12). It is drawn only from the right side in FIG.
  • the group of gate lead-out wirings 31 is formed on the lower lead-out wiring 31A covered with the gate insulating film 22 and the gate insulating film 22 in the same manner as the first wiring group 32 and the second wiring group 33 in the first embodiment.
  • the upper lead-out wiring 31B is provided, and the two lead-out wirings 31A and 31B constitute a two-layer wiring structure.
  • the lower layer extraction wiring 31A and the upper layer extraction wiring 31B are respectively formed from the same metal film as the gate wiring 21 and the source wiring 23, and are alternately arranged without overlapping each other in plan view. ing.
  • FIG. 13 shows a schematic plan view of the connection relationship between the sub-pixels p1 for each color and the gate lead-out wiring 31 that drives them in the present embodiment.
  • the lower layer lead-out wiring 31A and the upper layer lead-out wiring 31B of this embodiment are also formed separately for each color of the sub-pixel p1 having the TFT 24 electrically connected through the gate wiring 21.
  • the upper layer lead-out wiring 31B (SL, second lead-out wiring) is provided in the TFT 24 of the red (R, second color) and blue (B, fourth color) sub-pixel p1.
  • the fourth lead wiring is electrically connected.
  • the lower layer lead-out wiring 31A (GL, first lead-out wiring, second lead-out wiring) is electrically connected to the TFT 24 of the green (G, first color) and white (W, third color) sub-pixel p1. It is connected.
  • each gate lead-out wiring 31 electrically connected to the TFT 24 included in the subpixel p1 of the same color is formed from the same metal film, and the lower-layer lead-out wiring 31A
  • the upper layer lead wiring 31B is unified, the narrow frame structure is realized, and the variation in the effective voltage applied to the liquid crystal layer 14 by the pixel electrode 30 is suppressed between the sub-pixels p1 of the same color. The quality can be improved.
  • FIG. 14 is a schematic plan view showing a state in which a monochromatic halftone display is performed on the liquid crystal display device S in the present embodiment.
  • FIG. 15 is an enlarged plan view showing a pixel configuration of the display area D in the third embodiment.
  • FIG. 16 is a plan view showing a lead-out configuration of the gate wiring 21 of the TFT substrate 11 in the third embodiment.
  • each pixel P is composed of four sub-pixels p1, but in this embodiment, each pixel P is red (R, second color), green (G, G) as shown in FIG. It consists of sub-pixels p1 of three colors of first color) and blue (B, third color). These three color sub-pixels p1 (R), p1 (G), and p1 (B) are arranged in parallel in a striped manner in a juxtaposed manner along the scanning direction (Y-axis direction) in the same order in all the pixels P. .
  • the gate lead-out wiring 31 is alternately drawn out on one side and the other side of the display area D.
  • the gate wiring groups in units of pixels (hereinafter, simply referred to as gate wiring groups) composed of three gate wirings 21 for driving the three-color sub-pixels p1 (R), p1 (G), and p1 (B)
  • the gate wiring groups composed of three gate wirings 21 for driving the three-color sub-pixels p1 (R), p1 (G), and p1 (B)
  • the first wiring group 32 is configured.
  • the lower one gate wiring 21 of the odd-numbered gate wiring group from the upper side of the display area D and the lower two gate wirings 21 of the even-numbered gate wiring group are on the other side of the display area D (FIG. 16).
  • the second wiring group 33 is formed by being pulled out from the right side.
  • the first wiring group 32 and the second wiring group 33 are provided on the lower lead wiring (first lead wiring) 31A covered with the gate insulating film 22 and the gate insulating film 22, as in the first embodiment.
  • the upper layer lead wiring (second lead wiring, third lead wiring) 31B is constituted by the two lead wirings 31A and 31B to form a two-layer wiring structure.
  • one of the adjacent gate lead lines 31 drawn from the gate line 21 that drives the same pixel row is the lower layer lead line 31A, and the other is the upper layer lead. Wiring 31B.
  • These lower layer lead wiring 31A and upper layer lead wiring 31B are respectively formed from the same metal film as the gate wiring 21 and the source wiring 23, as in the first embodiment.
  • FIG. 17 shows a schematic plan view of the connection relationship between the sub-pixels p1 for each color and the gate lead-out wiring 31 that drives them in the present embodiment.
  • the lower layer lead-out wiring 31A and the upper layer lead-out wiring 31B of this embodiment are also formed separately for each color of the sub-pixel p1 having the TFT 24 electrically connected through the gate wiring 21.
  • the upper layer lead wiring 31B (SL) is electrically connected to the TFT 24 included in the red (R) and blue (B) subpixels p1.
  • the lower layer lead-out wiring 31A (GL) is electrically connected to the TFT 24 of the green (G) sub-pixel p1.
  • each gate lead-out wiring 31 electrically connected to the TFT 24 included in the subpixel p1 of the same color is formed from the same metal film, and the lower-layer lead wiring 31A
  • the upper layer lead wiring 31B is unified, the narrow frame structure is realized, and the variation in the effective voltage applied to the liquid crystal layer 14 by the pixel electrode 30 is suppressed between the sub-pixels p1 of the same color. The quality can be improved.
  • FIG. 18 is a schematic plan view showing a state in which a monochromatic halftone display is performed on the liquid crystal display device S in the present embodiment.
  • the upper layer lead wiring 31B (SL) is electrically connected to the TFT 24 included in the red (R) and blue (B) subpixels p1, and the TFT 24 included in the green (G) subpixel p1.
  • the lower lead line 31A (GL) is electrically connected to the TFT 24, but the present invention is not limited to this.
  • the TFT 24 included in the red (R, second color) sub-pixel p1 includes the upper lead line 31A (GL).
  • the wiring 31B (SL) is electrically connected, and the lower lead wiring 31A (GL) is electrically connected to the TFT 24 of the blue (B, first color) and green (G, third color) subpixels p1. It may be connected.
  • the liquid crystal display panel 10 is configured to be capable of triple scan driving.
  • the present invention is not limited to this, and the liquid crystal display panel 10 is driven by a so-called single scan driving. (Normal drive) may be possible.
  • the sub-pixels p1 of a plurality of colors that constitute each pixel P are arranged side by side in a stripe manner along a direction orthogonal to the scanning direction.
  • the source wiring 23 constitutes the first display wiring (one wiring) of the present invention
  • the gate wiring 21 forms the second display wiring (others) of the present invention. Wiring).
  • the group of source lead lines 35 that are first lead lines includes a lower lead line (second lead line, or a second lead line and a fourth lead line) covered with the gate insulating film 22, and the gate insulating film 22.
  • the upper layer lead wiring (the first lead wiring, or the first lead wiring and the third lead wiring) is provided on the upper layer, and the two lead wirings constitute a two-layer wiring structure.
  • the lower layer lead wiring and the upper layer lead wiring are respectively formed from the same metal film as the gate wiring 21 or the source wiring 23 as in the first embodiment.
  • the lower layer lead wiring and the upper layer lead wiring are formed separately for each color of the sub-pixel p1 having the TFT 24 electrically connected through the source wiring 23.
  • the effective voltage applied to the liquid crystal layer 14 by the pixel electrode 30 between the sub-pixels p1 of the same color while realizing a narrow frame structure even in the liquid crystal display device S that performs single scan driving.
  • Display quality can be improved by suppressing variations in the display quality.
  • the sub-pixels p1 of four colors of red (R), green (G), blue (B), and white (W) are arranged in stripes in a juxtaposed manner. Even if the color sub-pixels p1 are in other arrangements, the purpose of this patent is not affected as long as the gate wirings 21 are wired so as to be connected in common to the sub-pixels p1 of the same color.
  • the four color sub-pixels p1 may not be red (R), green (G), blue (B), and white (W), and a combination of sub-pixels p1 of various colors can be employed. For example, red (R), green (G), blue (B), and yellow (Y) may be used.
  • each pixel P is composed of four-color sub-pixels p1 (R), p1 (G), p1 (B), and p1 (W).
  • each pixel P is Although the three-color sub-pixels p1 (R), p1 (G), and p1 (B) are described, the present invention is not limited to this, and each pixel P may be formed of two-color sub-pixels p1.
  • each TFT 24 included in each sub-pixel p1 is a bottom-gate TFT.
  • the present invention is not limited to this, and each TFT 24 may be a top-gate TFT. .
  • the liquid crystal display device S has been described as an example.
  • the present invention is not limited to this, and is naturally applicable to other display devices such as an organic EL (ElectroLuminescence) display device and a plasma display device. Any color display device having a two-layer wiring structure can be widely applied.
  • the present invention is useful for a display device that performs multi-color display, and in particular, while realizing a narrow frame structure, variation in effective voltage applied by pixel electrodes between sub-pixels of the same color. It is suitable for a display device that is required to suppress and improve display quality.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

La présente invention concerne un dispositif d'affichage qui peut atténuer les réductions de qualité d'affichage causées par un motif rayé survenant le long du câblage de grille dans une structure de câblage à deux couches. La présente invention est constituée de telle sorte que, dans la structure de câblage à deux couches, les fils de câblage de grille (31) connectés électriquement à des TFT pour les sous-pixels de même couleur sont rendus uniformes en tant que fils de câblage de couche inférieure (31A) ou fils de câblage de couche supérieure (31B). Tout en obtenant une structure de châssis étroite, les variations de tension efficace appliquée à une couche de cristaux liquides par des électrodes de pixel entre les sous-pixels de même couleur sont supprimées et cette configuration améliore la qualité d'affichage.
PCT/JP2012/007598 2011-11-30 2012-11-27 Dispositif d'affichage WO2013080520A1 (fr)

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JP2011262700 2011-11-30
JP2011-262700 2011-11-30

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WO2015033840A1 (fr) * 2013-09-09 2015-03-12 シャープ株式会社 Substrat à matrice active et dispositif d'affichage
CN104700813A (zh) * 2015-04-01 2015-06-10 上海中航光电子有限公司 阵列基板及其形成方法
CN111971731A (zh) * 2018-03-28 2020-11-20 夏普株式会社 显示设备及显示设备的制造方法
CN112136169A (zh) * 2018-05-22 2020-12-25 夏普株式会社 显示装置

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JP2005091962A (ja) * 2003-09-19 2005-04-07 Sharp Corp 電極配線基板および表示装置
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JP2008064961A (ja) * 2006-09-06 2008-03-21 Mitsubishi Electric Corp 配線構造、及び表示装置
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WO2015033840A1 (fr) * 2013-09-09 2015-03-12 シャープ株式会社 Substrat à matrice active et dispositif d'affichage
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CN112136169A (zh) * 2018-05-22 2020-12-25 夏普株式会社 显示装置
CN112136169B (zh) * 2018-05-22 2022-04-29 夏普株式会社 显示装置

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