WO2013077577A1 - 클럭 임베디드 소스 싱크로너스 반도체 송수신 장치 및 이를 포함하는 반도체 시스템 - Google Patents
클럭 임베디드 소스 싱크로너스 반도체 송수신 장치 및 이를 포함하는 반도체 시스템 Download PDFInfo
- Publication number
- WO2013077577A1 WO2013077577A1 PCT/KR2012/009438 KR2012009438W WO2013077577A1 WO 2013077577 A1 WO2013077577 A1 WO 2013077577A1 KR 2012009438 W KR2012009438 W KR 2012009438W WO 2013077577 A1 WO2013077577 A1 WO 2013077577A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- differential
- clock signal
- data
- signal
- clock
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/06—Speed or phase control by synchronisation signals the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
Definitions
- the present invention relates to a semiconductor transceiver and a semiconductor system including the same, and more particularly, to a semiconductor transceiver and a semiconductor system including the same, which transmit data between a semiconductor device and a system by using clock embedded source synchronous signaling.
- a clock signal of a certain frequency is required and information about the clock signal is transmitted from the transmitter to the receiver to enable data recovery.
- known data transfer methods between semiconductor chips include clock-forwarded signaling and clock-embedded signaling.
- the former has a separate pin for transmitting a clock signal in addition to a pin for data transmission, and provides a clock signal for restoring directly to a receiver.
- a semiconductor memory chip and a CPU requiring multiple data transmission / reception channels are required. It is widely used for the large data transmission / reception method.
- This method also known as source-synchronous signaling, means that the clock signal is sent directly to synchronize.
- the latter uses a clock and data recovery (CDR) circuit for this role by extracting the transition information of the transmitted differential data signal itself from the receiver and restoring the clock signal itself and using it for data recovery.
- CDR clock and data recovery
- bit-error rate (BER) loss due to noise existing in / outside the chip becomes an important issue.
- Such noise is represented as jitter noise in which the transition time of the data signal is changed by power supply lines inside and outside the semiconductor chip. Since the symbol period, which represents the period of one bit of data, decreases as the data rate increases, the effect of jitter noise increases with increasing speed, and thus serves as an important factor to limit the limit rate.
- jitter noise affects the data signal and the clock signal differently, the receiver and the clock recover the data when the data is recovered.
- the latter case has historically been used to transmit and receive data over a long distance by using a transmission cable.
- the differential data in the transmission unit is used.
- the receiver recovers the clock signal from the information that the received digital data changes from 0 to 1, or 1 to 0, and uses it for data restoration. As a result, it is being applied to many semiconductor circuits.
- the CDRs used at this time are not only complicated circuits, but also the time delay of the CDRs themselves can not reflect the jitter noise of the data signal rapidly changing due to the power supply noise to the clock signal fast enough to increase the BER in high-speed data transmission and reception Acts as This approach also has the disadvantage of lowering power efficiency because the CDR must be operated continuously while data is being transmitted.
- the present invention is to improve the problem of the transmission and reception method between the conventional semiconductor chip, by mounting a clock signal in the differential data signal, and transmits the signal separated from the receiver and then used for data recovery problem in the conventional clock forwarded signaling method
- the data recovery capability is increased by minimizing the path difference between the transmission and reception of the in-data and the clock signal, and the power efficiency is reduced and the area burden of the transmission / reception circuit is reduced by eliminating the burden of the complex CDR circuit compared to the clock embedded signaling method. Disclosure of Invention It is an object of the present invention to provide a semiconductor transceiver device using the embedded source synchronous signaling, and a semiconductor system including the same.
- a semiconductor device may include a data providing unit providing differential data, a first clock signal provided to the data providing unit, and a second clock signal having a phase different from that of the first clock signal.
- a multi-phase clock generator for generating and a signal combiner for receiving the differential data and the second clock signal and combining them to generate a combined signal, wherein the second clock signal is a single clock signal and a symbol of the differential data It has n times (n is an integer of 2 or more) of the period, the first clock signal and the second clock signal has a phase difference of 90 degrees, characterized in that for transmitting the combined signal to the outside through a differential transmission line.
- the semiconductor system includes a first semiconductor device for receiving a differential reception signal through a differential transmission line, the first semiconductor device, A differential equalizer for selectively amplifying a high frequency band of the differential reception signal, a differential data recovery unit for amplifying a differential signal from the differential output of the differential equalizer, and restoring differential data, and extracting a common mode signal from the differential output of the equalizer A differential clock recovery unit for restoring a single clock signal and converting the restored single clock signal into a differential clock signal to generate a differential clock signal having a predetermined phase difference from the differential data; A data sampling unit for sampling the differential data using It is characterized by including.
- FIG. 1 is a block diagram illustrating an example of a semiconductor system and a semiconductor device according to an embodiment of the present invention.
- FIG. 2 is a block diagram illustrating an embodiment of the semiconductor system and the semiconductor device of FIG. 1.
- FIG. 3 is a circuit diagram illustrating an example of implementing a data driver, a clock driver, a signal combiner, and a filter of FIG. 2.
- FIG. 4 is a timing diagram illustrating an example of a signal transmitted through a transmission channel in the semiconductor system of FIG. 2.
- FIG. 5 is a diagram illustrating an example of a frequency spectrum of a transmission stage output when a symbol period of differential data is T.
- FIG. 6 is a circuit diagram illustrating two examples according to a common mode signal converter implementation as an example of implementing a differential equalizer including a common mode signal converter.
- FIG. 7 is a diagram illustrating frequency characteristics between input and output of the differential equalizer of FIG. 6.
- FIG. 8 is a circuit diagram illustrating an example of implementing a single-differential conversion (STD) circuit for the clock signal of FIG. 2.
- STD single-differential conversion
- FIG. 9 is a block diagram illustrating an example of a semiconductor device according to example embodiments of inventive concepts.
- FIG. 10 is a block diagram illustrating an example of a semiconductor device in a case where a common mode signal converter sharing a part of a differential equalizer circuit is used as in FIG. 6B.
- FIG. 11 is a block diagram illustrating an example of a semiconductor device according to example embodiments of the inventive concepts.
- FIG. 12 is a block diagram illustrating an embodiment of a semiconductor system in accordance with still another embodiment of the present invention.
- FIG. 13 is a block diagram illustrating an embodiment of a semiconductor system in accordance with still another embodiment of the present invention.
- FIG. 14 is a block diagram illustrating an embodiment of a semiconductor system in accordance with still another embodiment of the present invention.
- FIG. 15 is a block diagram illustrating an example embodiment of the semiconductor system and the semiconductor device of FIG. 14.
- FIG. 16 is a circuit diagram illustrating two implementations of the common mode signal converter of FIG. 15.
- the semiconductor system 100 includes a first semiconductor device 1000 for signal transmission and a second semiconductor device 2000 for signal reception.
- a transmission channel for transmitting and receiving a signal is disposed between the first semiconductor device 1000 and the second semiconductor device 2000.
- Each of the first semiconductor device 1000 and the second semiconductor device 2000 may be implemented as a semiconductor chip, a semiconductor package, or the like.
- the first semiconductor device 1000 is illustrated as a transmission chip for transmitting a signal and the second semiconductor device 2000 is a reception chip for receiving a signal, each semiconductor device is configured to transmit a signal and a signal. It can include any configuration for receiving.
- the first semiconductor device 1000 may further include components included in the second semiconductor device 2000 in addition to the components provided therein.
- the first semiconductor device 1000 combines a clock signal with differential signal data and transfers the combined signal to the second semiconductor device 2000 through a differential transmission line. send.
- the receiver also minimizes the difference between the differential data recovery path and the clock signal recovery path at high speed It has an advantageous structure.
- the first semiconductor device 1000 may include a data provider 1100, a multi-phase clock generator 1200, a data driver 1300, a clock driver 1400, and a signal combiner 1500. ) May be provided.
- the data provider 1100 receives the differential data generated in the first semiconductor device 1000 and outputs the same in synchronization with a predetermined clock.
- differential data txdat and txdatb are generated in the first semiconductor device 1000 and provided to the data provider 1100, and the data provider 1100 is provided from the multi-phase clock generator 1200.
- the differential data txdat and txdatb are provided to the data driver 1300 in response to at least one clock signal.
- the data driver 1300 receives the differential data txdat and txdatb and performs a driving operation to have a driving force for transmitting the received differential data txdat and txdatb through the differential transmission line.
- the multi-phase clock generator 1200 generates at least two clock signals having different phases. At least one of the generated clock signals is provided to the data provider 1100 to control the timing of providing the differential data txdat and txdatb. In addition, at least one of the generated clock signals is provided to the clock driver 1400, and the clock driver 1400 performs a driving operation on the received clock signal and provides it to the signal combiner 1500.
- the signal combiner 1500 combines and outputs the received differential data txdat and txdatb and a clock signal. The signal combiner 1500 may combine the signals by adding the differential data txdat and txdatb and a clock signal. .
- the data provider 1100 outputs differential data txdat and txdatb according to a predetermined symbol period.
- the multi-phase clock generator 1200 generates two or more clock signals having a period of n times (n is an integer of 2 or more) of the symbol period of the differential data txdat and txdatb. For example, assuming that at least one clock signal provided to the data provider 1100 is a first clock signal, and that at least one clock signal provided to the clock driver 1400 is a second clock signal. The first clock signal and the second clock signal have a predetermined phase difference.
- the first clock signal and the second clock signal have a period twice as long as the symbol period of the differential data (txdat, txdatb), and the first clock signal and the second clock signal have a phase difference of 90 degrees with each other.
- the signal combiner 1500 combines the differential data txdat and txdatb with a second clock signal having a phase difference of about 90 degrees, and outputs the combined signals comsig and comsigb through the differential transmission line.
- the second semiconductor device 2000 receives the combined signals comsig and comsigb through the differential transmission line, and thereby the differential data and the clock signal from the differential combined signal of which the high frequency band is amplified. Restore it.
- the second semiconductor device 2000 may include a differential equalizer 2050, a differential data recovery unit 2100, a differential clock recovery unit 2200, and a data sampling unit 2300.
- Combined signals (comsig, comsigb) transmitted through the differential transmission line is converted into a differential signal amplified by a high frequency band through a differential equalizer 2050 and provided to the differential data recovery unit 2100 and the differential clock recovery unit 2200, respectively. do.
- the differential equalizer 2050 accepts the received differential combined signal (comsig, comsigb) as an input to compensate for the signal loss of the high frequency band caused by the differential combined signal sent from the transmitter through a narrow transmission channel.
- the amplified differential combined signal is provided to the differential data recovery unit 2100 and the differential clock recovery unit 2200, respectively.
- the differential data recovery unit 2100 performs a processing operation on the differentially coupled signal in which the high frequency band is amplified and extracts differential data therefrom.
- the differential clock recovery unit 2200 extracts the differential clock signal from the differential clock signal by performing a processing operation on the differentially coupled signal in which the high frequency band is amplified.
- the differential clock recovery unit 2200 in extracting a differential clock signal from a high frequency band amplified differential combined signal, performing a first processing operation on the high frequency band amplified differential combined signal to extract a single clock signal, And performing a second processing operation on the single clock signal to generate a differential clock signal.
- the extracted differential data and the differential clock signal are provided to the data sampling unit 2300.
- the data sampling unit 2300 outputs differential data in synchronization with the differential clock signal.
- the output of the data sampling unit 2300 is transferred into the second semiconductor device 2000 as received data rxdat and rxdatb.
- FIG. 2 is a block diagram illustrating an embodiment of the semiconductor system and the semiconductor device of FIG. 1.
- the data providing unit 1100 may be implemented by including a multiplexer.
- a 2: 1 multiplexer may be applied to the multiplexer.
- the data provider 1100 receives differential data and multiplexes it to output the differential data.
- two differential data txdat1, txdat1b, txdat2, and txdat2b are provided to the data provider 1100, and at least one clock signal is provided from the multi-phase clock generator 1200 to the data provider 1100.
- the multi-phase clock generator 1200 may be implemented as a four-phase clock source for generating four different phase signals.
- the first clock signals having phases of 0 degrees and 180 degrees may be provided by the data provider 1100. Is provided.
- the data provider 1100 outputs the differential data txdat1, txdat1b, txdat2, and txdat2b in synchronization with a first clock signal.
- the first differential data txdat1 and txdat1b are output in synchronization with a first clock signal having a phase of 0 degrees
- the second differential data txdat2 and txdat2b are synchronized with a first clock signal having a phase of 180 degrees.
- the data provider 1100 outputs the differential data output at twice the data rate, and the symbol period of the differential data output from the data provider 1100 is 1/2 of the period of the clock signal. have.
- the output of the data provider 1100 is applied to the data driver 1300, and is transmitted to the differential transmission channel outside the first semiconductor device 1000 through the signal combiner 1500.
- at least one second clock signal from the multi-phase clock generator 1200 is provided to the signal combiner 1500 through a predetermined delay unit 1600 and a clock driver 1400.
- the second clock signal is a single clock signal and may have a phase difference of 90 degrees compared to a first clock signal having a phase of 0 degrees and a phase of 180 degrees provided to the data provider 1100.
- at least one of a single clock signal having a phase of 90 degrees and a phase of 270 degrees relative to the first clock signal is provided to the signal combiner 1500 via the clock driver 1400 as a second clock signal.
- FIG. 2 illustrates an example in which second clock signals having a phase of 90 degrees and a phase of 270 degrees are provided to the clock driver 1400, but only one single clock signal having a phase of 90 degrees or 270 degrees is clocked as a second clock signal. It may be provided to the driver 1400.
- the delay unit 1600 and a filter may be further provided in the first semiconductor device 1000. That is, in order to compensate for the phase difference between the differential data and the second clock signal, the input signal may be adjusted according to a delay time equivalent to the delay between the clock and the output in the data provider 1100, which may be implemented as a 2: 1 multiplexer or the like.
- a delay unit 1600 for delaying is provided.
- the second clock signal is provided to the clock driver 1400 via the delay unit 1600, and the output of the clock driver 1400 is added to the differential data at the final stage of the transmitter.
- the signal combiner 1500 may include one or more summers for summing signals, and the differential data and the clock signal are summed at the final stage through the same delay time path.
- the delay unit 1600 is illustrated as being arranged to delay the second clock signal, the delay unit 1600 may be arranged to delay the differential data.
- the filter 1700 may be arranged to amplify the high frequency component of the output of the clock driver 1400.
- the arrangement of the filter 1700 may reduce interference with differential data in a low frequency band at the time of signal coupling, and also generate an effect of amplifying the clock frequency of the second clock signal. Accordingly, under the same power use condition, the voltage of the recovered clock signal can be increased and jitter can be reduced.
- FIG. 3 is a circuit diagram illustrating an example of implementing the data driver 1300, the clock driver 1400, the signal combiner 1500, and the filter 1700 of FIG. 2.
- the data driver 1300 For convenience of description, an example in which differential data txdat and txdatb from the data provider 1100 is provided to the data driver 1300 is illustrated.
- the differential data txdat and txdatb are applied to an input terminal of the data driver 1300 including the MOS transistors M1 and M2, and the second clock signal clock is a clock driver including the MOS transistors M3 and M4. Are applied to the input terminals of 1400, respectively.
- the output of the data driver 1300 and the output of the clock driver 1400 are connected and coupled to each other. At this time, current sources for supplying a constant current to each driver are separated from each other.
- the capacitance Cs connected in parallel to the current source portion of the clock driver 1400 is a filter (for example, a high pass filter, 1700) by adding one zero and one pole to the clock driver 1400 frequency characteristics. ).
- the arrangement of the filter 1700 may reduce the clock driving constant current source, thereby reducing power consumption and reducing the jitter component.
- FIG. 4 is a timing diagram illustrating an example of a signal transmitted through a transmission channel in the semiconductor system of FIG. 2.
- a single-ended clock is a single clock signal having a phase difference of 90 degrees from a transition point of differential data, and the clock signal is delayed by half of the symbol period of the differential data signal ( 90 degrees phase difference) based on clock frequency.
- the time delay difference from the transition point of the optimal clock signal may be defined as t.
- the t value may have a positive value or a negative value.
- the cross point voltages of the combined signals constitute two voltage levels. do.
- the added clock signal has a somewhat smaller voltage magnitude than the data signal.
- the combined output signal passes through a bandwidth-limited circuit or communication channel, it produces jitter (data-dependent jitter or DDJ) that varies with the pattern of the data signal, because when the clock signal changes, the variation of the data signal around the data changes. This is affected by the direction, which increases the jitter amount as the absolute value of the t value increases and as the transition time increases.
- the generated jitter is concentrated in the clock signal to be restored.
- the most optimal signal recovery is possible when the transition time of the differential data and clock signal is 90 degrees out of phase with respect to the clock frequency.
- a symbol period of data is defined as a minimum time unit representing 1 or 0 digital data.
- T its inverse is called a symbol rate.
- the frequency spectrum of the transmission stage output data and the clock is shown in FIG. 5. That is, the frequency of the added clock signal is located at a half point of the symbol transmission rate (1 / T).
- a receiver equalizer used to selectively amplify only a high frequency band to compensate for a loss due to a limited bandwidth of a transmission channel serves to selectively amplify a frequency band near 1/2 of a symbol transmission rate.
- the recovery of the clock signal having the clock period corresponding to twice the symbol period of the differential data can be used by sharing the amplification frequency band of the differential equalizer 2050.
- the differential equalizer Common mode signal converters CMC included in the differential data recovery unit 2100 and for extracting and amplifying only a clock signal may be positioned in the differential clock recovery unit 2200 to have separate amplified frequency bands.
- the second semiconductor device 2000 may use a differential equalizer 2050 that amplifies a high frequency band of the differential reception signal.
- the circuit may further include a delay circuit 2400 delaying and outputting the restored differential clock signal by a predetermined time t2.
- the differential equalizer 2050 amplifies a specific high frequency band of the received differential combined signal with a specific amplification to a specific amplification for the purpose of compensating for the signal loss of the high frequency band caused by the narrow frequency bandwidth of the communication channel between the transmitting end and the receiving end. It increases the signal margin of the hour.
- 6 illustrates a source-degenerative differential amplifier circuit as an example of implementing a differential analog equalizer.
- the output stage load (ZL) may be configured as a resistor or an LC-tank circuit.
- the frequency band to be amplified and the amplification degree are determined according to the frequency characteristic of the equivalent impedance Zs facing the ground from the source terminal of M1 / M2 to the frequency characteristic of the given output terminal ZL.
- the frequency band and the degree of amplification are determined by adjusting the Rs value and the Cs value.
- one or more adjusting terminals Veq_ctl are provided for this purpose.
- the output of the equalizer 2050 has a high frequency band.
- the amplified combined signal is provided to the differential data recovery unit 2100 and the differential clock recovery unit 2200.
- the differential data recovery unit 2100 may include one or more differential amplifiers 2110 and 2120 for recovering differential data by obtaining a difference between the combined signals.
- Each of the amplifiers 2110 and 2120 may be implemented as a differential amplifier that receives a differential input and amplifies it to generate a differential output.
- the differential clock recovery unit 2200 may include a common-mode signal converter (CMC) 2210, a single-to-differential signal converter 2220 to obtain a sum of the combined signals, Or a STD circuit) and a differential amplifier 2230.
- the common mode signal converter (CMC) is also called a common-mode signal amplifier (CMS).
- the differential data recovery unit 2100 uses one or more amplifiers 2110 and 2120 to extract and amplify only differential data from the differential equalizer output signal in which the high frequency band is amplified and outputs the output.
- the data sampling unit 2300 is provided.
- the data sampling unit 2300 may include one or more sampling circuits (or sampling flip-flops 2310 and 2320).
- the clock signal included in the differentially coupled signal in which the high frequency band is amplified is regarded as a common mode signal by the differential amplifiers 2110 and 2120 and removed.
- a common mode signal converter (CMC) 2210 may be used to recover the clock signal from the differentially coupled signal with the high frequency band amplified.
- the common mode signal converter 2210 is a reciprocal of the differential amplifier concept.
- the common mode signal converter 2210 performs a summing of differential coupled signals to extract or amplify a common mode signal and attenuate the differential signal.
- 6A and 6B illustrate an example of implementing the common mode signal converter 2210.
- the common mode signal converter 2210 includes a resistor distribution circuit to perform the above function as illustrated in FIG. 6A. can do.
- the common mode signal converter 2210 uses separate amplifier circuits M3 and M4 that receive the received differential signal.
- the output load (ZL) can be implemented with a simple resistor, but LC-resonance or inductive-peaking structures with inductance can be used to improve amplification and accuracy.
- the common mode signal converter 2210 shown in FIG. 6B receives the differential received signal as the inputs of the separate amplifiers M3 and M4, extracts and amplifies the common mode signal by summing, and restores the recovered single clock signal.
- the output of the differential equalizer can be differentiated from the case of FIG. That is, in FIG. 6B, a part of the BPF function of the differential equalizer is shared with the common mode amplifier circuit, and the amplifier source terminal equivalent impedance (Zs) 2040 of FIG. 6B is shared. To become a target. As described above, by sharing a portion of the differential equalizer and the common mode amplifier circuit, power consumption due to the separated common mode amplifier stage 2210 of FIG. 2 may be reduced.
- FIG. 7 is a diagram illustrating the frequency characteristics between the input and the output of the differential equalizer 2050 circuit of FIG. 6.
- a band filter including one zero and z1 and two poles p1 and p2 in frequency analysis. (BPF) characteristics.
- BPF frequency analysis.
- the position of zero z1 is determined by Rs and Cs of the source terminal and is represented by 1 / (Rs * Cs).
- the first pole p1 can be expressed as (1 + gm * Rs / 2) / (Rs * Cs).
- the second pole p2 is the pole determined by the output terminal ZL. If ZL is composed of the parallel connection of the resistor RL and the capacitance CL, the position may be represented as 1 / (RL * CL).
- the differential equalizer 2050 and the common mode signal converter 2210 share a Zs circuit having an equivalent impedance seen from the source terminal of the differential equalizer toward the ground. Accordingly, the frequency characteristics of the differential equalizer and the common mode signal converter may have characteristics of sharing the positions of the zero pole z1 and the first pole p1 of FIG. 7.
- the position of the second pole p2 can be defined separately for each ZL of the differential equalizer and common-mode signal converter.
- the single clock signal is restored by the common mode signal converter 2210 of FIG. 2, and the restored single clock signal is provided to an input of the single-differential conversion circuit (STD circuit) 2220.
- the STD circuit 2220 converts a single clock signal into a differential clock signal.
- the STD circuit 2220 may have a circuit having a common-source common-drain (CS-CD) structure as shown in FIG. 8. It can be implemented with active BALUN circuit which is widely used in RF circuit to increase amplification degree. In this case, a circuit for correcting a phase offset of the restored differential clock signal may also be included.
- the capacitor Cc illustrated in FIG. 8 may be used.
- the recovered differential clock signal is amplified through the differential amplifier 2230 and then provided to the delay circuit 2400.
- a delay time difference may occur between the delay time of the data recovery path and the path delay time of the clock recovery circuit, and the delay circuit 2400 performs a delay operation on the differential clock signal by the delay time difference and samples the output thereof.
- section 2300 Provided to section 2300.
- the data sampling unit 2300 may include one or more sampling circuits.
- the data sampling unit 2300 may include first and second sampling circuits 2310 and 2320 as illustrated in FIG. 2.
- the differential data from the differential data recovery unit 2100 is provided to the input terminals of the first and second sampling circuits 2310 and 2320, respectively, and the differential clock signals from the differential clock recovery unit 2100 are respectively provided.
- the clock stages of the sampling circuits 2310 and 2320 are respectively provided.
- the first and second sampling circuits 2310 and 2320 respectively sample the differential data by means of differential clock signals having opposite phases. Accordingly, the symbol period of the differential data signal output by the data sampling unit 2300 is It has the same value as the period of the differential clock signal.
- the outputs rxdat1, rxdat1b, rxdat2, and rxdat2b of the data sampling unit 2300 are received differential data and are provided inside the second semiconductor device 2000.
- 9 is a block diagram illustrating an example of a semiconductor device according to example embodiments of inventive concepts. 9 illustrates an embodiment of the first semiconductor device 1000 for transmitting differential data.
- the first semiconductor device 1000 may include a multiplexer 1100 as a data provider, a clock source 1200 as a clock generator, a data driver 1300, a clock driver 1400, and a phase shifter. 1700). Since the multiplexer 1100, the data driver 1300, and the clock driver 1400 operate the same as or similar to those illustrated in FIG. 1, a detailed description thereof will be omitted.
- the clock source 1200 may generate only one single clock signal, or may generate two single clock signals having phases opposite to each other. As an example, a single clock signal having a phase of 0 degrees and 180 degrees, respectively, is generated and provided to the multiplexer 1100. The differential data as an output of the data driver 1300 is provided to the signal combiner 1500.
- the single clock signal is provided to the phase shifter 1700, and the phase shifter 1700 adjusts the phase of the received single clock signal to provide the signal combiner 1500 through the clock driver 1400.
- the phase shifter 1700 receives the same clock signal as the single clock signal provided to the multiplexer 1100, adjusts the phase, and outputs the same.
- the phase shifter 1700 is arranged to determine the phase of a single clock signal to be combined with the differential data, and preferably adjusts the phase of the single clock signal provided from the clock source 1200 by 90 degrees. Accordingly, the signal combiner 1500 combines the differential data with a single clock signal 90 degrees phase-adjusted thereto to generate a combined signal having a waveform as shown in FIG. 4.
- FIG. 10 is a block diagram illustrating an embodiment of a semiconductor system in accordance with still another embodiment of the present invention.
- FIG. 10 illustrates an example of the second semiconductor device 3000 for sharing some functions of the differential equalizer with the common mode signal converter as shown in FIG. 6B.
- the received differential signal is applied to an input of each of the differential equalizer 3050 and the common mode signal converter 3030.
- the differential equalizer 3050 and the common mode signal converter 3030 may reduce the power consumption by having an area 3040 shared with each other, and the differential signal output of the differential equalizer 3050 may be transferred to the data recovery unit 3100.
- the single clock output applied and recovered from the common mode signal converter 3030 is applied to the STD 3210 circuit of the differential clock recovery unit 3200 and converted into a differential clock signal.
- the differential clock recovery unit 3200 of FIG. 10 may include a single-differential signal converter (STD) 3210 and a differential amplifier 3220.
- STD single-differential signal converter
- FIG. 11 is a block diagram illustrating an embodiment of a semiconductor system in accordance with still another embodiment of the present invention.
- FIG. 11 illustrates an example of the second semiconductor device 4000 which recovers high frequency band amplification, differential data, and differential clock signals using differential reception signals.
- the differential data output from the data recovery circuit 4100 is provided to the differential input terminals of the sampling circuits of the data sampling unit 4300, while the differential clock signal output through the clock recovery circuit 4200 and the delay circuit 4400 is provided.
- Each is provided by a single clock stage of sampling circuits.
- one of the differential clock signals is provided to a single clock stage of the first sampling circuit 4310, and the other one of the differential clock signals is to a single clock stage of the second sampling circuit 4320. Is provided.
- the first and second sampling circuits 4310 alternately sample the differential data, and accordingly, symbol periods of the differential receive data (rxdat1, rxdat1b, rxdat2, and rxdat2b). Has the same value as the period of the differential clock signal.
- FIG. 12 is a block diagram illustrating an embodiment of a semiconductor system in accordance with still another embodiment of the present invention.
- FIG. 12 illustrates an example of the second semiconductor device 5000 which restores the differential data and the differential clock signal by using the differential reception signal.
- the clock recovery circuit 5200 includes an injection-locked frequency divider (ILFD) circuit, and applies a differential clock signal output restored by the STD circuit to the ILFD circuit to divide the frequency in half and simultaneously provide four phase signals. Create A control signal can be provided to the ILFD circuit to adjust the delay of the output phase for optimal data sampling. This control signal changes the self-resonance frequency of the ILFD, which changes the phase of the output from the difference from the input frequency.
- the clock recovery circuit 5200 may be implemented by including a phase delay circuit and a general frequency division circuit in place of the ILFD circuit.
- the data sampling unit 5300 may include four sampling circuits, and an optimal sampling phase may be obtained through training at an initial stage of driving, which scans all adjustable ranges. Afterwards, a well-known method can be introduced as a method of finding an optimal condition.
- the optimal phase condition is the point where the setup and hold time of the sampler can be secured the most.
- the symbol period of the decompression data rxdat1, rxdat1b, rxdat2, rxdat2b, rxdat3, rxdat3b, rxdat4, and rxdat4b output from the data sampling unit 5300 has the same value as the period of the supplied clock signal.
- FIG. 13 is a block diagram illustrating an embodiment of a semiconductor system in accordance with still another embodiment of the present invention.
- FIG. 13 illustrates an example of the second semiconductor device 6000 which recovers the differential data and the differential clock signal by using the differential reception signal.
- FIG. 13 shows an embodiment in which the above-described receiver is applied to an existing CDR structure.
- the second semiconductor device 6000 may further include a clock phase controller 6400 in addition to the data recovery circuit 6100, the clock recovery circuit 6200, and the data sampling unit 6300.
- the data recovery circuit 6100 restores differential data from the differential received signal
- the clock recovery circuit 6200 recovers the clock signal from the differential received signal and then converts the clock signal to the differential clock signal.
- the converted differential clock signal is provided to the clock phase adjuster 6400 after a predetermined amplification operation.
- the differential clock signal is converted into four clock signals through a voltage-controlled delay line circuit (VCDL circuit) and a phase splitter and then provided to a single clock stage of each sampling circuit of the data sampling unit 6300. do.
- the data sampling unit 6300 samples and outputs differential data rxdat1, rxdat1b, rxdat2, and rxdat2b in synchronization with the four clock signals, respectively.
- the sampled differential data rxdat1, rxdat1b, rxdat2, and rxdat2b are provided to the VCDL circuit through the phase detector PD, the charge pump CP, and the loop filter LF of the clock phase controller 6400.
- phase detector PD As an example of the phase detector PD, a half-rate 4 phase detector may be applied, and the phase splitter may be a phase splitter or a conventional phase interpolator structure or a poly-phase filter structure.
- the VCDL circuit adjusts the phase of the differential clock signal as the phases of the differential data rxdat1, rxdat1b, rxdat2, and rxdat2b shift so that the phase difference according to the signal processing between the data recovery circuit 6100 and the clock recovery circuit 6200. To compensate.
- FIG. 14 is another embodiment of the second semiconductor device of FIG. 1;
- the second semiconductor device 7000 may include a differential data recovery unit 7100 that restores differential data from the differential reception signal, a differential clock recovery unit 7200 that restores the differential clock signal from the differential reception signal, and a restored differential clock signal. And a data sampling unit 7300 for sampling the differential data using the data sampling unit.
- the differential equalizer of FIG. 1 may be included in the differential data recovery unit.
- FIG. 15 illustrates a specific implementation of FIG. 14.
- the differential data recovery unit 8100 uses one or more amplifiers 8110 and 8130 to extract and amplify only differential data from the differential received signal, and data-samples the output thereof. It is provided to the part 8300.
- the data sampling unit 8300 may include one or more sampling circuits (or sampling flip-flops 8310 and 8320). At this time, the clock signal included in the differential reception signal during the differential data recovery process is regarded as a common mode signal by the differential amplifiers 8110 and 8130 and removed.
- a differential equalizer 8120 may be included in the differential data recovery path for the purpose of amplifying the high frequency band of the received differential signal, which amplifies the high frequency component of the received signal reduced by the limited bandwidth by the communication channel. It is a means for increasing the margin at the time of data sampling.
- the differential equalizer 8120 may use a source-degenerative circuit as shown in FIG. 6 (except for the common mode signal converter 2210), and the circuit may arrange a resistive load or an LC-tank load at its output. The position of the differential equalizer 8120 may be located at the forefront of data restoration or immediately before the data sampling unit 8300, as necessary.
- the differential clock recovery unit 8200 for recovering the differential clock signal from the differential received signal may include a common mode signal converter 8210, a single-differential conversion circuit (STD circuit 8220), and a differential amplifier 8230.
- the common mode signal converter 8210 is a reciprocal of a differential amplifier concept.
- the common mode signal converter 8210 is a circuit that amplifies the common mode signal and attenuates the differential signal by summing up the received differential signals.
- 16A and 16B illustrate an example of implementing the common mode signal converter 8210, and the common mode signal converter 8210 includes a resistor distribution circuit to perform the above function as illustrated in FIG. 16A. can do.
- the common mode signal converter 8210 may use an amplifying circuit as shown in FIG.
- Gm denotes the same transconductance of the transistors M1 / M2, and Zd or Zs denotes an equivalent impedance at the end facing the output load ZL or an equivalent impedance at the end facing the source resistances Rs. .
- the output load (ZL) can be implemented with a simple resistor, but LC-resonance or inductive-peaking structures with inductance can be used to improve amplification and accuracy.
- the specific embodiments of the single-differential conversion circuit (STD circuit) 8220, the differential amplifier 8230, the delay circuit 8400, and the sampling unit 8300 may be identically applied to the embodiment of FIG. 2.
- Various embodiments of the sampling unit (FIGS. 11 to 13) may be similarly applied.
- the present invention can be applied to replace the conventional clock forwarded signaling method and the clock embedded signaling method of transmitting and receiving circuits that perform high-speed data transmission / reception functions between semiconductor chips and devices via PCB lines and transmission cables between semiconductor chips.
- it is possible to reduce the semiconductor area and power burden due to the addition of pins and CDR circuits for additional clock transmission, which is a disadvantage of the conventional method, and to maintain the correlation between clock and data in comparison with the conventional method in an environment where broadband noise is present. It is advantageously applicable to high speed data transmission.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Dc Digital Transmission (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (29)
- 차동 데이터를 제공하는 데이터 제공부;상기 데이터 제공부로 제공되는 제1 클럭신호와, 상기 제1 클럭신호와 서로 다른 위상을 갖는 제2 클럭신호를 생성하는 다중 위상 클럭 발생부; 및상기 차동 데이터와 상기 제2 클럭신호를 수신하고 이를 결합하여 결합 신호를 발생하는 신호 결합부를 구비하며,상기 제2 클럭신호는 단일 클럭신호이며, 상기 차동 데이터의 심볼 주기의 n 배(n은 2 이상의 정수)를 가지고, 상기 제1 클럭신호와 제2 클럭신호는 90 도의 위상 차이를 가지며,상기 제2 클럭신호는 상기 차동 데이터에 공통하게 결합되고, 상기 결합 신호는 차동 신호로서 크로스 포인트 전압 레벨을 가지며, 상기 크로스 포인트 전압 레벨은 상기 제2 클럭신호의 레벨에 따라 변동되고,상기 결합 신호를 차동 전송 라인을 통해 외부로 전송하는 것을 특징으로 하는 반도체 장치.
- 청구항 1항에 있어서,상기 제2 클럭신호는 상기 차동 데이터의 심볼 주기의 2 배의 주기를 가지며,상기 차동 데이터의 레벨이 천이하는 동안, 상기 제2 클럭신호는 로직 하이 또는 로직 로우의 레벨을 유지하는 것을 특징으로 하는 반도체 장치.
- 청구항 1항에 있어서,상기 데이터 제공부의 제1 클럭 신호의 입력 대비 출력 타이밍의 지연을 보상하기 위하여, 상기 차동 데이터 또는 상기 제2 클럭 신호를 수신하여 위상을 지연하여 출력하는 지연 회로를 더 구비하는 것을 특징으로 하는 반도체 장치.
- 청구항 1항에 있어서,상기 제2 클럭신호를 수신하고, 상기 제2 클럭신호의 고주파 성분을 증폭하여 이를 상기 신호 결합부로 제공하기 위한 하이패스 필터를 더 구비하는 것을 특징으로 하는 반도체 장치.
- 반도체 시스템에 있어서, 상기 반도체 시스템은 차동 전송라인을 통해 차동 수신 신호를 수신하는 제1 반도체 장치를 포함하고,상기 제1 반도체 장치는,상기 차동 수신 신호의 고주파 대역을 증폭하여 차동 신호로 출력하는 차동 이퀄라이저;상기 고주파 대역이 증폭된 차동 신호간의 차이를 검출함에 의하여 상기 차동 수신 신호로부터 차동 데이터를 복원하는 차동 데이터 복원부;상기 고주파 대역이 증폭된 차동 신호간의 합산에 의하여 공통 모드 신호를 추출하여, 상기 고주파 대역이 증폭된 차동 신호로부터 단일 클럭 신호를 복원하고, 상기 복원된 단일 클럭 신호를 차동 클럭 신호로 변환하여 상기 차동 데이터와 소정의 위상 차를 갖는 차동 클럭 신호를 생성하는 차동 클럭 복원부;상기 차동 데이터와 상기 차동 클럭 신호를 이용하여 상기 차동 데이터를 샘플링하는 데이터 샘플링부; 및상기 차동 데이터 복원부로부터의 차동 데이터의 출력 타이밍과 상기 차동 클럭 복원부로부터의 차동 클럭 신호의 출력 타이밍의 지연 차이를 보상하기 위하여, 상기 차동 데이터 또는 상기 차동 클럭 신호를 수신하여 위상을 지연하여 출력하는 지연 회로를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 5항에 있어서,상기 차동 데이터와 상기 차동 클럭 신호는 서로 90 도의 위상 차를 갖는 것을 특징으로 하는 반도체 시스템.
- 청구항 5항에 있어서, 상기 차동 클럭 복원부는,상기 고주파 대역이 증폭된 차동 신호로부터 상기 공통 모드 신호를 추출하여 이를 증폭하는 증폭 회로를 포함하는 것을 특징으로 하는 반도체 시스템.
- 청구항 5항에 있어서,상기 차동 클럭 복원부로부터 상기 차동 클럭 신호를 수신하고, 상기 데이터 샘플링부의 출력 위상에 기반하여 차동 클럭 신호의 위상을 조절하며, 상기 위상 조절된 차동 클럭 신호를 상기 데이터 샘플링부로 출력하는 전압 제어 딜레이 라인을 더 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 5항에 있어서, 상기 차동 클럭 복원부는,상기 생성된 단일 클럭 신호로부터 4 위상으로 변환된 클럭 신호를 생성하고, 상기 4 위상으로 변환된 클럭 신호를 상기 데이터 샘플링부로 출력하는 위상 변환기를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 5항에 있어서, 상기 차동 클럭 복원부는,상기 생성된 차동 클럭 신호를 주파수 분배하여 4 위상으로 변환된 클럭 신호를 생성하고, 상기 4 위상으로 변환된 클럭 신호를 상기 데이터 샘플링부로 출력하는 주파수 분배기를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 5항에 있어서, 상기 차동 클럭 복원부는,상기 생성된 차동 클럭 신호를 주파수 체배하여 주파수 변환된 차동 클럭 신호를 생성하고, 상기 주파수 변환된 차동 클럭 신호를 상기 데이터 샘플링부로 출력하는 주파수 체배기를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 5항에 있어서,상기 차동 데이터를 생성하여 이를 상기 차동 전송라인을 통해 출력하는 제2 반도체 장치를 더 구비하고,상기 제2 반도체 장치는,상기 차동 데이터를 제공하는 데이터 제공부;상기 데이터 제공부로 제공되는 제1 클럭신호와, 상기 제1 클럭신호와 서로 다른 위상을 갖는 제2 클럭신호를 생성하는 다중 위상 클럭 발생부; 및상기 차동 데이터와 상기 제2 클럭신호를 수신하고 이를 결합하여 결합 신호를 발생하는 신호 결합부를 구비하며,상기 제2 클럭신호는 단일 클럭신호이며, 상기 차동 데이터의 심볼 주기의 n 배(n은 2 이상의 정수)를 가지고, 상기 제1 클럭신호와 제2 클럭신호는 90 도의 위상 차이를 가지는 반도체 시스템.
- 반도체 시스템에 있어서, 상기 반도체 시스템은 차동 전송라인을 통해 차동 수신 신호를 수신하는 제1 반도체 장치를 포함하고,상기 제1 반도체 장치는,상기 차동 수신 신호간의 차이를 검출함에 의하여 상기 차동 수신 신호로부터 차동 데이터를 복원하는 차동 데이터 복원부;상기 차동 수신 신호간의 합산에 의하여 공통 모드 신호를 추출하여, 상기 차동 수신 신호로부터 단일 클럭 신호를 복원하고, 상기 복원된 단일 클럭 신호를 차동 클럭 신호로 변환하여 상기 차동 데이터와 소정의 위상 차를 갖는 차동 클럭 신호를 생성하는 차동 클럭 복원부;상기 차동 데이터와 상기 차동 클럭 신호를 이용하여 상기 차동 데이터를 샘플링하는 데이터 샘플링부; 및상기 차동 데이터 복원부로부터의 차동 데이터의 출력 타이밍과 상기 차동 클럭 복원부로부터의 차동 클럭 신호의 출력 타이밍의 지연 차이를 보상하기 위하여, 상기 차동 데이터 또는 상기 차동 클럭 신호를 수신하여 위상을 지연하여 출력하는 지연 회로를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 13항에 있어서,상기 차동 데이터와 상기 차동 클럭 신호는 서로 90 도의 위상 차를 갖는 것을 특징으로 하는 반도체 시스템.
- 청구항 13항에 있어서, 상기 차동 클럭 복원부는,상기 차동 수신 신호로부터 상기 공통 모드 신호를 추출하여 이를 증폭하는 증폭 회로를 포함하는 것을 특징으로 하는 반도체 시스템.
- 청구항 15항에 있어서, 상기 차동 데이터 복원부는,상기 차동 데이터에 대하여 상기 증폭 회로에 따른 시간 지연만큼 시간 지연을 부여하고 또한 고주파 대역의 신호 증폭을 위하여, 상기 증폭 회로의 차동 등가 회로로 구현되는 차동 이퀄라이저를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 13항에 있어서,상기 차동 클럭 복원부로부터 상기 차동 클럭 신호를 수신하고, 상기 데이터 샘플링부의 출력 위상에 기반하여 차동 클럭 신호의 위상을 조절하며, 상기 위상 조절된 차동 클럭 신호를 상기 데이터 샘플링부로 출력하는 전압 제어 딜레이 라인을 더 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 13항에 있어서, 상기 차동 클럭 복원부는,상기 생성된 단일 클럭 신호로부터 4 위상으로 변환된 클럭 신호를 생성하고, 상기 4 위상으로 변환된 클럭 신호를 상기 데이터 샘플링부로 출력하는 위상 변환기를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 13항에 있어서, 상기 차동 클럭 복원부는,상기 생성된 차동 클럭 신호를 주파수 분배하여 4 위상으로 변환된 차동 클럭 신호를 생성하고, 상기 4 위상으로 변환된 차동 클럭 신호를 상기 데이터 샘플링부로 출력하는 주파수 분배기를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 13항에 있어서, 상기 차동 클럭 복원부는,상기 생성된 차동 클럭 신호를 주파수 체배하여 주파수 변환된 차동 클럭 신호를 생성하고, 상기 주파수 변환된 차동 클럭 신호를 상기 데이터 샘플링부로 출력하는 주파수 체배기를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 13항에 있어서,상기 차동 데이터를 생성하여 이를 상기 차동 전송라인을 통해 출력하는 제2 반도체 장치를 더 구비하고,상기 제2 반도체 장치는,상기 차동 데이터를 제공하는 데이터 제공부;상기 데이터 제공부로 제공되는 제1 클럭신호와, 상기 제1 클럭신호와 서로 다른 위상을 갖는 제2 클럭신호를 생성하는 다중 위상 클럭 발생부; 및상기 차동 데이터와 상기 제2 클럭신호를 수신하고 이를 결합하여 결합 신호를 발생하는 신호 결합부를 구비하며,상기 제2 클럭신호는 단일 클럭신호이며, 상기 차동 데이터의 심볼 주기의 n 배(n은 2 이상의 정수)를 가지고, 상기 제1 클럭신호와 제2 클럭신호는 90 도의 위상 차이를 가지는 반도체 시스템.
- 반도체 시스템에 있어서, 상기 반도체 시스템은 차동 전송라인을 통해 차동 수신 신호를 수신하는 제1 반도체 장치를 포함하고,상기 제1 반도체 장치는,상기 차동 수신 신호의 고주파 대역을 증폭하여 차동 신호로 출력하는 차동 이퀄라이저;상기 고주파 대역이 증폭된 차동 신호간의 차이를 검출함에 의하여 상기 차동 수신 신호로부터 차동 데이터를 복원하는 차동 데이터 복원부;상기 차동 이퀄라이저의 일부 기능을 공유하면서 차동 수신 신호간의 합산에 의하여 공통 모드 신호를 추출하여, 상기 차동 수신 신호로부터 단일 클럭 신호를 복원하는 단일 클럭 복원부;상기 복원된 단일 클럭 신호를 차동 클럭 신호로 변환하여 상기 차동 데이터와 소정의 위상 차를 갖는 차동 클럭 신호를 생성하는 차동 클럭 복원부;상기 차동 데이터와 상기 차동 클럭 신호를 이용하여 상기 차동 데이터를 샘플링하는 데이터 샘플링부; 및상기 차동 데이터 복원부로부터의 차동 데이터의 출력 타이밍과 상기 차동 클럭 복원부로부터의 차동 클럭 신호의 출력 타이밍의 지연 차이를 보상하기 위하여, 상기 차동 데이터 또는 상기 차동 클럭 신호를 수신하여 위상을 지연하여 출력하는 지연 회로를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 22에 있어서,상기 차동 데이터와 상기 차동 클럭 신호는 서로 90 도의 위상 차를 갖는 것을 특징으로 하는 반도체 시스템.
- 청구항 22에 있어서, 상기 단일 클럭 복원부는,상기 차동 이퀄라이저의 고주파 증폭 회로을 공유하여 상기 차동 수신 신호간의 합산으로부터 증폭된 공통 모드 신호를 추출하는 것을 특징으로 하는 반도체 시스템.
- 청구항 22에 있어서,상기 차동 클럭 복원부로부터 상기 차동 클럭 신호를 수신하고, 상기 데이터 샘플링부의 출력 위상에 기반하여 차동 클럭 신호의 위상을 조절하며, 상기 위상 조절된 차동 클럭 신호를 상기 데이터 샘플링부로 출력하는 전압 제어 딜레이 라인을 더 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 22에 있어서, 상기 차동 클럭 복원부는,상기 생성된 단일 클럭 신호로부터 4 위상으로 변환된 클럭 신호를 생성하고, 상기 4 위상으로 변환된 클럭 신호를 상기 데이터 샘플링부로 출력하는 위상 변환기를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 22에 있어서, 상기 차동 클럭 복원부는,상기 생성된 차동 클럭 신호를 주파수 분배하여 4 위상으로 변환된 클럭 신호를 생성하고, 상기 4 위상으로 변환된 클럭 신호를 상기 데이터 샘플링부로 출력하는 주파수 분배기를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 22에 있어서, 상기 차동 클럭 복원부는,상기 생성된 차동 클럭 신호를 주파수 체배하여 주파수 변환된 차동 클럭 신호를 생성하고, 상기 주파수 변환된 차동 클럭 신호를 상기 데이터 샘플링부로 출력하는 주파수 체배기를 구비하는 것을 특징으로 하는 반도체 시스템.
- 청구항 22항에 있어서,상기 차동 데이터를 생성하여 이를 상기 차동 전송라인을 통해 출력하는 제2 반도체 장치를 더 구비하고,상기 제2 반도체 장치는,상기 차동 데이터를 제공하는 데이터 제공부;상기 데이터 제공부로 제공되는 제1 클럭신호와, 상기 제1 클럭신호와 서로 다른 위상을 갖는 제2 클럭신호를 생성하는 다중 위상 클럭 발생부; 및상기 차동 데이터와 상기 제2 클럭신호를 수신하고 이를 결합하여 결합 신호를 발생하는 신호 결합부를 구비하며,상기 제2 클럭신호는 단일 클럭신호이며, 상기 차동 데이터의 심볼 주기의 n 배(n은 2 이상의 정수)를 가지고, 상기 제1 클럭신호와 제2 클럭신호는 90 도의 위상 차이를 가지는 반도체 시스템.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/360,044 US8976875B2 (en) | 2011-11-24 | 2012-11-09 | Clock-embedded source synchronous semiconductor transmitting and receiving apparatus and semiconductor system including same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020110123670A KR101190091B1 (ko) | 2011-11-24 | 2011-11-24 | 클럭 임베디드 소스 싱크로너스 시그널링을 이용하는 반도체 송수신 장치 및 이를 포함하는 반도체 시스템 |
KR10-2011-0123670 | 2011-11-24 | ||
KR10-2012-0119693 | 2012-10-26 | ||
KR1020120119693A KR101355357B1 (ko) | 2012-10-26 | 2012-10-26 | 클럭 임베디드 소스 싱크로너스 시그널링을 이용하는 반도체 수신 장치 및 이를 포함하는 반도체 시스템 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013077577A1 true WO2013077577A1 (ko) | 2013-05-30 |
Family
ID=48469981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/KR2012/009438 WO2013077577A1 (ko) | 2011-11-24 | 2012-11-09 | 클럭 임베디드 소스 싱크로너스 반도체 송수신 장치 및 이를 포함하는 반도체 시스템 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8976875B2 (ko) |
WO (1) | WO2013077577A1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103616580A (zh) * | 2013-11-08 | 2014-03-05 | 北京博电新力电气股份有限公司 | 合并单元数据转换角差测试方法 |
CN104793077A (zh) * | 2015-04-11 | 2015-07-22 | 国家电网公司 | 一种模拟量输入合并单元相位误差检测方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9898997B2 (en) | 2014-01-27 | 2018-02-20 | Samsung Electronics Co., Ltd. | Display driving circuit |
US9832094B2 (en) | 2014-03-24 | 2017-11-28 | Qualcomm Incorporated | Multi-wire electrical parameter measurements via test patterns |
US9608611B1 (en) * | 2016-01-28 | 2017-03-28 | Xilinx, Inc. | Phase interpolator and method of implementing a phase interpolator |
US10541897B2 (en) | 2017-05-16 | 2020-01-21 | Western Digital Technologies, Inc. | Mismatch compensation at differential signal receiver |
US10033524B1 (en) * | 2017-05-16 | 2018-07-24 | Western Digital Technologies, Inc. | Differential signal mismatch compensation |
KR20220153964A (ko) | 2021-05-12 | 2022-11-21 | 삼성전자주식회사 | 전원 전압 변화를 보상하는 인터페이스 회로 및 이의 동작 방법 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20070024195A (ko) * | 2005-08-26 | 2007-03-02 | 삼성전자주식회사 | 신호 전송 장치 및 신호 전송 방법 |
JP2007155611A (ja) * | 2005-12-07 | 2007-06-21 | Seiko Epson Corp | 半導体集積回路 |
KR20080066327A (ko) * | 2007-01-12 | 2008-07-16 | 삼성전자주식회사 | 클럭 임베디드 신호를 이용한 직렬 통신 방법 및 장치 |
KR100942976B1 (ko) * | 2008-04-30 | 2010-02-17 | 주식회사 하이닉스반도체 | 데이터 정렬 회로와 그의 구동 방법 |
KR100948415B1 (ko) * | 2008-04-29 | 2010-03-19 | 김현수 | 임베디드 데이터 복구 장치 및 그 방법 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9565036B2 (en) * | 2009-06-30 | 2017-02-07 | Rambus Inc. | Techniques for adjusting clock signals to compensate for noise |
US8743973B2 (en) * | 2010-05-25 | 2014-06-03 | Rambus Inc. | Receiver resistor network for common-mode signaling |
JP2012124571A (ja) * | 2010-12-06 | 2012-06-28 | Toshiba Corp | 差動信号出力装置、および、携帯機器 |
US8767841B1 (en) * | 2013-03-04 | 2014-07-01 | Qualcomm Incorporated | System and method for de-modulating a high-supply-domain differential signal and a common-mode clock in a front-end receiver |
-
2012
- 2012-11-09 US US14/360,044 patent/US8976875B2/en not_active Expired - Fee Related
- 2012-11-09 WO PCT/KR2012/009438 patent/WO2013077577A1/ko active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20070024195A (ko) * | 2005-08-26 | 2007-03-02 | 삼성전자주식회사 | 신호 전송 장치 및 신호 전송 방법 |
JP2007155611A (ja) * | 2005-12-07 | 2007-06-21 | Seiko Epson Corp | 半導体集積回路 |
KR20080066327A (ko) * | 2007-01-12 | 2008-07-16 | 삼성전자주식회사 | 클럭 임베디드 신호를 이용한 직렬 통신 방법 및 장치 |
KR100948415B1 (ko) * | 2008-04-29 | 2010-03-19 | 김현수 | 임베디드 데이터 복구 장치 및 그 방법 |
KR100942976B1 (ko) * | 2008-04-30 | 2010-02-17 | 주식회사 하이닉스반도체 | 데이터 정렬 회로와 그의 구동 방법 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103616580A (zh) * | 2013-11-08 | 2014-03-05 | 北京博电新力电气股份有限公司 | 合并单元数据转换角差测试方法 |
CN104793077A (zh) * | 2015-04-11 | 2015-07-22 | 国家电网公司 | 一种模拟量输入合并单元相位误差检测方法 |
Also Published As
Publication number | Publication date |
---|---|
US8976875B2 (en) | 2015-03-10 |
US20140334583A1 (en) | 2014-11-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2013077577A1 (ko) | 클럭 임베디드 소스 싱크로너스 반도체 송수신 장치 및 이를 포함하는 반도체 시스템 | |
US11329701B2 (en) | Master reference for base station network interface sourced from distributed antenna system | |
US7254183B2 (en) | Dual link DVI transmitter serviced by single phase locked loop | |
KR100694726B1 (ko) | 클럭 신호 라인을 통하여 데이터 신호를 송신하고 수신하는 시스템 및 방법 | |
US8773964B2 (en) | CDMA-based crosstalk cancellation for on-chip global high-speed links | |
JP4718933B2 (ja) | 並列信号のスキュー調整回路及びスキュー調整方法 | |
WO2016108650A1 (ko) | 디지털 맵핑 데이터 전송 방법 | |
WO2013152588A1 (zh) | 一种全双工无线通信装置、方法及系统 | |
US6341142B2 (en) | Serial data transceiver including elements which facilitate functional testing requiring access to only the serial data ports, and an associated test method | |
US6208621B1 (en) | Apparatus and method for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency | |
US10735176B1 (en) | High-speed data recovery with minimal clock generation and recovery | |
CN113395223A (zh) | 用于处理串行数据流的装置 | |
CN114846837A (zh) | 传输速率适配 | |
EP1000469B1 (en) | Cable interface for data and power supply | |
US7663442B2 (en) | Data receiver including a transconductance amplifier | |
CN114124278A (zh) | 一种用于数字同时多波束发射的数字同步电路及方法 | |
US20210136551A1 (en) | Multi-member bluetooth device capable of synchronizing audio playback between different bluetooth circuits | |
KR101190091B1 (ko) | 클럭 임베디드 소스 싱크로너스 시그널링을 이용하는 반도체 송수신 장치 및 이를 포함하는 반도체 시스템 | |
JP4309427B2 (ja) | 送信信号の完全性をテストする技法 | |
US11751153B2 (en) | Multi-member bluetooth device capable of synchronizing audio playback between different bluetooth circuits | |
US20050094583A1 (en) | Full duplex transceiver | |
US11035900B2 (en) | Scan-chain testing via deserializer port | |
KR101355357B1 (ko) | 클럭 임베디드 소스 싱크로너스 시그널링을 이용하는 반도체 수신 장치 및 이를 포함하는 반도체 시스템 | |
WO2022193328A1 (zh) | 串行/解串行电路、串行数据接收方法和芯片 | |
CN114731167A (zh) | 用于噪声降低的互补数据流 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12852209 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14360044 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 04/11/2014) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 12852209 Country of ref document: EP Kind code of ref document: A1 |