WO2013075587A1 - 有机薄膜晶体管、有机薄膜晶体管阵列基板及显示装置 - Google Patents

有机薄膜晶体管、有机薄膜晶体管阵列基板及显示装置 Download PDF

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WO2013075587A1
WO2013075587A1 PCT/CN2012/084336 CN2012084336W WO2013075587A1 WO 2013075587 A1 WO2013075587 A1 WO 2013075587A1 CN 2012084336 W CN2012084336 W CN 2012084336W WO 2013075587 A1 WO2013075587 A1 WO 2013075587A1
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Prior art keywords
partition wall
thin film
film transistor
organic thin
drain
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PCT/CN2012/084336
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English (en)
French (fr)
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刘则
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京东方科技集团股份有限公司
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Priority to US13/806,215 priority Critical patent/US9312324B2/en
Publication of WO2013075587A1 publication Critical patent/WO2013075587A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/464—Lateral top-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/125—Active-matrix OLED [AMOLED] displays including organic TFTs [OTFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes

Definitions

  • Organic thin film transistor, organic thin film transistor array substrate and display device are organic thin film transistors, organic thin film transistor array substrate and display device
  • Embodiments of the present invention relate to an organic thin film transistor, an organic thin film transistor array substrate, and a display device. Background technique
  • Organic Thin Film Transistor has the advantages of simple process, low cost and good flexibility, and has broad application prospects in the field of flat panel display. Therefore, research and development of organic thin film transistor (OTFT) array substrates have received extensive attention. Multiple patterning processes are typically required during the fabrication of an OTFT array substrate to form a patterned layer structure.
  • a typical OTFT has a structure in which a gate electrode and an active layer made of an organic semiconductor material are formed on a substrate with a gate insulating film interposed therebetween, and source and drain electrodes separated from each other contact the active layer, and Corresponding to both sides of the gate electrode and insulated from the gate electrode.
  • Organic semiconductor materials generally have low chemical stability and optical stability, and their patterning is difficult to complicate.
  • This ink jet printing process is a process of printing ink droplets (i.e., a paste formed by dissolving a material for forming a pattern in a specific solvent) in a region where a pattern is to be formed to form a desired pattern.
  • ink droplets i.e., a paste formed by dissolving a material for forming a pattern in a specific solvent
  • the pattern of the active layer may not strictly meet the process requirements due to the fluidity of the ink droplets, that is, the active layer is formed.
  • the pattern is not precise enough to affect the performance of the OTFT, which in turn affects the performance of the OTFT array substrate. Summary of the invention
  • An embodiment of the present invention provides an organic thin film transistor including: a transparent substrate; a source and a drain formed on the transparent substrate; an active layer formed on the transparent substrate, and disposed at the Between the source and the drain, the active layer is formed of an organic semiconductor material; a gate insulating layer is formed on the active layer; a gate is formed on the gate insulating layer; and the first a partition wall and a second partition wall are disposed on the transparent substrate, and the source and the drain respectively cover An inner side of the first partition wall and an inner side of the second partition wall.
  • an organic thin film transistor array substrate including a transparent substrate and an organic thin film transistor formed on the transparent substrate, the organic thin film transistor including: a source and a drain, formed in the On the transparent substrate; an active layer formed on the transparent substrate and disposed between the source and the drain, the active layer being formed of an organic semiconductor material; a gate insulating layer formed at On the active layer; a gate electrode formed on the gate insulating layer; and a first isolation wall and a second isolation wall disposed on the transparent substrate, the source and the drain respectively covering the The inside of the first partition wall and the inner side of the second partition wall.
  • Another embodiment of the present invention provides a display device including an organic thin film transistor array substrate including a transparent substrate and an organic thin film transistor formed on the transparent substrate, the organic thin film transistor
  • the method includes: a source and a drain formed on the transparent substrate; an active layer formed on the transparent substrate, and disposed between the source and the drain, the active layer being organic a semiconductor material is formed; a gate insulating layer is formed on the active layer; a gate electrode is formed on the gate insulating layer; and a first isolation wall and a second isolation wall are disposed on the transparent substrate, A source and the drain cover an inner side of the first partition wall and an inner side of the second partition wall, respectively.
  • FIG. 1 is a schematic cross-sectional view showing an organic thin film transistor (OTFT) according to an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional structural view of an OTFT array substrate according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide an organic thin film transistor to improve characteristics of an organic thin film transistor, simplify its manufacturing process, and reduce its manufacturing cost. Embodiments of the present invention also provide an organic thin film transistor array substrate and a display device including the above organic thin film transistor.
  • an organic thin film transistor provided by an embodiment of the present invention includes, for example, a transparent substrate 1 , a source electrode 21 and a drain electrode 22 formed on the transparent substrate 1 , and an active layer 4 formed on the transparent substrate 1 .
  • the active layer 4 is formed of an organic semiconductor material;
  • the gate insulating layer 5 is formed on the active layer 4;
  • the gate electrode 6 is formed on the gate insulating layer 5;
  • a partition wall 31 and a second partition wall 32 are disposed on the transparent substrate 1, and the source 21 and the drain 22 cover the inner side of the first partition wall 31 and the inner side of the second partition wall 32, respectively.
  • the transparent substrate 1 may be a glass substrate, a plastic substrate or the like.
  • the first partition wall 31 and the second partition wall 32 may be formed of an organic material (for example, a photocurable resin or a thermosetting resin), or may be formed of an inorganic material.
  • the side of the first partition wall 31 and the second partition wall 32 toward the active layer 4, respectively, is referred to as the inner side of the first partition wall 31 and the inner side of the second partition wall 32.
  • the source and the drain of the organic thin film transistor are respectively required to cover the inner side of the first isolation wall and the inner side of the second isolation wall, for the first isolation wall and the second Other parts of the wall may or may not be covered by the source and drain.
  • the source 21 and the drain 22 of the organic thin film transistor cover the inner side of the first partition wall 31 and the inner side of the second partition wall 32, respectively, and also cover the first partition respectively.
  • the upper surface of the wall 31 and the second partition wall 32, that is, the source 21 and the drain 22 of the organic thin film transistor completely cover the first partition wall 31 and the second partition wall 32, respectively.
  • the first partition wall 31 and the second partition wall 32 may be disposed in the same layer, but in other embodiments of the present invention, the first partition wall 31 and the second partition wall 32 may be disposed in different layers.
  • the same layer refers to the same layer of film made of the same material
  • the same layer arrangement is for at least two patterns, and refers to at least two patterns formed by the same layer of film.
  • the structure is at least two patterns formed on the same film made of the same material by a patterning process.
  • the first partition wall and the second partition wall are disposed in the same layer, that is, the first partition wall and the second partition wall are two patterns formed by the same layer of film made of the same material.
  • first partition wall and the second partition wall are two patterns having the same shape and different positions.
  • the heights of the first partition wall 31 and the second partition wall 32 are, for example, about 1 to 5 ⁇ m, but in other embodiments of the present invention, the first partition wall 31 and the second partition wall 31 may have other Different heights.
  • the shape of the gate electrode 6 and the gate insulating layer 5 are identical.
  • the shape is uniform, that is, the shape and size of the top view of the gate electrode 6 and the gate insulating layer 5 are exactly the same, so that the same mask plate can be used to form the gate electrode 6 and the gate insulating layer 5 having the same shape. Helps reduce production costs.
  • the shapes of the gate insulating layer 5 and the gate electrode 6 may also be inconsistent.
  • the gate insulating layer completely covers the entire transparent substrate.
  • an area for forming an active layer is defined by a source and a drain which are respectively heightened by the isolation wall, so that an inkjet printing process can be utilized in the defined area.
  • the active layer is formed, so that the pattern of the active layer can be precisely controlled, and the active layer can be made to have a larger area contact with the source and the drain, thereby improving the characteristics of the OTFT.
  • the manufacturing method of the organic thin film transistor includes the following steps, for example:
  • the first partition wall and the second partition wall are formed by printing and using an organic material such as a resin, and the resin can be formed by photocuring or heat curing.
  • step S1 may also employ a sputtering or chemical vapor deposition process in combination with a photolithography process and using an inorganic material to form the first barrier and the second barrier.
  • an electrode material such as a metal or a metal oxide on the first and second isolation walls, and forming a source and a drain by a photolithography (including exposure, development, etc.) process and an etching process.
  • the organic semiconductor material is printed in an area defined by the source and the drain by an inkjet printing method to form an active layer.
  • the gate and the gate insulating layer may be separately formed as a conventional thin film transistor, and the gate insulating layer and the gate electrode are formed in an inconsistent shape, and the gate insulating layer can completely cover the entire surface. Transparent substrate.
  • the organic thin film transistor shown in Fig. 1 of the embodiment of the present invention can be manufactured by the above method.
  • an OTFT array substrate according to an embodiment of the present invention will be described with reference to FIG.
  • the OTFT array substrate provided by the embodiment of the present invention may include a plurality of gate lines and data lines crossing each other to define a plurality of pixel units arranged in an array, and FIG. 2 only shows the OTFT array substrate.
  • an OTFT array substrate provided by an embodiment of the present invention includes, for example, a transparent substrate 1 and an organic thin film transistor formed on the transparent substrate 1.
  • the organic thin film transistor includes: a source 21 and a drain 22, which are formed in a transparent On the substrate 1; an active layer 4 is formed on the transparent substrate 1 and disposed between the source 21 and the drain 22, the active layer 4 is formed of an organic semiconductor material; and a gate insulating layer 5 is formed on the active layer 4.
  • a gate electrode 6 is formed on the gate insulating layer 5; and a first isolation wall 31 and a second isolation wall 32 are disposed on the transparent substrate 1, and the source electrode 21 and the drain electrode 22 respectively cover the inner side of the first isolation wall 31 And the inner side of the second partition wall 32.
  • the OTFT array substrate further includes: a passivation layer 7 covering the organic thin film transistor, the passivation layer 7 is formed with a via hole; and the pixel electrode 8 and the via hole and the organic film passing through the passivation layer 7 The drain 22 of the transistor is electrically connected.
  • the transparent substrate 1 may be a glass substrate, a plastic substrate, or the like.
  • the first partition wall 31 and the second partition wall 32 may be formed of an organic material (for example, a photocurable resin or a thermosetting resin), or may be formed of an inorganic material.
  • the side of the first partition wall 31 and the second partition wall 32 toward the active layer 4, respectively, is referred to as the inner side of the first partition wall 31 and the inner side of the second partition wall 32.
  • the source and the drain of the organic thin film transistor are respectively required to cover the inner side of the first isolation wall and the inner side of the second isolation wall, for the first isolation wall and the second Other parts of the wall may or may not be covered by the source and drain.
  • the source 21 and the drain 22 of the organic thin film transistor cover the inner side of the first partition wall 31 and the inner side of the second partition wall 32, respectively, and also cover the first partition wall 31, respectively.
  • the upper surface of the second partition wall 32, that is, the source 21 and the drain 22 of the organic thin film transistor completely cover the first partition wall 31 and the second partition wall 32, respectively.
  • the first partition wall 31 and the second partition wall 32 may be disposed in the same layer, but in other embodiments of the present invention, the first partition wall 31 and the second partition wall 31 may be disposed in different layers.
  • the same layer refers to the same layer of film made of the same material
  • the same layer arrangement is for at least two patterns, and refers to at least two patterns formed by the same layer of film.
  • the structure is at least two patterns formed on the same film made of the same material by a patterning process.
  • the first partition wall and the second partition wall are disposed in the same layer, that is, the first partition wall and the second partition wall are two patterns formed by the same layer of film made of the same material.
  • first partition wall and the second partition wall are two patterns having the same shape and different positions.
  • the heights of the first partition wall 31 and the second partition wall 32 are, for example, about 1 to 5 microns, but in other embodiments of the present invention, the first partition wall 31 and the second partition wall 32 may also have Other different heights.
  • the shape of the gate electrode 6 and the gate insulating layer 5 are identical.
  • the same mask can be used to form the gate 6 and the gate insulating layer 5 having the same shape, which is advantageous in reducing the production cost and simplifying the process.
  • the shapes of the gate electrode 6 and the gate insulating layer 5 may also be inconsistent.
  • an area for forming an active layer is defined by a source and a drain which are respectively heightened by the isolation wall, so that an inkjet printing process can be utilized in the defined area.
  • the active layer is formed, so that the pattern of the active layer can be precisely controlled, and the contact area between the active layer and the source and drain can be increased, and the characteristics of the OTFT array substrate can be greatly improved.
  • not only the organic material of the isolation wall but also the metal or metal oxide of the source and the drain are in contact with the active layer, so that different processing methods are required in order to make the active layer uniform. The process is complicated, and in the embodiment of the present invention, only the metal and metal oxide of the source and the drain are in contact with the active layer, so that the process is simpler when the active layer is formed by the inkjet printing process.
  • the method for fabricating the OTFT array substrate shown in Fig. 2 can be combined with the method for fabricating the organic thin film transistor shown in Fig. 1 (including steps S1 - S5). After the organic thin film transistor is completed, the following steps can be continued to fabricate the OTFT array substrate.
  • a material for forming a passivation layer is deposited by a plasma chemical vapor deposition process, and a passivation layer is formed by a patterning process, and the passivation layer is formed to connect pixels.
  • a material for forming a pixel electrode on the passivation layer such as indium tin oxide (ITO), indium oxide (IZO) or other transparent conductive material, and forming a pixel electrode by a patterning process, the pixel electrode is passivated
  • ITO indium tin oxide
  • IZO indium oxide
  • the via of the layer is electrically connected to the drain of the organic thin film transistor.
  • Embodiments of the present invention also provide a display device including the above OTFT array substrate, the display device including any of the above OTFT array substrates.
  • the display device provided by the embodiment of the present invention includes, for example, a display device such as a liquid crystal panel, an organic light-emitting diode (OLED) panel, an electrophoretic display panel, a mobile phone, a monitor, and a tablet.
  • a display device such as a liquid crystal panel, an organic light-emitting diode (OLED) panel, an electrophoretic display panel, a mobile phone, a monitor, and a tablet.

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Abstract

提供一种有机薄膜晶体管，有机薄膜晶体管阵列基板及显示装置。有机薄膜晶体管包括：透明基板（1），形成在透明基板（1）上的源极（21）和漏极（22），形成在透明基板（1）上并设置在源极（21）与漏极（22）之间的有源层（4），有源层（4）由有机半导体材料形成，形成在有源层（4）上的栅绝缘层（5），形成在栅绝缘层（5）上的栅极（6），以及设置在透明基板（1）上的第一隔离墙（31）和第二隔离墙（32），源极（21）和漏极（22）分别覆盖第一隔离墙（31）和第二隔离墙（32）的内侧。

Description

有机薄膜晶体管、 有机薄膜晶体管阵列基板及显示装置 技术领域
本发明的实施例涉及有机薄膜晶体管、 有机薄膜晶体管阵列基板及显示 装置。 背景技术
有机薄膜晶体管 （ Organic Thin Film Transistor , OTFT )具有工艺简单、 成本低及柔韧性良好等优点， 在平板显示领域中应用前景广阔。 因此， 有机 薄膜晶体管（OTFT )阵列基板的研究与开发受到了广泛关注。 通常在 OTFT 阵列基板的制造过程中需要多次构图工艺， 以形成图案化的层结构。 典型的 OTFT具有这样的结构： 栅电极和由有机半导体材料制成的有源层形成在基 板上， 栅极绝缘膜置于它们之间， 彼此分隔的源电极和漏电极接触有源层， 并对应于栅电极的两侧且与栅电极绝缘。 有机半导体材料通常具有低化学稳 定性和光学稳定性， 其图案化艮难 JU艮复杂。 目前出现一种喷墨打印工艺， 用以形成 OTFT的有源层。 这种喷墨打印工艺是将墨滴 （即， 将形成图案所 釆用的材料溶解在特定溶剂中而形成的溶浆 )打印在需要形成图案的区域中， 以形成所需图案的工艺。
在制造 OTFT或 OTFT 阵列基板的过程中， 当使用喷墨打印工艺形成 OTFT 的有源层时， 由于墨滴的流动性会造成有源层的图案不能严格达到工 艺要求， 即造成有源层的图案不够精准， 从而影响 OTFT的性能， 进而影响 OTFT阵列基板的性能。 发明内容
本发明的一个实施例提供了一种有机薄膜晶体管， 其包括： 透明基板； 源极和漏极， 形成在所述透明基板上； 有源层， 形成在所述透明基板上， 并 且设置在所述源极与所述漏极之间， 所述有源层由有机半导体材料形成； 栅 绝缘层， 形成在所述有源层上； 栅极， 形成在所述栅绝缘层上； 以及第一隔 离墙和第二隔离墙， 设置在所述透明基板上， 所述源极和所述漏极分别覆盖 所述第一隔离墙的内侧和所述第二隔离墙的内侧。
本发明的另一个实施例提供了一种有机薄膜晶体管阵列基板， 其包括透 明基板以及形成在所述透明基板上的有机薄膜晶体管， 所述有机薄膜晶体管 包括： 源极和漏极， 形成在所述透明基板上； 有源层， 形成在所述透明基板 上， 并且设置在所述源极与所述漏极之间， 所述有源层由有机半导体材料形 成； 栅绝缘层， 形成在所述有源层上； 栅极， 形成在所述栅绝缘层上； 以及 第一隔离墙和第二隔离墙， 设置在所述透明基板上， 所述源极和所述漏极分 别覆盖所述第一隔离墙的内侧和所述第二隔离墙的内侧。
本发明的另一个实施例提供了一种显示装置， 其包括有机薄膜晶体管阵 列基板， 所述有机薄膜晶体管阵列基板包括透明基板以及形成在所述透明基 板上的有机薄膜晶体管， 所述有机薄膜晶体管包括： 源极和漏极， 形成在所 述透明基板上； 有源层， 形成在所述透明基板上， 并且设置在所述源极与所 述漏极之间， 所述有源层由有机半导体材料形成； 栅绝缘层， 形成在所述有 源层上； 栅极， 形成在所述栅绝缘层上； 以及第一隔离墙和第二隔离墙， 设 置在所述透明基板上， 所述源极和所述漏极分别覆盖所述第一隔离墙的内侧 和所述第二隔离墙的内侧。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1 为本发明的实施例提供的一种有机薄膜晶体管 （OTFT ) 的剖面结 构示意图； 以及
图 2为本发明的实施例提供的一种 OTFT阵列基板的剖面结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个"或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。
本发明的实施例提供了一种有机薄膜晶体管， 以提高有机薄膜晶体管的 特性， 简化其制造工艺， 以及降低其制造成本。 本发明的实施例还提供了包 括上述有机薄膜晶体管的有机薄膜晶体管阵列基板和显示装置。
下面参照图 1说明本发明的实施例提供的有机薄膜晶体管。
如图 1所示， 本发明的实施例提供的有机薄膜晶体管例如包括： 透明基 板 1 ; 源极 21和漏极 22, 形成在透明基板 1上； 有源层 4, 形成在透明基板 1上， 并且设置在源极 21与漏极 22之间， 有源层 4由有机半导体材料形成； 栅绝缘层 5 , 形成在有源层 4上； 栅极 6, 形成在栅绝缘层 5上； 以及第一隔 离墙 31和第二隔离墙 32, 设置在透明基板 1上， 源极 21和漏极 22分别覆 盖第一隔离墙 31的内侧和第二隔离墙 32的内侧。
在本发明的实施例中， 透明基板 1可以是玻璃基板、 塑料基板等。
在本发明的实施例中， 第一隔离墙 31和第二隔离墙 32可以由有机材料 (例如， 光固化树脂或热固化树脂）形成， 或者也可以由无机材料形成。
在本发明的实施例中， 分别将第一隔离墙 31和第二隔离墙 32朝向有源 层 4的一侧称为第一隔离墙 31的内侧和第二隔离墙 32的内侧。
需要说明的是， 在本发明的实施例中， 只需要有机薄膜晶体管的源极和 漏极分别覆盖第一隔离墙的内侧和第二隔离墙的内侧即可， 对于第一隔离墙 和第二隔离墙的其它部分可以被源极和漏极覆盖， 也可以不被覆盖。
在本实施例中， 如图 1所示， 有机薄膜晶体管的源极 21和漏极 22分别 覆盖第一隔离墙 31的内侧和第二隔离墙 32的内侧， 并且还分别覆盖第一隔 离墙 31和第二隔离墙 32的上表面， 即， 有机薄膜晶体管的源极 21和漏极 22分别完全覆盖第一隔离墙 31和第二隔离墙 32。
在本实施例中第一隔离墙 31和第二隔离墙 32可以同层设置， 但是在本 发明的其它实施例中第一隔离墙 31和第二隔离墙 32也可以设置在不同层中。 在本发明的实施例中， 同层是指利用同种材料制成的同一层薄膜， 同层设置 是针对至少两种图案而言的， 是指由同一层薄膜所形成的至少两种图案这种 结构， 例如， 是通过构图工艺在同种材料制成的同一层薄膜上形成的至少两 种图案。 本实施例中第一隔离墙和第二隔离墙同层设置是指， 第一隔离墙和 第二隔离墙是由同种材料制成的同一层薄膜所形成的两种图案。 需要说明的 是， 在本实施例中第一隔离墙和第二隔离墙是形状相同、 位置不同的两种图 案。 在本实施例中第一隔离墙 31和第二隔离墙 32的高度为例如大约 1 ~5微 米， 但是在本发明的其它实施例中第一隔离墙 31和第二隔离墙 31也可以具 有其它不同的高度。
在本实施例中， 如图 1所示， 栅极 6和栅绝缘层 5的形状一致。 在本发 明的实施例中， 形状一致是指栅极 6和栅绝缘层 5的俯视图的形状和大小完 全相同，这样就可以利用同一个掩模板形成形状一致的栅极 6和栅绝缘层 5 , 有利于减少生产成本。 当然， 在本发明的其它实施例中， 栅绝缘层 5和栅极 6 的形状也可以不一致， 比如如传统的薄膜晶体管一样， 栅绝缘层完全覆盖 整个透明基板。
在本发明的实施例提供的有机薄膜晶体管中， 通过分别被隔离墙垫高的 源极和漏极来限定用于形成有源层的区域， 从而能够在所限定的区域中利用 喷墨打印工艺形成有源层， 这样就可以精确地控制有源层的图案， 并且可以 使有源层与源极和漏极实现更大面积的接触， 从而提高了 OTFT的特性。 另 外， 在现有技术中， 与有源层接触的不仅有隔离墙的有机材料， 而且有源极 和漏极的金属或金属氧化物等， 这样为了使有源层成膜均匀， 需要不同的处 理方法， 工艺复杂， 而在本发明的实施例中， 与有源层接触的只有源极和漏 极的金属或金属氧化物等， 这样就使得利用喷墨打印工艺形成有源层时工艺 更简单。
下面说明本发明的实施例提供的有机薄膜晶体管的制造方法， 其可用于 制造图 1所示的有机薄膜晶体管。 本发明的实施例提供的有机薄膜晶体管 （参照图 1 ) 的制造方法例如包 括以下步骤：
51、 在透明基板上， 釆用印刷方式并且使用有机材料例如树脂形成第一 隔离墙和第二隔离墙， 树脂的成型方式可以釆用光固化或者热固化。 当然， 在本发明的其它实施例中， 步骤 S1 也可以釆用例如溅射或化学气相沉积工 艺并结合光刻工艺并且使用无机材料形成第一隔离墙和第二隔离墙。
52、 沉积金属或金属氧化物等电极材料在第一和第二隔离墙上， 并通过 光刻 （包括曝光、 显影等）工艺和刻蚀工艺形成源极和漏极。
53、 釆用喷墨打印方式将有机半导体材料打印在源极和漏极限定的区域 中， 形成有源层。
54、 旋涂或沉积栅极绝缘材料于有源层上方， 形成栅绝缘层。
55、 在栅绝缘层上沉积金属或金属氧化物等电极材料， 然后利用同一掩 模板，通过一次掩模形成栅极和栅绝缘层。 当然， 在本发明的其它实施例中， 也可以如传统的薄膜晶体管一样分别掩模形成栅极和栅绝缘层， 这样形成的 栅绝缘层和栅极的形状不一致， 栅绝缘层可以完全覆盖整个透明基板。
通过上述方法，可以制造本发明实施例的如图 1所示的有机薄膜晶体管。 下面参照图 2说明本发明的实施例提供的 OTFT阵列基板。 本发明的实 施例提供的 OTFT阵列基板可以包括多条栅线和数据线， 这些栅线和数据线 彼此交叉而限定了排列为阵列的多个像素单元， 图 2仅示出了 OTFT阵列基 板上的一个像素单元的结构。
如图 2所示， 本发明的实施例提供的 OTFT阵列基板例如包括透明基板 1 以及形成在透明基板 1上的有机薄膜晶体管， 该有机薄膜晶体管包括： 源 极 21和漏极 22, 形成在透明基板 1上； 有源层 4, 形成在透明基板 1上， 并 且设置在源极 21与漏极 22之间， 有源层 4由有机半导体材料形成； 栅绝缘 层 5 , 形成在有源层 4上； 栅极 6, 形成在栅绝缘层 5上； 以及第一隔离墙 31和第二隔离墙 32,设置在透明基板 1上， 源极 21和漏极 22分别覆盖第一 隔离墙 31的内侧和第二隔离墙 32的内侧。在本发明的实施例中，上述 OTFT 阵列基板还包括： 覆盖有机薄膜晶体管的钝化层 7 , 钝化层 7形成有过孔； 以及像素电极 8, 通过钝化层 7的过孔与有机薄膜晶体管的漏极 22电连接。
在本发明的实施例中， 透明基板 1可以是玻璃基板、 塑料基板等。 在本发明的实施例中， 第一隔离墙 31和第二隔离墙 32可以由有机材料 (例如， 光固化树脂或热固化树脂）形成， 或者也可以由无机材料形成。
在本发明的实施例中， 分别将第一隔离墙 31和第二隔离墙 32朝向有源 层 4的一侧称为第一隔离墙 31的内侧和第二隔离墙 32的内侧。
需要说明的是， 在本发明的实施例中， 只需要有机薄膜晶体管的源极和 漏极分别覆盖第一隔离墙的内侧和第二隔离墙的内侧即可， 对于第一隔离墙 和第二隔离墙的其它部分可以被源极和漏极覆盖， 也可以不被覆盖。
在本实施例中， 如图 2所示， 有机薄膜晶体管的源极 21和漏极 22分别 覆盖第一隔离墙 31的内侧和第二隔离墙 32的内侧， 并且还分别覆盖第一隔 离墙 31和第二隔离墙 32的上表面， 即， 有机薄膜晶体管的源极 21和漏极 22分别完全覆盖第一隔离墙 31和第二隔离墙 32。
在本实施例中第一隔离墙 31和第二隔离墙 32可以同层设置， 但是在本 发明的其它实施例中第一隔离墙 31和第二隔离墙 31也可以设置在不同层中。 在本发明的实施例中， 同层是指利用同种材料制成的同一层薄膜， 同层设置 是针对至少两种图案而言的， 是指由同一层薄膜所形成的至少两种图案这种 结构， 例如， 是通过构图工艺在同种材料制成的同一层薄膜上形成的至少两 种图案。 本实施例中第一隔离墙和第二隔离墙同层设置是指， 第一隔离墙和 第二隔离墙是由同种材料制成的同一层薄膜所形成的两种图案。 需要说明的 是， 在本实施例中第一隔离墙和第二隔离墙是形状相同、 位置不同的两种图 案。 在本实施例中， 第一隔离墙 31和第二隔离墙 32的高度为例如大约 1~5 微米， 但是在本发明的其它实施例中第一隔离墙 31和第二隔离墙 32也可以 具有其它不同的高度。
在本实施例中， 如图 2所示， 栅极 6和栅绝缘层 5的形状一致。 这样就 可以利用同一个掩模板形成形状一致的栅极 6和栅绝缘层 5 , 有利于减少生 产成本， 简化工艺。 当然， 在本发明的其它实施例中， 栅极 6和栅绝缘层 5 的形状也可以不一致。
在本发明的实施例提供的 OTFT阵列基板中， 通过分别被隔离墙垫高的 源极和漏极来限定用于形成有源层的区域， 从而能够在所限定的区域中利用 喷墨打印工艺形成有源层， 这样就可以精确控制有源层的图案， 同时可以增 大有源层与源漏极的接触面积， 大大提高 OTFT阵列基板的特性。 另外， 在 现有技术中， 与有源层接触的不仅有隔离墙的有机材料， 而且有源极和漏极 的金属或金属氧化物等，这样为了使有源层成膜均匀，需要不同的处理方法， 工艺复杂， 而在本发明的实施例中， 与有源层接触的只有源极和漏极的金属 或金属氧化物等 , 这样就使得利用喷墨打印工艺形成有源层时工艺更简单。
下面说明本发明的实施例提供的 OTFT阵列基板的制造方法， 其可用于 制造图 2所示的 OTFT阵列基板。
图 2所示的 OTFT阵列基板的制造方法可以结合图 1所示的有机薄膜晶 体管的制造方法（包括步骤 S1-S5 ) , 在完成有机薄膜晶体管后， 可以继续 进行以下步骤制造 OTFT阵列基板。
56、 在形成有上述有机薄膜晶体管的透明基板上， 釆用等离子体化学气 相沉积工艺沉积用于形成钝化层的材料， 并通过构图工艺形成钝化层， 该钝 化层形成有用于连接像素电极和有机薄膜晶体管的漏极的过孔。
57、 在钝化层上沉积用于形成像素电极的材料， 例如氧化铟锡（ITO ) 、 氧化铟辞（IZO )或其它透明导电材料， 并通过构图工艺形成像素电极， 该 像素电极通过钝化层的过孔而与有机薄膜晶体管的漏极电连接。
本发明的实施例还提供了一种包括上述 OTFT阵列基板的显示装置， 该 显示装置包括上述任一 OTFT阵列基板。 本发明的实施例提供的显示装置例 如包括液晶面板、 有机发光二极管（ Organic Light-Emitting Diode , OLED ) 面板、 电泳显示面板、 手机、 监视器、 平板电脑等显示装置。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种有机薄膜晶体管， 包括：
透明基板；
源极和漏极， 形成在所述透明基板上；
有源层，形成在所述透明基板上，并且设置在所述源极与所述漏极之间， 所述有源层由有机半导体材料形成；
栅绝缘层， 形成在所述有源层上；
栅极， 形成在所述栅绝缘层上； 以及
第一隔离墙和第二隔离墙， 设置在所述透明基板上， 所述源极和所述漏 极分别覆盖所述第一隔离墙的内侧和所述第二隔离墙的内侧。
2、根据权利要求 1所述的有机薄膜晶体管， 其中， 所述源极和所述漏极 分别完全覆盖所述第一隔离墙和所述第二隔离墙。
3、根据权利要求 1所述的有机薄膜晶体管， 其中， 所述第一隔离墙和所 述第二隔离墙由光固化树脂或热固化树脂形成。
4、根据权利要求 1所述的有机薄膜晶体管， 其中， 所述栅极和所述栅绝 缘层的形状一致。
5、根据权利要求 1所述的有机薄膜晶体管， 其中， 所述第一隔离墙和所 述第二隔离墙同层设置。
6、根据权利要求 5所述的有机薄膜晶体管， 其中， 所述第一隔离墙和所 述第二隔离墙的高度的范围是 1~5微米。
7、一种有机薄膜晶体管阵列基板， 包括透明基板以及形成在所述透明基 板上的有机薄膜晶体管， 所述有机薄膜晶体管包括：
源极和漏极， 形成在所述透明基板上；
有源层，形成在所述透明基板上，并且设置在所述源极与所述漏极之间， 所述有源层由有机半导体材料形成；
栅绝缘层， 形成在所述有源层上；
栅极， 形成在所述栅绝缘层上； 以及
第一隔离墙和第二隔离墙， 设置在所述透明基板上， 所述源极和所述漏 极分别覆盖所述第一隔离墙的内侧和所述第二隔离墙的内侧。
8、根据权利要求 7所述的有机薄膜晶体管阵列基板， 其中， 所述源极和 漏极分别完全覆盖所述第一隔离墙和第二隔离墙。
9、 根据权利要求 7所述的有机薄膜晶体管阵列基板， 还包括： 钝化层， 覆盖所述有机薄膜晶体管， 所述钝化层形成有过孔； 以及 像素电极， 通过所述过孔而与所述漏极电连接。
10、 根据权利要求 7所述的有机薄膜晶体管阵列基板， 其中， 所述第一 隔离墙和所述第二隔离墙由光固化树脂或热固化树脂形成。
11、 根据权利要求 7所述的有机薄膜晶体管阵列基板， 其中， 所述栅极 和所述栅绝缘层的形状一致。
12、 根据权利要求 7所述的有机薄膜晶体管阵列基板， 其中， 所述第一 隔离墙和所述第二隔离墙同层设置。
13、根据权利要求 12所述的有机薄膜晶体管阵列基板， 其中， 所述第一 隔离墙和所述第二隔离墙的高度的范围是 1~5微米。
14、 一种显示装置， 包括有机薄膜晶体管阵列基板， 所述有机薄膜晶体 管阵列基板包括透明基板以及形成在所述透明基板上的有机薄膜晶体管， 所 述有机薄膜晶体管包括：
源极和漏极， 形成在所述透明基板上；
有源层，形成在所述透明基板上，并且设置在所述源极与所述漏极之间， 所述有源层由有机半导体材料形成；
栅绝缘层， 形成在所述有源层上；
栅极， 形成在所述栅绝缘层上； 以及
第一隔离墙和第二隔离墙， 设置在所述透明基板上， 所述源极和所述漏 极分别覆盖所述第一隔离墙的内侧和所述第二隔离墙的内侧。
15、根据权利要求 14所述的显示装置， 其中， 所述源极和漏极分别完全 覆盖所述第一隔离墙和第二隔离墙。
16、根据权利要求 14所述的显示装置，所述有机薄膜晶体管阵列基板还 包括：
钝化层， 覆盖所述有机薄膜晶体管， 所述钝化层形成有过孔； 以及 像素电极， 通过所述过孔而与所述漏极电连接。
17、根据权利要求 14所述的显示装置， 其中， 所述第一隔离墙和所述第 二隔离墙由光固化树脂或热固化树脂形成。
18、根据权利要求 14所述的显示装置， 其中 所述栅极和所述栅绝缘层 的形状一致。
19、根据权利要求 14所述的显示装置， 其中 所述第一隔离墙和所述第 二隔离墙同层设置。
20、根据权利要求 19所述的显示装置， 其中 所述第一隔离墙和所述第 二隔离墙的高度的范围是 1~5微米。
PCT/CN2012/084336 2011-11-23 2012-11-08 有机薄膜晶体管、有机薄膜晶体管阵列基板及显示装置 WO2013075587A1 (zh)

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