WO2013075367A1 - 液晶显示面板及液晶显示装置 - Google Patents

液晶显示面板及液晶显示装置 Download PDF

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Publication number
WO2013075367A1
WO2013075367A1 PCT/CN2011/083489 CN2011083489W WO2013075367A1 WO 2013075367 A1 WO2013075367 A1 WO 2013075367A1 CN 2011083489 W CN2011083489 W CN 2011083489W WO 2013075367 A1 WO2013075367 A1 WO 2013075367A1
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WIPO (PCT)
Prior art keywords
scan
charging
liquid crystal
thin film
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2011/083489
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English (en)
French (fr)
Inventor
侯鸿龙
李佳育
贺成明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US13/381,081 priority Critical patent/US8665264B2/en
Publication of WO2013075367A1 publication Critical patent/WO2013075367A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present invention relates to a liquid crystal display panel, and more particularly to a liquid crystal display panel capable of operating at a higher update rate.
  • the present invention also relates to a liquid crystal display device using the liquid crystal display panel.
  • the liquid crystal display panel is widely used in modern information equipment such as televisions, notebooks, computers, mobile phones, and personal digital assistants.
  • each of the gate electrodes can be charged while scanning the scanning lines. Since the number of gates included in the liquid crystal display panel in the high-definition liquid crystal display device is large, the charging time available for each gate becomes shorter. If the operation of the higher update rate is performed again, the problem that the gate charging time is insufficient will become more conspicuous, resulting in a decrease in the product experience of the liquid crystal display device.
  • the present invention provides a charging time that can be utilized by the gate and can satisfy a higher update rate. Operating liquid crystal display panel.
  • the present invention also provides a liquid crystal display device in which an operation time at which a gate can be utilized is sufficient and a higher update rate can be satisfied.
  • the technical solution adopted by the present invention is to provide a liquid crystal display panel including a plurality of charging scan lines, a plurality of discharge scan lines, a plurality of first data lines, a plurality of second data lines, and a plurality of columns of pixels.
  • each pixel unit includes a charge thin film transistor, a discharge thin film transistor and a pixel electrode, and a gate of the charge thin film transistor is electrically connected to the charge scan line,
  • the source of the charge thin film transistor is electrically connected to the first data line or the second data line
  • the drain of the charge thin film transistor is electrically connected to the pixel electrode
  • the gate of the discharge thin film transistor is electrically connected to the discharge scan line
  • the source of the discharge thin film transistor is electrically connected
  • the discharge scan line is located on a charge scan line of the same pixel unit row, and the discharge thin film transistor
  • the pole electrode is connected to the
  • one scan is defined as one scan time frame, and in the case that the liquid crystal display panel scans and charges two adjacent charging scan lines, the time frame is the first scan time frame, and the liquid crystal display The panel scans the discharge scan line of the same pixel unit connected to the two adjacent charged scan lines scanned in the third scan time frame pair.
  • one of the pixel units corresponding to two adjacent charging scan lines passes through the charging film of the pixel unit.
  • the source of the transistor is electrically connected to the first data line
  • the other pixel unit is electrically connected to the second data line via the source of the charging thin film transistor of the pixel unit, and the first data line and the second data line are respectively adjacent to the two data lines
  • the source of the charge thin film transistor of the pixel unit corresponding to the charge scan line inputs a data signal.
  • the liquid crystal display panel scans four adjacent charging scan lines, and simultaneously, in the same time frame, four phases of different pixel unit rows with the four adjacent charging scan lines scanned.
  • the adjacent discharge scan line is scanned.
  • the data driver applies different time-series data signals to the first data line and the second data line to implement two-dimensional display/three-dimensional display switching.
  • a liquid crystal display panel including a plurality of charging scan lines, a plurality of discharge scan lines, a plurality of first data lines, and a plurality of second data lines.
  • the wires are arranged in parallel with each other in the second direction and are insulated from the charge scan line and the discharge scan line.
  • Each pixel unit includes a charge thin film transistor, a discharge thin film transistor and a pixel electrode, and the gate of the charge thin film transistor is electrically connected to the charge scan line, and the charge film
  • the source of the transistor is electrically connected to the first data line or the second data line
  • the drain of the charge thin film transistor is electrically connected to the pixel electrode
  • the gate of the discharge thin film transistor is electrically connected to the discharge scan line
  • the source of the discharge thin film transistor is electrically connected to the
  • the discharge scan line is located on the charge scan line of the same pixel unit row
  • the drain of the discharge thin film transistor is electrically connected a liquid electrode display panel in which two adjacent charged charging scan lines are scanned, and two adjacent charging scanning lines are scanned in two rows of different pixel unit rows in the same time frame The adjacent discharge scan line is scanned.
  • one scan is defined as one scan time frame, and in the case that the liquid crystal display panel scans and charges two adjacent charging scan lines, the time frame is the first scan time frame, and the liquid crystal display The panel scans the discharge scan line of the same pixel unit connected to the two adjacent charged scan lines scanned in the third scan time frame pair.
  • one of the pixel units corresponding to two adjacent charging scan lines passes through the charging film of the pixel unit.
  • the source of the transistor is electrically connected to the first data line
  • the other pixel unit is electrically connected to the second data line via the source of the charging thin film transistor of the pixel unit, and the first data line and the second data line are respectively adjacent to the two data lines
  • the source of the charge thin film transistor of the pixel unit corresponding to the charge scan line inputs a data signal.
  • the liquid crystal display panel scans four adjacent charging scan lines, and simultaneously, in the same time frame, four phases of different pixel unit rows with the four adjacent charging scan lines scanned.
  • the adjacent discharge scan line is scanned.
  • one scan is defined as one scan time frame, and in a case where the liquid crystal display panel scans and charges four adjacent charging scan lines, the time frame is the first scan time frame, and the liquid crystal display panel At the second scan, the frame scans the discharge scan lines that are connected to the four adjacent charged scan lines that are connected to the same pixel unit.
  • the liquid crystal display panel further includes a data driver, and the plurality of first data lines and the plurality of second data lines are respectively electrically connected to the data driver, and the data signals are transmitted to the source of the charging thin film transistor.
  • the data driver applies different time-series data signals to the first data line and the second data line to implement two-dimensional display/three-dimensional display switching.
  • the liquid crystal display panel further includes a scan driver, the scan driver includes a plurality of first output ends and a plurality of second output ends, and the plurality of first output ends and the plurality of second output ends are alternately arranged.
  • One output terminal is electrically connected to two adjacent charging scan lines
  • the second output end is electrically connected to two adjacent discharge scan lines
  • two charging scan lines connected to the same first output end are electrically connected by means of an over-the-line method, and are connected to the same
  • the two discharge scan lines at the second output are electrically connected by an over-the-line method.
  • the charge thin film transistor further includes a first charge thin film transistor and a second charge thin film transistor, the pixel electrode further comprising two first sub-pixel electrodes and second sub-pixel electrodes having different orientations, the first charge
  • the drain of the thin film transistor is electrically connected to the first sub-pixel electrode
  • the drain of the second charging thin film transistor is electrically connected to the second sub-pixel electrode
  • the gate of the first charging thin film transistor and the gate of the second charging thin film transistor are electrically connected to the same strip
  • the charging scan line, the source of the first charging thin film transistor and the source of the second charging thin film transistor are electrically connected to the same first data line or the second data line.
  • Still another technical solution adopted by the embodiment of the present invention is to provide a liquid crystal display device including a liquid crystal display panel.
  • the liquid crystal display panel includes a plurality of charging scan lines, a plurality of discharge scan lines, a plurality of first data lines, a plurality of second data lines, and a plurality of columns of pixel units, and the charge scan lines and the discharge scan lines are mutually identical to each other in the first direction.
  • each of the pixel units includes a charge thin film transistor, a discharge thin film transistor, and a pixel electrode, and the charge film
  • the gate of the transistor is electrically connected to the charging scan line
  • the source of the charging thin film transistor is electrically connected to the first data line or the second data line
  • the drain of the charging thin film transistor is electrically connected to the pixel electrode
  • the gate of the discharging thin film transistor is electrically connected to the discharging scan line
  • the source of the charging thin film transistor is electrically connected to the charging scan line
  • the drain of the charging thin film transistor is electrically connected to the pixel electrode, wherein the liquid crystal display panel scans two adjacent charging scan lines while in the same time frame Two adjacent discharge sweeps in different pixel cell rows with two adjacent charged scan lines being scanned Line scan.
  • one scan is defined as one scan time frame, and in the case that the liquid crystal display panel scans and charges two adjacent charging scan lines, the time frame is the first scan time frame, and the liquid crystal display The panel scans the discharge scan line of the same pixel unit connected to the two adjacent charged scan lines scanned in the third scan time frame pair.
  • one of the pixel units corresponding to two adjacent charging scan lines passes through the charging film of the pixel unit.
  • the source of the transistor is electrically connected to the first data line
  • the other pixel unit is electrically connected to the second data line via the source of the charging thin film transistor of the pixel unit, and the first data line and the second data line are respectively adjacent to the two data lines
  • the source of the charge thin film transistor of the pixel unit corresponding to the charge scan line inputs a data signal.
  • the liquid crystal display panel scans four adjacent charging scan lines, and simultaneously, in the same time frame, four phases of different pixel unit rows with the four adjacent charging scan lines scanned.
  • the adjacent discharge scan line is scanned.
  • the liquid crystal display panel further includes a data driver, and the plurality of first data lines and the plurality of second data lines are respectively electrically connected to the data driver, and the data signals are transmitted to the source of the charging thin film transistor.
  • the liquid crystal display panel further includes a scan driver, the scan driver includes a plurality of first output ends and a plurality of second output ends, and the plurality of first output ends and the plurality of second output ends are alternately arranged.
  • One output terminal is electrically connected to two adjacent charging scan lines
  • the second output end is electrically connected to two adjacent discharge scan lines
  • two charging scan lines connected to the same first output end are electrically connected by means of an over-the-line method, and are connected to the same
  • the two discharge scan lines at the second output are electrically connected by an over-the-line method.
  • the liquid crystal display panel provided by the embodiment of the present invention scans two adjacent charging scan lines and simultaneously and simultaneously in the same time frame.
  • the two adjacent charging scan lines scanned are scanned by two adjacent discharge scan lines of different pixel unit rows, and only one scan line is scanned with respect to one scan time.
  • the embodiment of the present invention can reduce the number of scans.
  • the charging time of the gate of the thin film transistor is increased, and the liquid crystal display panel can be operated at a high update frequency, thereby improving the product experience of the liquid crystal display panel and the liquid crystal display device.
  • FIG. 1 is a simplified schematic view showing an electrode wiring relationship of a liquid crystal display panel of the present invention
  • FIG. 2 is a schematic view showing the electrode structure of the first embodiment of the liquid crystal display panel of the present invention and the scanning signal timing thereof;
  • FIG. 3 is a schematic view showing an electrode structure of a second embodiment of the liquid crystal display panel of the present invention, and a scan signal timing thereof;
  • FIG. 4 is a schematic structural view of a liquid crystal display device of the present invention.
  • a specific embodiment of a liquid crystal display panel of the present invention is as follows:
  • a liquid crystal display panel 1 is a simplified schematic view showing an electrode wiring relationship of a liquid crystal display panel of the present invention.
  • a liquid crystal display panel 1 includes a plurality of charging scan lines 11 , a plurality of discharge scan lines 12 , a plurality of first data lines 13 , a plurality of second data lines 14 , and a plurality of thin film transistors (Thin Film Transistor (not labeled), multi-column pixel unit (not labeled), scan driver 15 and data driver 16.
  • the plurality of charging scanning lines 11 and the plurality of discharging scanning lines 12 are alternately arranged in parallel with each other in the first direction, and one charging scanning line 11 and one discharging scanning line 12 are connected to the pixel unit of the same row (ie, the same pixel unit row).
  • the first data lines 13 are arranged in parallel with each other in the column direction and insulated from the charge scan lines 11 and the discharge scan lines 12, and the second data lines 14 are arranged in parallel with each other in the column direction and insulated from the charge scan lines 11 and the discharge scan lines 12, And the first data line 13 and the second data line 14 are alternately arranged.
  • Each of the pixel units includes a charge thin film transistor, a discharge thin film transistor, and a pixel electrode.
  • the gate of the charge thin film transistor is electrically connected to the charge scan line 11.
  • the source of the charge thin film transistor is electrically connected to the first data line 13 or the second data line 14, and is charged.
  • the drain of the thin film transistor is electrically connected to the pixel electrode, the gate of the discharge thin film transistor is electrically connected to the discharge scan line 12, and the source of the discharge thin film transistor is electrically connected to the charge scan line 12 of the same pixel unit row, the discharge thin film transistor The drain is electrically connected to the pixel electrode.
  • the gate of the charge thin film transistor When the charging scan line 11 of the liquid crystal display panel 1 inputs a scan pulse, the gate of the charge thin film transistor is turned on, and the data signal of the first data line or the second data line is input to the pixel electrode via the source of the charge thin film transistor.
  • the discharge scan line 12 of the liquid crystal display panel 1 After the scanning of the charging scan line 11 is completed, the discharge scan line 12 of the liquid crystal display panel 1 inputs a scan pulse, the gate of the discharge thin film transistor is turned on, and the charge scan line 11 located in the same pixel unit row as the discharge scan line 12 passes through the discharge charge thin film transistor.
  • the source is electrically connected to the pixel electrode, and since the charging scan line 11 located in the same pixel unit row as the discharge scanning line 12 has finished scanning and remains at a zero potential, the pixel electrode is discharged.
  • the charging thin film transistor further includes a first charging thin film transistor and a second charging thin film transistor
  • the pixel electrode further includes two first sub-pixel electrodes and second sub-pixel electrodes having different pointing directions
  • a drain of a charging thin film transistor is electrically connected to the first sub-pixel electrode
  • a drain of the second charging thin film transistor is electrically connected to the second sub-pixel electrode
  • a gate of the first charging thin film transistor and a gate of the second charging thin film transistor are electrically connected
  • the source of the first charging thin film transistor and the source of the second charging thin film transistor are electrically connected to the same first data line or the second data line.
  • the liquid crystal molecules can be driven to be aligned along different directions by two differently directed sub-pixel electrodes, thereby improving the wide viewing angle performance of the liquid crystal display panel.
  • the liquid crystal display panel 1 further includes a data driver 16 and a scan driver 15.
  • the plurality of first data lines 13 and the plurality of second data lines 14 are electrically connected to the data driver 16, respectively, and transmit the data signals to the source of the charge thin film transistor.
  • the data driver 16 can apply different timing data signals to the first data line 13 and the second data line 14 to implement two-dimensional display/three-dimensional (2D/3D) display switching.
  • the scan driver 15 includes a plurality of first output terminals (not labeled) and a plurality of second output terminals (not labeled), the plurality of first output terminals and the plurality of second output terminals are alternately arranged, and the first output terminal is electrically connected to the two Adjacent charging scan lines 11 and second output terminals electrically connect two adjacent discharge scan lines 12.
  • the two charging scan lines connected to the same first output end are electrically connected by an over-the-line method, and the two discharge scan lines connected to the same second output end are electrically connected by an over-line method.
  • the charge scan line 11 represents the charge scan line N to the charge scan line N+7
  • the discharge scan line 12 represents the discharge scan line N to the discharge scan line N+7, the same number of charge scan lines and discharge scan lines.
  • the pixel cells electrically connected to the same row, for example, the charge scan line N and the discharge scan line N are electrically connected to the pixel unit of the Nth row, and t1 to t6 represent the time-order scan time frames.
  • the charge scan line N and the charge scan line N+2 are simultaneously input with a high-level scan pulse signal by the scan driver 15, and the charge scan line N and the charge scan line N+2 are electrically charged.
  • the gate of the connected thin film transistor is turned on and the data voltage is input through the first data line 13 and the second data line 14 to cause the pixel unit to display a corresponding image.
  • the discharge scan line N and the discharge scan line N+2 are simultaneously turned off. Therefore, when the frame at the time t1 ends, the data voltage of the pixel unit corresponding to the charging scan line N and the charging scan line N+2 can continue to be maintained by the storage capacitor.
  • the charge scan line N and the charge scan line N+2 simultaneously end the scan to maintain the low level, and the charge scan line N+1 and the charge scan line N+3 are simultaneously input to the scan pulse of the high level by the scan driver 15.
  • the signal, the gate of the thin film transistor electrically connected to the charge scan line N+1 and the charge scan line N+3 is turned on and the data voltage is input through the first data line 13 and the second data line 14 to cause the pixel unit to display a corresponding image.
  • the charge scan line N+1 and the charge scan line N+3 end the scan to maintain the low level, the charge scan line N+2 and the charge scan line N+4, and the discharge scan line N and the discharge scan line N+ 2 simultaneously inputting a high-level scan pulse signal by the scan driver 15, the gate of the thin film transistor electrically connected to the charge scan line N+2 and the charge scan line N+4 is turned on and passes through the first data line 13 and the second data line
  • the input data voltage is input to cause the pixel unit to display the corresponding image, and since the gate of the thin film transistor electrically connected to the discharge scan line N and the discharge scan line N+2 is turned on, the charge scan line N and the charge scan line N+2 correspond to The data voltage of the pixel unit is discharged after maintaining two times of t1 and t2.
  • the charge scan line N+2 and the charge scan line N+4 end the scan to maintain the low level, the charge scan line N+3 and the charge scan line N+5, and the discharge scan line N+1 and the discharge scan line.
  • N+3 is simultaneously input with a high-level scan pulse signal by the scan driver 15, and the gate of the thin film transistor electrically connected to the charge scan line N+3 and the charge scan line N+5 is turned on and passes through the first data line 13 and the second
  • the data line 14 inputs a data voltage to cause the pixel unit to display a corresponding image, and, since the gate of the thin film transistor electrically connected to the discharge scan line N+1 and the discharge scan line N+3 is turned on, the charge scan line N+1 and the charge scan
  • the data voltage of the pixel unit corresponding to the line N+3 is discharged after maintaining two times of t2 and t3.
  • the charge scan line N+3 and the charge scan line N+5 end the scan to maintain the low level, the charge scan line N+4 and the charge scan line N+6, and the discharge scan line N+2 and the discharge scan line.
  • N+4 is simultaneously input with a high-level scan pulse signal by the scan driver 15, and the gate of the thin film transistor electrically connected to the charge scan line N+4 and the charge scan line N+6 is turned on and passes through the first data line 13 and the second
  • the data line 14 inputs the data voltage to cause the pixel unit to display the corresponding image, and, since the gate of the thin film transistor electrically connected to the discharge scan line N+2 and the discharge scan line N+4 is turned on, the charge scan line N+2 and the charge scan
  • the data voltage of the pixel unit corresponding to the line N+4 is discharged after maintaining two times of t3 and t4.
  • the charge scan line N+4 and the charge scan line N+6 end the scan to maintain the low level, the charge scan line N+5 and the charge scan line N+7, and the discharge scan line N+3 and the discharge scan line.
  • N+5 is simultaneously input with a high-level scan pulse signal by the scan driver 15, and the gate of the thin film transistor electrically connected to the charge scan line N+5 and the charge scan line N+7 is turned on and passes through the first data line 13 and the second
  • the data line 14 inputs the data voltage to cause the pixel unit to display the corresponding image, and, since the gate of the thin film transistor electrically connected to the discharge scan line N+3 and the discharge scan line N+5 is turned on, the charge scan line N+3 and the charge scan
  • the data voltage of the pixel unit corresponding to the line N+5 is discharged after maintaining two times of t3 and t4.
  • the electrode structure of the first embodiment of the liquid crystal display panel of the liquid crystal display panel of FIG. 2 and the scanning signal timing thereof are described in detail above, and the subsequent scanning and charging operations are similarly performed, that is, by simultaneously scanning the two charging scan lines, thereby The total number of scans for scanning one image is reduced, and the scan pulse duration of each charge scan line is extended accordingly, and the charging time of the gate of the charge thin film transistor electrically connected to the charge scan line is ensured.
  • the liquid crystal display panel scans two adjacent charging scan lines simultaneously and simultaneously in the same time frame.
  • the adjacent charge scan lines are scanned on two adjacent discharge scan lines of different pixel unit rows (ie, rows that are not in the same pixel unit as the two adjacent charge scan lines being scanned).
  • the source of one of the pixel units via the charging thin film transistor of the pixel unit is electrically connected, and the other pixel unit is electrically connected to the second data line via the source of the charging thin film transistor of the pixel unit, and the first data line and the second data line are respectively connected to two adjacent charging scan lines.
  • the source of the charged thin film transistor of the corresponding pixel unit inputs a data signal.
  • the present invention can reduce the total number of scans of one image, correspondingly extend the scan pulse duration of each charge scan line, and ensure the charging time of the gate of the charge thin film transistor. That is, compared with the conventional liquid crystal display panel, the gate of the liquid crystal display panel 1 of the present invention has sufficient (2 times) charging time, so that a high update frequency operation can be performed, thereby improving the product experience of the liquid crystal display panel 1. effect.
  • the liquid crystal display panel 1 can also scan four adjacent charging scan lines while simultaneously scanning four adjacent discharge lines of different pixel unit rows with the four adjacent charged scan lines scanned in the same time frame. The scan line is scanned.
  • the following describes an example of the driving method when the liquid crystal display panel 1 simultaneously scans four adjacent charging scan lines.
  • the charge scan line 11 represents the charge scan line N to the charge scan line N+7
  • the discharge scan line 12 represents the discharge scan line N to the discharge scan line N+7
  • the line is electrically connected to the pixel unit of the same row, for example, the charging scanning line N and the discharging scanning line N are electrically connected to the pixel unit of the Nth row, and t1 to t3 represent the scanning time frame according to the chronological order.
  • the charge scan line N, the charge scan line N+1, the charge scan line N+2, and the charge scan line N+3 are simultaneously input with a high-level scan pulse signal by the scan driver 15.
  • the gate of the thin film transistor electrically connected to the charge scan line N, the charge scan line N+1, the charge scan line N+2, and the charge scan line N+3 is turned on and input through the first data line 13 and the second data line 14.
  • the data voltage is such that the pixel unit displays the corresponding image.
  • the discharge scan line N, the discharge scan line N+1, the discharge scan line N+2, and the discharge scan line N+3 are simultaneously turned off, and therefore, the frame ends when t1
  • the data voltages of the pixel units corresponding to the charge scan line N, the charge scan line N+1, the charge scan line N+2, and the charge scan line N+3 can continue to be maintained by the storage capacitor.
  • the charge scan line N, the charge scan line N+1, the charge scan line N+2, and the charge scan line N+3 simultaneously end the scan to maintain the low level, the charge scan line N+4, and the charge scan line N. +5, charging scan line N+6, charge scan line N+7 and discharge scan line N, discharge scan line N+1, discharge scan line N+2, discharge scan line N+3 are simultaneously input high by scan driver 15.
  • the flat scan pulse signal the gate of the thin film transistor electrically connected to the charge scan line N+4, the charge scan line N+5, the charge scan line N+6, and the charge scan line N+7 is turned on and passes through the first data line 13 And inputting a data voltage to the second data line 14 to cause the pixel unit to display a corresponding image, and a film electrically connected to the discharge scan line N, the discharge scan line N+1, the discharge scan line N+2, and the discharge scan line N+3
  • the gate of the transistor is turned on, and the data voltage of the pixel unit corresponding to the charge scan line N, the charge scan line N+1, the charge scan line N+2, and the charge scan line N+3 is discharged after maintaining the frame time of t1.
  • the charging scan line N+4, the charge scan line N+5, the charge scan line N+6, and the charge scan line N+7 simultaneously end the scan to maintain the low level, and the charge scan line N+8 (Fig. Show), charge scan line N+9 (not shown), charge scan line N+10 (not shown), charge scan line N+11 (not shown), discharge scan line N+4, discharge scan line N +5, the discharge scan line N+6 and the discharge scan line N+7 are simultaneously input to the scan pulse signal of the high level by the scan driver 15, and the charge scan line N+8 (not shown) and the charge scan line N+9 (
  • the gate of the thin film transistor electrically connected to the charging scan line N+10 (not shown) and the charging scan line N+11 (not shown) is turned on and passes through the first data line 13 and the second data line 14.
  • the data voltage is input to cause the pixel unit to display the corresponding image, and the gate of the thin film transistor electrically connected to the discharge scan line N+4, the discharge scan line N+5, the discharge scan line N+6, and the discharge scan line N+7 Turn on, the data voltage of the pixel unit corresponding to the charging scan line N+4, the charge scan line N+5, the charge scan line N+6, and the charge scan line N+7 is Holding time t2 after a discharge.
  • Subsequent scanning and charging actions are similar, that is, by scanning four charging scan lines at the same time, the total number of scans of one image is further reduced, and the duration of the scan pulse of each charging scan line is further extended, thereby ensuring The charging time of the gate of the charging thin film transistor electrically connected to the charging scan line. It can be understood that when the liquid crystal display panel 1 simultaneously scans four charging scan lines, the gate of the liquid crystal display panel 1 has sufficient (4 times) charging time, so that a higher update frequency operation can be performed, thereby further Improve the product experience of the liquid crystal display panel 1.
  • the liquid crystal display panel 1 can achieve free switching of scanning two or four charging scan lines simultaneously without changing the current driver IC specifications.
  • the liquid crystal display panel of the present invention has the advantages that the liquid crystal display panel of the present invention has the advantages that the gate can be used for a longer charging time, can adapt to a higher update rate, and can be switched between two driving modes.
  • the present invention also provides a liquid crystal display device 5 including the liquid crystal display panel 1 described above.
  • the liquid crystal display device 5 also has the advantages that the gate can be used for a long charging time, can adapt to a higher update rate, and can be switched with two driving modes.

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Abstract

一种液晶显示装置（5）及液晶显示面板（1）。该液晶显示面板（1）包括多条充电扫描线（11）、多条放电扫描线（12）、多条第一数据线（13）、多条第二数据线（14）、多列像素单元，多条充电扫描线（11）和多条放电扫描线（12）沿第一方向相互平行交替排列，第一数据线（13）和第二数据线（14）沿第二方向相互平行排列并与充电扫描线（11）和放电扫描线（12）绝缘相交，每个像素单元包括充电薄膜晶体管、放电薄膜晶体管和像素电极，其中，液晶显示面板（1）在对两条相邻的充电扫描线（11）进行扫描的同时，在同一时帧内对与被扫描的两条相邻的充电扫描线（11）位于不同像素单元行的两条相邻的放电扫描线（12）进行扫描。提供的液晶显示面板（1）具有栅极扫描的充电时间较长、能够适应较高更新率操作和具有两种显示模式可切换等优点。

Description

液晶显示面板及液晶显示装置
【技术领域】
本发明涉及一种液晶显示面板，特别是一种能够适应较高更新率操作的液晶显示面板，本发明还涉及一种采用所述液晶显示面板的液晶显示装置。
【背景技术】
由于液晶显示面板具有轻、薄、耗电小等优点，广泛应用于电视、笔记本、计算机、行动电话、个人数字助理等现代化信息设备。
在高精细度的液晶显示装置上，对扫描线进行扫描时，可以对各栅极进行充电。由于高精细度的液晶显示装置中的液晶显示面板所包括的栅极数量较多，导致各栅极可利用的充电时间变得较短。如果再进行较高更新率的操作，栅极充电时间不足的问题会更加明显，从而导致液晶显示装置的产品体验效果下降。
【发明内容】
为了克服现有技术中液晶显示面板栅极可利用的充电时间不足、不能满足较高更新率的操作等问题，本发明提供一种栅极可利用的充电时间充足、能够满足较高更新率的操作的液晶显示面板。
本发明还提供一种栅极可利用的充电时间充足、能够满足较高更新率的操作的液晶显示装置。
本发明解决技术问题所采用的技术方案是：提供一种液晶显示面板，其包括多条充电扫描线、多条放电扫描线、多条第一数据线、多条第二数据线、多列像素单元、数据驱动器以及扫描驱动器；多条充电扫描线和所述多条放电扫描线沿第一方向相互平行交替排列，一充电扫描线与一放电扫描线连接同一像素单元，第一数据线和第二数据线沿第二方向相互平行排列并与充电扫描线和放电扫描线绝缘相交；每个像素单元包括充电薄膜晶体管、放电薄膜晶体管和像素电极，充电薄膜晶体管的栅极电连接充电扫描线，充电薄膜晶体管的源极电连接第一数据线或第二数据线，充电薄膜晶体管的漏极电连接像素电极，放电薄膜晶体管的栅极电连接放电扫描线，放电薄膜晶体管的源极电连接与所述放电扫描线位于同一像素单元行的充电扫描线，放电薄膜晶体管的漏极电连接像素电极；多条第一数据线和多条第二数据线分别与数据驱动器电连接，并将数据信号传输至充电薄膜晶体管的源极；扫描驱动器包括多个第一输出端和多个第二输出端，所述多个第一输出端与所述多个第二输出端交替排列，所述第一输出端电连接两条相邻的充电扫描线，第二输出端电连接两条相邻的放电扫描线，连接同一第一输出端的两条充电扫描线通过跨线方式进行电连接，连接同一第二输出端的两条放电扫描线通过跨线方式进行电连接；其中，液晶显示面板在对两条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的两条相邻的充电扫描线位于不同像素单元行的两条相邻的放电扫描线进行扫描。
根据本发明一优选实施方式，定义一次扫描为一个扫描时帧，在液晶显示面板在对两条相邻的充电扫描线进行扫描充电的时帧为第一个扫描时帧的情况下，液晶显示面板在第三个扫描时帧对与被扫描的两条相邻的充电扫描线连接同一像素单元的放电扫描线进行扫描。
根据本发明一优选实施方式，当同时对两条相邻的充电扫描线进行扫描充电时，两条相邻的充电扫描线所对应的像素单元中，其中一个像素单元经由该像素单元的充电薄膜晶体管的源极与第一数据线电连接，另一个像素单元经由该像素单元的充电薄膜晶体管的源极与第二数据线电连接，第一数据线和第二数据线分别向两条相邻的充电扫描线所对应的像素单元的充电薄膜晶体管的源极输入数据信号。
根据本发明一优选实施方式，液晶显示面板在对四条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的四条相邻的充电扫描线位于不同像素单元行的四条相邻的放电扫描线进行扫描。
根据本发明一优选实施方式，数据驱动器对第一数据线和第二数据线施加不同时序的数据信号，以实现二维显示/三维显示切换。
本发明解决技术问题所采用的另一个技术方案是：提供一种液晶显示面板，液晶显示面板包括多条充电扫描线、多条放电扫描线、多条第一数据线、多条第二数据线、多列像素单元，多条充电扫描线和所述多条放电扫描线沿第一方向相互平行交替排列，一充电扫描线与一放电扫描线连接同一像素单元，第一数据线和第二数据线沿第二方向相互平行排列并与充电扫描线和放电扫描线绝缘相交，每个像素单元包括充电薄膜晶体管、放电薄膜晶体管和像素电极，充电薄膜晶体管的栅极电连接充电扫描线，充电薄膜晶体管的源极电连接第一数据线或第二数据线，充电薄膜晶体管的漏极电连接像素电极，放电薄膜晶体管的栅极电连接放电扫描线，放电薄膜晶体管的源极电连接与所述放电扫描线位于同一像素单元行的充电扫描线，放电薄膜晶体管的漏极电连接像素电极，其中，液晶显示面板在对两条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的两条相邻的充电扫描线位于不同像素单元行的两条相邻的放电扫描线进行扫描。
根据本发明一优选实施方式，定义一次扫描为一个扫描时帧，在液晶显示面板在对两条相邻的充电扫描线进行扫描充电的时帧为第一个扫描时帧的情况下，液晶显示面板在第三个扫描时帧对与被扫描的两条相邻的充电扫描线连接同一像素单元的放电扫描线进行扫描。
根据本发明一优选实施方式，当同时对两条相邻的充电扫描线进行扫描充电时，两条相邻的充电扫描线所对应的像素单元中，其中一个像素单元经由该像素单元的充电薄膜晶体管的源极与第一数据线电连接，另一个像素单元经由该像素单元的充电薄膜晶体管的源极与第二数据线电连接，第一数据线和第二数据线分别向两条相邻的充电扫描线所对应的像素单元的充电薄膜晶体管的源极输入数据信号。
根据本发明一优选实施方式，液晶显示面板在对四条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的四条相邻的充电扫描线位于不同像素单元行的四条相邻的放电扫描线进行扫描。
根据本发明一优选实施方式，定义一次扫描为一个扫描时帧，在液晶显示面板在对四条相邻的充电扫描线进行扫描充电的时帧为第一个扫描时帧的情况下，液晶显示面板在第二个扫描时帧对与被扫描的四条相邻的充电扫描线连接同一像素单元的放电扫描线进行扫描。
根据本发明一优选实施方式，液晶显示面板进一步包括数据驱动器，多条第一数据线和多条第二数据线分别与数据驱动器电连接，并将数据信号传输至充电薄膜晶体管的源极。
根据本发明一优选实施方式，数据驱动器对第一数据线和第二数据线施加不同时序的数据信号，以实现二维显示/三维显示切换。
根据本发明一优选实施方式，液晶显示面板进一步包括扫描驱动器，扫描驱动器包括多个第一输出端和多个第二输出端，多个第一输出端与多个第二输出端交替排列，第一输出端电连接两条相邻的充电扫描线，第二输出端电连接两条相邻的放电扫描线，连接同一第一输出端的两条充电扫描线通过跨线方式进行电连接，连接同一第二输出端的两条放电扫描线通过跨线方式进行电连接。
根据本发明一优选实施方式，充电薄膜晶体管进一步包括第一充电薄膜晶体管和第二充电薄膜晶体管，像素电极进一步包括两个具有不同指向的第一子像素电极和第二子像素电极，第一充电薄膜晶体管的漏极电连接第一子像素电极，第二充电薄膜晶体管的漏极电连接第二子像素电极，第一充电薄膜晶体管的栅极和第二充电薄膜晶体管的栅极电连接同一条充电扫描线，第一充电薄膜晶体管的源极和第二充电薄膜晶体管的源极电连接同一条第一数据线或第二数据线。
本发明实施方式采用的又一个技术方案是：提供一种液晶显示装置，液晶显示装置包括液晶显示面板。液晶显示面板包括多条充电扫描线、多条放电扫描线、多条第一数据线、多条第二数据线、多列像素单元，充电扫描线和放电扫描线沿第一方向相互同一像素单元行平行排列，第一数据线和第二数据线沿第二方向相互平行排列并与充电扫描线和放电扫描线绝缘相交，每个像素单元包括充电薄膜晶体管、放电薄膜晶体管和像素电极，充电薄膜晶体管的栅极电连接充电扫描线，充电薄膜晶体管的源极电连接第一数据线或第二数据线，充电薄膜晶体管的漏极电连接像素电极，放电薄膜晶体管的栅极电连接放电扫描线，充电薄膜晶体管的源极电连接充电扫描线，充电薄膜晶体管的漏极电连接像素电极，其中，液晶显示面板在对两条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的两条相邻的充电扫描线位于不同像素单元行的两条相邻的放电扫描线进行扫描。
根据本发明一优选实施方式，定义一次扫描为一个扫描时帧，在液晶显示面板在对两条相邻的充电扫描线进行扫描充电的时帧为第一个扫描时帧的情况下，液晶显示面板在第三个扫描时帧对与被扫描的两条相邻的充电扫描线连接同一像素单元的放电扫描线进行扫描。
根据本发明一优选实施方式，当同时对两条相邻的充电扫描线进行扫描充电时，两条相邻的充电扫描线所对应的像素单元中，其中一个像素单元经由该像素单元的充电薄膜晶体管的源极与第一数据线电连接，另一个像素单元经由该像素单元的充电薄膜晶体管的源极与第二数据线电连接，第一数据线和第二数据线分别向两条相邻的充电扫描线所对应的像素单元的充电薄膜晶体管的源极输入数据信号。
根据本发明一优选实施方式，液晶显示面板在对四条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的四条相邻的充电扫描线位于不同像素单元行的四条相邻的放电扫描线进行扫描。
根据本发明一优选实施方式，液晶显示面板进一步包括数据驱动器，多条第一数据线和多条第二数据线分别与数据驱动器电连接，并将数据信号传输至充电薄膜晶体管的源极。
根据本发明一优选实施方式，液晶显示面板进一步包括扫描驱动器，扫描驱动器包括多个第一输出端和多个第二输出端，多个第一输出端与多个第二输出端交替排列，第一输出端电连接两条相邻的充电扫描线，第二输出端电连接两条相邻的放电扫描线，连接同一第一输出端的两条充电扫描线通过跨线方式进行电连接，连接同一第二输出端的两条放电扫描线通过跨线方式进行电连接。
本发明实施方式的有益效果是：区别于现有技术的情况，本发明实施方式提供的液晶显示面板，在对两条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的两条相邻的充电扫描线位于不同像素单元行的两条相邻的放电扫描线进行扫描，相对于传统的一个扫描时间仅对一条扫描线进行扫描，本发明实施方式可以减少扫描次数，进而增加薄膜晶体管的栅极的充电时间，液晶显示面板可以进行高更新频率的操作，从而可以提升液晶显示面板及液晶显示装置的产品体验效果。
【附图说明】
图1为本发明的液晶显示面板的电极布线关系简化示意图；
图2为本发明的液晶显示面板扫描驱动的第一实施方式的电极结构及其扫描信号时序的示意图；
图3为本发明的液晶显示面板扫描驱动的第二实施方式的电极结构及其扫描信号时序的示意图；以及
图4为本发明液晶显示装置的结构示意图。
【具体实施方式】
下面对本发明的较佳实施方式进行详细阐述，以使本发明的优点和特征能更易于被本领域技术人员理解，从而对本发明的保护范围做出更为清楚明确的界定。
请参阅图1，本发明的液晶显示面板的具体实施方式如下：
图1为本发明的液晶显示面板的电极布线关系简化示意图。如图1所示，一种液晶显示面板1，包括多条充电扫描线11、多条放电扫描线12、多条第一数据线13、多条第二数据线14、多个薄膜晶体管（Thin Film Transistor，未标示）、多列像素单元（未标示）、扫描驱动器15和数据驱动器16。
其中，多条充电扫描线11和多条放电扫描线12沿第一方向相互平行交替排列，一充电扫描线11与一放电扫描线12连接同一行的像素单元（即同一像素单元行）。第一数据线13沿列方向相互平行排列并与充电扫描线11及放电扫描线12绝缘相交，第二数据线14沿列方向相互平行排列并与充电扫描线11及放电扫描线12绝缘相交，且第一数据线13与第二数据线14交替设置。
每个像素单元包括充电薄膜晶体管、放电薄膜晶体管和像素电极，充电薄膜晶体管的栅极电连接充电扫描线11，充电薄膜晶体管的源极电连接第一数据线13或第二数据线14，充电薄膜晶体管的漏极电连接像素电极，放电薄膜晶体管的栅极电连接放电扫描线12，放电薄膜晶体管的源极电连接与放电扫描线12位于同一像素单元行的充电扫描线11，放电薄膜晶体管的漏极电连接像素电极。
当液晶显示面板1的充电扫描线11输入扫描脉冲时，充电薄膜晶体管的栅极开启，第一数据线或第二数据线的数据信号经由充电薄膜晶体管的源极输入像素电极。在充电扫描线11结束扫描之后，液晶显示面板1的放电扫描线12输入扫描脉冲，放电薄膜晶体管的栅极开启，与放电扫描线12位于同一像素单元行的充电扫描线11经由放电充电薄膜晶体管的源极电连接至像素电极，由于此时与放电扫描线12位于同一像素单元行的充电扫描线11已经结束扫描而保持零电位，因此像素电极进行放电。
为提高液晶显示面板的广视角特性，充电薄膜晶体管进一步包括第一充电薄膜晶体管和第二充电薄膜晶体管，像素电极进一步包括两个具有不同指向的第一子像素电极和第二子像素电极，第一充电薄膜晶体管的漏极电连接第一子像素电极，第二充电薄膜晶体管的漏极电连接第二子像素电极，第一充电薄膜晶体管的栅极和第二充电薄膜晶体管的栅极电连接同一条充电扫描线，第一充电薄膜晶体管的源极和第二充电薄膜晶体管的源极电连接同一条第一数据线或第二数据线。通过两个不同指向的子像素电极，可以驱动液晶分子沿不同的指向排列，进而可以提高液晶显示面板的广视角性能。
液晶显示面板1进一步包括数据驱动器16和扫描驱动器15。多条第一数据线13和多条第二数据线14分别与数据驱动器16电连接，并将数据信号传输至充电薄膜晶体管的源极。数据驱动器16可以对第一数据线13和第二数据线14施加不同时序的数据信号，以实现二维显示/三维（2D/3D）显示切换。
扫描驱动器15包括多个第一输出端（未标示）和多个第二输出端（未标示），多个第一输出端与多个第二输出端交替排列，第一输出端电连接两条相邻的充电扫描线11，第二输出端电连接两条相邻的放电扫描线12。其中，连接同一第一输出端的两条充电扫描线通过跨线方式进行电连接，连接同一第二输出端的两条放电扫描线通过跨线方式进行电连接。
图2为本发明的液晶显示面板扫描驱动的第一实施方式的电极结构及其扫描信号时序的示意图。请参阅图2，充电扫描线11表示充电扫描线N至充电扫描线N+7，放电扫描线12表示放电扫描线N至示放电扫描线N+7，相同标号的充电扫描线和放电扫描线电连接同一行的像素单元，例如充电扫描线N和放电扫描线N电连接第N行的像素单元，t1至t6表示依据时间顺序的扫描时帧。
如图2所示，在t1时帧内，充电扫描线N和充电扫描线N+2同时被扫描驱动器15输入高电平的扫描脉冲信号，与充电扫描线N和充电扫描线N+2电连接的薄膜晶体管的栅极开启并通过第一数据线13和第二数据线14输入数据电压以使像素单元显示对应图像，此时，放电扫描线N和放电扫描线N+2同时处于关闭状态，因此，当t1时帧结束时，充电扫描线N和充电扫描线N+2所对应的像素单元的数据电压仍可以在储存电容的作用下继续维持。
在t2时帧内，充电扫描线N和充电扫描线N+2同时结束扫描维持低电平，充电扫描线N+1和充电扫描线N+3同时被扫描驱动器15输入高电平的扫描脉冲信号，与充电扫描线N+1和充电扫描线N+3电连接的薄膜晶体管的栅极开启并通过第一数据线13和第二数据线14输入数据电压以使像素单元显示对应图像。
在t3时帧内，充电扫描线N+1和充电扫描线N+3结束扫描维持低电平，充电扫描线N+2和充电扫描线N+4以及放电扫描线N和放电扫描线N+2同时被扫描驱动器15输入高电平的扫描脉冲信号，与充电扫描线N+2和充电扫描线N+4电连接的薄膜晶体管的栅极开启并通过第一数据线13和第二数据线14输入数据电压以使像素单元显示对应图像，并且，由于与放电扫描线N和放电扫描线N+2电连接的薄膜晶体管的栅极开启，充电扫描线N和充电扫描线N+2所对应的像素单元的数据电压在维持t1和t2两帧时间后被放电。
在t4时帧内，充电扫描线N+2和充电扫描线N+4结束扫描维持低电平，充电扫描线N+3和充电扫描线N+5以及放电扫描线N+1和放电扫描线N+3同时被扫描驱动器15输入高电平的扫描脉冲信号，与充电扫描线N+3和充电扫描线N+5电连接的薄膜晶体管的栅极开启并通过第一数据线13和第二数据线14输入数据电压以使像素单元显示对应图像，并且，由于与放电扫描线N+1和放电扫描线N+3电连接的薄膜晶体管的栅极开启，充电扫描线N+1和充电扫描线N+3所对应的像素单元的数据电压在维持t2和t3两帧时间后被放电。
在t5时帧内，充电扫描线N+3和充电扫描线N+5结束扫描维持低电平，充电扫描线N+4和充电扫描线N+6以及放电扫描线N+2和放电扫描线N+4同时被扫描驱动器15输入高电平的扫描脉冲信号，与充电扫描线N+4和充电扫描线N+6电连接的薄膜晶体管的栅极开启并通过第一数据线13和第二数据线14输入数据电压以使像素单元显示对应图像，并且，由于与放电扫描线N+2和放电扫描线N+4电连接的薄膜晶体管的栅极开启，充电扫描线N+2和充电扫描线N+4所对应的像素单元的数据电压在维持t3和t4两帧时间后被放电。
在t6时帧内，充电扫描线N+4和充电扫描线N+6结束扫描维持低电平，充电扫描线N+5和充电扫描线N+7以及放电扫描线N+3和放电扫描线N+5同时被扫描驱动器15输入高电平的扫描脉冲信号，与充电扫描线N+5和充电扫描线N+7电连接的薄膜晶体管的栅极开启并通过第一数据线13和第二数据线14输入数据电压以使像素单元显示对应图像，并且，由于与放电扫描线N+3和放电扫描线N+5电连接的薄膜晶体管的栅极开启，充电扫描线N+3和充电扫描线N+5所对应的像素单元的数据电压在维持t3和t4两帧时间后被放电。
以上详细描述了图2所示的液晶显示面板扫描驱动的第一实施方式的电极结构及其扫描信号时序，后续扫描和充电动作依此类推，即通过同时对两条充电扫描线进行扫描，从而降低了扫描一幅图像的总扫描次数，相应延长了每条充电扫描线的扫描脉冲持续时间，保证了与充电扫描线电连接的充电薄膜晶体管的栅极的充电时间。总结本发明液晶显示面板1扫描驱动的第一实施方式，可以得出以下结论，液晶显示面板在对两条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的两条相邻的充电扫描线位于不同像素单元行（即与被扫描的两条相邻的充电扫描线不在同一像素单元行）的两条相邻的放电扫描线进行扫描。
定义一次扫描为一个扫描时帧，在液晶显示面板在对两条相邻的充电扫描线进行扫描充电的时帧为第一个扫描时帧的情况下，液晶显示面板在第三个扫描时帧对与被扫描的两条相邻的充电扫描线连接同一像素单元的放电扫描线进行扫描。
进一步的，当同时对两条相邻的充电扫描线进行扫描充电时，两条相邻的充电扫描线所对应的像素单元中，其中一个像素单元经由该像素单元的充电薄膜晶体管的源极与第一数据线电连接，另一个像素单元经由该像素单元的充电薄膜晶体管的源极与第二数据线电连接，第一数据线和第二数据线分别向两条相邻的充电扫描线所对应的像素单元的充电薄膜晶体管的源极输入数据信号。
其中，由于在一个扫描时间中，对两行相邻的充电扫描线11或两行相邻的放电扫描线12同时进行扫描，相对于传统的一个扫描时间仅对一行扫描线进行扫描，本发明实施方式可以减少一幅图像的总扫描次数，相应延长了每条充电扫描线的扫描脉冲持续时间，保证了充电薄膜晶体管的栅极的充电时间。即，相较于现有的液晶显示面板，本发明液晶显示面板1的栅极有足够（2倍）的充电时间，因此可以进行高更新频率的操作，从而可以提升液晶显示面板1的产品体验效果。
此外，液晶显示面板1还可以在对四条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的四条相邻的充电扫描线位于不同像素单元行的四条相邻的放电扫描线进行扫描。
定义一次扫描为一个扫描时帧，在液晶显示面板在对四条相邻的充电扫描线进行扫描充电的时帧为第一个扫描时帧的情况下，在液晶显示面板在第二个扫描时帧对与被扫描的四条相邻的充电扫描线连接同一像素单元的放电扫描线进行扫描。
以下举例说明液晶显示面板1同时对四条相邻的充电扫描线进行扫描时的驱动方式。
图3为本发明的液晶显示面板扫描驱动的第二实施方式的电极结构及其扫描信号时序的示意图。如图3所示，充电扫描线11表示充电扫描线N至充电扫描线N+7，放电扫描线12表示放电扫描线N至示放电扫描线N+7，相同标号的充电扫描线和放电扫描线电连接同一行的像素单元，例如充电扫描线N和放电扫描线N电连接第N行的像素单元，t1至t3表示依据时间顺序的扫描时帧。
如图3所示，在t1时帧内，充电扫描线N、充电扫描线N+1、充电扫描线N+2以及充电扫描线N+3同时被扫描驱动器15输入高电平的扫描脉冲信号，与充电扫描线N、充电扫描线N+1、充电扫描线N+2以及充电扫描线N+3电连接的薄膜晶体管的栅极开启并通过第一数据线13和第二数据线14输入数据电压以使像素单元显示对应图像，此时，放电扫描线N、放电扫描线N+1、放电扫描线N+2以及放电扫描线N+3同时处于关闭状态，因此，当t1时帧结束时，充电扫描线N、充电扫描线N+1、充电扫描线N+2以及充电扫描线N+3所对应的像素单元的数据电压仍可以在储存电容的作用下继续维持。
在t2时帧内，充电扫描线N、充电扫描线N+1、充电扫描线N+2以及充电扫描线N+3同时结束扫描维持低电平，充电扫描线N+4、充电扫描线N+5、充电扫描线N+6、充电扫描线N+7以及放电扫描线N、放电扫描线N+1、放电扫描线N+2、放电扫描线N+3同时被扫描驱动器15输入高电平的扫描脉冲信号，与充电扫描线N+4、充电扫描线N+5、充电扫描线N+6以及充电扫描线N+7电连接的薄膜晶体管的栅极开启并通过第一数据线13和第二数据线14输入数据电压以使像素单元显示对应图像，并且，由于与放电扫描线N、放电扫描线N+1、放电扫描线N+2以及放电扫描线N+3电连接的薄膜晶体管的栅极开启，充电扫描线N、充电扫描线N+1、充电扫描线N+2以及充电扫描线N+3所对应的像素单元的数据电压在维持t1一帧时间后被放电。
在t3时帧内，充电扫描线N+4、充电扫描线N+5、充电扫描线N+6以及充电扫描线N+7同时结束扫描维持低电平，充电扫描线N+8（图未示）、充电扫描线N+9（图未示）、充电扫描线N+10（图未示）、充电扫描线N+11（图未示）以及放电扫描线N+4、放电扫描线N+5、放电扫描线N+6、放电扫描线N+7同时被扫描驱动器15输入高电平的扫描脉冲信号，与充电扫描线N+8（图未示）、充电扫描线N+9（图未示）、充电扫描线N+10（图未示）以及充电扫描线N+11（图未示）电连接的薄膜晶体管的栅极开启并通过第一数据线13和第二数据线14输入数据电压以使像素单元显示对应图像，并且，由于与放电扫描线N+4、放电扫描线N+5、放电扫描线N+6以及放电扫描线N+7电连接的薄膜晶体管的栅极开启，充电扫描线N+4、充电扫描线N+5、充电扫描线N+6以及充电扫描线N+7所对应的像素单元的数据电压在维持t2一帧时间后被放电。
后续扫描和充电动作依此类推，即通过同时对四条充电扫描线进行扫描，从而进一步降低了扫描一幅图像的总扫描次数，相应的进一步延长了每条充电扫描线的扫描脉冲持续时间，保证了与充电扫描线电连接的充电薄膜晶体管的栅极的充电时间。可以理解的是，当液晶显示面板1同时对四条充电扫描线进行扫描时，液晶显示面板1的栅极有足够（4倍）的充电时间，因此可以进行更高更新频率的操作，从而可以进一步提升液晶显示面板1的产品体验效果。
根据不同的需求，可以在不改动目前的驱动IC规格的情况下，液晶显示面板1可达到对两条或四条充电扫描线同时进行扫描的自由切换。
综上所述，本发明的液晶显示面板的有益效果为：本发明的液晶显示面板具有栅极可用充电时间较长、能够适应较高更新率的操作和具有两种驱动模式可切换等优点。
图4为本发明液晶显示装置的结构示意图。请参阅图4，本发明还提供一种液晶显示装置5，液晶显示装置5包括上述的液晶显示面板1。对应的，液晶显示装置5同样具有栅极可用充电时间较长、能够适应较高更新率的操作和具有两种驱动模式可切换等优点。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种液晶显示面板，其特征在于：
    包括多条充电扫描线、多条放电扫描线、多条第一数据线、多条第二数据线、多列像素单元、数据驱动器以及扫描驱动器；
    所述多条充电扫描线和所述多条放电扫描线沿第一方向相互平行交替排列，一充电扫描线与一放电扫描线连接同一像素单元行，所述第一数据线和所述第二数据线沿第二方向相互平行交替排列并与所述充电扫描线和所述放电扫描线绝缘相交；
    每个像素单元包括充电薄膜晶体管、放电薄膜晶体管和像素电极，所述充电薄膜晶体管的栅极电连接所述充电扫描线，所述充电薄膜晶体管的源极电连接所述第一数据线或所述第二数据线，所述充电薄膜晶体管的漏极电连接所述像素电极，所述放电薄膜晶体管的栅极电连接所述放电扫描线，所述放电薄膜晶体管的源极电连接与所述放电扫描线位于同一像素单元行的所述充电扫描线，所述放电薄膜晶体管的漏极电连接所述像素电极；
    所述多条第一数据线和所述多条第二数据线分别与所述数据驱动器电连接，并将数据信号传输至所述充电薄膜晶体管的源极；
    所述扫描驱动器包括多个第一输出端和多个第二输出端，所述多个第一输出端与所述多个第二输出端交替排列，所述第一输出端电连接两条相邻的充电扫描线，所述第二输出端电连接两条相邻的放电扫描线，连接同一第一输出端的两条充电扫描线通过跨线方式进行电连接，连接同一第二输出端的两条放电扫描线通过跨线方式进行电连接；
    其中，所述液晶显示面板在对两条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的所述两条相邻的充电扫描线位于不同像素单元行的两条相邻的放电扫描线进行扫描。
  2. 根据权利要求1所述的液晶显示面板，其特征在于，定义一次扫描为一个扫描时帧，在所述液晶显示面板在对两条相邻的所述充电扫描线进行扫描充电的时帧为第一个扫描时帧的情况下，所述液晶显示面板在第三个扫描时帧对与被扫描的两条相邻的所述充电扫描线连接同一像素单元的放电扫描线进行扫描。
  3. 根据权利要求1所述的液晶显示面板，其特征在于，当同时对两条相邻的所述充电扫描线进行扫描充电时，两条相邻的所述充电扫描线所对应的像素单元中，其中一个像素单元经由所述像素单元的充电薄膜晶体管的源极与所述第一数据线电连接，另一个像素单元经由所述像素单元的充电薄膜晶体管的源极与所述第二数据线电连接，所述第一数据线和所述第二数据线分别向两条相邻的所述充电扫描线所对应的像素单元的充电薄膜晶体管的源极输入数据信号。
  4. 根据权利要求1所述的液晶显示面板，其特征在于，所述液晶显示面板在对四条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的所述四条相邻的充电扫描线位于不同像素单元行的四条相邻的放电扫描线进行扫描。
  5. 根据权利要求1所述的液晶显示面板，其特征在于，所述数据驱动器对所述第一数据线和所述第二数据线施加不同时序的数据信号，以实现二维显示/三维显示切换。
  6. 一种液晶显示面板，其特征在于：包括多条充电扫描线、多条放电扫描线、多条第一数据线、多条第二数据线、多列像素单元，所述多条充电扫描线和所述多条放电扫描线沿第一方向相互平行交替排列，一充电扫描线与一放电扫描线连接同一像素单元行，所述第一数据线和所述第二数据线沿第二方向相互平行交替排列并与所述充电扫描线和所述放电扫描线绝缘相交，每个像素单元包括充电薄膜晶体管、放电薄膜晶体管和像素电极，所述充电薄膜晶体管的栅极电连接所述充电扫描线，所述充电薄膜晶体管的源极电连接所述第一数据线或所述第二数据线，所述充电薄膜晶体管的漏极电连接所述像素电极，所述放电薄膜晶体管的栅极电连接所述放电扫描线，所述放电薄膜晶体管的源极电连接与所述放电扫描线位于同一像素单元行的所述充电扫描线，所述放电薄膜晶体管的漏极电连接所述像素电极，其中，所述液晶显示面板在对两条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的所述两条相邻的充电扫描线位于不同像素单元行的两条相邻的放电扫描线进行扫描。
  7. 根据权利要求6所述的液晶显示面板，其特征在于，定义一次扫描为一个扫描时帧，在所述液晶显示面板在对两条相邻的所述充电扫描线进行扫描充电的时帧为第一个扫描时帧的情况下，所述液晶显示面板在第三个扫描时帧对与被扫描的两条相邻的所述充电扫描线连接同一像素单元的放电扫描线进行扫描。
  8. 根据权利要求6所述的液晶显示面板，其特征在于，当同时对两条相邻的所述充电扫描线进行扫描充电时，两条相邻的所述充电扫描线所对应的像素单元中，其中一个像素单元经由所述像素单元的充电薄膜晶体管的源极与所述第一数据线电连接，另一个像素单元经由所述像素单元的充电薄膜晶体管的源极与所述第二数据线电连接，所述第一数据线和所述第二数据线分别向两条相邻的所述充电扫描线所对应的像素单元的充电薄膜晶体管的源极输入数据信号。
  9. 根据权利要求6所述的液晶显示面板，其特征在于，所述液晶显示面板在对四条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的所述四条相邻的充电扫描线位于不同像素单元行的四条相邻的放电扫描线进行扫描。
  10. 根据权利要求9所述的液晶显示面板，其特征在于，定义一次扫描为一个扫描时帧，在所述液晶显示面板在对四条相邻的所述充电扫描线进行扫描充电的时帧为第一个扫描时帧的情况下，所述液晶显示面板在第二个扫描时帧对与被扫描的四条相邻的所述充电扫描线连接同一像素单元的放电扫描线进行扫描。
  11. 根据权利要求6所述的液晶显示面板，其特征在于，所述液晶显示面板进一步包括数据驱动器，所述多条第一数据线和所述多条第二数据线分别与所述数据驱动器电连接，并将数据信号传输至所述充电薄膜晶体管的源极。
  12. 根据权利要求11所述的液晶显示面板，其特征在于，所述数据驱动器对所述第一数据线和所述第二数据线施加不同时序的数据信号，以实现二维显示/三维显示切换。
  13. 根据权利要求6所述的液晶显示面板，其特征在于，所述液晶显示面板进一步包括扫描驱动器，所述扫描驱动器包括多个第一输出端和多个第二输出端，所述多个第一输出端与所述多个第二输出端交替排列，所述第一输出端电连接两条相邻的充电扫描线，所述第二输出端电连接两条相邻的放电扫描线，连接同一第一输出端的两条充电扫描线通过跨线方式进行电连接，连接同一第二输出端的两条放电扫描线通过跨线方式进行电连接。
  14. 根据权利要求6所述的液晶显示面板，其特征在于，所述充电薄膜晶体管进一步包括第一充电薄膜晶体管和第二充电薄膜晶体管，所述像素电极进一步包括两个具有不同指向的第一子像素电极和第二子像素电极，所述第一充电薄膜晶体管的漏极电连接第一子像素电极，所述第二充电薄膜晶体管的漏极电连接第二子像素电极，所述第一充电薄膜晶体管的栅极和所述第二充电薄膜晶体管的栅极电连接同一条所述充电扫描线，所述第一充电薄膜晶体管的源极和所述第二充电薄膜晶体管的源极电连接同一条所述第一数据线或所述第二数据线。
  15. 一种液晶显示装置，其特征在于，包括液晶显示面板，所述液晶显示面板包括多条充电扫描线、多条放电扫描线、多条第一数据线、多条第二数据线、多列像素单元，所述多条充电扫描线和所述多条放电扫描线沿第一方向相互平行交替排列，一充电扫描线与一放电扫描线连接同一像素单元行，所述第一数据线和所述第二数据线沿第二方向相互平行交替排列并与所述充电扫描线和所述放电扫描线绝缘相交，每个像素单元包括充电薄膜晶体管、放电薄膜晶体管和像素电极，所述充电薄膜晶体管的栅极电连接所述充电扫描线，所述充电薄膜晶体管的源极电连接所述第一数据线或所述第二数据线，所述充电薄膜晶体管的漏极电连接所述像素电极，所述放电薄膜晶体管的栅极电连接所述放电扫描线，所述放电薄膜晶体管的源极电连接与所述放电扫描线位于同一像素单元行的所述充电扫描线，所述放电薄膜晶体管的漏极电连接所述像素电极，其中，所述液晶显示面板在对两条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的所述两条相邻的充电扫描线位于不同像素单元行的两条相邻的放电扫描线进行扫描。
  16. 根据权利要求15所述的液晶显示装置，其特征在于，定义一次扫描为一个扫描时帧，在所述液晶显示面板在对两条相邻的所述充电扫描线进行扫描充电的时帧为第一个扫描时帧的情况下，所述液晶显示面板在第三个扫描时帧对与被扫描的两条相邻的所述充电扫描线连接同一像素单元的放电扫描线进行扫描。
  17. 根据权利要求15所述的液晶显示装置，其特征在于，当同时对两条相邻的所述充电扫描线进行扫描充电时，两条相邻的所述充电扫描线所对应的像素单元中，其中一个像素单元经由所述像素单元的充电薄膜晶体管的源极与所述第一数据线电连接，另一个像素单元经由所述像素单元的充电薄膜晶体管的源极与所述第二数据线电连接，所述第一数据线和所述第二数据线分别向两条相邻的所述充电扫描线所对应的像素单元的充电薄膜晶体管的源极输入数据信号。
  18. 根据权利要求15所述的液晶显示装置，其特征在于，所述液晶显示面板在对四条相邻的充电扫描线进行扫描的同时，在同一时帧内对与被扫描的所述四条相邻的充电扫描线位于不同像素单元行的四条相邻的放电扫描线进行扫描。
  19. 根据权利要求15所述的液晶显示装置，其特征在于，所述液晶显示面板进一步包括数据驱动器，所述多条第一数据线和所述多条第二数据线分别与所述数据驱动器电连接，并将数据信号传输至所述充电薄膜晶体管的源极。
  20. 根据权利要求15所述的液晶显示装置，其特征在于，所述液晶显示面板进一步包括扫描驱动器，所述扫描驱动器包括多个第一输出端和多个第二输出端，所述多个第一输出端与所述多个第二输出端交替排列，所述第一输出端电连接两条相邻的充电扫描线，所述第二输出端电连接两条相邻的放电扫描线，连接同一第一输出端的两条充电扫描线通过跨线方式进行电连接，连接同一第二输出端的两条放电扫描线通过跨线方式进行电连接。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102789769B (zh) * 2012-07-05 2014-07-30 青岛海信电器股份有限公司 3d液晶显示驱动方法及3d液晶显示系统
CN102955313B (zh) * 2012-11-19 2015-12-02 京东方科技集团股份有限公司 阵列基板、显示装置、电子器件
CN104155820B (zh) * 2014-08-13 2017-09-22 深圳市华星光电技术有限公司 一种阵列基板及驱动方法
CN204758983U (zh) * 2015-05-26 2015-11-11 京东方科技集团股份有限公司 一种阵列基板、液晶面板及液晶显示装置
US10754216B2 (en) 2015-05-26 2020-08-25 Boe Technology Group Co., Ltd. Array substrate and driving method thereof, liquid crystal display panel, and liquid crystal display device
CN105629614A (zh) 2016-03-29 2016-06-01 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板和显示装置
CN105761703B (zh) * 2016-05-20 2018-05-25 京东方科技集团股份有限公司 阵列基板、显示装置以及充电控制方法
CN106920525B (zh) * 2017-04-17 2020-01-31 深圳市华星光电半导体显示技术有限公司 三栅极驱动架构液晶显示器的驱动方法
CN114420025A (zh) * 2020-10-28 2022-04-29 北京京东方显示技术有限公司 显示面板的驱动方法、驱动装置及显示装置
CN113488487A (zh) * 2021-06-30 2021-10-08 昆山龙腾光电股份有限公司 一种薄膜晶体管阵列基板及显示装置
TWI802138B (zh) * 2021-12-09 2023-05-11 奕力科技股份有限公司 顯示驅動電路及其顯示驅動方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080068524A1 (en) * 2006-09-18 2008-03-20 Samsung Electronics Co., Ltd. Liquid crystal display and method of driving the same
CN101512628A (zh) * 2006-11-02 2009-08-19 夏普株式会社 有源矩阵基板及具备该有源矩阵基板的显示装置
CN101520578A (zh) * 2008-02-25 2009-09-02 奇美电子股份有限公司 液晶显示装置及其影像显示方法
CN101903938A (zh) * 2007-12-27 2010-12-01 夏普株式会社 液晶显示装置、液晶显示装置的驱动方法、以及电视接收机
WO2010137230A1 (ja) * 2009-05-25 2010-12-02 シャープ株式会社 アクティブマトリクス基板、液晶パネル、液晶表示装置、テレビジョン受像機
WO2011045978A1 (ja) * 2009-10-16 2011-04-21 シャープ株式会社 液晶表示装置
CN102034448A (zh) * 2009-10-02 2011-04-27 索尼公司 图像显示装置和驱动图像显示装置的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1877406A (zh) * 2006-07-04 2006-12-13 友达光电股份有限公司 场序式液晶显示装置及其驱动方法
KR20080046873A (ko) * 2006-11-23 2008-05-28 삼성전자주식회사 표시패널
KR101480002B1 (ko) * 2008-02-20 2015-01-08 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080068524A1 (en) * 2006-09-18 2008-03-20 Samsung Electronics Co., Ltd. Liquid crystal display and method of driving the same
CN101512628A (zh) * 2006-11-02 2009-08-19 夏普株式会社 有源矩阵基板及具备该有源矩阵基板的显示装置
CN101903938A (zh) * 2007-12-27 2010-12-01 夏普株式会社 液晶显示装置、液晶显示装置的驱动方法、以及电视接收机
CN101520578A (zh) * 2008-02-25 2009-09-02 奇美电子股份有限公司 液晶显示装置及其影像显示方法
WO2010137230A1 (ja) * 2009-05-25 2010-12-02 シャープ株式会社 アクティブマトリクス基板、液晶パネル、液晶表示装置、テレビジョン受像機
CN102034448A (zh) * 2009-10-02 2011-04-27 索尼公司 图像显示装置和驱动图像显示装置的方法
WO2011045978A1 (ja) * 2009-10-16 2011-04-21 シャープ株式会社 液晶表示装置

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