WO2013060034A1 - 用于相变存储器的硅掺杂的铋碲基存储材料及制备方法 - Google Patents

用于相变存储器的硅掺杂的铋碲基存储材料及制备方法 Download PDF

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WO2013060034A1
WO2013060034A1 PCT/CN2011/081680 CN2011081680W WO2013060034A1 WO 2013060034 A1 WO2013060034 A1 WO 2013060034A1 CN 2011081680 W CN2011081680 W CN 2011081680W WO 2013060034 A1 WO2013060034 A1 WO 2013060034A1
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phase
silicon
phase change
changing
tellurium
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程晓敏
缪向水
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华中科技大学
鞠晨
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    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C12/00—Alloys based on antimony or bismuth
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C1/00—Making non-ferrous alloys
    • C22C1/10—Alloys containing non-metals
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C28/00—Alloys based on a metal not provided for in groups C22C5/00 - C22C27/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Switching materials based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors

Definitions

  • Silicon-doped germanium-based memory material for phase change memory and preparation method thereof Silicon-doped germanium-based memory material for phase change memory and preparation method thereof
  • the invention belongs to the field of microelectronics, and particularly relates to a phase change memory material which can be used for a phase change memory and a preparation method thereof.
  • phase change memory has high-speed read, high erasability, radiation resistance, non-volatility, small component size, multi-level memory, and compatibility with CMOS processes.
  • the good advantage which is considered by the International Semiconductor Industry Association to be the most likely to replace the current flash memory, is one of the mainstream memory products of the future, and the first generation of memory devices that may be commercially available.
  • phase change memory technology is based on Ovshinsky's proposed in the late 1960s (Phys. Rev. Lett., 21, 1450 ⁇ 1453, 1968) and early 1970s (Appl. Phys. Lett., 18, 254-257, 1971).
  • the phase change film material can be applied to the concept of phase change memory media.
  • the basic principle of the phase change memory is to use the phase change film material as the storage medium, and the programmed electrical pulse is used to reversibly convert the phase change film between different structural phases to store data.
  • the state of the memory cell is non-volatile, that is, when it is set to a state, even if the power is turned off, the memory cell maintains the set resistance value unless reset.
  • the memory cells are defined by small holes defined by the dielectric material and filled with phase change material. Electrode contact causes current to flow through the channel to generate Joule heat. The cell is programmed or the resistance state of the cell is read.
  • the phase change memory formed by the integration of the control circuit formed by the CMOS process and the phase change memory cell is the recordable phase change film functional material.
  • phase change materials currently used for phase change memories are mainly sulfur-based compounds, such as GeSbTe, AgInSbTe, GeTeAsSi, GeBiTe, InTe, AsSbTe, GeSbTeN, GeSbTeSn, AgInSbTe, GeSbTeO, AsTeAg, and AuSbTe.
  • higher storage density and faster data transfer requirements place more demands on phase change materials.
  • the materials used must have the ability to rapidly crystallize and recrystallize to ensure maximum data transfer rates.
  • the erase process (crystallization) current pulse is high.
  • phase change memory storage material with a faster phase change speed and overcome the above disadvantages.
  • the invention of the publication No. CN102185106A discloses a SiBiTe-based thin film material for a phase change memory which has a large amount of Si present in an amorphous form around the BiTe material, and the Si atoms are not incorporated into the BiTe material. It only acts as an isolation. Only phase changes of BiTe grains occur during the phase transition. The defects are: Due to the high resistance of amorphous Si, the material remains in a high crystalline and amorphous state. The resistance (crystalline above 10 4 ohms, amorphous 10 6 ohms or more) results in a large write current and erase current.
  • the object of the present invention is to provide a storage material for a phase change memory, which has a fast phase change speed, a low current pulse in an erase process, and good compatibility with a semiconductor fabrication process, in view of the deficiencies of the existing phase change materials.
  • the present invention provides a germanium-based memory material for a phase-change random access memory, the compositional expression of which is Bi x Te y Si -( ⁇ + ⁇ ) , where x, y satisfy: 0 ⁇ x ⁇ 40, 0 ⁇ y ⁇ 60, 90 x+y ⁇ 100.
  • the ruthenium-based memory material is a memory material in which a resistance can be reversibly converted between high resistance and low resistance under the action of external energy, and the magnitude of the resistance change is more than one order of magnitude.
  • a method of preparing the silicon-doped germanium-based memory material is specifically -
  • the sputtering power is 0 to 60 W
  • the sputtering Ar gas pressure is 0.78 to 0.82 Pa.
  • the sputtering power was 50 W
  • the sputtering Ar gas pressure was 0.8 Pa.
  • the present invention Compared with the existing phase change memory material, the BiTe-based phase change memory material provided by the invention has a faster crystallization rate, and the crystal resistance of the BiTe group is small. Effectively reduces the current pulse during the erase process. Considering that the crystallization temperature of BiTe-based phase change material is relatively low, it will affect its room temperature stability and its application in phase change memory. Therefore, the present invention performs Si doping on a BiTe-based phase change material, and utilizes the BiTe material itself to make defects. The doped element Si replaces the position of Te in the BiTe-based material and bonds with Bi to form a uniform film of the formula BixTeySi ⁇ y).
  • the silicon-doped bismuth telluride present invention yl crystalline phase change memory material resistance (about 102 ohms) to the amorphous state resistance (about 104 ohms) are small, effectively reducing the write current and the erase current.
  • the phase change memory material BiJbySiKx ⁇ y) film has obvious switching characteristics, and the threshold current increases as the Si doping content increases.
  • FIG 1 is a schematic view showing the structure of a phase change memory cell based on a silicon-doped germanium-based memory material.
  • Figure 3 is based on a silicon doped germanium based memory material Bi4.
  • T e5 RI characteristic graph of a phase change memory cell of Si 1 () .
  • Figure 4 shows the deposited state of the silicon-doped germanium-based memory material and the X-ray diffraction pattern after annealing.
  • Fig. 5 XPS line diagram of 2p electrons of Si atoms in a silicon-doped germanium-based memory material.
  • Fig. 6 XPS line diagram of Bi atom 4f electrons in a silicon-doped germanium-based memory material.
  • Figure 7 is a schematic view showing the structure of a "T" shaped phase change memory cell which can be used in the present invention.
  • Fig. 8 is a schematic view showing the structure of a "gong" shaped phase change memory unit which can be used in the present invention.
  • Figure 9 is a schematic view showing the structure of a linear phase change memory cell to which the present invention can be applied.
  • a phase change memory material is a Si-doped BiTe-based material having a chemical composition formula of Bi x TeySi 1 (XHx+ y), wherein x and y satisfy: 0 ⁇ x 40, 0 ⁇ y ⁇ 60, 90 x+y ⁇ 100.
  • the Si-doped BiTe-based material provided by the invention can easily form an amorphous state, and when the electric pulse signal is applied, the resistance of the storage material of the present invention undergoes a reversible conversion characteristic between high resistance and low resistance.
  • the magnitude of the change is more than an order of magnitude.
  • a method of preparing the silicon-doped germanium-based memory material is specifically -
  • the sputtering power is 0 to 60 W (preferably 50 W), and the sputtering Ar gas pressure is 0.78 to 0.82 Pa (preferably 0.8 Pa).
  • the method for preparing the Si-doped BiTe-based memory material according to the present invention may be any one of a sputtering method, a chemical vapor deposition method, an evaporation method, an atomic layer deposition method, a metal organic material thermal decomposition method or a laser-assisted deposition method. Preparation method.
  • a Si-doped Bi 2 Te 3 film was prepared by a magnetron sputtering method.
  • a Bi 2 Te 3 target with a diameter of 100 mm and a thickness of 5 mm was prepared.
  • the purity of the target was 99.999% (atomic percent), and the Si piece having a size of 2*10 mm was uniformly attached to the Bi 2 Te 3 alloy target.
  • the sputtering gas pressure is adjusted to change the atomic ratio of Bi to Te, and the amount of doping is changed by changing the number of Si pieces.
  • Ar gas having a purity of 99.999% was introduced during sputtering.
  • the specific process parameters are as follows: 81 2 3
  • the target uses RF power supply, the power is 50W; the sputtering pressure is 0.8Pa ; pre-sputtering for 1 hour before each sputtering to ensure that the Si0 2 on the surface of the Si wafer is removed.
  • Bi x Te y Si ⁇ S variable memory films with different Si contents can be obtained each time the number of Si sheets attached to the Bi 2 Te 3 target is changed.
  • the thickness of the film was analyzed by a step meter, and the atomic percentage of each element in the film was obtained by analysis with a spectrometer attached to a scanning electron microscope.
  • the Bi 2 Te 3 target RF power is 50W, when the Si film is not added, the film composition is Bi 2 Te 3 ; Bi 2 Te 3 target RF power is 50W, and the Si piece number is 6 pieces, the film The composition is Bi 40 Te 57 Si 3 ; the Bi 2 Te 3 target has a radio frequency power of 50 W and the number of Si sheets is 10, and the film composition is Bi 4 . Te 54 Si 6 ; Bi 2 Te 3 target RF power is 50W, when the number of Si sheets is 14 pieces, the film composition is Bi 4 oTe5oSiio;
  • a simple three-layer structure as shown in Figure 1 in which 1 is the upper electrode and 2 is the phase change functional material. 3 is the lower electrode and 4 is the substrate.
  • the middle storage material is made of BixTeySiuxH ⁇ y) film material with different compositions. The dimensions of each film layer are as follows: The substrate is a Si wafer covered with a layer of SiO 2 film; the lower electrode is TiW, and the film thickness is 150 nm ; and the phase is a phase change functional material with Bi 4 .
  • Te 54 Si 6 has a thickness of 60 nm ; the upper electrode is TiW, and the film thickness is 120 nm ; and the planar size of the three-layer structure is 60 ⁇ m *80 ⁇ m.
  • the current-voltage (IV) test is performed on the three-layer structural unit of the above configuration by using the probe station, and the two probes are respectively contacted at the upper and lower electrodes, and a DC current pulse signal with a gradually increasing amplitude is applied, and the corresponding measurement of the storage unit is performed.
  • the voltage obtained, as shown in Fig. 2 shows the threshold current and threshold voltage and resistance change characteristics of the phase change memory memory cell of the material.
  • the apparent switching characteristics of the BixTeySi ⁇ y) film can be seen from the figure.
  • the threshold current of the phase change memory material increases significantly as the Si doping content increases, reflecting the stability of the amorphous state, that is, the improvement of the data retention. Therefore, in practical applications, the threshold current and the crystallization temperature can be changed by adjusting the Si content.
  • Figure 3 shows Bi 4 .
  • Te 54 Si 6 is taken as an example to illustrate the two-state resistance change of the silicon-doped germanium-based memory material of the present invention.
  • the resistance value is reduced from 6865.9 ohms in the initial amorphous state to 188.4 ohms in the crystalline state, and the variation range is greater than one order of magnitude. .
  • the Bi 40 Te5oSi 10 which is one of the silicon-doped germanium-based memory materials described in the first embodiment is subjected to X-ray diffraction test after deposition and annealing, and the test results are shown in FIG. 4 .
  • a is a deposited state
  • b is a polycrystalline state after annealing at 300 ° C for 3 min. It can be seen from the XRD pattern that the Si-doped BiTe-based phase change memory material exhibits a single trigonal structure in the crystalline state.
  • the silicon-doped germanium-based memory material described in the first embodiment is subjected to XPS testing, and the test results are shown in FIGS. 5 and 6.
  • Figure 5 is a Si atom 2p in a silicon-doped germanium-based memory material.
  • the XPS line of the electron excludes the possibility of the Si-0 bond (103. leV) and the Si-Si bond (98.6ev) by its energy value (101.75 eV);
  • Figure 6 shows the silicon-doped germanium-based memory material.
  • the XPS line of the 4f electron in the Bi atom has two new peaks (162.6eV and 157.3eV) at lower energy than the Bi atom in the undoped germanium-based storage material.
  • the energy value of the peak position excludes the possibility of Bi-0 (164.5eV and 159.1eV) bonds or Bi-Bi (162eV and 156.65eV) bonds, indicating that Si bonds with Bi atoms.
  • the silicon-doped germanium-based material provided by the invention effectively improves the amorphous state of the BiTe-based material, has a uniform structure, a single crystal phase, and stable device performance. At the same time, the silicon-doped germanium-based material provided by the invention has a small resistance value, which effectively reduces the write current and the erase current pulse.
  • the invention is effective in addition to the "T"-shaped phase change memory cell structure, and is equally effective for the "work"-shaped structure, the linear structure, the asymmetric structure, and the edge contact type structure.
  • 7 and 8 are schematic views showing the structure of a "T"-shaped and "work”-shaped phase change memory cell which can be used in the present invention, wherein 1 is an upper electrode and 2 is a phase change functional material. 3 is the lower electrode, 4 is the substrate, and 5 is the isolation layer.
  • Figure 9 is a schematic view showing the structure of a linear phase change memory cell in which the present invention can be applied. In Fig. 9, 1 is a left electrode, and 2 is a phase change functional material. 3 is the right electrode, 4 is the substrate, and 5 is the isolation layer.

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Abstract

本发明提供了一种用于相变存储器的硅掺杂的铋碲基材料及其制备方法，本发明硅掺杂的铋碲基材料的化学通式为BixTeySi100-(x+y)，其中x、y满足：0<x≤40，0<y≤60，90≤x+y<100。所发明的硅掺杂的铋碲基材料，在施加电脉冲信号的情况下，发生了高阻态与低阻态之间的可逆转换特性，可以用于相变存储器。与传统的用于相变存储器的GeTe、SiSbTe、GeSbTe等相变薄膜材料相比，本发明硅掺杂的铋碲基材料组分简单、相变速度更快、相变所需能量更低，且与互补金属氧化物半导体（CMOS）器件制造工艺兼容性非常好，是一种优异的相变存储器的新存储材料。

Description

用于相变存储器的硅掺杂的铋碲基存储材料及制备方法 技术领域
本发明属于微电子领域， 具体涉及一种可用于相变存储器的相变存储 材料及其制备方法。
背景技术
更高的密度、 更低的功耗， 更低的成本和更快的速度是存储器设计和 制造者追求的永恒目标。 在现有的存储技术中， 相变存储器 （PCRAM) 由 于具有高速读取、 高可擦写次数、 抗辐射、 非易失性、 元件尺寸小、 可实 现多级存储、 以及与 CMOS工艺兼容性好的优点， 被国际半导体工业协会 认为最有可能取代目前的闪存存储器而成为未来存储器主流产品之一， 也 是最先可能商用化的下一代存储器件。
相变存储器技术是基于 Ovshinsky在 20世纪 60年代末 (Phys. Rev. Lett.， 21， 1450~1453，1968)和 70年代初 (Appl. Phys. Lett., 18， 254-257, 1971 ) 提出的相变薄膜材料可以应用于相变存储器介质的构想建立起来的。 相变 存储器的基本原理是利用相变薄膜材料为存储介质， 采用编程的电脉冲使 相变薄膜在不同的结构相之间进行可逆的转换来存储数据。 而且该存储单 元的状态是非易失的， 即当其被设置为一个状态时， 即使切断电源， 该存 储单元仍保持设置后的电阻值， 除非重新设置。 存储单元由电介质材料所 限定的小孔并被相变材料所填充。 电极接触使电流通过该通道产生焦耳热 对该单元进行编程， 或者读取该单元的电阻状态。 由 CMOS工艺形成的控 制电路与相变存储单元集成以后形成的相变存储器， 其关键为可记录的相 变薄膜功能材料。
目前用于相变存储器的相变材料主要为硫系化合物， 有 GeSbTe、 AgInSbTe、 GeTeAsSi、 GeBiTe、 InTe、 AsSbTe、 GeSbTeN、 GeSbTeSn、 AgInSbTe、 GeSbTeO、 AsTeAg、 和 AuSbTe等等。 但是更高的存储密度和 更快的数据传输率的要求对相变材料提出了更多的要求。 为保持与其他存 储技术的竞争力， 所使用的材料必须具有快速结晶和再结晶的能力以保证 最大的数据传输速率。 为了得到更高的存储密度， 还有一些问题必须解决， 例如擦除过程 (晶化)电流脉冲高。 同时某些相变材料的组元比较复杂， 而某 些相变材料与半导体制备工艺兼容性也不好， 制作成本大， 不适合大批量 生产。 寻找相变速度更快的相变存储器存储材料， 克服如上这些缺点， 正 是本发明的出发点。
目前最常用的主要是 Ge2Sb2Te5 和 Sb2Te3。 如申请公布号为 CN102185106A的发明文献揭示了一种用于相变存储器的 SiBiTe系薄膜材 料，该材料将大量的 Si以非晶的形态存在于 BiTe材料周围， Si原子并未掺 入 BiTe材料中，只起到隔离的作用，在相变过程中只有 BiTe晶粒发生相变， 这样的缺陷在于： 由于非晶 Si电阻很高， 导致了材料在晶态与非晶态都保 持在一个很高的电阻 （晶态 104欧姆以上， 非晶态 106欧姆以上）， 导致了 很大的写电流与擦除电流。
发明内容
本发明的目的在于针对目前现有相变材料的存在的不足， 提供一种用 于相变存储器的存储材料， 具有相变速度快、 擦除过程电流脉冲低以及与 半导体制备工艺兼容性好的特点。
本发明提供一种用于相变随机存储器的铋碲基存储材料， 其组分表达 式为 BixTeySi謂 -(χ+γ)， 其中 x、 y满足： 0<x^40, 0<y^60, 90 x+y<100。
进一步地， 所述铋碲基存储材料为电阻会在外部能量的作用下发生高 阻和低阻之间的可逆转换的存储材料， 电阻变化幅度在一个数量级以上。
制备所述的硅掺杂的铋碲基存储材料的方法， 具体为-
1 ) 制备 BixTey合金靶；
2) 对 BixTey合金靶上贴置 Si片；
3 ) 以 Ar作为溅射气体对贴置 Si片后的合金靶进行溅射， 制备得到硅 掺杂的铋碲基存储存储材料。
进一步地， 溅射功率为 0~60W， 溅射 Ar气压为 0.78~0.82Pa。
进一步地， 溅射功率为 50W， 溅射 Ar气压为 0.8Pa。
本发明的技术效果体现在： 与现有的相变存储材料相比， 本发明提供 的 BiTe基相变存储材料具有更快的晶化速度， 同时 BiTe基的晶态电阻小， 有效降低了擦除过程电流脉冲。 考虑到 BiTe基相变材料晶化温度比较低， 将影响其室温稳定性及其在相变存储器中的应用， 因此本发明对 BiTe基相 变材料进行 Si掺杂，利用 BiTe材料自身缺陷，使掺杂的元素 Si取代了 BiTe 基材料中的 Te的位置， 与 Bi成键， 形成均一的化学式为 BixTeySi^^y)的 薄膜。 由于 Si的高配位数 （4) 以及相对较高的键能， 提高了 BiTe基材料 非晶态的稳定性。 本发明所述的硅掺杂铋碲基相变存储材料晶态电阻 （102 欧姆左右） 与非晶态电阻 （104欧姆左右） 都较小， 有效降低了写电流与擦 除电流。 所述相变存储材料 BiJbySiKx^y)薄膜有明显的开关特性， 阈值电 流随着 Si掺杂含量的提高而增大。
附图说明
图 1基于硅掺杂的铋碲基存储材料的相变存储单元的结构示意图。 图 2基于硅掺杂的铋碲基存储材料 Bi4。Te54Si6的相变存储器单元的 I-V 特性曲线图。
图 3基于硅掺杂的铋碲基存储材料 Bi4。Te5。Si1()的相变存储器单元的 R-I 特性曲线图。
图 4硅掺杂的铋碲基存储材料沉积态与退火后的进行 X射线衍射图谱。 图 5硅掺杂的铋碲基存储材料中 Si原子 2p电子的 XPS谱线图。
图 6硅掺杂的铋碲基存储材料中 Bi原子 4f电子的 XPS谱线图。
图 7本发明可用于的 "T"字形相变存储器单元结构示意图。
图 8本发明可用于的 "工"字形相变存储器单元结构示意图。
图 9本发明可用于的线型相变存储器单元结构示意图。
具体实施方式
下面通过具体实施例的阐述， 以进一步说明本发明实质性特点和显著 的进步， 但本发明绝非仅局限于实施例。
本实施例所述的一种相变存储材料为 Si掺杂的 BiTe基材料，其化学组 成式为 BixTeySi1(XHx+y)，其中 x、 y满足： 0<x 40， 0<y^60, 90 x+y<100。
本发明提供的 Si掺杂的 BiTe基材料很容易形成非晶态，在施加电脉冲 信号时， 本发明存储材料的电阻会发生高阻和低阻之间的可逆转换特性， 变化幅度在一个数量级以上， 这两个不同的电阻状态可以分别用于代表存 储的 "0"态和 " 1 "态， 因此利用这种阻值的可逆变化现象， 可以构造电 可擦写的非易失性存储器。
制备所述的硅掺杂的铋碲基存储材料的方法， 具体为-
1 ) 制备 BixTey合金靶；
2) 对 BixTey合金靶上贴置 Si片；
3 ) 以 Ar作为溅射气体对贴置 Si片后的合金靶进行溅射， 制备得到硅 掺杂的铋碲基存储存储材料。
溅射功率为 0~60W (优选 50W)， 溅射 Ar气压为 0.78~0.82Pa (优选 0.8Pa)。
实施例一
本发明所述的 Si掺杂的 BiTe基存储材料的制备方法可采用溅射法、化 学气相沉积法、 蒸发法、 原子层沉积法、 金属有机物热分解法或激光辅助 沉积法等方法中任意一种制备方法。
本文实施例选用磁控溅射方法制备 Si 掺杂 Bi2Te3薄膜。首先制备好直 径为 100mm、 厚度为 5mm的 Bi2Te3靶材， 靶的纯度为 99.999% (原子百分 比），大小为 2*10mm的 Si片均匀地贴在 Bi2Te3合金靶上，通过调节溅射气 压来改变 Bi与 Te的原子比， 通过改变 Si片的数量来改变掺杂量多少。 然 后用磁控溅射的方法， 溅射时通入纯度为 99.999%的 Ar气。
具体的工艺参数如下： 812 3靶采用射频功率电源， 功率为 50W; 溅 射气压为 0.8Pa; 每次溅射前预溅射 1小时以保证 Si片表面的 Si02被去除 干净。 每次改变贴在 Bi2Te3靶上的 Si 片数量就可以得到不同 Si 含量的 BixTeySi^S变存储薄膜。通过台阶仪分析得到薄膜的厚度，用扫描电子显微 镜附带的能谱仪分析， 可以得到薄膜中各个元素所占的原子百分比。 运用 如上的分析测试得到 Bi2Te3靶射频功率为 50W， 不加 Si片时， 薄膜组分为 Bi2Te3； Bi2Te3靶射频功率为 50W、 Si 片数量为 6 片时， 薄膜组分为 Bi40Te57Si3 ; Bi2Te3靶射频功率为 50W、 Si片数量为 10片时， 薄膜组分为 Bi4。Te54Si6 ; Bi2Te3靶射频功率为 50W、 Si片数量为 14片时， 薄膜组分为 Bi4oTe5oSiio;
实施例二
为了方便地测试 BiTe基存储材料的电学性能， 采用如图 1所示的简单 的三层结构， 图中 1为上电极， 2为相变功能材料
Figure imgf000007_0001
3为下电 极， 4为衬底。 其中的中间的存储材料采用不同成分的 BixTeySiuxH^y)薄膜 材料。 各膜层的尺寸如下： 衬底为覆盖一层 Si02薄膜的 Si片； 下电极为 TiW，膜厚为 150nm;中间为相变功能材料以 Bi4。Te54Si6为例，厚度为 60nm; 上电极为 TiW， 膜厚为 120nm; 三层结构的平面尺寸为 60 μ m *80 μ m。 用 探针台对上述构造的三层结构单元进行电流一电压 （I-V) 测试， 让两个探 针分别于上、 下电极接触， 施加幅度逐渐增加的直流电流脉冲信号， 并测 量存储单元所对应的电压， 得到的结果如图 2所示， 由图可知材料的相变 存储器存储单元的阈值电流和阈值电压及电阻变化特性。 从图中可看出 BixTeySi^^y)薄膜明显的开关特性。 对于本发明而言， 所述相变存储材料 的阈值电流随着 Si掺杂含量的提高而明显增大， 体现了非晶态的稳定性即 数据保持力的提高。 因此， 在实际应用中可以通过调节 Si含量而改变阈值 电流与结晶温度。
图 3以 Bi4。Te54Si6为例说明了本发明所述硅掺杂的铋碲基存储材料两态 的电阻变化， 电阻值由初始非晶态的 6865.9欧姆降到了晶态的 188.4欧姆， 变化幅度大于一个数量级。
实施例三
本实施里针对实施例一所述的硅掺杂的铋碲基存储材料之一 Bi40Te5oSi10, 进行沉积态与退火后的进行 X射线衍射测试， 测试结果如图 4 所示。 图中 a为沉积态， b为 300° C退火 3min后的多晶态。 由 XRD图谱 可知， Si掺杂的 BiTe基相变存储材料在晶态时表现出单一的三角晶系的结 构。
实施例四
本实施例对实施例一所述的硅掺杂的铋碲基存储材料进行 XPS测试， 测试结果如图 5和图 6所示。 图 5为硅掺杂的铋碲基存储材料中 Si原子 2p 电子的 XPS谱线， 由其能量值 （101.75eV) 排除了 Si-0键 （103. leV) 与 Si-Si键 （98.6ev) 存在的可能； 图 6为硅掺杂的铋碲基存储材料中 Bi原子 4f电子的 XPS谱线，与未掺杂的铋碲基存储材料中的 Bi原子相比，在较低 能量的地方出现了两个新的峰（162.6eV与 157.3eV)，且由峰位的能量值排 除了 Bi-0 ( 164.5eV与 159.1eV) 键或 Bi-Bi ( 162eV与 156.65eV) 键的可 能， 说明了 Si与 Bi原子成键。
本发明提供的硅掺杂的铋碲基材料有效地提高了 BiTe基材料非晶态的 稳定性， 结构均匀、 晶相单一， 器件性能稳定。 同时本发明提供的硅掺杂 的铋碲基材料电阻值较小， 有效地降低了写电流和擦写电流脉冲。
本发明除应用于 "T"字形相变存储器单元结构有效外， 对 "工"字形 结构、 线型结构、 非对称结构以及边接触型结构同样有效。 图 7和 8分别 为本发明可用于的 "T"字形和 "工"字形相变存储器单元结构示意图， 图 中 1为上电极， 2为相变功能材料
Figure imgf000008_0001
3为下电极， 4为衬底， 5为隔离层。 图 9本发明可用于的线型相变存储器单元结构示意图， 图 9中 1为左电极， 2为相变功能材料
Figure imgf000008_0002
3为右电极， 4为衬底， 5 为隔离层。

Claims

权 利 要 求
1、 一种用于相变随机存储器的硅掺杂的铋碲基存储材料， 其组分表达 式为
Figure imgf000009_0001
90 x+y<100。
2、 根据权利要求 1所述的硅掺杂的铋碲基存储材料， 其特征在于， 其 为电阻会在外部能量的作用下发生高阻和低阻之间的可逆转换的存储材 料， 电阻变化幅度在一个数量级以上。
3、 一种制备权利要求 1所述的硅掺杂的铋碲基存储材料的方法， 具体 为-
1 ) 制备 BixTey合金靶；
2 ) 对 BixTey合金靶上贴置 Si片；
3 ) 以 Ar作为溅射气体对贴置 Si片后的合金靶进行溅射， 制备得到硅 掺杂的铋碲基存储存储材料。
4、 根据权利要求 3所述的硅掺杂的铋碲基存储材料的方法， 其特征在 于， 溅射功率为 0~60W， 溅射 Ar气压为 0.78~0.82Pa。
5、 根据权利要求 3所述的硅掺杂的铋碲基存储材料的方法， 其特征在 于， 溅射功率为 50W， 溅射 Ar气压为 0.8Pa。
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