WO2013046863A1

WO2013046863A1 - Semiconductor device and method for manufacturing same

Info

Publication number: WO2013046863A1
Application number: PCT/JP2012/067801
Authority: WO
Inventors: 和則麻埜
Original assignee: ルネサスエレクトロニクス株式会社
Priority date: 2011-09-28
Filing date: 2012-07-12
Publication date: 2013-04-04
Also published as: JP2014239082A

Abstract

Provided is a technology for improving semiconductor device performance by providing an ohmic electrode wherein contact resistance is reduced and deterioration of surface morphology (surface roughness) is suppressed at the same time, said ohmic electrode being in ohmic contact with a nitride semiconductor layer. In the case where a thickness of a first molybdenum (Mo) film (MF1) inserted into between an AlGaN layer (AGNL) and an aluminum (Al) film (ALF) is X nm, the relationship of 2 nm≤X≤10 nm is satisfied. The ohmic electrode wherein surface morphology is improved and contact resistance is reduced at the same time can be formed on the AlGaN layer (AGNL) by, for instance, heat treating at a high temperature of 650-850°C a laminated body (LAB) thus configured.

Description

Semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor device and its manufacturing technology, and more particularly to a semiconductor device having an ohmic electrode in ohmic contact with a nitride semiconductor layer and a technology effectively applicable to its manufacturing technology.

In Japanese Patent No. 3154364 (Patent Document 1), titanium (Ti), aluminum (Al), refractory metal (nickel (Ni) or titanium (Ti)), gold (gold (Ni) or titanium (Ti)) are sequentially deposited on an n-type GaN layer from the bottom. The ohmic electrode which laminated | stacked Au) is described. By heat-treating this ohmic electrode at a high temperature of 800 ° C. or higher, a good ohmic electrode with low contact resistance can be obtained.

JP 2009-200290 A (patent document 2) has a structure in which a niobium (Nb) film is inserted between an aluminum (Al) film and a platinum (Pt) film (or a molybdenum (Mo) film). Ohmic electrodes are described. The niobium (Nb) film introduced into this ohmic electrode has a function to prevent the aluminum (Al) film from forming a eutectic with other metal films and to prevent an increase in contact resistance. It is supposed to be.

In Non-Patent Document 1, molybdenum (Mo) (15 nm), aluminum (Al) (60 nm), molybdenum (Mo) (35 nm) and gold (Au) (50 nm) are sequentially stacked from the bottom on the AlGaN layer. It is described that a good ohmic electrode is formed by heat treatment at a high temperature of 650 ° C. or higher.

Patent No. 3154364 JP, 2009-200290, A

In a semiconductor device having a nitride semiconductor layer typified by a GaN layer or an AlGaN layer, an ohmic electrode is generally formed to have an ohmic contact with the nitride semiconductor layer. For example, a layered structure of titanium (Ti) and aluminum (Al) or a layered structure of molybdenum (Mo) and aluminum (Al) is used as an ohmic electrode in ohmic contact with an n-type nitride semiconductor layer. . Such an ohmic electrode not only reduces the contact resistance (contact resistance) between the ohmic electrode and the nitride semiconductor layer from the viewpoint of the performance improvement (including the reliability improvement) of the semiconductor device, but also the ohmic electrode and the nitriding It is required to suppress deterioration of surface morphology (surface roughness) at the interface with the object semiconductor layer.

However, as a result of examining the ohmic electrode having the laminated structure of the present invention, as a result, the contact resistance (contact resistance) between the ohmic electrode and the nitride semiconductor layer is reduced, and the interface between the ohmic electrode and the nitride semiconductor layer It has become clear that it is difficult in the current ohmic electrode structure to simultaneously achieve the suppression of the deterioration of the surface morphology (surface roughness) in the above.

Among the means for solving the problems disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A semiconductor device and a method of manufacturing the same according to one embodiment include an electrode formed by performing heat treatment on a stacked body. The laminated body includes a first molybdenum film formed on a nitride semiconductor layer, an aluminum film formed on the first molybdenum film, a second molybdenum film formed on the aluminum film, and a second molybdenum film. If the film thickness of the first molybdenum film is X, the relationship of 2 nm ≦ X ≦ 10 nm is satisfied.

(2) The semiconductor device and the method of manufacturing the same according to one embodiment include an electrode formed by performing heat treatment on the stacked body. The laminated body includes a first molybdenum film formed on a nitride semiconductor layer, an aluminum film formed on the first molybdenum film, a second molybdenum film formed on the aluminum film, and a second molybdenum film. If the film thickness of the aluminum film is Y and the film thickness of the gold film is Z, the relationship of Y ≦ Z ≦ 2Y is satisfied.

(3) The semiconductor device in one embodiment is formed on a nitride semiconductor layer, has a structure in which aluminum, molybdenum, and gold interdiffuse, and an ohmic contact with the nitride semiconductor layer. And an ohmic electrode. At this time, at the interface between the nitride semiconductor layer and the ohmic electrode, the atomic percent of aluminum is the largest among aluminum, molybdenum, and gold.

According to one embodiment, in the ohmic electrode in ohmic contact with the nitride semiconductor layer, the reduction of the contact resistance (contact resistance) and the suppression of the deterioration of the surface morphology (surface roughness) can be compatible. Thereby, the performance of the semiconductor device can be improved.

It is a figure which shows each band structure before making the metal and n-type semiconductor which comprise a Schottky contact contact. FIG. 5 shows the band structure in equilibrium in Schottky contact. In Schottky contact, it is a figure which shows the band structure of a forward state. FIG. 5 shows a band structure in the reverse direction in Schottky contact. It is the graph which showed the current-voltage characteristic in Schottky contact. It is a figure which shows each band structure before making the metal and n-type semiconductor which comprise ohmic contact contact. It is a figure which shows the band structure of an equilibrium state in ohmic contact. FIG. 5 is a diagram showing a band structure in a forward direction in ohmic contact. It is a figure which shows the band structure of a reverse state in ohmic contact. It is the graph which showed the current-voltage characteristic in ohmic contact. It is a schematic diagram which shows the structure of the ohmic electrode described in the examination technique 1. FIG. FIG. 6 is a schematic view showing a structure of an ohmic electrode described in Study Technique 2. FIG. 2 is a schematic view showing a configuration of a laminate in Embodiment 1; FIG. 2 is a schematic view showing a configuration of a laminate in Embodiment 1; It is a graph which shows the relationship between the film thickness of a 1st molybdenum (Mo) film | membrane, and the contact resistance of an ohmic electrode and a semiconductor layer. It is a graph which shows the relationship between the film thickness of a 1st molybdenum (Mo) film | membrane, and the surface roughness (RMS) in the interface of an ohmic electrode and a semiconductor layer. FIG. 7 is a cross-sectional view showing the manufacturing process of the ohmic electrode in the first embodiment. FIG. 18 is a cross-sectional view showing the manufacturing process of the ohmic electrode continued from FIG. 17; FIG. 19 is a cross-sectional view showing the manufacturing process of the ohmic electrode continued from FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the ohmic electrode continued from FIG. 19; FIG. 21 is a cross-sectional view showing the manufacturing process of the ohmic electrode continued from FIG. 20; FIG. 22 is a cross-sectional view showing the manufacturing process of the ohmic electrode continued from FIG. 21; FIG. 10 is a schematic view showing a configuration of a laminate in Embodiment 2; FIG. 10 is a schematic view showing a configuration of a laminate in Embodiment 2; It is a graph which shows the relationship between Au / Al film thickness ratio, and the contact resistance of an ohmic electrode and a semiconductor layer. It is a graph which shows the relationship between Au / Al film thickness ratio, and the surface roughness (RMS) in the interface of an ohmic electrode and a semiconductor layer. FIG. 14 is a cross-sectional view showing the manufacturing process of the ohmic electrode in the second embodiment. FIG. 28 is a cross-sectional view showing the manufacturing process of the ohmic electrode continued from FIG. 27; FIG. 29 is a cross-sectional view showing the manufacturing process of the ohmic electrode continued from FIG. 28; FIG. 30 is a cross-sectional view showing the manufacturing process of the ohmic electrode continued from FIG. 29; FIG. 18 is a cross-sectional view showing the configuration of the HEMT in Embodiment 3; FIG. 7 is a band diagram for illustrating the off operation of the HEMT. FIG. 7 is a band diagram for explaining the on operation of the HEMT. FIG. 18 is a cross-sectional view showing the manufacturing process of the HEMT in the third embodiment. FIG. 35 is a cross-sectional view showing the manufacturing process of the HEMT, following FIG. 34; FIG. 36 is a cross-sectional view showing the manufacturing process of the HEMT, following FIG. 35; FIG. 37 is a cross-sectional view showing the manufacturing process of the HEMT, following FIG. 36; FIG. 38 is a cross-sectional view showing the manufacturing process of the HEMT, following FIG. 37; FIG. 39 is a cross-sectional view showing the manufacturing process of the HEMT, following FIG. 38; FIG. 40 is a cross-sectional view showing the manufacturing process of the HEMT, following FIG. 39; FIG. 41 is a cross-sectional view showing the manufacturing process of the HEMT, following FIG. 40; FIG. 42 is a cross-sectional view showing the manufacturing process of the HEMT, following FIG. 41; FIG. 21 is a cross-sectional view showing the configuration of the MISFET in the fourth embodiment. It is a schematic diagram for demonstrating the off operation | movement of MISFET. It is a schematic diagram for demonstrating ON operation | movement of MISFET. FIG. 21 is a cross-sectional view showing a configuration of a blue light-emitting diode in Embodiment 5; It is a band figure for demonstrating the OFF operation | movement of a blue light emitting diode. FIG. 6 is a band diagram for illustrating the on operation of the blue light emitting diode.

In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but they are not unrelated to each other unless specifically stated otherwise, one is the other And some or all of the variations, details, and supplementary explanations.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. It is not limited to the specific number except for the number, and may be more or less than the specific number.

Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless explicitly stated or considered to be obviously essential in principle. Needless to say.

Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components etc., unless specifically stated otherwise and in principle not considered otherwise in principle, etc., It includes those that are similar or similar to the shape etc. The same applies to the above numerical values and ranges.

Further, in all the drawings for describing the embodiments, the same reference numeral is attached to the same member in principle, and the repetitive description thereof will be omitted. In order to make the drawings easy to understand, hatching may be attached even to a plan view.

Embodiment 1
<Shotkey contact>
In a semiconductor device, for example, a semiconductor layer is formed on a semiconductor device, and a metal film is used for a wire (including an electrode). Therefore, a circuit is configured by electrically connecting the semiconductor device and the wire. In order to achieve this, it is necessary to bring the semiconductor layer and the metal film into contact with each other. Generally, when the semiconductor layer and the metal film are brought into contact, they may be in Schottky contact or in ohmic contact. In the case of merely electrically connecting the semiconductor layer and the metal film, it is necessary to make ohmic contact instead of Schottky contact. In the following, first, Schottky contact and ohmic contact will be described, and in the case of merely electrically connecting the semiconductor layer and the metal film, it will be described that it is necessary to make ohmic contact.

FIG. 1 is a view showing respective band structures before contacting a metal and an n-type semiconductor. The metal band structure is shown on the left side of FIG. 1, and the band structure of the n-type semiconductor is shown on the right side of FIG. What is indicated by a broken line in FIG. 1 is a vacuum level, which indicates the energy level of vacuum. In the metal band structure shown on the left side of FIG. 1, the Fermi level ε _FM of the metal is shown, and the difference between the Fermi level ε _FM of the metal and the vacuum level is the work function _{m m} . The work function _{m m} has the meaning of energy required to extract an electron having Fermi energy in the metal from the metal into a vacuum. On the other hand, in the band structure of the n-type semiconductor shown on the right side of FIG. 1, the valence band E _v and the conduction band E _c are shown, and the Fermi level ε _FS of the n-type semiconductor is near the conduction band E _c To be present. The difference between the Fermi level ε _FS of the n-type semiconductor and the vacuum level is the work function _{s s} . This work function _{s s} has the meaning of the energy required to extract an electron having Fermi energy in an n-type semiconductor into a vacuum.

Here, in FIG. 1, the magnitude of the work function _{m m} of the metal is larger than the work function Φ _s of the n-type semiconductor. In this case, when the metal and the n-type semiconductor are in contact, the metal and the n-type semiconductor Contact is a Schottky contact. In other words, when the position of the Fermi level ε _FM of the metal before contacting the metal and the n-type semiconductor is lower than the Fermi level ε _FS of the n-type semiconductor, the metal and the n-type semiconductor Contact is a Schottky contact.

Below, the mechanism in which a Schottky contact is formed is demonstrated. For example, when the metal and the n-type semiconductor are brought into contact from the state shown in FIG. 1, the position of the Fermi level ε _FM of the metal is lower than the Fermi level ε _{FS of} the n-type semiconductor. A large number of electrons near the bottom of E _c have lower energy when they are present in the metal than in the n-type semiconductor. From this, when the metal and the n-type semiconductor are brought into contact, electrons present in the vicinity of the bottom of the conduction band E _c of the n-type semiconductor flow from the n-type semiconductor toward the metal. As a result, positively charged donor ions are left on the surface region of the n-type semiconductor in contact with the metal, and the same amount of negative charge (electrons) is induced on the metal side. Then, an electric field is generated in a direction from the n-type semiconductor toward the metal, and the electric field suppresses the influx of electrons present in the vicinity of the bottom of the conduction band E _c of the n-type semiconductor from the n-type semiconductor into the metal. . That is, after a certain amount of electrons flow into the metal from the n-type semiconductor, the electrons no longer flow into the metal, and an equilibrium state is realized.

FIG. 2 shows the band structure in this equilibrium state. That is, as shown in FIG. 2, in the equilibrium state, the Fermi level ε _FM of the metal and the Fermi level ε _FS of the n-type semiconductor coincide with each other. At this time, since the electron density does not change from the state before contact in the sufficient interior of the n-type semiconductor, the energy difference between the Fermi level ε _FS of the n-type semiconductor and the bottom of the conduction band E _c does not change. The band of the semiconductor will bend upward, as shown in FIG. As a result, in the contact area with the n-type semiconductor of metal, the bottom energy of the conduction band E _c is, to become higher than the bottom energy of the n-type semiconductor inside the conduction band E _c, a metal of the n-type semiconductor Electrons do not exist in the contact region with and a depletion layer is formed. Thus, when the magnitude of the work function _{m m} of the metal is larger than the work function Φ _s of the n-type semiconductor, when the metal and the n-type semiconductor are brought into contact with each other, the contact of the metal and the n-type semiconductor becomes Schottky contact Become. At this time, the height Φ _B of the Schottky barrier is defined as the difference between the energy at the bottom of the conduction band E _c in the contact region of the n-type semiconductor with the metal and the Fermi level ε _FM of the metal.

Here, it is assumed that a forward voltage is applied between a metal forming a Schottky contact and an n-type semiconductor. That is, a case is considered in which a voltage is applied such that the metal side has a positive potential with respect to the n-type semiconductor side. In this case, most of the forward voltage is applied to the high resistance depletion layer, so the external electric field due to this forward voltage suppresses the inflow of electrons from the n-type semiconductor to the metal in the depletion layer. It will weaken. As a result, electrons flow from the n-type semiconductor into the metal, and current flows from the metal to the n-type semiconductor. This is the forward direction.

FIG. 3 is a diagram showing a band structure in the forward direction. As shown in FIG. 3, when a forward voltage V is applied between the metal and the n-type semiconductor, the n-type semiconductor is energetically higher than the metal for electrons, so the n-type semiconductor is The Fermi level ε _{FS of} is higher by qV than the Fermi level ε _FM of the metal. Then, the energy barrier seen from the electrons in the n-type semiconductor is qV lower than the energy barrier in an equilibrium state (voltage Φ _{B of the} Schottky barrier) in which no voltage is applied. As a result, electrons flow from the n-type semiconductor to the metal, and a current (forward current) flows from the metal to the n-type semiconductor.

On the other hand, consider the case where a reverse voltage is applied between the metal forming the Schottky contact and the n-type semiconductor. That is, a case is considered in which a voltage is applied such that the metal side has a negative potential with respect to the n-type semiconductor side. In this case, most of the reverse voltage is applied to the high resistance depletion layer, and an external electric field due to this reverse voltage is generated to strengthen the electric field in the depletion layer. As a result, the flow of electrons from the n-type semiconductor into the metal does not occur, and almost no current flows. This is the opposite direction.

FIG. 4 is a diagram showing a band structure in the reverse direction. As shown in FIG. 4, when a reverse voltage V is applied between a metal and an n-type semiconductor, the n-type semiconductor is lower in energy than the metal for electrons, so the n-type semiconductor The Fermi level ε _{FS of} is lower by qV than the Fermi level ε _FM of the metal. Then, the energy barrier seen from electrons in the n-type semiconductor becomes qV higher than the energy barrier in an equilibrium state (the height Φ _{B of the} Schottky barrier) in which no voltage is applied. As a result, it is understood that electrons are less likely to flow from the n-type semiconductor to the metal, and almost no current flows from the metal to the n-type semiconductor. Here, the reason that almost no current flows is that in the reverse state, as a result of the slight flow of electrons from the metal to the n-type semiconductor, a slight reverse current flows from the n-type semiconductor to the metal . That is, when the reverse voltage V is applied, as shown in FIG. 4, the Fermi level ε _FM of the metal becomes qV higher than the Fermi level ε _FS of the n-type semiconductor, so the electrons are rather It flows from metal to n-type semiconductor. That is, in the reverse state, since the Fermi level ε _FM of the metal is qV higher than the Fermi level ε _FS of the n-type semiconductor, the Fermi level ε _FM in the metal is higher than the height φ _{B of the} Schottky barrier There are more electrons having larger energy than electrons having energy larger than (Φ _B -qV) from the Fermi level ε _FS in the n-type semiconductor. From this, the electrons flow from the metal into the n-type semiconductor due to the diffusion phenomenon caused by the difference in concentration of the electrons. As a result, a small amount of reverse current flows from the n-type semiconductor to the metal.

The above is the characteristic of the Schottky contact. FIG. 5 is a graph showing current-voltage characteristics at Schottky contact. In FIG. 5, the horizontal axis shows the voltage applied between the Schottky contacts, and the vertical axis shows the current flowing between the Schottky contacts. As shown in FIG. 5, when a forward voltage is applied to the Schottky contact, the forward current rises exponentially as the forward voltage increases. On the other hand, when a reverse voltage is applied to the Schottky contact, the reverse current is constant at a substantially small value even if the reverse voltage increases. From this, it can be seen that the current-voltage characteristics of the Schottky contact are completely different from the current-voltage characteristics in the forward direction and the current-voltage characteristics in the reverse direction. That is, it can be seen that the Schottky contact has a rectifying characteristic that a current flows sufficiently in the forward direction, and a current hardly flows in the reverse direction.

Here, when it is considered that a semiconductor device having a semiconductor layer and a wiring formed of a metal film are electrically connected to form a circuit, there is a disadvantage that the contact between the semiconductor layer and the metal film is a Schottky contact. It occurs. This is because even if the semiconductor layer and the metal film are electrically connected, if the contact between the semiconductor layer and the metal film is a Schottky contact, the Schottky contact has a rectifying characteristic like a diode. As a result, a diode is additionally connected between the semiconductor layer and the metal film, which is different from the intended circuit configuration. From this, the contact of the semiconductor layer and the metal film requires a resistive ohmic contact having no rectifying characteristic.

<Ohmic contact>
Below, this ohmic contact is demonstrated. FIG. 6 is a view showing respective band structures before contacting a metal and an n-type semiconductor. The metal band structure is shown on the left side of FIG. 6, and the band structure of the n-type semiconductor is shown on the right side of FIG. In FIG. 6, the magnitude of the work function _{m m} of the metal is smaller than the work function Φ _s of the n-type semiconductor. In this case, when the metal and the n-type semiconductor are in contact, the contact of the metal and the n-type semiconductor is Ohmic contact. In other words, when the position of the Fermi level ε _FM of the metal before bringing the metal and the n-type semiconductor into contact with each other is higher than the Fermi level ε _FS of the n-type semiconductor, the metal and the n-type semiconductor Contact is an ohmic contact.

Next, the mechanism by which the ohmic contact is formed will be described. For example, when the metal and the n-type semiconductor are brought into contact from the state shown in FIG. 6, the position of the Fermi level ε _FM of the metal is higher than the Fermi level ε _FS of the n-type semiconductor. The energy is lower in the n-type semiconductor than in the metal. From this, when the metal and the n-type semiconductor are brought into contact, electrons present in the metal flow from the metal toward the n-type semiconductor. As a result, the electron concentration of the surface region of the n-type semiconductor in contact with the metal becomes high, and the same amount of positive charge is induced on the metal side. Then, an electric field is generated in a direction from the metal to the n-type semiconductor, and the electric field suppresses the inflow of electrons present in the metal from the metal to the n-type semiconductor. That is, after a certain amount of electrons flow from the metal into the n-type semiconductor, the electrons no longer flow into the n-type semiconductor, and an equilibrium state is realized.

FIG. 7 shows the band structure in this equilibrium state. That is, as shown in FIG. 7, in the equilibrium state, the Fermi level ε _FM of the metal and the Fermi level ε _FS of the n-type semiconductor coincide with each other. At this time, since the electron density does not change from the state before contact in the sufficient interior of the n-type semiconductor, the energy difference between the Fermi level ε _FS of the n-type semiconductor and the bottom of the conduction band E _c does not change. The band of the semiconductor bends downward as shown in FIG. As a result, in the contact area with the n-type semiconductor of metal, the bottom energy of the conduction band E _c is, becomes lower than the bottom energy of the n-type semiconductor inside the conduction band E _c, a metal of the n-type semiconductor Many electrons will be present in the contact area with. Thus, when the size of the work function _{m m} of the metal is smaller than the work function Φ _s of the n-type semiconductor, when the metal and the n-type semiconductor are brought into contact, the contact between the metal and the n-type semiconductor becomes an ohmic contact . At this time, it is understood that in the ohmic contact, a Schottky barrier different from the Schottky contact is not formed.

Here, it is assumed that a first voltage is applied between the metal forming the ohmic contact and the n-type semiconductor such that the metal side has a positive potential with respect to the n-type semiconductor side. FIG. 8 is a diagram showing a band structure when the first voltage is applied so that the metal side has a positive potential with respect to the n-type semiconductor side. As shown in FIG. 8, when the above-described first voltage V is applied between the metal and the n-type semiconductor, the metal is lower in energy than the n-type semiconductor for electrons, so the metal The Fermi level ε _{FM of} is lower by qV than the Fermi level ε _FS of the n-type semiconductor. Then, a large number of electrons present in the vicinity of the conduction band in the n-type semiconductor flow from the n-type semiconductor into the metal, and a current flows from the metal toward the n-type semiconductor.

On the other hand, a case is considered where a second voltage is applied between the metal forming the ohmic contact and the n-type semiconductor such that the metal side has a negative potential with respect to the n-type semiconductor side. FIG. 9 is a diagram showing a band structure when the second voltage is applied so that the metal side has a negative potential with respect to the n-type semiconductor side. As shown in FIG. 9, when the above-described second voltage V is applied between the metal and the n-type semiconductor, the metal is higher in energy than the n-type semiconductor for electrons, so the metal The Fermi level ε _{FM of} is higher by qV than the Fermi level ε _FS of the n-type semiconductor. Then, electrons present in the metal flow from the metal to the n-type semiconductor, and a current flows from the n-type semiconductor to the metal.

The above is the characteristic of the ohmic contact. FIG. 10 is a graph showing current-voltage characteristics in ohmic contact. In FIG. 10, the horizontal axis indicates the voltage applied between the ohmic contacts, and the vertical axis indicates the current flowing between the ohmic contacts. As shown in FIG. 10, when the first voltage is applied to the ohmic contact, the current in the positive direction rises linearly in a linear manner as the first voltage increases. On the other hand, when the second voltage is applied to the ohmic contact, the current in the negative direction rises linearly in a linear manner as the second voltage increases. From this, it is understood that the current-voltage characteristic of the ohmic contact is completely equal to the current-voltage characteristic at the first voltage polarity and the current-voltage characteristic at the second voltage polarity. That is, it can be understood that the ohmic contact is a resistive contact and does not have rectifying characteristics like a Schottky contact.

Therefore, considering that a semiconductor device having a semiconductor layer and a wiring formed of a metal film are electrically connected to form a circuit, it is considered that the contact between the semiconductor layer and the metal film is an ohmic contact. It proves to be advantageous because it has no rectifying properties like contacts. That is, when the semiconductor layer and the metal film make ohmic contact, it can be seen that the semiconductor layer and the metal film become resistive contact having no rectifying characteristic, and the target circuit configuration can be realized.

<Need to improve the characteristics of ohmic electrode>
As described above, in a device having a semiconductor layer, in many cases, it is necessary to electrically connect the semiconductor layer and the metal film to constitute an integrated circuit. At this time, an integrated circuit using a device having a semiconductor layer is realized by bringing the semiconductor layer and the metal film into ohmic contact with each other. The ohmic electrode is used, for example, as a source electrode or a drain electrode in a transistor, an electrode when a semiconductor layer is used as a resistance element, or the like. Therefore, in order to realize an integrated circuit using a device having a semiconductor layer, it is necessary to form an ohmic electrode in ohmic contact with the semiconductor layer. Then, from the viewpoint of improving the performance of the integrated circuit (including improving the reliability), not only the contact resistance (contact resistance) between the ohmic electrode and the semiconductor layer is reduced as much as possible, but also the surface morphology at the interface between the ohmic electrode and the semiconductor layer It is required to suppress the deterioration of (surface roughness). It is needless to say that it is necessary to reduce the contact resistance of the ohmic electrode from the viewpoint of improving the characteristics of the integrated circuit, but the deterioration of the surface morphology leads to the deterioration of the adhesion between the ohmic electrode and the semiconductor layer. This is because it is considered that this causes a device breakdown due to the peeling of the ohmic electrode and the occurrence of an unnecessary leak current and the like, which becomes a problem from the viewpoint of improving the reliability of the semiconductor device.

Here, a device having a nitride semiconductor which is a type of compound semiconductor is no exception, and in order to realize an integrated circuit using a device having a nitride semiconductor layer, an ohmic electrode in ohmic contact with the nitride semiconductor layer is used. It needs to be formed. Then, from the viewpoint of improving the performance of the integrated circuit (including improving the reliability), not only the contact resistance (contact resistance) between the ohmic electrode and the nitride semiconductor layer is reduced, but also the interface between the ohmic electrode and the nitride semiconductor layer It is also necessary to suppress the deterioration of surface morphology (surface roughness) in In particular, in the present invention, in the ohmic electrode in ohmic contact with the intrinsic nitride semiconductor layer (non-doped nitride semiconductor layer) and the n-type nitride semiconductor layer, reduction of contact resistance (contact resistance) and surface morphology (surface roughness) It is an object of the present invention to provide an ohmic electrode compatible with the suppression of the deterioration of The present invention is, in particular, a technical idea aiming to improve the characteristics of the ohmic electrode in the nitride semiconductor. At this time, the reason for focusing on the nitride semiconductor in the present invention is that among the compound semiconductors, there are many points where the characteristics of the nitride semiconductor are excellent. First, advantages of the nitride semiconductor, which is a type of compound semiconductor, in comparison with a compound semiconductor represented by GaAs will be described.

<Advantages of using nitride semiconductors>
For example, in compound semiconductors typified by GaAs and AlGaAs, in general, the mobility of electrons is higher than that of silicon (Si), while the mobility of holes is equivalent to that of silicon (Si) or silicon Less than (Si). Therefore, for example, when a compound semiconductor is used as a component of a device (semiconductor element), a device using electrons as a majority carrier can utilize the characteristics of the compound semiconductor.

Among compound semiconductors, nitride semiconductors typified by GaN and AlGaN have attracted attention in recent years, although they are compound semiconductors having such characteristics. This is because a nitride semiconductor (an example of a compound semiconductor) represented by GaN or AlGaN has a larger band gap than a compound semiconductor represented by GaAs or AlGaAs, and as a result, the dielectric breakdown voltage is increased. It is because Therefore, in recent years, nitride semiconductors represented by GaN and AlGaN are used, for example, in the field of high frequency devices and power devices.

Furthermore, when a heterojunction of an AlGaN layer and a GaN layer is formed, it is known from the difference in the band structure that a triangular well potential is formed near both interfaces and electrons are concentrated in this well potential. (Two-dimensional electron gas). Since the mobility of this two-dimensional electron gas becomes very high, according to the field effect transistor using the two-dimensional electron gas generated in the well type potential formed in the vicinity of both interfaces as a carrier, the electric field operates at high speed An effect transistor is realized. A field effect transistor using this two-dimensional electron gas is called a high electron mobility transistor (HEMT). As this HEMT, there is also one using a heterojunction of an AlGaAs layer and a GaAs layer, but the surface charge of the two-dimensional electron gas based on the heterojunction of an AlGaN layer and a GaN layer (for example, 1 × 10 ¹³ / cm ² ) Is sufficiently larger (for example, 10 times) than the surface charge (for example, 1 × 10 ¹² / cm ² ) of the two-dimensional electron gas based on the heterojunction of the AlGaAs layer and the GaAs layer. This conduction band discontinuity Delta] E _c of the AlGaN layer and the GaN layer is, with greater than the conduction band discontinuity Delta] E _c of the AlGaAs layer and the GaAs layer, a heterojunction AlGaN layer and the GaN layer, the piezoelectric effect due to spontaneous polarization By this, the bottom of the well potential is lowered to the lower side (the valence band side). As a result, the magnitude of the well potential formed at the heterojunction of the AlGaN layer and the GaN layer is larger than the magnitude of the well potential formed at the heterojunction of the AlGaAs layer and the GaAs layer. The surface charge of the two-dimensional electron gas based on the heterojunction of the AlGaN layer and the GaN layer becomes sufficiently larger than the surface charge of the two-dimensional electron gas based on the heterojunction of the AlGaAs layer and the GaAs layer. Therefore, according to the HEMT using the heterojunction of the AlGaN layer and the GaN layer, there is an advantage that it is easy to obtain a large current as compared with the HEMT using the heterojunction of the AlGaAs layer and the GaAs layer.

As described above, nitride semiconductors typified by GaN and AlGaN are used in the fields of high frequency devices and power devices, and in particular, according to HEMTs using nitride semiconductors, the above-mentioned advantages can be obtained. it can. Furthermore, in recent years, the application field of nitride semiconductors has also spread to the field of optical devices. For example, a nitride semiconductor represented by InGaN is used as a light emitting layer of a blue light emitting diode. As described above, the present invention focuses on the advantages of the nitride semiconductor and aims to improve the performance of the semiconductor device using the nitride semiconductor. In particular, the present invention focuses on improving the characteristics of the ohmic electrode in ohmic contact with the nitride semiconductor layer. In the following, first, a study technique for the ohmic electrode in ohmic contact with the nitride semiconductor layer and its problems will be described, and then the technical concept of the present invention will be described.

<Examination technology 1>
FIG. 11 is a schematic view prepared by the present inventor with reference to the ohmic electrode described in Study Technique 1 (Japanese Patent No. 3154364). As shown in FIG. 11, the ohmic electrode OE in Study Technique 1 is formed on the n-type GaN layer nGNL. The ohmic electrode OE is formed of an alloy film (or multilayer film) TAF formed of titanium (Ti) and aluminum (Al) formed on the n-type GaN layer nGNL, and a high melting point metal formed on the alloy film TAF. It comprises a film HMF and a gold film AUF formed on the refractory metal film HMF. In Study Technique 1, it is supposed that a good ohmic electrode OE with low contact resistance can be obtained by heat-treating this laminated structure at a high temperature of 800 ° C. or higher.

As a result of examination by the present inventor, it was found that the examination technique 1 had the following problems. The first problem of the examination technique 1 is that the surface morphology (surface roughness) of the ohmic electrode OE is poor. This is due to the fact that aluminum (Al) and a high melting point metal such as nickel (Ni) easily form an alloy at a low temperature, and this alloy is formed uneven in plan view. The deterioration of the surface morphology promotes the exfoliation of the ohmic electrode OE from the n-type GaN layer nGNL and causes the device breakdown (element breakdown) due to the exfoliation of the ohmic electrode OE. Alternatively, device breakdown due to local concentration of the electric field at a portion where the electrode edge becomes uneven may cause generation of unnecessary leak current and the like. As a result, the reliability of the semiconductor device is reduced.

In addition, as a second problem newly found by the inventors of the present invention, when titanium (Ti) is used so as to be in direct contact with the n-type GaN layer nGNL, usually between the substrate and the n-type GaN layer nGNL There is a problem that an unnecessary leak current occurs in the high resistance buffer layer provided in This is because when titanium (Ti) is heat-treated at high temperature, titanium (Ti) penetrates into the inside of the n-type GaN layer nGNL through crystal transition existing on the surface of the n-type GaN layer nGNL, and further, It is considered to be diffused to the resistive buffer layer. That is, when titanium (Ti) is diffused to the high resistance buffer layer, unnecessary leak current is increased by the titanium diffused to the high resistance buffer layer. Thus, in the ohmic electrode OE described in Study Technique 1, there is a problem that the characteristics of the ohmic electrode OE can not be sufficiently improved.

<Examination technology 2>
Subsequently, the examination technique 2 will be described. FIG. 12 is a schematic view created by the present inventor with reference to the ohmic electrode described in Study Technique 2 (Non-Patent Document 1). As shown in FIG. 12, the ohmic electrode OE in Study Technique 2 has the AlGaN layer AGNL formed on the GaN layer GNL, and is formed on the AlGaN layer AGNL. Specifically, the ohmic electrode OE in Study Technique 2 includes the first molybdenum (Mo) film MF1 formed on the AlGaN layer AGNL and the aluminum (Al) film formed on the first molybdenum (Mo) film MF1. It is composed of ALF, a second molybdenum (Mo) film MF2 formed on the aluminum (Al) film ALF, and a gold film AUF formed on the second molybdenum (Mo) film MF2. In the examination technique 2, it is supposed that a good ohmic electrode OE can be obtained by heat-treating this laminated structure at a high temperature of 650 ° C. or higher.

In Study Technique 2 configured in this way, the first molybdenum (Mo) film is formed in the lowermost layer of the ohmic electrode OE, but molybdenum (Mo) has a higher melting point than titanium (Ti) Therefore, the problem of diffusion of molybdenum (Mo) into, for example, a high resistance buffer layer through crystal transition is avoided. However, as a result of examination by the inventor, it was found that the ohmic electrode OE in the examination technique 2 has a problem in that the contact resistance and the surface morphology are not necessarily good. For example, in Study Technique 2, the thickness of the first molybdenum (Mo) film MF1 is 15 nm, the thickness of the aluminum (Al) film ALF is 60 nm, the thickness of the second molybdenum (Mo) film MF2 is 35 nm, and the gold film AUF The film thickness is 50 nm, but with these film thicknesses, the contact resistance and the surface morphology can not always be compatible. That is, in order to make the contact resistance and the surface morphology compatible, it is necessary to adjust the film thickness of each layer constituting the ohmic electrode OE well, and depending on the film thickness condition, there is a possibility that the contact resistance increases and the surface morphology deteriorates. There is

As described above, in Study Technology 1 and Study Technology 2, in the ohmic electrode in ohmic contact with the nitride semiconductor layer, both reduction in contact resistance (contact resistance) and suppression of deterioration in surface morphology (surface roughness) are both achieved. It is in the present condition that can not be done. Therefore, in the invention of the present application, in the ohmic electrode in ohmic contact with the nitride semiconductor layer, measures are taken to achieve both reduction in contact resistance (contact resistance) and suppression of deterioration in surface morphology (surface roughness). The technical idea of the present invention to which this device is applied will be described below.

<Configuration of Laminate in Present Invention>
FIG. 13 is a schematic view showing the configuration of the stacked body LAB in the first embodiment. In the first embodiment, the laminated body LAB shown in FIG. 13 is subjected to a heat treatment, whereby the ohmic electrode in the first embodiment is formed. That is, the stacked body LAB shown in FIG. 13 has a structure before heat treatment to form an ohmic electrode. As shown in FIG. 13, the stacked body LAB in the first embodiment is formed on the AlGaN layer AGNL formed on the GaN layer GNL. The stacked body LAB includes a first molybdenum (Mo) film MF1 formed on the AlGaN layer AGNL, an aluminum (Al) film ALF formed on the first molybdenum (Mo) film MF1, and an aluminum (Al) film. 2.) A second molybdenum (Mo) film MF2 formed on the film ALF, and a gold (Au) film AUF formed on the second molybdenum (Mo) film MF2.

Here, an aluminum (Al) film can be mentioned as a metal film in ohmic contact with the AlGaN layer AGNL. That is, the aluminum (Al) film ALF used in the stacked body LAB shown in FIG. 13 is a film having a function of ensuring ohmic contact with the AlGaN layer AGNL. At this time, it is conceivable to form an aluminum (Al) film ALF directly on the AlGaN layer AGNL from the viewpoint of securing an ohmic contact with the AlGaN layer AGNL. However, the adhesion between the aluminum (Al) film ALF and the AlGaN layer AGNL is poor. Therefore, in the structure in which the aluminum (Al) film ALF is in direct contact with the AlGaN layer AGNL, the phenomenon that the aluminum (Al) film ALF bulges due to surface tension when the heat treatment is performed to form the ohmic electrode (ball-up phenomenon and ), And the surface morphology at the interface between the AlGaN layer AGNL and the aluminum (Al) film ALF is degraded. Deterioration of the surface morphology leads to a decrease in adhesion between the ohmic electrode and the semiconductor layer, causing device breakdown due to peeling of the ohmic electrode and generation of unnecessary leak current, which becomes a problem from the viewpoint of improving the reliability of the semiconductor device. .

Therefore, in the first embodiment, the first molybdenum (Mo) film MF1 is inserted between the AlGaN layer AGNL and the aluminum (Al) film ALF. That is, the first molybdenum (Mo) film MF1 has a function of improving the adhesion between the AlGaN layer AGNL and the aluminum (Al) film ALF, and by forming the first molybdenum (Mo) film MF1, The surface morphology at the interface between the AlGaN layer AGNL and the aluminum (Al) film ALF can be improved.

Subsequently, the gold (Au) film AUF formed on the laminate LAB is subjected to a heat treatment on the laminate LAB to oxidize the surface of the aluminum (Al) film ALF when forming the ohmic electrode. Have a function to prevent That is, when the heat treatment is performed on the aluminum (Al) film ALF, the surface of the aluminum (Al) film ALF is easily oxidized. When the aluminum (Al) film ALF is oxidized, since the aluminum oxide is an insulator, the resistance of the ohmic electrode is increased, and the electrical characteristics of the ohmic electrode are deteriorated. From this, in order to prevent the oxidation of the aluminum film (Al) ALF during the heat treatment, the gold (Au) film AUF is formed on the aluminum (Al) film ALF. However, when the gold (Au) film AUF is formed on the aluminum (Al) film ALF so as to be in direct contact, when heat treatment is performed, the aluminum (Al) film ALF and the gold (Au) film AUF are formed. A rapid alloy reaction will occur. Since this alloy reaction also causes deterioration of the surface morphology, it is necessary to suppress the alloy reaction as much as possible. From this viewpoint, the second molybdenum (Mo) film MF2 which is a high melting point metal is formed as an intermediate layer between the aluminum (Al) film ALF and the gold (Au) film AUF. That is, the second molybdenum (Mo) film MF2 has a function of suppressing a rapid alloy reaction between the aluminum (Al) film ALF and the gold (Au) film AUF.

From the above, the laminated body LAB in the first embodiment includes the first molybdenum (Mo) film, the aluminum (Al) film ALF, the second molybdenum (Mo) film MF2, and the gold (Au) film AUF. It will be comprised from laminated film. Then, the functions of the respective films constituting laminated body LAB in the first embodiment are summarized as follows.

(1) First, the lowermost first molybdenum (Mo) film MF1 is a film that functions as an adhesion film, and the first molybdenum (Mo) film is formed between the AlGaN layer AGNL and the aluminum (Al) film ALF. By inserting the MF 1, the adhesion between the AlGaN layer AGNL and the aluminum (Al) film ALF can be improved. Thereby, the surface morphology at the interface between the AlGaN layer AGNL and the aluminum (Al) film ALF can be improved.

(2) The aluminum (Al) film ALF is a film that functions as an ohmic metal for achieving an ohmic contact with the AlGaN layer AGNL, and the aluminum (Al) film ALF is made between the aluminum (Al) film and the AlGaN layer AGNL. An ohmic electrode in ohmic contact can be formed. Further, since the resistance of the aluminum (Al) film ALF is relatively small, the contact resistance (contact resistance) between the ohmic electrode and the AlGaN layer AGNL can be reduced.

(3) The second molybdenum (Mo) film MF2 suppresses rapid alloy reaction between the aluminum (Al) film ALF and the gold (Au) film AUF when the laminate LAB is subjected to heat treatment The membrane has the function of Thus, by inserting the second molybdenum (Mo) film MF2 which is a high melting point metal between the aluminum (Al) film ALF and the gold (Au) film AUF, the aluminum (Al) film ALF and the gold (gold) Au) The rapid alloying reaction that occurs with the film AUF can be suppressed.

(4) The gold (Au) film AUF has a function of preventing the surface of the aluminum (Al) film ALF from being oxidized when the laminate LAB is subjected to heat treatment. By thus forming the gold (Au) film AUF on the aluminum (Al) film ALF, the oxidation of the aluminum (Al) film can be prevented, and the resistance increase of the ohmic electrode can be suppressed.

According to the laminated body LAB of Embodiment 1 configured as described above, first, a titanium (Ti) film is used as an adhesive film for improving the adhesion between the AlGaN layer AGNL and the aluminum (Al) film ALF. Instead, the first molybdenum (Mo) film MF1 is used. At this time, since molybdenum (Mo) has a melting point higher than that of titanium (Ti), diffusion of a metal into a semiconductor layer (for example, a high resistance buffer layer) can be suppressed through crystal transition. That is, the ohmic electrode is formed by performing the heat treatment on the laminate LAB in the first embodiment, but at this time, since molybdenum (Mo) has a higher melting point than titanium (Ti), Diffusion of molybdenum into the semiconductor layer (eg, high-resistance buffer layer) can be suppressed through crystal transition. As a result, it is possible to suppress the generation of unnecessary leak current in the semiconductor layer (for example, the high resistance buffer layer).

Further, in the laminated body LAB in the first embodiment, the first molybdenum (Mo) film formed in the lowermost layer as an intermediate layer inserted between the aluminum (Al) film ALF and the gold (Au) film AUF A second molybdenum (Mo) film MF2 which is a film of the same type as MF1 is used. For this reason, there is also an advantage that when the ohmic electrode is formed, the unnecessary alloy film is not easily formed by performing the heat treatment on the laminate LAB.

<New Challenges Found by the Inventor>
As described above, in the stacked body LAB in the first embodiment, the first molybdenum (Mo) film MF1 functioning as an adhesion film is inserted between the AlGaN layer AGNL and the aluminum (Al) film ALF. Thereby, the adhesion between the AlGaN layer AGNL and the aluminum (Al) film ALF can be improved, and the surface morphology can be improved. Thus, from the viewpoint of improving the surface morphology, it is desirable to insert the first molybdenum (Mo) film MF1 between the AlGaN layer AGNL and the aluminum (Al) film ALF. However, the inventor found that the contact resistance increases when the thickness of the first molybdenum (Mo) film MF1 is too large. That is, it has been found that it is a problem that the film thickness of the first molybdenum (Mo) film MF1 is too thick from the viewpoint of reducing the contact resistance (contact resistance). Here, in the case where the stacked body LAB is subjected to a heat treatment to form an ohmic electrode, atoms are mutually diffused from each layer constituting the stacked body LAB. At this time, for example, when the atomic percent of aluminum atoms is larger than the atomic percent of molybdenum atoms at the interface between the ohmic electrode and the AlGaN layer AGNL, the effect of the contact with the aluminum atoms becomes large. It is considered that the contact between AGNL and the ohmic electrode is an ohmic contact, and the contact resistance can be reduced. However, if the film thickness of the first molybdenum (Mo) film MF1 is too large, aluminum is formed at the interface between the ohmic electrode and the AlGaN layer AGNL, even when atoms interdiffuse from each layer constituting the stacked body LAB. It is considered that the atomic percent of atoms is often less than the atomic percent of molybdenum atoms. In this case, it is considered that the contact between the AlGaN layer AGNL and the ohmic electrode is greatly affected by the contact with the molybdenum forming the Schottky contact, and an increase in contact resistance occurs.

As described above, since the adhesion between the AlGaN layer AGNL and the aluminum (Al) film ALF is poor, the first molybdenum (between the AlGaN layer AGNL and the aluminum (Al) film ALF is used to improve the adhesion. Mo) It is necessary to insert the membrane MF1. However, the inventor found that the contact resistance (contact resistance) between the AlGaN layer AGNL and the ohmic electrode increases if the film thickness of the first molybdenum (Mo) film MF1 is too large. is there. That is, from the viewpoint of achieving both improvement in surface morphology and reduction in contact resistance, the thickness of the first molybdenum (Mo) film MF1 inserted between the AlGaN layer AGNL and the aluminum (Al) film ALF is devised It is necessary. Therefore, in the first embodiment, the thickness of the first molybdenum (Mo) film MF1 inserted between the AlGaN layer AGNL and the aluminum (Al) film ALF is devised. The technical idea in the first embodiment to which this device is applied will be described below.

<Features of First Embodiment>
As shown in FIG. 13, the stacked body LAB in the first embodiment is formed on the AlGaN layer AGNL formed on the GaN layer GNL. The stacked body LAB includes a first molybdenum (Mo) film MF1 formed on the AlGaN layer AGNL, an aluminum (Al) film ALF formed on the first molybdenum (Mo) film MF1, and an aluminum (Al) film. 2.) A second molybdenum (Mo) film MF2 formed on the film ALF, and a gold (Au) film AUF formed on the second molybdenum (Mo) film MF2.

Here, the feature of the first embodiment is that 2 nm ≦ X ≦ where the film thickness of the first molybdenum (Mo) film MF1 inserted between the AlGaN layer AGNL and the aluminum (Al) film ALF is X nm. It is characterized in that the 10 nm relationship is satisfied. In the first embodiment, the laminated electrode LAB configured in this way is heat-treated at a high temperature of 650 ° C. to 850 ° C., for example, to form an ohmic electrode that achieves both improvement of surface morphology and reduction of contact resistance. It can be formed on layer AGNL.

Here, for example, in the first embodiment, the film thickness of the film other than the first molybdenum (Mo) film MF1 (aluminum (Al) film ALF, second molybdenum (Mo) film MF2, gold (Au) film AUF) Is not particularly limited as long as the function of each film is exhibited. For example, as an example, the thickness of the aluminum (Al) film ALF is 70 nm, the thickness of the second molybdenum (Mo) film MF2 is 30 nm, and the thickness of the gold (Au) film AUF is 50 nm. ing.

Although FIG. 13 illustrates an example in which the stacked body LAB is formed on the AlGaN layer AGNL, for example, as shown in FIG. 14, the stacked body LAB is also formed on the n-type GaN layer nGNL. The technical idea in the first embodiment can be applied. Specifically, assuming that the thickness of the first molybdenum (Mo) film MF1 inserted between the n-type GaN layer nGNL and the aluminum (Al) film ALF is X nm, the relationship of 2 nm ≦ X ≦ 10 nm is satisfied. To form a stack LAB. Then, the laminated body LAB is heat-treated at a high temperature of, for example, 650 ° C. to 850 ° C. to form an ohmic electrode on the n-type GaN layer nGNL in which the improvement of the surface morphology and the reduction of the contact resistance are compatible. it can.

As described above, in the structure in which the aluminum (Al) film ALF is in direct contact with the AlGaN layer AGNL or the n-type GaN layer nGNL, the AlGaN layer AGNL or the n-type GaN layer nGNL and the aluminum (Al) film ALF Adhesion is bad. In this case, when the laminated body LAB is subjected to heat treatment to form an ohmic electrode, a phenomenon (called a ball-up phenomenon) in which the aluminum (Al) film ALF swells due to surface tension occurs, and the AlGaN layer AGNL or the n-type GaN layer nGNL The problem is that the surface morphology at the interface with the aluminum (Al) film ALF is deteriorated. As a countermeasure, it is effective to insert a first molybdenum (Mo) film MF1 functioning as an adhesion film between the AlGaN layer AGNL or the n-type GaN layer nGNL and the aluminum (Al) film ALF. However, if the film thickness of the first molybdenum (Mo) film MF1 is too thick, the contact resistance (contact resistance) will increase. Therefore, from the viewpoint of achieving both the improvement of the surface morphology and the reduction of the contact resistance, the first molybdenum (Mo) film MF1 inserted between the AlGaN layer AGNL or the n-type GaN layer nGNL and the aluminum (Al) film ALF. It is necessary to devise the film thickness of

Therefore, in the first embodiment, the thickness of the first molybdenum (Mo) film MF1 inserted between the AlGaN layer AGNL or the n-type GaN layer nGNL and the aluminum (Al) film ALF is devised . Specifically, in the first embodiment, the thickness of the first molybdenum (Mo) film MF1 inserted between the AlGaN layer AGNL or the n-type GaN layer nGNL and the aluminum (Al) film ALF is set to X nm. In this case, the stacked body LAB is configured to satisfy the relationship of 2 nm ≦ X ≦ 10 nm. In the first embodiment, the laminated electrode LAB configured in this way is heat-treated at a high temperature of, for example, 650 ° C. to 850 ° C., to thereby form an ohmic electrode that achieves both improvement in surface morphology and reduction in contact resistance. It can be formed on the AlGaN layer AGNL or on the n-type GaN layer nGNL.

FIG. 15 shows the relationship between the film thickness of the first molybdenum (Mo) film and the contact resistance between the ohmic electrode and the semiconductor layer (hereinafter, the AlGaN layer and the n-type GaN layer are collectively referred to as the semiconductor layer). Is a graph showing In FIG. 15, the horizontal axis indicates the film thickness (nm) of the first molybdenum (Mo) film, and the vertical axis indicates the contact resistance (Ω mm) between the ohmic electrode and the semiconductor layer.

Here, the film thickness of the first molybdenum (Mo) film indicates the film thickness when forming the laminate before forming the ohmic electrode. Then, heat treatment is performed on this laminated body, whereby the atoms of the respective films constituting the laminated body mutually diffuse, whereby an ohmic electrode is formed. At this time, the contact resistance shown in FIG. 15 indicates the contact resistance between the ohmic electrode and the semiconductor layer. This contact resistance is measured using the usual TLM method (Transmission Line Method).

As shown in FIG. 15, when the thickness of the first molybdenum (Mo) film is between 0 nm and 2 nm, the contact resistance between the ohmic electrode and the semiconductor layer is reduced from 0.3 Ωmm to 0.2 Ωmm. I understand. When the thickness of the first molybdenum (Mo) film is 2 nm or more and 7 nm or less, the contact resistance is low. After that, it can be seen that the contact resistance between the ohmic electrode and the semiconductor layer increases as the thickness of the first molybdenum (Mo) film increases. In particular, when the thickness of the first molybdenum (Mo) film exceeds 10 nm, it can be seen that the contact resistance between the ohmic electrode and the semiconductor layer is significantly increased.

The mechanism showing such behavior can be considered as shown below. That is, first, when the first molybdenum (Mo) film is not formed, the contact resistance between the ohmic electrode and the semiconductor layer is large because the adhesion between the aluminum (Al) film and the semiconductor layer is bad. It is thought that it will become. Then, when the first molybdenum (Mo) film is formed, the adhesion between the aluminum (Al) film and the semiconductor layer is improved, and the contact resistance between the ohmic electrode and the semiconductor layer is reduced. It is considered that this phenomenon occurs when the film thickness of the first molybdenum (Mo) film is between 0 nm and 2 nm. Thereafter, as the thickness of the first molybdenum (Mo) film increases, the contact resistance between the ohmic electrode and the semiconductor layer increases. This phenomenon can be considered as follows. That is, when the stack is subjected to heat treatment to form an ohmic electrode, atoms are mutually diffused from each layer constituting the stack. At this time, for example, when the film thickness of the first molybdenum (Mo) film is small, the atomic percentage of aluminum atoms diffused from the aluminum (Al) film to the interface between the ohmic electrode and the semiconductor layer is the ohmic electrode and the semiconductor layer In most cases, it is considered to be larger than the atomic percent of the molybdenum atom present at the interface of In this case, as a result of the influence of the contact with the aluminum atoms becoming large, the contact between the semiconductor layer and the ohmic electrode becomes an ohmic contact, and it is considered that the contact resistance can be reduced.

On the other hand, when the film thickness of the first molybdenum (Mo) film is too large, atoms of aluminum atoms are formed at the interface between the ohmic electrode and the semiconductor layer, even when atoms interdiffuse from each layer constituting the laminate. It is considered that in many cases the% will be less than the atomic% of the molybdenum atom. In this case, the contact between the semiconductor layer and the ohmic electrode is largely affected by the contact with the molybdenum that constitutes the Schottky contact, and it is considered that an increase in contact resistance occurs.

In particular, it is considered from FIG. 15 that the contact resistance between the ohmic electrode and the semiconductor layer can be reduced if the thickness of the first molybdenum (Mo) film is 0 nm or more and 10 nm or less. Specifically, when the film thickness of the first molybdenum (Mo) film is 0 nm or more and 10 nm or less, the contact resistance between the ohmic electrode and the semiconductor layer can be 0.4 Ωmm or less. In this case, the atomic percent of aluminum atoms diffused from the aluminum (Al) film to the interface between the ohmic electrode and the semiconductor layer is often larger than the atomic percent of molybdenum atoms present on the surface of the semiconductor layer It is guessed.

Next, FIG. 16 is a graph showing the relationship between the film thickness of the first molybdenum (Mo) film and the surface roughness (RMS) at the interface between the ohmic electrode and the semiconductor layer. In FIG. 16, the horizontal axis indicates the film thickness (nm) of the first molybdenum (Mo) film, and the vertical axis indicates the surface roughness (μm) at the interface between the ohmic electrode and the semiconductor layer.

Here, the film thickness of the first molybdenum (Mo) film indicates the film thickness when forming the laminate before forming the ohmic electrode. Then, heat treatment is performed on this laminated body, whereby the atoms of the respective films constituting the laminated body mutually diffuse, whereby an ohmic electrode is formed. At this time, the surface roughness shown in FIG. 16 indicates the surface roughness at the interface between the ohmic electrode and the semiconductor layer. That is, in the first embodiment, surface roughness is used as an index of surface morphology. This surface roughness is evaluated by using, for example, a surface roughness meter, a laser microscope, or an atomic force microscope. In FIG. 16, the result of having evaluated surface roughness using the laser microscope is shown.

As shown in FIG. 16, when the film thickness of the first molybdenum (Mo) film is 0 nm (when the aluminum (Al) film is in direct contact with the semiconductor layer), the surface roughness is 0.3 μm. On the other hand, when the film thickness of the first molybdenum (Mo) film is 2 nm or more, the surface roughness is smaller than 0.1 μm. Therefore, as apparent from FIG. 16, when the film thickness of the first molybdenum (Mo) film is 0 nm (when the aluminum (Al) film is in direct contact with the semiconductor layer), the surface roughness is extremely deteriorated. However, it has been shown that if the film thickness of the first molybdenum (Mo) film is 2 nm or more, the surface roughness can be sufficiently improved. This is because the first molybdenum (Mo) film contributes to the improvement of the adhesion between the aluminum (Al) film and the semiconductor layer, and suppresses the ball-up phenomenon of the aluminum (Al) film due to the heat treatment. It is because it is thought that it is acting. In other words, when the first molybdenum (Mo) film is not formed, the adhesion between the aluminum (Al) film and the semiconductor layer is degraded, so the ball-up phenomenon of the aluminum (Al) film due to the heat treatment is It is considered to be remarkable because it causes a significant deterioration of the surface roughness.

From the above, from the viewpoint of reducing the contact resistance between the ohmic electrode and the semiconductor layer, as shown in FIG. 15, it is desirable that the film thickness of the first molybdenum (Mo) film is 0 nm or more and 10 nm or less . On the other hand, from the viewpoint of improving the surface morphology (surface roughness) at the interface between the ohmic electrode and the semiconductor layer, there is no problem if the thickness of the first molybdenum (Mo) film is 2 nm or more, as shown in FIG. . Therefore, in consideration of FIGS. 15 and 16, in the first embodiment, the thickness of the first molybdenum (Mo) film inserted between the aluminum (Al) film and the semiconductor layer is X nm. The laminate is configured to satisfy the relationship of 2 nm ≦ X ≦ 10 nm. In the first embodiment, the laminated body configured in this manner is heat-treated at a high temperature of, for example, 650 ° C. to 850 ° C., to thereby form an ohmic electrode that achieves both improvement in surface morphology and reduction in contact resistance. It can be formed on a layer.

As can be seen from FIG. 15, when 2 nm ≦ X ≦ 7 nm, the contact resistance is about 0.2 Ωmm, and an ohmic electrode with a very low contact resistance can be formed.

<Method of Manufacturing Ohmic Electrode in First Embodiment>
Subsequently, a method of manufacturing the ohmic electrode in the first embodiment will be described with reference to the drawings. First, as shown in FIG. 17, a substrate 1S is prepared. The substrate 1S is made of, for example, a sapphire substrate, a SiC (silicon carbide) substrate, or a silicon (Si) substrate. Then, a buffer layer BUF, which is an epitaxial layer, is formed on the substrate 1S by using, for example, metal organic chemical vapor deposition (MOCVD method: Metal Organic Chemical Vapor Deposition). The buffer layer BUF is formed, for example, for the purpose of relaxing a mismatch between the crystal lattice forming the substrate and the crystal lattice forming the GaN layer formed on the buffer layer BUF. Thereafter, a GaN layer GNL which is a non-doped epitaxial layer to which a conductive impurity is not added is formed on the buffer layer BUF, for example, by using the MOCVD method, and a conductive impurity is formed on the GaN layer GNL. An AlGaN layer AGNL which is a non-doped epitaxial layer not doped is formed.

In the above description, the example in which the substrate 1S is formed of a nitride semiconductor substrate is not shown, but the substrate 1S may be a nitride semiconductor substrate such as GaN or AlGaN. In this case, since the substrate 1S is lattice-matched with GaN, the buffer layer BUF can be thin or eliminated.

Next, as shown in FIG. 18, after forming a resist film FR1 on the AlGaN layer AGNL, the resist film FR1 is patterned by subjecting the resist film FR1 to exposure and development processing. The patterning of the resist film FR1 is performed such that the opening OP1 is formed in the ohmic electrode formation region.

Then, as shown in FIG. 19, a laminated film is formed on the substrate 1S (AlGaN layer AGNL) on which the patterned resist film FR1 is formed by using, for example, an electron beam evaporation method. Specifically, the laminated film is formed on the first molybdenum (Mo) film MF1, the aluminum (Al) film ALF formed on the first molybdenum (Mo) film MF1, and the aluminum (Al) film ALF. A second molybdenum (Mo) film MF2 and a gold (Au) film AUF formed on the second molybdenum (Mo) film MF2 are formed. Specifically, as shown in FIG. 19, the laminated film is formed in the opening OP1 formed in the resist film FR1 and on the resist film FR1. At this time, in the first embodiment, assuming that the film thickness of the first molybdenum (Mo) film MF1 inserted between the aluminum (Al) film ALF and the AlGaN layer AGNL is X nm, 2 nm ≦ X ≦ 10 nm The laminated film is configured to satisfy the following relationship. Then, for example, the film thicknesses of the films (the aluminum (Al) film ALF, the second molybdenum (Mo) film MF2, the gold (Au) film AUF) other than the first molybdenum (Mo) film MF1 are, in particular, the respective films It is not particularly limited as long as the function possessed is exhibited. For example, as an example, the thickness of the aluminum (Al) film ALF is 70 nm, the thickness of the second molybdenum (Mo) film MF2 is 30 nm, and the thickness of the gold (Au) film AUF is 50 nm. ing.

Subsequently, as shown in FIG. 20, the resist film FR1 is removed. When the resist film FR1 is removed, the laminated film formed on the resist film FR1 is also removed by lift-off. Therefore, after removing the resist film FR1, only the laminated film formed in the opening OP1 of the resist film FR1 remains, thereby forming the laminated body LAB made of the laminated film in the ohmic electrode formation region. Can.

Thereafter, as shown in FIG. 21, for example, heat treatment is performed for 1 minute to 10 minutes at a temperature of 650 ° C. to 850 ° C. in a nitrogen atmosphere on substrate 1S on which laminate LAB is formed. . This heat treatment can be performed by, for example, furnace annealing using RTA (Rapid Thermal Anneal) or a heat treatment furnace. The heat treatment described above is performed in a temperature range of 650 ° C. to 850 ° C., preferably in a temperature range of 700 ° C. to 800 ° C. At lower temperatures, the surface morphology tends to be better, while the contact resistance tends to increase, while at higher temperatures, the surface morphology tends to deteriorate while the contact resistance tends to decrease. For this reason, the temperature of the heat treatment described above is determined in consideration of the balance between the improvement of the surface morphology and the reduction of the contact resistance. For example, in the case where priority is given to improvement in surface morphology, it is carried out in a relatively low temperature region of the above-mentioned temperature range, while in the case where priority is given to reducing contact resistance, the above-mentioned temperature range is relatively relatively It is conceivable to carry out in a high temperature region.

By performing the heat treatment as described above, aluminum (Al), molybdenum (Mo) and gold (Au) constituting the respective films constituting the stacked body LAB mutually diffuse, and the ohmic electrode OE shown in FIG. It is formed. At this time, since the film thickness of the first molybdenum (Mo) film is small in the first embodiment at the interface between the ohmic electrode OE and the AlGaN layer AGNL, the ohmic electrode OE and the AlGaN layer AGNL are formed of an aluminum (Al) film. It is considered that the atomic percent of the aluminum atoms diffused to the interface with is larger than the atomic percent of the molybdenum atoms present at the interface between the ohmic electrode OE and the AlGaN layer AGNL in many cases. That is, the average amount (atomic%) of aluminum atoms at the interface between the ohmic electrode OE and the AlGaN layer AGNL is larger than the average amount (atomic%) of molybdenum atoms. At this time, as a result of the influence of the contact with the aluminum atoms becoming large, the contact between the AlGaN layer AGNL and the ohmic electrode OE becomes an ohmic contact, and the contact resistance can be reduced. That is, in the first embodiment, assuming that the thickness of the first molybdenum (Mo) film MF1 inserted between the aluminum (Al) film and the AlGaN layer AGNL is X nm, the relationship of 2 nm ≦ X ≦ 10 nm. The laminated body LAB is configured to satisfy Then, in the first embodiment, an ohmic electrode in which the improvement of surface morphology and the reduction of contact resistance are compatible by heat treating laminated body LAB configured in this manner at a high temperature of 650 ° C. to 850 ° C., for example. OE can be formed on the AlGaN layer AGNL.

Second Embodiment
In the first embodiment, attention is paid to the film thickness of the first molybdenum (Mo) film inserted between the semiconductor layer and the aluminum (Al) film to achieve both improvement in surface morphology and reduction in contact resistance. The technical idea of forming the ohmic electrode OE on the semiconductor layer has been described. In the second embodiment, attention is paid to the relationship between the film thickness of the aluminum (Al) film constituting the laminate and the film thickness of the gold (Au) film, to achieve both improvement in surface morphology and reduction in contact resistance. The technical idea of forming the ohmic electrode OE on the semiconductor layer will be described.

<Features of Embodiment 2>
As shown in FIG. 23, the stacked body LAB in the second embodiment is formed on the AlGaN layer AGNL formed on the GaN layer GNL. The stacked body LAB includes a first molybdenum (Mo) film MF1 formed on the AlGaN layer AGNL, an aluminum (Al) film ALF formed on the first molybdenum (Mo) film MF1, and an aluminum (Al) film. 2.) A second molybdenum (Mo) film MF2 formed on the film ALF, and a gold (Au) film AUF formed on the second molybdenum (Mo) film MF2.

Here, when the film thickness of the aluminum (Al) film ALF is Y (nm) and the film thickness of the gold (Au) film AUF is Z (nm), the feature of the second embodiment is Y ≦ Z ≦ The point is that the 2Y relationship is satisfied. That is, in the second embodiment, in order to achieve both of the improvement of the surface morphology and the reduction of the contact resistance, the film thickness of the aluminum (Al) film ALF is constant between the film thickness of the gold (Au) film AUF. It is found out that it is necessary to satisfy the correlation of (1), and the realization of this finding is the technical idea in the second embodiment. In the second embodiment, the laminated electrode LAB configured in this way is heat-treated at a high temperature of 650 ° C. to 850 ° C., for example, to form an ohmic electrode that achieves both improvement in surface morphology and reduction in contact resistance. It can be formed on layer AGNL.

Here, for example, in the second embodiment, the film thickness of the aluminum (Al) film ALF and the film thickness of the gold (Au) film AUF may be within the range of the aforementioned correlation, and further, the first molybdenum The thickness of the (Mo) film MF1 and the thickness of the second molybdenum (Mo) film MF2 are not particularly limited as long as the functions of the respective films are exhibited. For example, as an example, the film thickness of the first molybdenum (Mo) film MF1 is 7 nm, the film thickness of the aluminum (Al) film ALF is 50 nm to 75 nm, the film thickness of the second molybdenum (Mo) film MF2 is 30 nm to 50 nm, and gold The film thickness of the (Au) film AUF can be set to 75 nm to 150 nm.

Although FIG. 23 illustrates an example in which the stacked body LAB is formed on the AlGaN layer AGNL, for example, as shown in FIG. 24, the stacked body LAB is also formed on the n-type GaN layer nGNL. The technical idea in the second embodiment can be applied. Specifically, in the stacked body LAB formed on the n-type GaN layer nGNL, the film thickness of the aluminum (Al) film ALF is Y (nm), and the film thickness of the gold (Au) film AUF is Z (nm) In this case, the relationship of Y ≦ Z ≦ 2Y is satisfied. Then, the laminated body LAB is heat-treated at a high temperature of, for example, 650 ° C. to 850 ° C. to form an ohmic electrode on the n-type GaN layer nGNL in which the improvement of the surface morphology and the reduction of the contact resistance are compatible. it can.

Thus, in the second embodiment, assuming that the film thickness of the aluminum (Al) film ALF is Y (nm) and the film thickness of the gold (Au) film AUF is Z (nm), then Y ≦ Z ≦ 2Y. Although it is characterized in that the relationship is satisfied, it explains the qualitative reason for introducing the aforementioned correlation between the film thickness of the aluminum (Al) film ALF and the film thickness of the gold (Au) film AUF. Do.

For example, when the film thickness of the aluminum (Al) film ALF is sufficiently large relative to the film thickness of the gold (Au) film AUF, aluminum (Al) will be present in excess with respect to gold (Au). In this case, when heat treatment is performed on the laminate, aluminum (Al) present in excess causes local alloy reaction with molybdenum (Mo) or gold (Au). As a result, the surface morphology is locally deteriorated. That is, when aluminum (Ai) is present in excess relative to gold (Au), excess aluminum (Al) causes an extra alloy reaction with molybdenum (Mo) or gold (Au). And the surface morphology gets worse. Therefore, it is desirable that the amount of aluminum (Al) does not exist in excess from gold (Au) from the viewpoint of improving the surface morphology, and from this viewpoint, the thickness of the aluminum (Al) film ALF is Au) It is necessary to make the film thickness of the film AUF or less.

On the other hand, for example, when the film thickness of the gold (Au) film AUF is sufficiently larger than the film thickness of the aluminum (Al) film ALF, gold (Au) is present in excess to aluminum (Al). become. In this case, when the stack is heat-treated, excess gold (Au) is diffused to reach the interface between the stack and the semiconductor layer. At this time, when the amount of gold (Au) reaching the interface between the stack and the semiconductor layer increases, the ratio between the stack and the semiconductor layer is more than atomic% of aluminum (Al) diffused to the interface between the stack and the semiconductor layer. It is considered that the atomic percent of gold (Au) reaching the interface may increase. At this time, aluminum (Al) diffused to the interface between the stacked body and the semiconductor layer forms ohmic contact with the semiconductor layer, while gold (Au) diffused to the interface between the stacked body and the semiconductor layer Form a Schottky contact with the semiconductor layer. For this reason, when the atomic percent of gold (Au) reaching the interface between the stacked body and the semiconductor layer increases, the contact between the semiconductor layer and the ohmic electrode is affected by the contact with gold (Au) constituting the Schottky contact. The contact resistance is considered to increase. Therefore, from the viewpoint of reducing the contact resistance of the ohmic electrode, it is not desirable that gold (Au) be present in excess to aluminum (Al), and the thickness of the aluminum (Al) film ALF is It is necessary to prevent the film thickness of the (Au) film AUF from becoming too large. From this, in the second embodiment, it is obtained that it should be avoided to make the film thickness of the gold (Au) film AUF sufficiently larger than the film thickness of the aluminum (Al) film ALF.

From the above, in order to obtain an ohmic electrode in which the improvement of the surface morphology and the reduction of the contact resistance are compatible, an appropriate ratio of the film thickness of the aluminum (Al) film ALF to the film thickness of the gold (Au) film AUF It turns out that it is necessary to set to.

Subsequently, the reason why the above-described correlation is introduced between the film thickness of the aluminum (Al) film ALF and the film thickness of the gold (Au) film AUF will be described from a quantitative viewpoint.

FIG. 25 shows the film thickness ratio between the aluminum (Al) film and the gold (Au) film (hereinafter referred to as Au / Al film thickness ratio) (Au film thickness / Al film thickness), the ohmic electrode and the semiconductor layer Hereinafter, it is a graph which shows a relationship with a contact resistance with an AlGaN layer and an n-type GaN layer collectively called a semiconductor layer. In FIG. 25, the horizontal axis indicates the Au / Al film thickness ratio, and the vertical axis indicates the contact resistance (Ω mm) between the ohmic electrode and the semiconductor layer.

Here, the Au / Al film thickness ratio indicates the film thickness ratio when forming the laminate before forming the ohmic electrode. Then, heat treatment is performed on this laminated body, whereby the atoms of the respective films constituting the laminated body mutually diffuse, whereby an ohmic electrode is formed. At this time, the contact resistance shown in FIG. 25 indicates the contact resistance between the ohmic electrode and the semiconductor layer. This contact resistance is measured using the usual TLM method (Transmission Line Method).

As shown in FIG. 25, when the Au / Al film thickness ratio is in the range of 0.5 to 2.0, the contact resistance is 0.3 Ωmm or less, and it can be seen that the contact resistance can be sufficiently reduced. However, when the Au / Al film thickness ratio exceeds 2.0, it can be seen that the contact resistance rises sharply. This may be due to the following reasons. That is, that the Au / Al film thickness ratio exceeds 2.0 means that the film thickness of the gold (Au) film AUF becomes sufficiently larger than the film thickness of the aluminum (Al) film ALF, As a result, gold (Au) is present in excess to aluminum (Al). In this case, when the stack is heat-treated, excess gold (Au) is diffused to reach the interface between the stack and the semiconductor layer. At this time, when the amount of gold (Au) reaching the interface between the stack and the semiconductor layer increases, the ratio between the stack and the semiconductor layer is more than atomic% of aluminum (Al) diffused to the interface between the stack and the semiconductor layer. It is considered that the atomic percent of gold (Au) reaching the interface may increase. For this reason, when the atomic percent of gold (Au) reaching the interface between the stacked body and the semiconductor layer increases, the contact between the semiconductor layer and the ohmic electrode is affected by the contact with gold (Au) constituting the Schottky contact. It is believed that a sharp increase in contact resistance will occur. From this, it is understood that the Au / Al film thickness ratio is preferably in the range of 0.5 to 2.0 from the viewpoint of reducing the contact resistance of the ohmic electrode.

Next, FIG. 26 is a graph showing the relationship between the Au / Al film thickness ratio and the surface roughness (RMS) at the interface between the ohmic electrode and the semiconductor layer. In FIG. 26, the horizontal axis indicates the Au / Al film thickness ratio, and the vertical axis indicates the surface roughness (μm) at the interface between the ohmic electrode and the semiconductor layer.

Here, the Au / Al film thickness ratio indicates the film thickness when forming the laminate before forming the ohmic electrode. Then, heat treatment is performed on this laminated body, whereby the atoms of the respective films constituting the laminated body mutually diffuse, whereby an ohmic electrode is formed. At this time, the surface roughness shown in FIG. 26 indicates the surface roughness at the interface between the ohmic electrode and the semiconductor layer. That is, in the second embodiment, surface roughness is used as an index of surface morphology. This surface roughness is evaluated by using, for example, a surface roughness meter, a laser microscope, or an atomic force microscope. In FIG. 26, the result of having evaluated surface roughness using the laser microscope is shown.

As shown in FIG. 26, in the range where the Au / Al film thickness ratio is 1 or more, the surface roughness is 0.1 μm or less, and it can be seen that the surface morphology can be sufficiently improved. However, it can be seen that when the Au / Al film thickness ratio becomes smaller than 1, the surface roughness rapidly increases. That is, FIG. 26 shows that the surface morphology is rapidly deteriorated when the Au / Al film thickness ratio is smaller than 1. This may be due to the following reasons. That is, the fact that the Au / Al film thickness ratio is smaller than 1 means that the film thickness of the aluminum (Al) film becomes sufficiently larger than the film thickness of the gold (Au) film. Al) will be present in excess to gold (Au). In this case, it is considered that, when the laminate is subjected to heat treatment, aluminum (Al) present in excess causes local alloy reaction with molybdenum (Mo) or gold (Au), whereby surface morphology is locally It is thought that it gets worse. From this, it is understood that the Au / Al film thickness ratio is desirably in the range of 1 or more from the viewpoint of improving the surface morphology at the interface between the ohmic electrode and the semiconductor layer. More preferably, the Au / Al film thickness ratio is preferably 1.3 or more.

From the above, from the viewpoint of reducing the contact resistance between the ohmic electrode and the semiconductor layer, as shown in FIG. 25, it is desirable that the Au / Al film thickness ratio be in the range of 0.5 to 2 . On the other hand, from the viewpoint of improving the surface morphology (surface roughness) at the interface between the ohmic electrode and the semiconductor layer, as shown in FIG. 26, it is desirable that the Au / Al film thickness ratio be in the range of 1 or more. Therefore, in consideration of FIGS. 25 and 26, in the second embodiment, the Au / Al film thickness ratio is configured to be in the range of 1 to 2. In other words, assuming that the film thickness of the aluminum (Al) film is Y (nm) and the film thickness of the gold (Au) film is Z (nm), the relationship of Y ≦ Z ≦ 2Y is satisfied. . In the second embodiment, the laminated body thus configured is heat-treated at a high temperature of, for example, 650 ° C. to 850 ° C. to form an ohmic electrode that achieves both improvement in surface morphology and reduction in contact resistance. It can be formed on a layer. From FIG. 26, since the surface roughness can be further reduced if the Au / Al film thickness ratio is 1.3 or more, the film thickness Z of gold (Au) further satisfies 1.3 Y ≦ Z ≦ 2Y. Can be flat, which is preferable.

<Method of Manufacturing Ohmic Electrode in Second Embodiment>
Subsequently, a method of manufacturing the ohmic electrode in the second embodiment will be described with reference to the drawings. First, as in the first embodiment shown in FIG. 17, the substrate 1S is prepared. The substrate 1S is made of, for example, a sapphire substrate, a SiC (silicon carbide) substrate, a silicon (Si) substrate, or a GaN substrate. Then, a buffer layer BUF, which is an epitaxial layer, is formed on the substrate 1S by using, for example, metal organic chemical vapor deposition (MOCVD method: Metal Organic Chemical Vapor Deposition). The buffer layer BUF is formed, for example, for the purpose of relaxing a mismatch between the crystal lattice forming the substrate and the crystal lattice forming the GaN layer formed on the buffer layer BUF. Thereafter, a GaN layer GNL which is a non-doped epitaxial layer to which a conductive impurity is not added is formed on the buffer layer BUF, for example, by using the MOCVD method, and a conductive impurity is formed on the GaN layer GNL. An AlGaN layer AGNL which is a non-doped epitaxial layer not doped is formed.

Next, as in the first embodiment shown in FIG. 18, after forming a resist film FR1 on the AlGaN layer AGNL, the resist film FR1 is exposed and developed to form a resist film FR1. Pattern it. The patterning of the resist film FR1 is performed such that the opening OP1 is formed in the ohmic electrode formation region.

Then, as shown in FIG. 27, a laminated film is formed on the substrate 1S on which the patterned resist film FR1 is formed, for example, by using an electron beam evaporation method or the like. Specifically, the laminated film is formed on the first molybdenum (Mo) film MF1, the aluminum (Al) film ALF formed on the first molybdenum (Mo) film MF1, and the aluminum (Al) film ALF. A second molybdenum (Mo) film MF2 and a gold (Au) film AUF formed on the second molybdenum (Mo) film MF2 are formed. Specifically, as shown in FIG. 27, the laminated film is formed in the opening OP1 formed in the resist film FR1 and on the resist film FR1. At this time, in the second embodiment, for example, the film thickness of the first molybdenum (Mo) film MF1 is 7 nm. In addition, when the film thickness of the aluminum (Al) film ALF is Y (nm) and the film thickness of the gold (Au) film AUF is Z (nm), the respective relationships satisfy Y ≦ Z ≦ 2Y. The film thickness is adjusted. For example, the film thickness of the aluminum (Al) film ALF is set to 75 nm, and the film thickness of the gold (Au) film AUF is set to 120 nm. Further, the thickness of the second molybdenum (Mo) film MF2 is not particularly limited, but is, for example, in the range of 30 nm to 50 nm.

Subsequently, as shown in FIG. 28, the resist film FR1 is removed. When the resist film FR1 is removed, the laminated film formed on the resist film FR1 is also removed by lift-off. Therefore, after removing the resist film FR1, only the laminated film formed in the opening OP1 of the resist film FR1 remains, thereby forming the laminated body LAB made of the laminated film in the ohmic electrode formation region. Can.

Thereafter, as shown in FIG. 29, for example, heat treatment is performed for 1 minute to 10 minutes at a temperature of 650 ° C. to 850 ° C. in a nitrogen atmosphere on substrate 1S on which laminated body LAB is formed. . This heat treatment can be performed by, for example, furnace annealing using RTA (Rapid Thermal Anneal) or a heat treatment furnace. The heat treatment described above is performed in a temperature range of 650 ° C. to 850 ° C., preferably in a temperature range of 700 ° C. to 800 ° C. At lower temperatures, the surface morphology tends to be better, while the contact resistance tends to increase, while at higher temperatures, the surface morphology tends to deteriorate while the contact resistance tends to decrease. For this reason, the temperature of the heat treatment described above is determined in consideration of the balance between the improvement of the surface morphology and the reduction of the contact resistance. For example, in the case where priority is given to improvement in surface morphology, it is carried out in a relatively low temperature region of the above-mentioned temperature range, while in the case where priority is given to reducing contact resistance, the above-mentioned temperature range is relatively relatively It is conceivable to carry out in a high temperature region.

By performing the heat treatment as described above, aluminum (Al), molybdenum (Mo) and gold (Au) constituting the respective films constituting the stacked body LAB mutually diffuse, and the ohmic electrode OE shown in FIG. It is formed. At this time, in the second embodiment, the film thickness of the aluminum (Al) film ALF is Y (nm) and the film thickness of the gold (Au) film AUF is Z (A) at the interface between the ohmic electrode OE and the AlGaN layer AGNL. In the case of nm), the relationship of Y ≦ Z ≦ 2Y is satisfied. Therefore, the atomic percent of aluminum atoms diffused from the aluminum (Al) film to the interface between the ohmic electrode OE and the AlGaN layer AGNL is more than the atomic percent of gold atoms diffused from the aluminum (Al) film to the interface between the ohmic electrode OE and the AlGaN layer AGNL It is thought that there will be many cases of becoming larger. At this time, as a result of the influence of the contact with the aluminum atoms becoming large, the contact between the AlGaN layer AGNL and the ohmic electrode OE becomes an ohmic contact, and the contact resistance can be reduced. That is, in the second embodiment, the Au / Al film thickness ratio is configured to be in the range of 1 to 2. Then, in the second embodiment, ohmic electrode in which improvement of surface morphology and reduction of contact resistance are compatible by heat treating laminated body LAB configured in this way at a high temperature of, for example, 650 ° C. to 850 ° C. OE can be formed on the AlGaN layer AGNL.

In the second embodiment, assuming that the film thickness of aluminum (Al) film ALF is Y (nm) and the film thickness of gold (Au) film AUF is Z (nm), the relationship of Y ≦ Z ≦ 2Y is satisfied. Is characterized in that the laminate LAB is configured such that And, with this feature point, it is possible to provide the ohmic electrode OE in which the improvement of the surface morphology and the reduction of the contact resistance are compatible. Therefore, in the second embodiment, the thickness of the first molybdenum (Mo) film MF1 formed in the lowermost layer of the stacked body LAB is not particularly limited. However, also in the second embodiment, similarly to the first embodiment, when the film thickness of the first molybdenum (Mo) film MF1 is X nm, the stacked body LAB is satisfied so as to satisfy the relationship of 2 nm ≦ X ≦ 10 nm. Due to the synergetic effect of the features of the first embodiment and the features of the second embodiment, the surface morphology of the ohmic electrode OE can be further improved and the contact resistance can be reduced. In this case, at the interface between the ohmic electrode OE and the AlGaN layer AGNL, the atomic percent of aluminum atoms diffused from the aluminum (Al) film to the interface between the ohmic electrode OE and the AlGaN layer AGNL corresponds to the ohmic electrode OE and the AlGaN layer AGNL It is considered that the atomic ratio of the gold atom diffused to the interface of Si is often larger than the atomic percentage of the gold atom, and the atomic ratio of the gold atom larger than the atomic percentage of the molybdenum atom is large. That is, it is considered that, at the interface between the semiconductor layer and the ohmic electrode OE, the atomic% of aluminum among aluminum, molybdenum, and gold is most often increased.

Third Embodiment
<Configuration of High Electron Mobility Transistor>
In the third embodiment, an example in which the ohmic electrode OE described in the first embodiment or the second embodiment is used for a high electron mobility transistor (HEMT) will be described.

FIG. 31 is a cross-sectional view showing the device structure of the HEMT in the third embodiment. As shown in FIG. 31, for example, a buffer layer BUF consisting of a GaN layer is formed on a substrate 1S composed of a sapphire substrate, a SiC (silicon carbide) substrate, a silicon (Si) substrate, or a GaN substrate. . Then, the non-doped GaN layer GNL in which the conductive impurity is not introduced is formed on the buffer layer BUF, and the non-doped AlGaN layer AGNL in which the conductive impurity is not introduced is formed on the GaN layer GNL. It is done. That is, in the HEMT according to the third embodiment, a heterojunction composed of the GaN layer GNL and the AlGaN layer AGNL is formed on the substrate 1S.

Next, on the AlGaN layer AGNL, the source electrode SE and the drain electrode DE which are disposed apart from each other are formed. The source electrode SE and the drain electrode DE are formed of an ohmic electrode OE, and the ohmic electrode OE has the features described in the first embodiment and the second embodiment. Therefore, according to the HEMT in the third embodiment, since the ohmic electrode OE to which the technical idea of the present invention is applied is used for the source electrode SE or the drain electrode DE, the surface of the source electrode SE or the drain electrode DE It is possible to improve the morphology and reduce the contact resistance. Specifically, the source electrode SE and the drain electrode DE are formed of an ohmic electrode OE in which aluminum, molybdenum and gold interdiffuse, and in particular, at the interface between the ohmic electrode OE and the AlGaN layer AGNL, The atomic% is considered to be larger than the atomic% of the molybdenum atom or the atomic% of the gold atom in many cases.

The gate electrode GE is formed on the AlGaN layer AGNL between the source electrode SE and the drain electrode DE. The gate electrode GE is formed of a laminated film of a nickel film NIF and a gold film AUF2, and the contact between the gate electrode GE and the AlGaN layer AGNL is a Schottky contact. Further, in the HEMT according to the third embodiment, a surface protection film PRF made of, for example, a silicon nitride film is formed on the surface of the AlGaN layer AGNL.

<Operation of High Electron Mobility Transistor>
The HEMT in the third embodiment is configured as described above, and the operation thereof will be described below. In particular, in the third embodiment, the operation will be described by taking a normally-on type HEMT as an example.

FIG. 32 is a diagram showing a band structure in the case where the negative voltage lower than the threshold voltage is applied to the gate electrode and the HEMT is turned off. The band structure of the metal constituting the gate electrode is shown on the left side of FIG. 32, and the band structure of the AlGaN layer is shown in the center of FIG. The band structure of the GaN layer is shown on the right side of FIG. Here, since a negative voltage is applied to the gate electrode with respect to the GaN layer, the Fermi level ε _FM of the gate electrode (metal) corresponds to the voltage applied from the Fermi level ε _FS2 of the GaN layer. Get higher. The conduction band of the AlGaN layer at the interface with the gate electrode is increased by a predetermined Schottky barrier height _{B B} , and there is a predetermined conduction band discontinuity ΔE _c at the interface between the AlGaN layer and the GaN layer. As the Fermi level ε _{FM of the} electrode increases, the conduction band is pulled and raised. As a result, since a two-dimensional electron gas is not formed at the interface between the AlGaN layer and the GaN layer, a channel for electrically connecting the source electrode SE and the drain electrode DE is not formed. As a result, the HEMT according to the third embodiment is turned off when a negative voltage equal to or lower than the threshold voltage is applied to the gate electrode. Incidentally, the energy difference of the conduction band of the conduction band and the GaN layer of the AlGaN layer, a predetermined conduction band discontinuity Delta] E _c between the conduction band of the conduction band and the GaN layer of the AlGaN layer is formed.

Subsequently, FIG. 33 is a diagram showing a band structure when the voltage of 0 V is applied to the gate electrode and the HEMT is turned on. The left side of FIG. 33 shows the band structure of the metal constituting the gate electrode, and the middle part of FIG. 33 shows the band structure of the AlGaN layer. The band structure of the GaN layer is shown on the right side of FIG. Here, since 0 V is applied to the gate electrode, the Fermi level ε _FM of the metal constituting the gate electrode and the Fermi level ε _FS2 of the GaN layer become equal. At this time, at a position lower than the Fermi level at the interface between the AlGaN layer and the GaN layer due to the conduction band discontinuity ΔE _c formed between the conduction band of the AlGaN layer and the conduction band of the GaN layer. A well potential is formed. As a result, electrons are accumulated in the well potential and a two-dimensional electron gas is formed. Thereby, when a voltage of 0 V is applied to the gate electrode, a two-dimensional electron gas is formed at the interface between the AlGaN layer and the GaN layer, and a channel for electrically connecting the source electrode SE and the drain electrode DE is formed. It will be As a result, the HEMT in the third embodiment is turned on when a voltage of 0 V is applied to the gate electrode. As described above, in the HEMT according to the third embodiment, it is understood that the on / off operation of the HEMT can be realized by controlling the voltage applied to the gate electrode.

<Method of Manufacturing High Mobility Transistor>
Next, a method of manufacturing the HEMT according to the third embodiment will be described. First, as shown in FIG. 34, a substrate 1S is prepared. The substrate 1S is made of, for example, a sapphire substrate, a SiC (silicon carbide) substrate, or a silicon (Si) substrate. Then, a buffer layer BUF, which is an epitaxial layer, is formed on the substrate 1S by using, for example, metal organic chemical vapor deposition (MOCVD method: Metal Organic Chemical Vapor Deposition). The buffer layer BUF is formed, for example, for the purpose of relaxing a mismatch between the crystal lattice forming the substrate and the crystal lattice forming the GaN layer formed on the buffer layer BUF. Thereafter, a GaN layer GNL which is a non-doped epitaxial layer to which a conductive impurity is not added is formed on the buffer layer BUF, for example, by using the MOCVD method, and a conductive impurity is formed on the GaN layer GNL. An AlGaN layer AGNL which is a non-doped epitaxial layer not doped is formed.

Next, as shown in FIG. 35, after forming a resist film FR2 over the AlGaN layer AGNL, the resist film FR2 is patterned by subjecting the resist film FR2 to exposure and development processing. The patterning of the resist film FR2 is performed such that an opening OP2 is formed in the source electrode formation region and the drain electrode formation region.

Then, as shown in FIG. 36, a laminated film is formed on the substrate 1S on which the patterned resist film FR2 is formed by using, for example, an electron beam evaporation method. Specifically, the laminated film is formed on the first molybdenum (Mo) film MF1, the aluminum (Al) film ALF formed on the first molybdenum (Mo) film MF1, and the aluminum (Al) film ALF. A second molybdenum (Mo) film MF2 and a gold (Au) film AUF formed on the second molybdenum (Mo) film MF2 are formed. Specifically, as shown in FIG. 36, the laminated film is formed in the opening OP2 formed in the resist film FR2 and on the resist film FR2. At this time, in the third embodiment, for example, 2 nm ≦ X where the film thickness of the first molybdenum (Mo) film MF1 inserted between the aluminum (Al) film ALF and the AlGaN layer AGNL is X nm. The first molybdenum (Mo) film MF1 is formed to satisfy the relationship of ≦ 10 nm. In addition, when the film thickness of the aluminum (Al) film ALF is Y (nm) and the film thickness of the gold (Au) film AUF is Z (nm), the respective relationships satisfy Y ≦ Z ≦ 2Y. The film thickness is adjusted.

Subsequently, as shown in FIG. 37, the resist film FR2 is removed. When the resist film FR2 is removed, the laminated film formed on the resist film FR2 is also removed by lift-off. Therefore, after removing the resist film FR2, only the laminated film formed in the opening OP2 of the resist film FR2 remains, thereby forming the laminated body LAB1 made of the laminated film in the drain electrode formation region. As a result, the stacked body LAB2 made of a stacked film can be formed in the source electrode formation region.

Thereafter, for example, heat treatment is performed for 1 minute to 10 minutes at a temperature of 650 ° C. to 850 ° C. in a nitrogen atmosphere on the substrate 1S on which the laminate LAB is formed. This heat treatment can be performed by, for example, furnace annealing using RTA (Rapid Thermal Anneal) or a heat treatment furnace. The heat treatment described above is performed in a temperature range of 650 ° C. to 850 ° C., preferably in a temperature range of 700 ° C. to 800 ° C. At lower temperatures, the surface morphology tends to be better, while the contact resistance tends to increase, while at higher temperatures, the surface morphology tends to deteriorate while the contact resistance tends to decrease. For this reason, the temperature of the heat treatment described above is determined in consideration of the balance between the improvement of the surface morphology and the reduction of the contact resistance. For example, in the case where priority is given to improvement in surface morphology, it is carried out in a relatively low temperature region of the above-mentioned temperature range, while in the case where priority is given to reducing contact resistance, the above-mentioned temperature range is relatively relatively It is conceivable to carry out in a high temperature region.

By performing the heat treatment as described above, aluminum (Al), molybdenum (Mo) and gold (Au) constituting the respective films constituting the stacked body LAB mutually diffuse, and the ohmic electrode OE shown in FIG. It is formed. That is, the source electrode SE and the drain electrode DE configured of the ohmic electrode OE can be formed. At this time, in the third embodiment, the film thickness of the aluminum (Al) film ALF is Y (nm) and the film thickness of the gold (Au) film AUF is Z (A) at the interface between the ohmic electrode OE and the AlGaN layer AGNL. In the case of nm), the relationship of Y ≦ Z ≦ 2Y is satisfied. Therefore, the atomic percent of aluminum atoms diffused from the aluminum (Al) film to the interface between the ohmic electrode OE and the AlGaN layer AGNL is more than the atomic percent of gold atoms diffused from the aluminum (Al) film to the interface between the ohmic electrode OE and the AlGaN layer AGNL It is thought that there will be many cases of becoming larger. At this time, as a result of the influence of the contact with the aluminum atoms becoming large, the contact between the AlGaN layer AGNL and the ohmic electrode OE becomes an ohmic contact, and the contact resistance can be reduced. That is, in the third embodiment, the Au / Al film thickness ratio is configured to be in the range of 1 to 2. Then, in the third embodiment, the stacked body LAB configured as described above is heat-treated at a high temperature of, for example, 650 ° C. to 850 ° C., thereby achieving a source electrode having both improvement in surface morphology and reduction in contact resistance. SE (ohmic electrode OE) and drain electrode DE (ohmic electrode OE) can be formed on the AlGaN layer AGNL.

In the third embodiment, when the film thickness of the first molybdenum (Mo) film MF1 is X nm, the stacked body LAB is configured to satisfy the relationship of 2 nm ≦ X ≦ 10 nm. Thus, in the third embodiment, the surface morphology of the source electrode SE and the drain electrode DE is further improved and the contact resistance is reduced by the synergistic effect of the features of the first embodiment and the features of the second embodiment. Can be In this case, at the interface between the ohmic electrode OE (the source electrode SE and the drain electrode DE) and the AlGaN layer AGNL, atomic% of aluminum atoms diffused from the aluminum (Al) film to the interface between the ohmic electrode OE and the AlGaN layer AGNL is It is considered that the atomic ratio of gold atoms diffused to the interface between the ohmic electrode OE and the AlGaN layer AGNL increases in many cases, and the atomic ratio of molybdenum atoms increases in many cases. That is, it is considered that, at the interface between the semiconductor layer and the ohmic electrode OE, the atomic% of aluminum among aluminum, molybdenum, and gold is most often increased.

Next, as shown in FIG. 39, a surface protection film PRF made of, for example, a silicon nitride film is formed on the surface of the AlGaN layer AGNL. Thereafter, as shown in FIG. 40, a resist film FR3 is coated on the substrate 1S, and the resist film FR3 is exposed and developed to be patterned. The patterning of the resist film FR3 is performed so as to cover the element formation region with the resist film FR3 and to open the insulation formation region between the element formation regions. Then, for example, boron (boron), nitrogen, or helium is introduced by an ion implantation method using the patterned resist film FR3 as a mask to form an insulating region.

Subsequently, as shown in FIG. 41, after removing the patterned resist film FR3, a new resist film FR4 is coated on the substrate 1S. Then, the resist film FR4 is exposed and developed to perform patterning. The patterning of the resist film FR4 is performed to form an opening OP3 in the gate electrode formation region. Thereafter, the surface protective film PRF exposed from the opening OP3 is removed by etching using the patterned resist film FR4 as a mask. As a result, the AlGaN layer AGNL is exposed at the bottom of the opening OP3.

Next, as shown in FIG. 42, for example, a laminated film is formed on the substrate 1S on which the patterned resist film FR4 is formed by using an electron beam evaporation method or the like. Specifically, the laminated film is composed of a nickel film NIF and a gold film AUF2. As shown in FIG. 42, the laminated film is formed in the opening OP3 formed in the resist film FR4 and on the resist film FR4.

Subsequently, the resist film FR4 is removed. When removing the resist film FR4, the laminated film formed on the resist film FR4 is also removed by lift-off. Therefore, after the resist film FR4 is removed, only the laminated film formed in the opening OP3 of the resist film FR4 remains, whereby the gate electrode GE formed of the nickel film NIF and the gold film AUF shown in FIG. It can be formed. As described above, the HEMT according to the third embodiment can be manufactured.

Embodiment 4
<Configuration of Field Effect Transistor>
In the fourth embodiment, an example in which the ohmic electrode OE described in the first embodiment and the second embodiment is used for an insulated gate field effect transistor (MISFET (Metal Insulator Semiconductor Field Effect Transistor)) will be described.

FIG. 43 is a cross-sectional view showing the device structure of the MISFET in the fourth embodiment. As shown in FIG. 43, for example, a buffer layer BUF consisting of a GaN layer is formed on a substrate 1S composed of a sapphire substrate, a SiC (silicon carbide) substrate, a GaN substrate, or a silicon (Si) substrate. . Then, over the buffer layer BUF, an n-type GaN layer nGNL into which an n-type impurity is introduced is formed.

Next, on the n-type GaN layer nGNL, the source electrode SE and the drain electrode DE which are disposed apart from each other are formed. The source electrode SE and the drain electrode DE are formed of an ohmic electrode OE, and the ohmic electrode OE has the features described in the first embodiment and the second embodiment. Therefore, according to the MISFET in the fourth embodiment, since the ohmic electrode OE to which the technical idea of the present invention is applied is used for the source electrode SE or the drain electrode DE, the surface of the source electrode SE or the drain electrode DE It is possible to improve the morphology and reduce the contact resistance. Specifically, the source electrode SE and the drain electrode DE are formed of an ohmic electrode OE in which aluminum, molybdenum and gold interdiffuse, and in particular, at the interface between the ohmic electrode OE and the n-type GaN layer nGNL, aluminum The atomic% of atoms is considered to be larger than the atomic% of molybdenum atoms or the atomic% of gold atoms in many cases.

Then, over the n-type GaN layer nGNL between the source electrode SE and the drain electrode DE, the gate electrode GE is formed via the gate insulating film GOX. The gate insulating film GOX is formed of, for example, an aluminum oxide film or a silicon oxide film. The gate electrode GE is formed of a polysilicon film or a metal film. Further, in the MISFET in the fourth embodiment, a surface protection film PRF made of, for example, a silicon nitride film is formed on the surface of the n-type GaN layer nGNL.

<Operation of Field Effect Transistor>
The MISFET in the fourth embodiment is configured as described above, and the operation thereof will be described below. In particular, in the fourth embodiment, the operation of the normally-on type MISFET will be described as an example.

FIG. 44 is a schematic view showing a state in which the MISFET is turned off when a negative voltage lower than the threshold voltage is applied to the gate electrode GE. As shown in FIG. 44, when a negative voltage is applied to the gate electrode GE, the depletion layer DPL formed in the n-type GaN layer nGNL immediately below the gate electrode GE extends. As a result, depletion layer DPL reaches the bottom of n-type GaN layer nGNL. Since this depletion layer DPL functions as an insulating region, the electrical connection between the source electrode SE and the drain electrode DE is interrupted by the depletion layer DPL. Therefore, when a negative voltage lower than the threshold voltage is applied to the gate electrode GE, the MISFET turns off.

Subsequently, FIG. 45 is a schematic view showing a state in which a voltage of 0 V is applied to the gate electrode and the MISFET is turned on. As shown in FIG. 45, when 0 V is applied to the gate electrode GE, the depletion layer DPL does not extend more than when a negative voltage is applied to the gate electrode GE, as shown in FIG. A channel consisting of the n-type GaN layer nGNL is formed in Thereby, the source electrode SE and the drain electrode DE are electrically connected. That is, electrons flow from the source electrode SE toward the drain electrode DE. In other words, a current flows from the drain electrode DE toward the source electrode SE. Therefore, when 0 V is applied to the gate electrode GE, the MISFET is turned on. As described above, in the MISFET according to the fourth embodiment, it is understood that the on / off operation of the MISFET can be realized by controlling the voltage applied to the gate electrode GE.

Fifth Embodiment
<Configuration of blue light emitting diode>
In the fifth embodiment, an example in which the ohmic electrode OE described in the first embodiment or the second embodiment is used for a blue light emitting diode will be described.

FIG. 46 is a cross sectional view showing a device structure of a blue light emitting diode in the fifth embodiment. As shown in FIG. 46, for example, a buffer layer BUF made of a GaN layer is formed on a sapphire substrate SS, and an n-type GaN layer nGNL is formed on the buffer layer BUF. An n-type ohmic electrode OE (n) is formed on the n-type GaN layer nGNL in ohmic contact with the n-type GaN layer nGNL. Further, an n-type AlGaN layer nAGNL is formed in another region on the n-type GaN layer nGNL, and an InGaN layer IGNL doped with zinc (Zn) is formed on the n-type AlGaN layer nAGNL. Then, a p-type AlGaN layer pAGNL is formed on the InGaN layer IGNL, and a p-type GaN layer pGNL is formed on the p-type AlGaN layer pAGNL. Furthermore, on the p-type GaN layer pGNL, a p-type ohmic electrode OE (p) is formed in ohmic contact with the p-type GaN layer pGNL.

The blue light emitting diode having the above-described configuration has a configuration in which a double hetero structure including the p-type GaN layer pGNL and the n-type GaN layer nGNL and the p-type AlGaN layer pAGNL / InGaN layer IGNL / n-type AlGaN layer nAGNL is sandwiched. It is a blue light emitting diode with extremely high brightness.

Here, the n-type ohmic electrode OE (n) has the features described in the first embodiment and the second embodiment. Therefore, according to the blue light emitting diode in the fifth embodiment, since the n-type ohmic electrode OE (n) to which the technical idea of the present invention is applied is used, the surface of the n-type ohmic electrode OE (n) It is possible to improve the morphology and reduce the contact resistance. Specifically, n-type ohmic electrode OE (n) is formed of an electrode in which aluminum, molybdenum and gold interdiffuse, and in particular, at the interface between ohmic electrode OE (n) and n-type GaN layer nGNL The atomic percent of the aluminum atom is considered to be larger than the atomic percent of the molybdenum atom or the atomic percent of the gold atom in many cases.

<Operation of blue light emitting diode>
The blue light emitting diode in the fifth embodiment is configured as described above, and the operation thereof will be described below.

FIG. 47 is a diagram showing a band structure of the double hetero structure when the blue light emitting diode is off. In FIG. 47, the structure in which the InGaN layer is sandwiched between the p-type AlGaN layer and the n-type AlGaN layer from both sides is a double hetero structure. As shown in FIG. 47, when the blue light emitting diode is off, the Fermi levels of the respective layers coincide with each other.

Next, FIG. 48 is a diagram showing a band structure of the double hetero structure when the blue light emitting diode is on. As shown in FIG. 48, forward voltage (a positive voltage is applied to the p-type AlGaN layer and a negative voltage is applied to the n-type AlGaN layer) is applied to the blue light emitting diode. Then, electrons are injected at high density from the large band gap n-type AlGaN layer to the small band gap InGaN layer. Similarly, holes are injected at high density from the large band gap p-type AlGaN layer to the small band gap InGaN layer. As a result, in the InGaN layer, the density of electrons and holes is much higher than the density in the thermal equilibrium state, and the probability of recombination is increased. Then, in the InGaN layer, the electrons present in the conduction band and the holes present in the valence band recombine to emit light (hv) having energy corresponding to the band gap. As described above, the blue light emitting diode in the fifth embodiment operates.

As mentioned above, although the invention made by the present inventor was concretely explained based on the embodiment, the present invention is not limited to the embodiment, and can be variously changed in the range which does not deviate from the summary. Needless to say.

In the embodiment, an example in which the technical idea of the present invention is applied to an ohmic electrode in ohmic contact with a nitride semiconductor is described, and in particular, a nitride semiconductor containing gallium is described as an example of the nitride semiconductor. ing. And although AlGaN and GaN were mentioned as an example and explained as a concrete example of a nitride semiconductor containing gallium, a technical idea of the present invention is not limited to this, for example, nitride semiconductors such as InGaN and AlInGaN. It can be widely applied to ohmic electrodes in ohmic contact with

The present invention can be widely used in the manufacturing industry that manufactures semiconductor devices.

1S substrate AGNL AlGaN layer ALF aluminum film AUF gold film AUF2 gold film BUF buffer layer DE drain electrode DPL depletion layer E _c conduction band E _v valence band FR1 resist film FR2 resist film FR3 resist film FR4 resist film GE gate electrode GNL GaN layer GOX gate insulating film HMF refractory metal film IGNL InGaN layer LAB laminated body LAB1 laminated body LAB2 laminated body MF1 first molybdenum film MF2 second molybdenum film nAGNL n-type AlGaN layer nGNL n-type GaN layer NIF nickel film OE ohmic electrode OE (n ) N-type ohmic electrode OE (p) p-type ohmic electrode OP1 opening OP2 opening OP3 opening pAGNL p-type AlGaN layer pGNL p-type GaN layer PRF surface protection film SE source electrode S sapphire substrate TAF alloy film ε _FM Fermi level ε _FS Fermi level ε _FS2 Fermi level Φ _m work function Φ _s work function

Claims

(A) forming a laminate on the nitride semiconductor layer;
(B) forming an electrode by performing heat treatment on the laminate after the step (a);
The laminate is
A first molybdenum film formed on the nitride semiconductor layer;
An aluminum film formed on the first molybdenum film;
A second molybdenum film formed on the aluminum film;
A gold film formed on the second molybdenum film;
A method of manufacturing a semiconductor device satisfying the relationship of 2 nm ≦ X ≦ 10 nm, where X is a thickness of the first molybdenum film.
The method of manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device satisfying the relationship of Y ≦ Z ≦ 2Y, where Y is a film thickness of the aluminum film and Z is a film thickness of the gold film.
The method of manufacturing a semiconductor device according to claim 1,
In the step (a),
(A1) forming a resist film having an opening on the nitride semiconductor layer;
(A2) forming the first molybdenum film on the resist film including the inside of the opening;
(A3) forming the aluminum film on the first molybdenum film;
(A4) forming a second molybdenum film on the aluminum film;
(A5) forming a gold film on the second molybdenum film;
(A6) After the step (a5), the resist film is removed to lift off the first molybdenum film, the aluminum film, the second molybdenum film, and the gold film formed on the resist film. And a step of forming the stacked body.
The method of manufacturing a semiconductor device according to claim 1,
The method further includes the step of forming the nitride semiconductor layer on a substrate before the step (a),
The method of manufacturing a semiconductor device, wherein the substrate is formed of any of a sapphire substrate, a silicon carbide substrate, or a silicon substrate.
The method of manufacturing a semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the nitride semiconductor layer is a nitride semiconductor layer containing gallium.
The method of manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the nitride semiconductor layer is a GaN layer or an AlGaN layer.
The method of manufacturing a semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the temperature of the heat treatment performed in the step (b) is 650 ° C. or more and 850 ° C. or less.
8. A method of manufacturing a semiconductor device according to claim 7, wherein
A method of manufacturing a semiconductor device, wherein the temperature of the heat treatment performed in the step (b) is 700 ° C. or more and 800 ° C. or less.
A method of manufacturing a semiconductor device according to any one of claims 1 to 8, wherein
A method of manufacturing a semiconductor device, wherein the electrode is in ohmic contact with the nitride semiconductor layer by performing the heat treatment.
(A) forming a laminate on the nitride semiconductor layer;
(B) forming an electrode by performing heat treatment on the laminate after the step (a);
The laminate is
A first molybdenum film formed on the nitride semiconductor layer;
An aluminum film formed on the first molybdenum film;
A second molybdenum film formed on the aluminum film;
A gold film formed on the second molybdenum film;
A method of manufacturing a semiconductor device satisfying the relationship of Y ≦ Z ≦ 2Y, where Y is a film thickness of the aluminum film and Z is a film thickness of the gold film.
A method of manufacturing a semiconductor device according to claim 10, wherein
In the step (a),
(A1) forming a resist film having an opening on the nitride semiconductor layer;
(A2) forming the first molybdenum film on the resist film including the inside of the opening;
(A3) forming the aluminum film on the first molybdenum film;
(A4) forming a second molybdenum film on the aluminum film;
(A5) forming a gold film on the second molybdenum film;
(A6) After the step (a5), the resist film is removed to lift off the first molybdenum film, the aluminum film, the second molybdenum film, and the gold film formed on the resist film. And a step of forming the stacked body.
A method of manufacturing a semiconductor device according to claim 10, wherein
Before the step (c), the method further includes the step of forming a nitride semiconductor layer on the substrate,
The method of manufacturing a semiconductor device, wherein the substrate is formed of any of a sapphire substrate, a silicon carbide substrate, or a silicon substrate.
A method of manufacturing a semiconductor device according to claim 10, wherein
The method of manufacturing a semiconductor device, wherein the nitride semiconductor layer is a nitride semiconductor layer containing gallium.
A method of manufacturing a semiconductor device according to claim 10, wherein
The method for manufacturing a semiconductor device, wherein the nitride semiconductor layer is a GaN layer or an AlGaN layer.
A method of manufacturing a semiconductor device according to claim 10, wherein
A method of manufacturing a semiconductor device, wherein the temperature of the heat treatment performed in the step (b) is 650 ° C. or more and 850 ° C. or less.
16. The method of manufacturing a semiconductor device according to claim 15.
A method of manufacturing a semiconductor device, wherein the temperature of the heat treatment performed in the step (b) is 700 ° C. or more and 800 ° C. or less.
(A) a nitride semiconductor layer,
(B) An electrode formed on the nitride semiconductor layer and having a structure in which aluminum, molybdenum and gold interdiffuse.
The electrode is formed by performing a heat treatment on the laminate formed on the nitride semiconductor layer,
The laminate is
(C1) a first molybdenum film formed on the nitride semiconductor layer;
(C2) an aluminum film formed on the first molybdenum film;
(C3) a second molybdenum film formed on the aluminum film;
(C4) a gold film formed on the second molybdenum film,
A semiconductor device satisfying the relationship of 2 nm ≦ X ≦ 10 nm, where X is a thickness of the first molybdenum film.
The semiconductor device according to claim 17, wherein
A semiconductor device satisfying the relationship of Y ≦ Z ≦ 2Y, where Y is a film thickness of the aluminum film and Z is a film thickness of the gold film.
(A) a nitride semiconductor layer,
(B) An electrode formed on the nitride semiconductor layer and having a structure in which aluminum, molybdenum and gold interdiffuse.
The electrode is formed by performing a heat treatment on the laminate formed on the nitride semiconductor layer,
The laminate is
(C1) a first molybdenum film formed on the nitride semiconductor layer;
(C2) an aluminum film formed on the first molybdenum film;
(C3) a second molybdenum film formed on the aluminum film;
(C4) a gold film formed on the second molybdenum film,
A semiconductor device satisfying the relationship of Y ≦ Z ≦ 2Y, where Y is a film thickness of the aluminum film and Z is a film thickness of the gold film.
The semiconductor device according to any one of claims 17 to 19, wherein
The semiconductor device in which the electrode is in ohmic contact with the nitride semiconductor layer.
(A) a nitride semiconductor layer,
(B) An ohmic electrode formed on the nitride semiconductor layer, having a structure in which aluminum, molybdenum, and gold are mutually diffused, and in ohmic contact with the nitride semiconductor layer, Equipped with
The semiconductor device, wherein the atomic percent of the aluminum is larger than the atomic percent of the molybdenum at the interface between the nitride semiconductor layer and the ohmic electrode.
22. The semiconductor device according to claim 21, wherein
The semiconductor device having the largest atomic% of aluminum among aluminum, molybdenum, and gold at the interface between the nitride semiconductor layer and the ohmic electrode.
(A) a nitride semiconductor layer,
(B) An ohmic electrode formed on the nitride semiconductor layer, having a structure in which aluminum, molybdenum, and gold are mutually diffused, and in ohmic contact with the nitride semiconductor layer, Equipped with
The semiconductor device, wherein the atomic percent of the aluminum is larger than the atomic percent of the gold at the interface between the nitride semiconductor layer and the ohmic electrode.