WO2013044566A1 - 一种芯片的封装方法及其封装结构 - Google Patents

一种芯片的封装方法及其封装结构 Download PDF

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Publication number
WO2013044566A1
WO2013044566A1 PCT/CN2011/084993 CN2011084993W WO2013044566A1 WO 2013044566 A1 WO2013044566 A1 WO 2013044566A1 CN 2011084993 W CN2011084993 W CN 2011084993W WO 2013044566 A1 WO2013044566 A1 WO 2013044566A1
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Prior art keywords
substrate
chip
lead frame
package
chip lead
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PCT/CN2011/084993
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English (en)
French (fr)
Inventor
濮必得
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山东华芯半导体有限公司
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Publication of WO2013044566A1 publication Critical patent/WO2013044566A1/zh

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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Definitions

  • Chip packaging method and package structure thereof are Chip packaging method and package structure thereof
  • the invention belongs to the field of electronic components, and relates to a chip packaging method, in particular to a high reliability, high density chip packaging method and a package structure thereof, which can be applied to any computer, notebook, workstation and other semiconductors.
  • a chip packaging method in particular to a high reliability, high density chip packaging method and a package structure thereof, which can be applied to any computer, notebook, workstation and other semiconductors.
  • high-density packaging of memory or other semiconductor chips can be realized, that is, smaller pins, better stability, and better thermal performance.
  • Today's computer systems use a separate chip package, a single semiconductor chip package or a so-called multi-chip package.
  • Today's multi-chip packages use one of two methods: 1) The semiconductor chips are mounted on a shared substrate, and they do not overlap in the vertical direction, which is relative to a conventional PCB board (printed circuit board). A layout of the printed circuit board; 2) The semiconductor chips are stacked one on another, soldered or placed on the application board with respect to the entire horizontal area of the package. In this case, usually four chips are placed in the vertical direction.
  • the layout based on 2) has similar disadvantages. Although the pin area is small, the package is easily deformed and distorted, and the stacking and adhesion stability of the multilayer is worse.
  • the pads are connected to the outside of a single chip and are used for bonding connections. Because the middle chip is isolated and connected with very small leads, it does not have good thermal conductivity, so its temperature performance will be poor (see Figure 2).
  • the present invention provides a chip packaging method and a package structure thereof that can avoid package deformation, high package stability, good electrical performance, and wide application range.
  • a chip packaging method includes the following steps:
  • step 2) 1) mounting the chip on a separate chip lead frame or substrate; 2) Connect one side of the chip lead frame or substrate obtained in step 1) to the external package substrate.
  • the chip lead frame or substrate is used as a external package pin by passing through a metal pin disposed on the chip lead frame or the substrate through a pin hole provided in the package substrate.
  • step 2) is:
  • the chip lead frame or substrate is connected to the solder balls of the external package substrate by wires.
  • the above chip lead frame or substrate is one or more.
  • the lead frame or the substrate is vertically connected to the plane of the external package substrate.
  • the chip lead frame or the substrate is plural, the plurality of lead frames or the substrates are disposed in parallel with each other. Compound filling is performed between the lead frame or the substrate.
  • a package structure of a chip which is special in: a package structure of the chip includes a chip, a chip lead frame or a substrate, and an outer package substrate; the chip is mounted on a chip lead frame or a substrate; the chip lead frame or One side of the substrate is connected to the external package substrate.
  • the chip lead frame or substrate and the outer package substrate are connected by a rounded end or a non-circular end.
  • the metal pin disposed on the chip lead frame or the substrate passes through the pin hole of the package substrate and is directly used as an external package pin.
  • the round end is connected to the solder ball of the external package substrate through a wire on the package substrate.
  • the chip lead frame or the substrate is vertically connected to the external package substrate; the chip lead frame or the substrate is one or more, and when the chip lead frame or the substrate is plural, between the plurality of chip lead frames or the substrate Parallel to each other.
  • the chip packaging method provided by the invention is that the chip is vertically connected to the bottom substrate and the chip itself does not have vertical overlap, and each chip is directly connected to the external package substrate through a lead frame or a metal pin, which is very firm. It can avoid package deformation, is completely reliable, and has high package stability. 2. Good electrical performance.
  • the chip packaging method mentioned in the present invention can place another package substrate on the top of the package, which will be more symmetrical without any deformation, and the heat dissipation protection is better.
  • the individual chips are mounted on separate chip lead frames or substrates. These lead frames or substrates are directly connected to the bottom substrate and do not need to be connected to the bottom substrate.
  • the chip lead frame or substrate is very simple. The connection is also short, the cost is low, and the electrical performance is good.
  • the chip packaging method mentioned in the present invention can be applied to any computer, notebook, workstation, and other electronic application products using semiconductor devices, and can realize high reliability and high density packaging of a memory or other semiconductor chip, and has a wide application range.
  • FIG. 1 is a schematic diagram of a layout of a chip on a shared substrate in the prior art
  • FIG. 2 is a schematic diagram of a horizontal overlapping layout of a chip in the prior art
  • FIG. 3 is a schematic structural view of a chip placed on a lead frame in the prior art
  • FIG. 4 is a schematic view showing the structure of a first embodiment of a single-sided lead frame having a non-circular end according to the package method provided by the present invention
  • Figure 5 is a schematic view showing the structure of a second embodiment of a single-sided lead frame having a rounded end based on a package method according to the present invention
  • FIG. 6 is a schematic structural view of a chip mounted on a substrate in the prior art
  • FIG. 7 is a schematic structural view of a first embodiment of a chip mounted on a single-sided substrate having a non-circular end based on a packaging method provided by the present invention
  • FIG. 8 is a schematic structural view of a second embodiment of a chip mounted on a single-sided substrate having a rounded end based on a packaging method provided by the present invention
  • FIG. 9 is a schematic structural view of an embodiment of implementing high-density packaging of a chip based on FIG. 4 or FIG. 7;
  • FIG. 10 is a schematic structural view of an embodiment of implementing high-density packaging of a chip based on FIG. 5 or FIG.
  • the invention provides a chip packaging method, the method comprising the following steps: 1) mounting the chip 1 on a separate chip lead frame or substrate (lead frame 3 or substrate 4);
  • the chip lead frame or the substrate is directly used as an external package pin through a metal pin disposed on the chip lead frame or the substrate, or the chip lead frame or the substrate is connected to the external package by wire connection. Ball 5 on.
  • step 2) Fill the chip lead frame or substrate in step 2) with compound.
  • the chip lead frame or the substrate When the chip lead frame or the substrate is plural, the chip lead frame or the substrate is vertically placed on the plane of the outer package; the plurality of chip lead frames or the substrates are disposed in parallel with each other.
  • a package structure of a chip the package structure of the chip comprises a chip 1, a chip lead frame 3 or a substrate 4 and an outer package substrate 6; the chip 1 is disposed on the chip lead frame 3 or the substrate 4 and passes through the lead 2 and the chip lead frame 3 Or the metal pins of the substrate 4 are connected; one side of the chip lead frame 3 or the substrate 4 is connected to the external package substrate 6.
  • the chip lead frame 3 or the substrate 4 is used as a pin for the external package through a metal pin provided on the chip lead frame 3 or the substrate 4 through a pin hole provided in the package substrate.
  • the portion where the chip lead frame 3 or the substrate 4 is connected to the outer package substrate 6 has a rounded end.
  • the portion of the lead frame 3 or the substrate 4 connected to the external package substrate 6 is a circular end or a non-circular end.
  • the lead frame 3 or the portion of the substrate 4 connected to the external package substrate 6 is a non-circular end, the lead frame 3 or the substrate
  • the pins of 4 are directly used as pins of the external package; the leads of the lead frame 3 or the substrate 4 are directly used as external package pins through the pin holes 10 of the package substrate provided on the external package substrate 6.
  • the portion of the lead frame 3 or the substrate 4 metal pin that is connected to the external package substrate 6 is a rounded end, the rounded end is connected to the package solder ball 7 through a wire 8 on the external package substrate.
  • the chip lead frame 3 or the substrate 4 is one or more, the chip lead frame 3 or the substrate 4 is vertically disposed on the outer package substrate 6; when the chip lead frame 3 or the substrate 4 is plural, the plurality of chip lead frames 3 or the substrate 4 Parallel to each other.
  • the chip 1 first needs to be mounted on a separate chip leadframe or substrate, similar to the prior art.
  • Figures 3 and 6 show the layout of the prior art.
  • One chip 1 is mounted on On the lead frame 3 or on the substrate 4 (chip lead frame or substrate). It is obvious that the prior art does not achieve the proposed high density, high reliability package.
  • the bows of all the chips 1 are connected to one side of the outer package substrate 6.
  • a new package form can be achieved by using the chip leadframe or substrate layout of Figures 4, 5, 7, and 8.
  • the metal pins of the leadframe 3 or the substrate 4 pass directly through the pin holes provided on the package substrate as an external The package pin is used.
  • the metal pins of the lead frame 3 or the substrate 4 are directly used as external package pins, as shown in FIG. Another configuration is shown in Figure 9.
  • the external leads are located on the outer package substrate 6, ie in the form of a typical package solder ball 7.
  • the vertical layout of the chip leadframe or substrate can be inserted into the mold of the chip package, which can be used as a high-density chip module.
  • a plurality of semiconductor memory chips can be placed in a high-density memory structure and finally packaged through the package.
  • This approach has the additional advantage over prior art techniques because the chips are mounted on a single chip leadframe or substrate that can be individually processed and tested before being ultimately mounted on the external package substrate and mold. Such defective chips can be discovered and replaced earlier.
  • Figures 9 and 10 show the overall construction of the new package.
  • the chips are placed vertically on the bottom package substrate but the chips 1 themselves do not have vertical overlap. This has good thermal conductivity because each chip is directly connected to the bottom package substrate 6 via the lead frame 3 or the substrate 4.
  • this layout is very robust to avoid package distortion and is completely reliable.
  • another package substrate can be placed on top of this package, which will be better symmetrical without any distortion.
  • the individual chips are mounted on separate chip lead frames or substrates. These lead frames or substrates are directly connected to the bottom package substrate 6, and the wires on the substrate are not required to be connected to the bottom package substrate.
  • the chip lead frame or substrate is very Simple, the connection is also very short. The result is low cost and good electrical performance.

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  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明涉及一种芯片的封装方法及其封装结构，该芯片的封装方法包括以下步骤：1)将芯片安装在单独的芯片引线框或基板上；2)将步骤1)所得到的芯片引线框或基板的一边连接到外部封装基板。本发明提供了一种可避免封装变形、封装稳定性高、电气性能好以及应用范围广的芯片的封装方法及其封装结构。

Description

一种芯片的封装方法及其封装结构 技术领域
本发明属电子元器件领域， 涉及一种芯片的封装方式， 尤其涉及一种高可 靠、 高密度芯片的封装方法及其封装结构， 该芯片封装能够应用于任何计算机、 笔记本、 工作站以及其他使用半导体器件的电子应用产品中， 可以实现存储器 或其它半导体芯片的高密度封装， 即更小的引脚、 更好的稳定性以及更优秀的 热性能。
背景技术
现在的计算机系统使用单独的芯片封装， 即单个半导体芯片封装或所谓的 多芯片封装。 如今的多芯片封装都采用以下两种方式其中的一种： 1 ) 半导体芯 片安装在一个共享的基板上， 而且它们在垂直的方向上并没有重叠， 这是相对 于传统 PCB板 （printed circuit board 印刷电路板） 的一种排布方式； 2) 半导体 芯片相互层叠放置， 相对于水平面积的整个封装焊接或者安放在应用电路板上。 这种情况下， 通常在垂直方向上放置四个芯片。
上述的这两种方式存在很大的缺点： 任何类似 1 ) 共享相同基板的排布形式 需要很大面积的引脚。 基板的成本很高、 信号的特性很差， 因为信号需要从半 导体芯片下面连接到封装外部。 这种封装的稳定性也不是很高， 因为芯片基板 的面积很大， 芯片和基板的温度系数不匹配， 容易使封装变形扭曲 （见图 1 ) 。
基于 2) 的布局也有类似的缺点。 引脚面积虽然小但是封装容易变形扭曲， 而且因为多层的叠加和粘合稳定性更差。 焊盘连接到单个芯片的外面被用于键 合连接。 因为中间的芯片被隔离， 并用很小的引线连接， 不能有很好的导热性， 因此它的温度性能会很差 （见图 2) 。
发明内容
为了解决背景技术中存在的上述问题， 本发明提供了一种可避免封装变形、 封装稳定性高、 电气性能好以及应用范围广的芯片的封装方法及其封装结构。
一种芯片的封装方法， 包括以下步骤：
1 ) 将芯片安装在单独的芯片引线框或基板上； 2) 将步骤 1 ) 所得到的芯片引线框或基板的一边连接到外部封装基板。 上述步骤 2) 的具体实现方式是：
芯片引线框或基板通过设置在芯片引线框或基板上的金属引脚穿过设置在 封装基板引脚孔直接作为外部封装引脚使用。
上述步骤 2) 的具体实现方式是：
芯片引线框或基板通过连线连接到外部封装基板的焊球上。
上述芯片引线框或基板是一个或多个。
上述引线框或基板垂直连接在外部封装基板的平面上。
上述芯片引线框或基板是多个时， 所述多个引线框或基板相互平行设置。 上述引线框或基板之间进行化合物填充。
一种芯片的封装结构， 其特殊之处在于： 所述芯片的封装结构包括芯片、 芯片引线框或基板以及外部封装基板； 所述芯片安装在芯片引线框或基板上； 所述芯片引线框或基板的一边连接到外部封装基板。
上述芯片引线框或基板与外部封装基板是通过圆形末端或非圆形末端进行 连接。
上述芯片引线框或基板与外部封装基板连接的部分是非圆形末端时， 所述 通过设置在芯片引线框或基板上的金属引脚穿过设置在封装基板引脚孔直接作 为外部封装引脚使用。
上述芯片引线框或基板与外部封装基板连接的部分是圆形末端时， 所述圆 形末端通过封装基板上的连线连接到外部封装基板的焊球上。
上述芯片引线框或基板垂直连接在外部封装基板上； 所述芯片引线框或基 板是一个或多个， 所述芯片引线框或基板是多个时， 所述多个芯片引线框或基 板之间相互平行。
本发明的优点是：
1、 可避免封装变形， 封装稳定性高。 本发明所提供的芯片封装方法， 是将 芯片垂直的连接底部基板上而且芯片本身并没有垂直的重叠， 每个芯片都是通 过引线框或金属引脚直接连接到外部封装基板上， 非常牢固的可以避免封装变 形， 完全可靠， 封装稳定性高。 2、 电气性能好。 本发明所提及的这种芯片的封装方法是将另外一个封装基 板可以放在这个封装的顶部， 这将会更好的对称而没有任何变形， 散热保护更 好。 同时， 单个的芯片安装在单独的芯片引线框或基板上， 这些引线框或基板 直接的连接在底部基板上， 并不需要连线连接到底部基板上， 芯片引线框或基 板是非常简单的， 连线也很短， 其成本低廉， 电气性能好。
3、 应用范围广。 本发明所提及的芯片封装方法能够应用于任何计算机、 笔 记本、 工作站以及其他使用半导体器件的电子应用产品中， 能够实现存储器或 其它半导体芯片的高可靠性、 高密度封装， 应用范围非常广阔。
附图说明
图 1是现有技术中芯片在共享基板上的布局示意图；
图 2是现有技术中芯片水平重叠布局示意图；
图 3是现有技术中芯片安放在引线框上的结构示意图；
图 4是基于本发明所提供封装方法的芯片安放在具有非圆形末端单边引线 框第一实施例的结构示意图；
图 5是基于本发明所提供封装方法的芯片安放在具有圆形末端的单边引线 框第二实施例的结构示意图；
图 6是现有技术中芯片安放在基板上的结构示意图；
图 7是基于本发明所提供封装方法的芯片安放在具有非圆形末端单边基板 上第一实施例结构示意图；
图 8是基于本发明所提供封装方法的芯片安放在具有圆形末端的单边基板 上第二实施例结构示意图；
图 9是基于图 4或图 7而实现芯片的高密度封装的实施例结构示意图； 图 10是基于图 5或图 8而实现芯片的高密度封装的实施例结构示意图。
其中：
1-芯片； 2-引线； 3-引线框； 4-基板； 5-焊球； 6-外部封装基板； 7-封装焊球; 8-封装基板上的连线； 9-封装壳； 10-封装基板的引脚孔。
具体实施方式
本发明提供了一种芯片的封装方法， 该方法包括以下步骤： 1 ) 将芯片 1安装在单独的芯片引线框或基板 （引线框 3或基板 4) 上；
2 )将步骤 1 ) 所得到的芯片引线框或基板的一边连接到外部封装基板 6， 芯 片引线框或基板是一个或多个。
芯片引线框或基板通过设置在芯片引线框或基板上的金属引脚穿过设置在 封装基板引脚孔直接作为外部封装引脚使用， 或者芯片引线框或基板通过连线 连接到外部封装的焊球 5上。
3 ) 对步骤 2) 中的芯片引线框或基板进行化合物填充。
芯片引线框或基板是多个时， 芯片引线框或基板垂直的安放在外部封装的 平面上； 多个芯片引线框或基板之间相互平行设置。
一种芯片的封装结构， 该芯片的封装结构包括芯片 1、 芯片引线框 3或基板 4 以及外部封装基板 6; 芯片 1设置于芯片引线框 3或基板 4上并通过引线 2与芯片引 线框 3或基板 4的金属引脚连接； 芯片引线框 3或基板 4的一边连接到外部封装基 板 6。
芯片引线框 3或基板 4通过设置在芯片引线框 3或基板 4上的金属引脚穿过设 置在封装基板引脚孔直接作为外部封装弓 I脚使用。
芯片引线框 3或基板 4与外部封装基板 6的封装焊球 7连接时， 芯片引线框 3或 基板 4与外部封装基板 6连接的部分呈圆形末端。
引线框 3或基板 4与外部封装基板 6连接的部分是圆形末端或非圆形末端， 当 引线框 3或基板 4与外部封装基板 6连接的部分是非圆形末端时， 引线框 3或基板 4 的引脚直接作为外部封装的引脚使用； 引线框 3或基板 4的引脚通过设置在外部 封装基板 6上的封装基板的引脚孔 10直接作为外部封装引脚使用。 当引线框 3或 基板 4金属引脚与外部封装基板 6连接的部分是圆形末端时， 圆形末端通过外部 封装基板上的连线 8连接到封装焊球 7上。
芯片引线框 3或基板 4是一个或多个， 芯片引线框 3或基板 4垂直设置在外部 封装基板 6上； 芯片引线框 3或基板 4是多个时， 多个芯片引线框 3或基板 4相互平 行。
为了实现上述的封装形式， 芯片 1首先需要安装在单独的芯片引线框或基板 上， 这类似于之前的技术。 图 3和图 6显示了之前技术的布局。 一个芯片 1安装在 引线框 3上或者基板 4上 （芯片引线框或基板） 。 先前的技术不能实现所提出的 高密度、 高可靠性的封装， 这是显而易见的。 对于新的封装形式， 所有芯片 1的 弓 I脚都连接到外部的封装基板 6的一边。 通过使用图 4、 图 5、 图 7和图 8的芯片引 线框或基板布局可以实现新的封装形式。 如果引线框金属和其它的引脚可以连 接到外部封装的引脚， 两种构造都是可能的： 引线框 3或基板 4的金属引脚穿过 设置在封装基板上的引脚孔直接作为外部封装引脚使用。 这种情况下， 引线框 3 或基板 4的金属引脚直接作为外部封装引脚使用， 如图 10所示。 另外一种构造如 图 9所示。 外部引脚位于外部封装基板 6上， 即典型的封装焊球 7形式。
上述两种情况， 芯片引线框或基板的垂直布局的模具可以插入芯片封装的 模具中， 这样可以作为高密度芯片模组使用。 例如， 多个半导体存储芯片可以 放到高密度存储构造中， 最后经过封装壳 9进行封装。 相对于现有的技术， 这种 方法还有另外一个优点， 因为芯片是安装在单个的芯片引线框或基板上， 在最 终安装在外部封装基板和模具之前， 它们能够被单个的处理和测试。 这样有缺 陷的芯片可以更早的发现和替换。
图 9和图 10显示了新的封装的全部构造。 芯片是垂直的放在底部封装基板上 但是芯片 1本身并没有垂直的重叠。 这有很好的热传导性能， 因为每个芯片都是 通过引线框 3或基板 4直接连接到底部封装基板 6上。 另外， 这种布局是非常牢固 的可以避免封装变形， 完全可靠的。 为了更好的对称和更好的散热保护， 另外 一个封装基板可以放在这个封装的顶部， 这将会更好的对称而没有任何变形。 单个的芯片安装在单独的芯片引线框或基板上， 这些引线框或基板直接连接在 底部封装基板 6上， 并不需要基板上的连线连接到底部封装基板上， 芯片引线框 或基板是非常简单的， 连线也很短。 这样的结果是， 成本很低、 电气性能很好。

Claims

权 利 要 求 书
1、 一种芯片的封装方法， 其特征在于： 所述方法包括以下步骤：
1 ) 将芯片安装在单独的芯片引线框或基板上；
2) 将步骤 1 ) 所得到的芯片引线框或基板的一边连接到外部封装基板。 2、 根据权利要求 1所述的芯片的封装方法， 其特征在于： 所述步骤 2 ) 的具 体实现方式是：
芯片引线框或基板通过设置在芯片引线框或基板上的金属引脚穿过设置在 封装基板引脚孔直接作为外部封装引脚使用。
3、 根据权利要求 1所述的芯片的封装方法， 其特征在于： 所述步骤 2 ) 的具 体实现方式是：
所述芯片引线框或基板通过连线连接到外部封装基板的焊球上。
4、 根据权利要求 2或 3所述的芯片的封装方法， 其特征在于： 所述芯片引线 框或基板是一个或多个； 所述芯片引线框或基板是多个时， 所述多个引线框或 基板相互平行设置； 所述引线框或基板垂直连接在外部封装基板的平面上。
5、 根据权利要求 4所述的芯片的封装方法， 其特征在于： 所述芯片的封装 方法还包括：
3 ) 引线框或基板之间进行化合物填充。
6、 一种芯片的封装结构， 其特征在于： 所述芯片的封装结构包括芯片、 芯 片引线框或基板以及外部封装基板； 所述芯片安装在芯片引线框或基板上； 所 述芯片引线框或基板的一边连接到外部封装基板。
7、 根据权利要求 6所述的芯片的封装结构， 其特征在于： 所述芯片引线框 或基板与外部封装基板是通过圆形末端或非圆形末端进行连接。
8、 根据权利要求 7所述的芯片的封装结构， 其特征在于： 所述芯片引线框 或基板与外部封装基板连接的部分是非圆形末端时， 所述通过设置在芯片引线 框或基板上的金属引脚穿过设置在封装基板引脚孔直接作为外部封装引脚使 用。
9、 根据权利要求 7或 8所述的芯片的封装结构， 其特征在于： 所述芯片引线 框或基板与外部封装基板连接的部分是圆形末端时， 所述圆形末端通过封装基 板上的连线连接到外部封装基板的焊球上。
10、 根据权利要求 9所述的芯片的封装结构， 其特征在于： 所述芯片引线框 或基板垂直连接在外部封装基板上； 所述芯片引线框或基板是一个或多个， 所 述芯片引线框或基板是多个时， 所述多个芯片引线框或基板之间相互平行。
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CN1443370A (zh) * 2000-07-19 2003-09-17 新藤电子工业株式会社 半导体装置

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