WO2013031275A1 - 駆動回路および宅側装置 - Google Patents
駆動回路および宅側装置 Download PDFInfo
- Publication number
- WO2013031275A1 WO2013031275A1 PCT/JP2012/058949 JP2012058949W WO2013031275A1 WO 2013031275 A1 WO2013031275 A1 WO 2013031275A1 JP 2012058949 W JP2012058949 W JP 2012058949W WO 2013031275 A1 WO2013031275 A1 WO 2013031275A1
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- WIPO (PCT)
- Prior art keywords
- circuit
- light emitting
- drive circuit
- emitting element
- current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/06—Arrangements for controlling the laser output parameters, e.g. by operating on the active medium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
- H01S5/0427—Electrical excitation ; Circuits therefor for applying modulation to the laser
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J14/00—Optical multiplex systems
- H04J14/08—Time-division multiplex systems
Definitions
- the present invention relates to a drive circuit and a home apparatus, and more particularly to a drive circuit for driving a light emitting element for transmitting an optical signal, and a home apparatus including the same.
- ADSL Asymmetric Digital Subscriber Line
- FTH Fiber To The Home
- Non-Patent Document 1 a plurality of optical network units (ONUs) share an optical communication line and a station-side apparatus (OLT: Optical Line Terminal)
- PON Passive Optical Network
- EPON Ethernet (registered trademark) PON
- MPCP Multi-Point Control Protocol
- OAM Operations Administration and Maintenance
- Non-Patent Document 1 describes a method of registering a new home apparatus, a report indicating a bandwidth allocation request, and a gate indicating a transmission instruction by an MPCP message.
- IEEE 802.3av registered trademark
- GE-PON Giga Bit Ethernet (registered trademark) Passive Optical Network) that is an EPON that realizes a communication speed of 1 gigabit / sec.
- the access control protocol is assumed to be MPCP even in the case of 10G-EPON, that is, an EPON having a communication speed of 10 gigabits per second.
- the laser drive circuit includes a modulation circuit that supplies a modulation current to the laser diode in accordance with the input burst data, and a bias circuit that supplies a bias current to the laser diode.
- the modulation circuit includes a differential drive circuit, and the differential drive circuit and the laser diode are AC-coupled by a capacitive element.
- a termination resistor for impedance matching is connected between the pair of transistors and the power supply line.
- a time division multiplexing system is adopted as an uplink communication system from the home apparatus to the station apparatus.
- the home apparatus transmits a burst optical signal to the station apparatus. Therefore, in the home apparatus, it is necessary to supply a current to a light emitting element such as a laser diode in a period in which a burst optical signal is to be transmitted, and to stop the supply of the current in the other period.
- the burst response characteristic that is, the on / off speed characteristic of the current supplied to the light emitting element is important.
- the present invention has been made to solve the above-described problems, and an object thereof is to provide a drive circuit and a home-side device capable of reducing reactive current which does not contribute to driving of a light emitting element for transmitting an optical signal. To provide.
- a drive circuit includes a bias current supply circuit for supplying a bias current to the light emitting element in a light emitting circuit including a light emitting element for transmitting an optical signal; And a modulation current supply circuit for supplying a modulation current having a magnitude corresponding to the logic value of data to be transmitted to the light emitting element, the modulation current supply circuit generating the light emission according to the logic value of the data
- the differential drive circuit and the light emission circuit include a differential drive circuit for switching whether to supply a current to the element and a termination resistor connected between differential outputs of the differential drive circuit The power of the current coupled to the light emitting element, which the differential drive circuit supplies to the light emitting element, is supplied from the light emitting circuit.
- the impedance of the path of the reactive current is increased, so that the reactive current that does not contribute to the drive of the light emitting element can be reduced, and the power consumption can be reduced.
- the termination resistor is AC coupled to the node to which a fixed voltage is supplied without passing through the light emitting circuit.
- the differential drive circuit comprises: a first transistor having a first conduction electrode DC-coupled to the first end of the light emitting element; and a second conduction electrode; and a DC current at the second end of the light emitting element
- a second transistor having a coupled first conduction electrode and a second conduction electrode electrically connected to the second conduction electrode of the first transistor; a first conduction electrode of the first transistor; A first termination resistor and a second termination resistor connected in series between the first conduction electrodes of the second transistor, the connection of the first conduction electrode of the first transistor and the first termination resistance
- the node is DC-coupled to the connection node of the first end of the light emitting element and the node to which the DC power supply voltage is supplied, and the connection node of the first conduction electrode of the second transistor and the second termination resistor is the light emitting element Are DC coupled to the connection node of the second end and the bias current supply circuit.
- the modulation current supply circuit further includes a capacitor connected between a node supplied with a fixed voltage and a connection node of the first termination resistor and the second termination resistor.
- Such a configuration makes it possible to provide an appropriate circuit for stabilizing the potential of the connection node of each termination resistor.
- a home apparatus is a home apparatus in a communication system in which optical signals from a plurality of home apparatuses to a station apparatus are time division multiplexed,
- a light emitting circuit including a light emitting element for transmitting an optical signal, and a drive circuit for driving the light emitting element, the drive circuit including a bias current supply circuit for supplying a bias current to the light emitting element And a modulation current supply circuit for supplying a modulation current having a magnitude according to the logic value of data to be transmitted to the light emitting element, the modulation current supply circuit generating the modulation current according to the logic value of the data
- the differential drive circuit and the light emitting circuit include: a differential drive circuit for switching whether to supply current to the light emitting element; and a termination resistor connected between differential outputs of the differential drive circuit; DC coupled And which, the differential driver circuit power supply of the current supplied to the light emitting element is supplied from the light emitting circuit.
- the impedance of the path of the reactive current is increased, so that the reactive current that does not contribute to the drive of the light emitting element can be reduced, and the power consumption can be reduced.
- the present invention it is possible to reduce the reactive current which does not contribute to the drive of the light emitting element for transmitting the light signal.
- FIG. 1 is a diagram showing a configuration of a PON system according to an embodiment of the present invention. It is a figure which shows the structure of the residential
- FIG. 6 is a diagram showing a configuration when it is assumed that no reactive current countermeasure is taken in the drive circuit of the optical transceiver according to the embodiment of the present invention.
- FIG. It is a figure which shows the reactive current which flows in the drive circuit shown in FIG. It is a figure which shows the structure of the drive circuit of the optical transceiver which concerns on embodiment of this invention. It is a figure which shows the structure of the drive circuit of the optical transceiver which concerns on embodiment of this invention. It is a figure which shows the measurement result of the optical signal (continuous signal) which the drive circuit 51 outputs. It is a figure which shows the measurement result of the optical signal (continuous signal) which the drive circuit 52 outputs. It is a figure which shows the measurement result of the optical signal (continuous signal) which the drive circuit 53 outputs. It is a figure which shows the measurement result of the burst light signal which the drive circuit 51 outputs. It is a figure which shows the measurement result of the burst light signal which the drive circuit 52 outputs. It is a figure which shows the measurement result of the burst light signal which the drive circuit 53 outputs.
- FIG. 1 is a diagram showing the configuration of a PON system according to an embodiment of the present invention.
- PON system 301 is, for example, 10G-EPON, and includes home apparatuses 202A, 202B, 202C, 202D, station apparatus 201, and splitters SP1, SP2.
- the home apparatuses 202A, 202B, 202C and the office apparatus 201 are connected via the splitters SP1 and SP2 and the optical fiber OPTF, and transmit and receive optical signals to each other.
- the home apparatus 202D and the station apparatus 201 are connected via the splitter SP2 and the optical fiber OPTF, and transmit and receive optical signals to each other.
- optical signals from the home apparatuses 202A, 202B, 202C, 202D to the station apparatus 201 are time division multiplexed.
- FIG. 2 is a diagram showing a configuration of a home side apparatus in the PON system according to the embodiment of the present invention.
- the home apparatus 202 includes an optical transceiver 21, a PON reception processing unit 22, a buffer memory 23, an UN transmission processing unit 24, an UNI (User Network Interface) port 25, and an UN reception process.
- a unit 26, a buffer memory 27, a PON transmission processing unit 28, and a control unit 29 are provided.
- the optical transceiver 21 is removable from the home apparatus 202.
- the optical transceiver 21 receives the downstream optical signal transmitted from the station apparatus 201, converts it into an electrical signal, and outputs it.
- the PON reception processing unit 22 reconstructs a frame from the electric signal received from the optical transceiver 21 and distributes the frame to the control unit 29 or the UN transmission processing unit 24 according to the type of the frame. Specifically, the PON reception processing unit 22 outputs the data frame to the UN transmission processing unit 24 via the buffer memory 23 and outputs the control frame to the control unit 29.
- the control unit 29 generates a control frame including various control information, and outputs the control frame to the UN transmission processing unit 24.
- the UN transmission processing unit 24 transmits the data frame received from the PON reception processing unit 22 and the control frame received from the control unit 29 to a user terminal such as a personal computer (not shown) via the UNI port 25.
- the UN reception processing unit 26 outputs the data frame received from the user terminal via the UNI port 25 to the PON transmission processing unit 28 via the buffer memory 27, and the control frame received from the user terminal via the UNI port 25 Output to
- the control unit 29 performs home-side processing related to control and management of the PON line between the station-side device 201 and the home-side device 202, such as MPCP and OAM. That is, various controls such as access control are performed by exchanging MPCP messages and OAM messages with the station-side apparatus 201 connected to the PON line.
- the control unit 29 generates a control frame including various control information, and outputs the control frame to the PON transmission processing unit 28. Further, the control unit 29 performs various setting processing of each unit in the home apparatus 202.
- the PON transmission processing unit 28 outputs the data frame received from the UN reception processing unit 26 and the control frame received from the control unit 29 to the optical transceiver 21.
- the optical transceiver 21 converts the data frame and control frame received from the PON transmission processing unit 28 into an optical signal and transmits the optical signal to the station-side device 201.
- FIG. 3 is a diagram showing in detail the configuration of the transmission side of the optical transceiver in the home apparatus according to the embodiment of the present invention.
- the optical transceiver 21 includes a pre-buffer circuit 61, an equalizer circuit 62, a driving circuit 51, current sources 64 to 66, a timing circuit 67, a light emitting circuit 75, and a master I / F ( Interface) 69, a central processing unit (CPU) 70, a slave I / F 71, a control register 72, and capacitors C1 and C2.
- the drive circuit 51 includes an output buffer circuit (modulation current supply circuit) 63 and a bias current supply circuit 68.
- the prebuffer circuit 61 includes a termination resistor R11.
- the light emitting circuit 75 includes a light emitting element LD and inductors 31 and 32.
- CPU 70 includes a storage unit 73 which is, for example, an EEPROM (Electrically Erasable Programmable Read Only Memory).
- the prebuffer circuit 61 receives the data frame from the UN reception processing unit 26 and the transmission data as the control frame from the control unit 29 via the capacitors C1 and C2 at the termination resistor R11, amplifies the transmission data, and outputs the amplified data. Do.
- the prebuffer circuit 61 receives the transmission data from the signal lines INP and INN as a balanced signal.
- Equalizer circuit 62 performs waveform shaping of transmission data received from prebuffer circuit 61, for example, correction of phase distortion, and outputs the corrected data.
- the drive circuit 51 drives the light emitting element LD in the light emitting circuit 75.
- output buffer circuit 63 includes, for example, a differential drive circuit having two transistors, and based on the transmission data received from equalizer circuit 62, supplies differential modulation current to light emission circuit 75.
- This modulation current is a current having a magnitude according to the logic value of data to be transmitted to the station-side device 201.
- the configuration using the differential drive circuit can improve the response speed of the modulation current to the change of the logic value of the transmission data.
- the light emitting circuit 75 transmits the upstream optical signal to the station apparatus 201.
- the light emitting element LD is connected to the power supply node to which the power supply voltage Vcc2 is supplied via the inductor 31 and to the bias current supply circuit 68 via the inductor 32.
- the light emitting element LD emits light based on the bias current supplied from the bias current supply circuit 68 and the modulation current supplied from the output buffer circuit 63, and changes the light emission intensity.
- the current sources 64 to 66 can supply, for example, current as electric power to the pre-buffer circuit 61, the equalizer circuit 62, and the output buffer circuit 63, respectively, and can control start and stop of the power supply. More specifically, the current sources 64 to 66 respectively switch whether to supply power to the pre-buffer circuit 61, the equalizer circuit 62 and the output buffer circuit 63 based on the transmission enable signal received from the control unit 29.
- current sources 64 to 66 supply power to pre-buffer circuit 61, equalizer circuit 62 and output buffer circuit 63 when the transmission enable signal is activated, and the transmission enable signal is inactive. Stop the power supply if it is
- the timing circuit 67 also performs control to forcibly stop the supply of the modulation current from the output buffer circuit 63 to the light emitting element LD.
- the bias current supply circuit 68 supplies a bias current as power to the light emitting circuit 75. Further, based on the transmission enable signal received from the control unit 29, the bias current supply circuit 68 switches whether to supply a bias current to the light emitting circuit 75 or not.
- the value of the bias current is set so that the light emitting element LD emits light when the bias current is supplied to the light emitting element LD. Be done.
- inductor 31 has a first end connected to a power supply node to which power supply voltage Vcc2 is supplied, and a second end.
- the light emitting element LD is, for example, a laser diode, and has an anode connected to the second end of the inductor 31 and a cathode connected to the first end of the inductor 32.
- the modulation current output from the output buffer circuit 63 flows from the anode to the cathode of the light emitting element LD.
- Power supply voltage Vcc2 is higher in level than power supply voltage Vcc1.
- Power supply voltage Vcc1 is supplied, for example, to pre-buffer circuit 61 and equalizer circuit 62. Further, power supply voltage Vcc2 is supplied, for example, to output buffer circuit 63.
- Power supply voltage Vcc1 and power supply voltage Vcc2 are DC voltages.
- the CPU 70 exchanges various data with the control unit 29 via, for example, an I2C bus including a signal line SCL and a signal line SDA.
- Master I / F 69 provides an interface function between CPU 70 and the I2C bus.
- the slave I / F 71 provides an interface function between the CPU 70 and the control register 72.
- the CPU 70 writes various control data to the control register 72 via the slave I / F 71.
- the current source 66 changes the amount of current supplied to the output buffer circuit 63 based on the control data APC1 written to the control register 72.
- the bias current supply circuit 68 changes the amount of current supplied to the light emitting circuit 75 based on the control data APC2 written to the control register 72.
- FIG. 4 is a diagram showing light output and transmission enable signals in the optical transceiver of the home apparatus according to the embodiment of the present invention.
- the portion indicated by "data” is actually a combination of the "bias” portion and the “bias” portion and the “data” portion according to the logical value of the transmission data.
- the waveform changes with the level.
- the transmission enable signal is inactivated during a period in which transmission of an upstream optical signal is not permitted from station apparatus 201.
- the bias current supply circuit 68 does not operate and no bias current is generated.
- the transmission enable signal is activated in order to transmit the upstream optical signal from the home-side apparatus 202.
- the bias current supply circuit 68 starts operation, generates a bias current, and supplies it to the light emitting element LD.
- the current sources 64 to 66 start operation, and current is supplied to the pre-buffer circuit 61, the equalizer circuit 62 and the output buffer circuit 63, respectively.
- the modulation current from the output buffer circuit 63 is not supplied to the light emitting element LD by the control of the timing circuit 67 (timing t1).
- the timing circuit 67 forcibly stops the supply of the modulation current from the output buffer circuit 63 to the light emitting element LD in a period from the timing t1 to the timing t2 after the elapse of the time TDL.
- the timing circuit 67 it is possible to prevent the occurrence of an overshoot or the like caused by the flow of the modulation current in a state where the level of the bias current is unstable, so that the circuit operation can be stabilized.
- timing t2 when the time TDL elapses and supply of the modulation current to the light emitting element LD is started (timing t2), the preamble which is invalid data starts to be transmitted, and thereafter, transmission of valid data is started.
- the output buffer circuit 63 and the bias current supply circuit 68 stop operating. , Generation of the bias current and the modulation current is stopped.
- FIG. 5 is a diagram showing a configuration in the case where no reactive current countermeasure is taken in the drive circuit of the optical transceiver according to the embodiment of the present invention.
- drive circuit 51 further includes resistors 13 and 14 and filter circuit 17.
- Output buffer circuit 63 includes resistors 11 and 12 and differential drive circuit 41.
- Differential drive circuit 41 includes N channel MOS transistors 15 and 16.
- the bias current supply circuit 68 includes a current source 33.
- the differential drive circuit 41 switches whether to supply current to the light emitting element LD according to the logical value of the transmission data.
- the resistors 11 and 12 are connected between differential outputs of the differential drive circuit 41.
- the resistors 11 and 12 are connected in series between the drain of the N channel MOS transistor 15 and the drain of the N channel MOS transistor 16.
- resistor 11 has a first end connected to the power supply node to which power supply voltage Vcc2 is supplied, and a second end.
- Resistor 12 has a first end connected to a power supply node to which power supply voltage Vcc2 is supplied, and a second end.
- N channel MOS transistor 15 has a drain connected to the second end of resistor 11, a source connected to the first end of current source 66, and a gate connected to data node N0.
- N channel MOS transistor 16 has a drain connected to the second end of resistor 12, a source connected to the first end of current source 66, and a gate connected to data node N1.
- the second end of current source 66 is connected to the ground node supplied with the ground voltage.
- the current source 33 in the bias current supply circuit 68 is connected between the second end of the inductor 32 and the ground node.
- Data node N0 is activated when transmission data has a logic value "0"
- data node N1 is activated when transmission data has a logic value "1".
- the differential drive circuit 41 and the light emission circuit 75 are DC-coupled (DC-coupled). That is, the connection node of N channel MOS transistor 15 and resistor 11 is DC-coupled to the connection node of the anode of light-emitting element LD and the node to which power supply voltage Vcc2, which is a DC power supply voltage, is supplied. A connection node of N channel MOS transistor 16 and resistor 12 is DC-coupled to a connection node of light emitting element LD and a connection node of bias current supply circuit 68.
- connection node of the second end of the resistor 11 and the drain of the N-channel MOS transistor 15 is connected via the resistor 13 to the connection node of the second end of the inductor 31 and the anode of the light emitting element LD.
- a connection node of the second end of resistor 12 and the drain of N channel MOS transistor 16 is connected via a resistor 14 to a connection node of a first end of inductor 32 and a cathode of light emitting element LD.
- the resistors 11 and 12 are termination resistors for impedance matching.
- 10G-EPON is useful for preventing ringing of burst optical signals.
- the light emitting element LD is incorporated, for example, in an assembled light emitting module.
- the output buffer circuit 63, the filter circuit 17, the resistors 13 and 14, the light emitting circuit 75, and the bias current supply circuit 68 are mounted on a printed circuit board (PCB: Print Circuit Board).
- PCB Print Circuit Board
- the light emitting circuit 75 and the light emitting module are connected via a flexible printed circuit (FPC).
- the differential output of the differential drive circuit 41 in the output buffer circuit 63 and the light emitting element LD are connected by a transmission path. More specifically, the connection node between the drain of the N channel MOS transistor 15 and the resistor 11 and the anode of the light emitting element LD are connected by a transmission line such as a microstrip line. The connection node between the drain of the N channel MOS transistor 16 and the resistor 12 and the cathode of the light emitting element LD are connected by a transmission line such as a microstrip line. The length of this transmission line is, for example, 25 mm to 30 mm, and the characteristic impedance is, for example, 25 ⁇ .
- the light emission circuit 75 and the bias current supply circuit 68 do not particularly need to consider the impedance, and preferably have a low impedance in DC and a high impedance in AC.
- the resistors 13 and 14 are damping resistors provided to correct the frequency characteristics of the burst optical signal and to compensate for the drop in impedance due to the parasitic capacitance on the output buffer circuit 63 side.
- the filter circuit 17 is provided between the resistor 13 and the resistor 14 in order to remove a high frequency component such as a modulation current flowing between the differential drive circuit 41 and the light emitting circuit 75.
- the operation of the drive circuit 51 is as follows. That is, when the transmission data has the logic value "1", the N channel MOS transistor 15 is turned off and the N channel MOS transistor 16 is turned on. Thereby, current IM1 flows from the power supply node of light emitting circuit 75 to the ground node of output buffer circuit 63 via light emitting element LD and N channel MOS transistor 16 of differential drive circuit 41. That is, the modulation current of a certain magnitude is supplied to the light emitting element LD.
- the N channel MOS transistor 15 is turned on and the N channel MOS transistor 16 is turned off.
- current IM 0 flows from the power supply node of light emitting circuit 75 to the ground node of output buffer circuit 63 via N channel MOS transistor 15 of differential drive circuit 41 without passing through light emitting element LD. That is, the magnitude of the modulation current to the light emitting element LD becomes zero.
- the bias current Ibias flows from the power supply node of the light emission circuit 75 to the ground node of the bias current supply circuit 68 via the light emitting element LD by the current source 33.
- FIG. 6 is a diagram showing the reactive current flowing in the drive circuit shown in FIG.
- the resistance of each of the resistors 11 and 12 is Rout
- the resistance of each of the resistors 13 and 14 is Rdamp
- the forward voltage and the differential resistance of the light emitting element LD are Vf and Rd, respectively.
- the reactive current INE is reduced by adopting the following configuration in the drive circuit of the optical transceiver 21.
- FIG. 7 is a diagram showing a configuration of a drive circuit of the optical transceiver according to the embodiment of the present invention.
- the first end of the resistor 11 and the first end of the resistor 12 are not connected to the power supply node.
- the power of the current supplied from the differential drive circuit 41 to the light emitting element LD is supplied from the light emitting circuit 75. That is, the differential drive circuit 41 supplies a current to the light emitting element LD by the power supplied from the light emitting circuit 75.
- the connection node between the resistor 11 and the resistor 12 is lower in potential than the power supply node of the light emitting circuit 75 by the voltage drop of the resistor 13 and the resistor 11. That is, the potential of the connection node between the resistors 11 and 12 is determined by the power supply voltage Vcc2 supplied from the power supply node of the light emission circuit 75.
- the output buffer circuit 63 and the light emitting circuit 75 are DC-coupled. Therefore, since it is possible to supply DC power from the light emitting circuit 75 through the DC coupling, it is not necessary to connect the connection node of the resistor 11 and the resistor 12 to the power supply node.
- connection node between resistors 11 and 12 is not connected to the power supply node, so that the reactive current INE flowing between output buffer circuit 63 and bias current supply circuit 68 via light emitting circuit 75.
- Path includes the path between the power supply node of the light emitting circuit 75 and the output buffer circuit 63.
- reactive current INE passes from the power supply node of light emitting circuit 75 to ground node via inductor 31, resistor 13, resistor 11, resistor 12, resistor 14, inductor 32 and bias current supply circuit 68 in this order. Flow. As a result, the impedance of the path of the reactive current INE increases compared to the drive circuit 51 shown in FIG. 5, so that the reactive current INE can be reduced.
- the current consumption can be reduced by 22.6 mA as compared with the drive circuit 51 shown in FIG.
- the drive circuit 52 if the duty ratio of transmission data is constant, the potential at the connection node of the resistors 11 and 12 does not change, so the AC ground potential is stable at the connection node. That is, when the optical transceiver 21 transmits a continuous optical signal, stable transmission characteristics can be obtained.
- the optical transceiver 21 transmits a burst optical signal
- the duty ratio of transmission data in a period in which the optical signal is not transmitted is zero, and the duty ratio fluctuates at the transmission start timing of the optical signal.
- the potential at the connection node between the resistor 11 and the resistor 12 becomes unstable, and ringing may occur in the burst optical signal.
- FIG. 8 is a diagram showing a configuration of a drive circuit of the optical transceiver according to the embodiment of the present invention.
- output buffer circuit 63 further includes a capacitor 19 as compared with drive circuit 52 shown in FIG. 7.
- Capacitor 19 is connected between a node supplied with power supply voltage Vcc2, which is a fixed voltage, and a connection node between resistor 11 and resistor 12. That is, the first end of the resistor 11 and the first end of the resistor 12 are connected to the power supply node via the capacitor 19.
- the capacitance value of capacitor 19 is, for example, 1000 pF.
- the resistors 11 and 12 are AC-coupled to the node to which the fixed voltage is supplied without passing through the light emitting circuit 75.
- the fixed voltage is not limited to the power supply voltage Vcc2, but may be, for example, the ground voltage.
- a capacitive element is connected between the connection node of each termination resistor whose potential may become unstable in the drive circuit 52 shown in FIG. 7 and the power supply node.
- connection node can be stabilized at the power supply voltage Vcc2. Further, since the power supply node and each termination resistor are AC-coupled, it is possible to prevent the reactive current INE from flowing from the power supply node as shown in FIG. In the drive circuit 53, the reactive current INE similar to that of the drive circuit 52 shown in FIG. 7 flows.
- the consumption current can be reduced by 22.6 mA as compared with the drive circuit 51 shown in FIG.
- FIG. 9 is a diagram showing the measurement results of the optical signal (continuous signal) output by the drive circuit 51.
- FIG. 10 is a diagram showing the measurement results of the optical signal (continuous signal) output from the drive circuit 52.
- FIG. 11 is a view showing the measurement results of the optical signal (continuous signal) output from the drive circuit 53.
- FIG. 12 is a diagram showing the measurement results of the burst light signal output from the drive circuit 51.
- FIG. 13 is a diagram showing the measurement results of the burst light signal output from the drive circuit 52.
- FIG. FIG. 14 is a diagram showing the measurement results of the burst light signal output from the drive circuit 53.
- FIG. 10 is a diagram showing the measurement results of the optical signal (continuous signal) output from the drive circuit 52.
- FIG. 11 is a view showing the measurement results of the optical signal (continuous signal) output from the drive circuit 53.
- FIG. 12 is a diagram showing the measurement results of the burst light signal output from the drive circuit 51.
- FIG. 9 to 11 show eye patterns of optical signals.
- B is a portion in which the optical signal repeats a logic high level and a logic low level.
- the output buffer circuit 63 supplies the light emitting element LD with a modulation current having a magnitude corresponding to the logic value of data to be transmitted.
- the differential drive circuit 41 switches whether to supply current to the light emitting element LD according to the logic value of data.
- the resistors 11 and 12 are connected between differential outputs of the differential drive circuit 41.
- the differential drive circuit 41 and the light emitting circuit 75 are DC-coupled, and the power of the current supplied from the differential drive circuit 41 to the light emitting element LD is supplied from the light emitting circuit 75.
- the power supply of the output buffer circuit 63 is supplied from the power supply node for bias current, that is, the power supply node of the light emission circuit 75.
- the impedance of the path of the reactive current is increased, so that the reactive current not contributing to the drive of the light emitting element can be halved as described in FIG. 7, for example, so power consumption can be reduced.
- the resistors 11 and 12 are AC-coupled without passing through the light-emitting circuit 75 and the node to which the fixed voltage is supplied.
- Such a configuration makes it possible to reduce the reactive current not contributing to the drive of the light emitting element and stabilize the burst response.
- resistor 11 and resistor 12 are connected in series between the drain of N channel MOS transistor 15 and the drain of N channel MOS transistor 16.
- the connection node of the drain of N channel MOS transistor 15 and resistor 11 is DC-coupled to the connection node of the anode of light-emitting element LD and the node to which a DC power supply voltage is supplied.
- the connection node of the drain of N channel MOS transistor 16 and resistor 12 is DC-coupled to the connection node of the cathode of light emitting element LD and bias current supply circuit 68.
- capacitor 19 is connected between the node to which the fixed voltage is supplied and the connection node of resistor 11 and resistor 12.
- Such a configuration makes it possible to provide an appropriate circuit that stabilizes the potential of the connection node of the termination resistor 11 and the termination resistor 12.
- the differential drive circuit 41 is configured to include a single-stage transistor circuit, the present invention is not limited to this.
- the differential drive circuit 41 may be configured to include a plurality of stages of transistor circuits. In this case, it is sufficient if a DC power supply current is supplied from the light emitting circuit 75 to the circuit of the final stage.
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Abstract
Description
INE=Vf/(Rout+Rdamp)
y=Imod+[{Vf+(Rd+Rdamp)×Imod}/Rout]
x=Ibias+Vf/(Rout+Rdamp)
x=Ibias+45.2
INE=Vf/{2×(Rout+Rdamp)
y=Imod+[{Vf+(Rd+Rdamp)×Imod}/Rout]
x=Ibias+Vf/{2×(Rout+Rdamp)}
x=Ibias+22.6
INE=Vf/{2×(Rout+Rdamp)
y=Imod+[{Vf+(Rd+Rdamp)×Imod}/Rout]
x=Ibias+Vf/{2×(Rout+Rdamp)}
x=Ibias+22.6
15,16 NチャネルMOSトランジスタ
17 フィルタ回路
19 キャパシタ
21 光トランシーバ
22 PON受信処理部
23 バッファメモリ
24 UN送信処理部
25 UNIポート
26 UN受信処理部
27 バッファメモリ
28 PON送信処理部
29 制御部
31,32 インダクタ
33 電流源
41 差動駆動回路
51~53 駆動回路
61 プリバッファ回路
62 イコライザ回路
63 出力バッファ回路(変調電流供給回路)
64~66 電流源
67 タイミング回路
68 バイアス電流供給回路
69 マスタI/F(インタフェース)
70 CPU
71 スレイブI/F
72 制御レジスタ
73 記憶部
75 発光回路
201 局側装置
202A,202B,202C,202D 宅側装置
301 PONシステム
C1,C2 キャパシタ
LD 発光素子
SP1,SP2 スプリッタ
OPTF 光ファイバ
Claims (5)
- 光信号を送信するための発光素子を含む発光回路における前記発光素子にバイアス電流を供給するためのバイアス電流供給回路と、
送信すべきデータの論理値に応じた大きさの変調電流を前記発光素子に供給するための変調電流供給回路とを備え、
前記変調電流供給回路は、
前記データの論理値に応じて、前記発光素子に電流を供給するか否かを切り替えるための差動駆動回路と、
前記差動駆動回路の差動出力間に接続された終端抵抗とを含み、
前記差動駆動回路および前記発光回路は直流結合されており、前記差動駆動回路が前記発光素子に供給する前記電流の電源は前記発光回路から供給される、駆動回路。 - 前記終端抵抗は、固定電圧が供給されるノードと前記発光回路を経由せずに交流結合されている、請求項1に記載の駆動回路。
- 前記差動駆動回路は、
前記発光素子の第1端に直流結合された第1導通電極と、第2導通電極とを有する第1のトランジスタと、
前記発光素子の第2端に直流結合された第1導通電極と、前記第1のトランジスタの第2導通電極と電気的に接続された第2導通電極とを有する第2のトランジスタと、
前記第1のトランジスタの第1導通電極および前記第2のトランジスタの第1導通電極間に直列接続された第1の終端抵抗および第2の終端抵抗とを含み、
前記第1のトランジスタの第1導通電極および前記第1の終端抵抗の接続ノードが前記発光素子の第1端および直流電源電圧が供給されるノードの接続ノードと直流結合され、
前記第2のトランジスタの第1導通電極および前記第2の終端抵抗の接続ノードが前記発光素子の第2端および前記バイアス電流供給回路の接続ノードと直流結合されている、
請求項1または請求項2に記載の駆動回路。 - 前記変調電流供給回路は、さらに、
固定電圧が供給されるノードと前記第1の終端抵抗および前記第2の終端抵抗の接続ノードとの間に接続されたキャパシタを含む、請求項3に記載の駆動回路。 - 複数の宅側装置から局側装置への光信号が時分割多重される通信システムにおける宅側装置であって、
前記光信号を送信するための発光素子を含む発光回路と、
前記発光素子を駆動するための駆動回路とを備え、
前記駆動回路は、
前記発光素子にバイアス電流を供給するためのバイアス電流供給回路と、
送信すべきデータの論理値に応じた大きさの変調電流を前記発光素子に供給するための変調電流供給回路とを含み、
前記変調電流供給回路は、
前記データの論理値に応じて、前記発光素子に電流を供給するか否かを切り替えるための差動駆動回路と、
前記差動駆動回路の差動出力間に接続された終端抵抗とを含み、
前記差動駆動回路および前記発光回路は直流結合されており、前記差動駆動回路が前記発光素子に供給する前記電流の電源は前記発光回路から供給される、宅側装置。
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JP2018502459A (ja) * | 2014-12-31 | 2018-01-25 | メイコム テクノロジー ソリューションズ ホールディングス インコーポレイテッド | Ac結合終端素子を有するdc結合レーザドライバ |
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TWI750216B (zh) | 2016-08-30 | 2021-12-21 | 美商Macom技術方案控股公司 | 具分散式架構之驅動器 |
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