WO2013031154A1 - 半導体ウエハの製造方法及び半導体ウエハ - Google Patents
半導体ウエハの製造方法及び半導体ウエハ Download PDFInfo
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- WO2013031154A1 WO2013031154A1 PCT/JP2012/005301 JP2012005301W WO2013031154A1 WO 2013031154 A1 WO2013031154 A1 WO 2013031154A1 JP 2012005301 W JP2012005301 W JP 2012005301W WO 2013031154 A1 WO2013031154 A1 WO 2013031154A1
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- semiconductor wafer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 239000013078 crystal Substances 0.000 claims abstract description 108
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 80
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 79
- 238000010438 heat treatment Methods 0.000 claims abstract description 63
- 239000007791 liquid phase Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 48
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000012071 phase Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 189
- 229910010271 silicon carbide Inorganic materials 0.000 description 121
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 52
- 229910052751 metal Inorganic materials 0.000 description 34
- 239000002184 metal Substances 0.000 description 34
- 239000000463 material Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 229910003468 tantalcarbide Inorganic materials 0.000 description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 239000002904 solvent Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000009036 growth inhibition Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000002452 interceptive effect Effects 0.000 description 2
- 239000002086 nanomaterial Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 2
- QIJNJJZPYXGIQM-UHFFFAOYSA-N 1lambda4,2lambda4-dimolybdacyclopropa-1,2,3-triene Chemical compound [Mo]=C=[Mo] QIJNJJZPYXGIQM-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910039444 MoC Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910026551 ZrC Inorganic materials 0.000 description 1
- OTCHGXYCWNXDOA-UHFFFAOYSA-N [C].[Zr] Chemical compound [C].[Zr] OTCHGXYCWNXDOA-UHFFFAOYSA-N 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- WHJFNYXPKGDKBB-UHFFFAOYSA-N hafnium;methane Chemical compound C.[Hf] WHJFNYXPKGDKBB-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004949 mass spectrometry Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000001247 metal acetylides Chemical class 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000007666 vacuum forming Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B19/00—Liquid-phase epitaxial-layer growth
- C30B19/02—Liquid-phase epitaxial-layer growth using molten solvents, e.g. flux
- C30B19/04—Liquid-phase epitaxial-layer growth using molten solvents, e.g. flux the solvent being a component of the crystal composition
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B19/00—Liquid-phase epitaxial-layer growth
- C30B19/12—Liquid-phase epitaxial-layer growth characterised by the substrate
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/36—Carbides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02378—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/02447—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02625—Liquid deposition using melted materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
Definitions
- the present invention relates to a method for manufacturing a semiconductor wafer using a substrate having at least a surface made of SiC.
- silicon (Si), gallium arsenide (GaAs), and the like are conventionally known.
- the field of application of high-frequency devices has been rapidly expanding in recent years, and along with this, opportunities for use in severe areas such as high-temperature environments have increased. Therefore, the realization of a high-frequency device that can withstand a high temperature environment is one of the important issues for improving operation reliability and a large amount of information processing / controllability in a wide range of application environments.
- SiC Silicon carbide
- SiC has attracted attention as one of the materials for producing a semiconductor wafer having excellent heat resistance.
- SiC is excellent in mechanical strength and resistant to radiation.
- SiC can easily control valence electrons of electrons and holes by adding impurities, and has a wide forbidden band width (about 3.0 eV for 6H type single crystal SiC and 3.2 eV for 4H type single crystal SiC. ), High breakdown electric field (4H type single crystal SiC, about 10 times that of Si or GaAs, 2.8 MV / cm), electron saturation drift velocity (4H type single crystal SiC, about 2 times that of Si). 2 ⁇ 10 7 cm / s). For these reasons, SiC is expected as a material for next-generation power devices that can realize high temperatures, high frequencies, withstand voltages, and environmental resistance that cannot be realized with the above-described existing semiconductor materials.
- Patent Documents 1 to 3 disclose such a manufacturing method.
- the SiC epitaxial layer is formed by a CVD (Chemical Vapor Deposition) method.
- CVD Chemical Vapor Deposition
- the epitaxial growth step it is possible to form a SiC epitaxial layer with few defects by introducing a defect generation inhibiting layer whose growth rate is suppressed to 1 ⁇ m or less per hour.
- Patent Document 2 discloses the following method for forming an SiC epitaxial layer. That is, the method for forming the SiC epitaxial layer includes a step of growing a bulk crystal of SiC using a seed crystal addition sublimation technique and a step of liquid phase epitaxial growth on the surface of the bulk crystal. In the liquid phase epitaxial growth step, by performing melt growth, micropipe defects propagated from the seed crystal to the bulk crystal substrate can be blocked, and an SiC epitaxial layer with few micropipe defects can be formed. Become.
- a metastable solvent epitaxy (MSE) method is disclosed as a method for causing near-liquid phase epitaxial growth of single crystal SiC.
- MSE metastable solvent epitaxy
- a seed substrate made of single crystal SiC and a carbon supply feed substrate having a higher free energy than the seed substrate are arranged to face each other, and a Si melt layer is formed between the seed substrate and the carbon supply feed substrate. It intervenes as a solvent (carbon transfer medium).
- the single crystal SiC is epitaxially grown on the surface of the seed substrate by heat-treating the seed substrate and the carbon supply feed substrate in a vacuum high temperature environment.
- Patent Documents 1 to 3 require a seed substrate composed of single crystal SiC in order to form an epitaxial layer composed of single crystal SiC.
- a substrate made of single crystal SiC is very expensive, the methods of Patent Documents 1 to 3 increase the manufacturing cost of semiconductor devices.
- the present invention has been made in view of the above circumstances, and an object thereof is a method for manufacturing a semiconductor wafer in which an epitaxial layer of single-crystal SiC is formed on the surface of a substrate.
- the object is to provide a method capable of calibrating.
- this semiconductor wafer manufacturing method includes a carbon layer forming step, a through-hole forming step, a feed layer forming step, and an epitaxial layer forming step.
- a carbon layer is formed on the surface of the substrate having at least the surface made of polycrystalline SiC.
- a through hole is formed in the carbon layer by irradiating the carbon layer formed on the substrate with a laser beam or the like.
- an Si layer is formed on the surface of the carbon layer formed on the substrate, and a feed layer composed of polycrystalline SiC is formed on the surface of the Si layer.
- the substrate is subjected to a heat treatment in a temperature range of 1600 ° C. or higher and 2300 ° C. or lower so that the surface of the substrate exposed through the through hole is made of 4H—SiC single crystal.
- the seed crystal is grown in a near liquid phase epitaxial manner to form an epitaxial layer composed of 4H—SiC single crystal.
- a semiconductor wafer can be manufactured using a substrate having at least a surface made of polycrystalline SiC. Since a substrate made of polycrystalline SiC is less expensive than a substrate made of single crystal SiC, the manufacturing cost of a semiconductor wafer can be reduced. Further, since a substrate having a larger diameter can be obtained as a substrate made of polycrystalline SiC than a substrate made of single crystal SiC, a semiconductor wafer having a larger diameter can be manufactured.
- the following is preferable. That is, a plurality of grooves or walls are formed on the surface of the substrate. In the through hole forming step, the through hole is formed for each region surrounded by the groove or the wall. In the epitaxial layer forming step, the epitaxial layer composed of 4H—SiC single crystal is formed for each region.
- a semiconductor wafer on which an epitaxial layer for a plurality of chips is formed can be manufactured with high quality in a shorter growth time than growing from a single seed crystal to the entire area of the wafer.
- heating is performed in a vacuum range of 1500 ° C. to 2300 ° C. and 10 ⁇ 2 Torr or less, preferably 10 ⁇ 5 Torr or less.
- the carbon layer is formed by sublimating Si atoms on the surface of the substrate.
- the carbon layer in the semiconductor wafer manufacturing method, in the carbon layer forming step, the carbon layer may be formed by a chemical vapor deposition method, an organic resist method, or an electron cyclotron resonance sputtering method.
- the method for manufacturing a semiconductor wafer it is preferable that through holes are formed using infrared laser light in the through hole forming step, and the spot diameter of the laser light is 100 ⁇ m or less, preferably 50 ⁇ m or less.
- the epitaxial growth rate in the horizontal direction (a-axis direction) of the epitaxial layer composed of 4H—SiC single crystal is controlled in the thickness direction by controlling the heat treatment temperature. It can grow 5 to 10 times faster than the epitaxial growth rate in the (c-axis direction).
- a semiconductor wafer having the following configuration is provided. That is, this semiconductor wafer is manufactured by the semiconductor wafer manufacturing method described above, and the horizontal direction of the epitaxial layer composed of 4H—SiC single crystal is controlled by controlling the heat treatment temperature at which the seed crystal is grown in near liquid phase epitaxial growth (The dimension in the (a-axis direction) is controlled to an aspect ratio of 5 to 10 times the dimension in the thickness direction (c-axis direction).
- FIG. 5 is a process diagram showing the first half of a method for manufacturing a semiconductor wafer in which a 4H—SiC single crystal layer is formed using a polycrystalline SiC substrate having a groove formed at the boundary of a semiconductor device.
- the process figure which shows the second half of the manufacturing method of the semiconductor wafer which forms a 4H-SiC single-crystal layer using the polycrystalline SiC substrate of the structure which formed the groove part in the boundary of a semiconductor device.
- a cross-sectional photomicrograph showing an example of a polycrystalline SiC substrate and a carbon layer formed on the surface of the substrate.
- the microscope picture which shows an example of the through-hole formed in the carbon layer by laser irradiation.
- the microscope picture which shows an example of the epitaxial layer in the middle of growing from the through-hole formed in the carbon layer.
- FIG. 5 is a process diagram showing the first half of a method for manufacturing a semiconductor wafer in which a 4H—SiC single crystal layer is formed using a polycrystalline SiC substrate having a structure in which a wall is formed at the boundary of a semiconductor device.
- the process figure which shows the second half of the manufacturing method of the semiconductor wafer which forms a 4H-SiC single crystal layer using the polycrystalline SiC substrate of the structure which formed the wall part in the boundary of a semiconductor device.
- the graph which shows the relationship between the growth rate and the thickness of Si melt in several growth temperature.
- FIG. 1 is a schematic view showing a high-temperature vacuum furnace 11 used for heat treatment for manufacturing a semiconductor wafer.
- FIG. 2 is a cross-sectional view showing the main heating chamber 21 and the preheating chamber 22 of the high-temperature vacuum furnace 11 in detail.
- FIG. 3A is an external view photograph of the crucible 2 taken from above, and
- FIG. 3B is a cross-sectional micrograph of the crucible 2.
- the high-temperature vacuum furnace 11 includes a main heating chamber 21 capable of heating the object to be processed to a temperature of 1000 ° C. to 2300 ° C., and a temperature of the object to be processed of 500 ° C. or more. And a preheating chamber 22 that can be preheated.
- the preheating chamber 22 is disposed below the main heating chamber 21 and is adjacent to the main heating chamber 21 in the vertical direction.
- the high-temperature vacuum furnace 11 includes a heat insulating chamber 23 disposed below the preheating chamber 22. The heat insulation chamber 23 is adjacent to the preheating chamber 22 in the vertical direction.
- the high-temperature vacuum furnace 11 includes a vacuum chamber 19, and the main heating chamber 21 and the preheating chamber 22 are provided inside the vacuum chamber 19.
- a turbo molecular pump 34 as a vacuum forming device is connected to the vacuum chamber 19 so that a vacuum of, for example, 10 ⁇ 2 Pa or less, preferably 10 ⁇ 7 Pa or less can be obtained in the vacuum chamber 19. Yes.
- a gate valve 25 is interposed between the turbo molecular pump 34 and the vacuum chamber 19. Further, an auxiliary rotary pump 26 is connected to the turbo molecular pump 34.
- the high-temperature vacuum furnace 11 includes a moving mechanism 27 that can move an object to be processed in the vertical direction between the preheating chamber 22 and the main heating chamber 21.
- the moving mechanism 27 includes a support body 28 that can support an object to be processed, and a cylinder portion 29 that can move the support body 28 up and down.
- the cylinder portion 29 includes a cylinder rod 30, and one end of the cylinder rod 30 is connected to the support body 28.
- the high-temperature vacuum furnace 11 is provided with a vacuum gauge 31 for measuring the degree of vacuum and a mass analyzer 32 for performing mass spectrometry.
- the vacuum chamber 19 is connected to a stock chamber (not shown) for storing an object to be processed through a transfer path 65.
- the transport path 65 can be opened and closed by a gate valve 66.
- the main heating chamber 21 is formed in a regular hexagonal shape in a plan sectional view and is disposed in the upper part of the internal space of the vacuum chamber 19. As shown in FIG. 2, a mesh heater 33 as a heater is provided inside the main heating chamber 21.
- a first multilayer heat reflecting metal plate 41 is fixed to the side wall and ceiling of the main heating chamber 21, and the heat of the mesh heater 33 is directed toward the center of the main heating chamber 21 by the first multilayer heat reflecting metal plate 41. It is configured to reflect.
- the mesh heater 33 is disposed so as to surround the object to be heat-treated in the main heating chamber 21 and the multilayer heat-reflecting metal plate 41 is further disposed outside the mesh heater 33. Accordingly, the object to be processed can be heated strongly and evenly, and the temperature can be raised to a temperature of 1000 ° C. or higher and 2300 ° C. or lower.
- the ceiling side of the main heating chamber 21 is closed by the first multilayer heat-reflecting metal plate 41, while a through-hole 55 is formed in the first multilayer heat-reflecting metal plate 41 on the bottom surface.
- the object to be processed can move between the main heating chamber 21 and the preheating chamber 22 adjacent to the lower side of the main heating chamber 21 through the through hole 55.
- the support 28 has a configuration in which a second multilayer heat-reflecting metal plate 42, a third multilayer heat-reflecting metal plate 43, and a fourth multilayer heat-reflecting metal plate 44 are arranged at intervals from each other in order from the top. .
- the three multilayer heat-reflecting metal plates 42 to 44 are all arranged horizontally and connected to each other by a column portion 35 provided in the vertical direction.
- the receiving stand 36 is arrange
- the cradle 36 is made of tantalum carbide.
- a flange is formed at the end of the cylinder rod 30 of the cylinder portion 29, and this flange is fixed to the lower surface of the fourth multilayer heat reflecting metal plate 44.
- the preheating chamber 22 is configured by surrounding the lower space of the main heating chamber 21 with a multilayer heat reflecting metal plate 46.
- the preheating chamber 22 is configured to be circular in a plan sectional view. In the preheating chamber 22, no heating means such as the mesh heater 33 is provided.
- a through hole 56 is formed in the multilayer heat reflecting metal plate 46 at the bottom surface of the preheating chamber 22. Further, in the multilayer heat reflecting metal plate 46 that forms the side wall of the preheating chamber 22, a passage hole 50 is formed in a portion facing the transport path 65. Further, the high temperature vacuum furnace 11 includes an opening / closing member 51 capable of closing the passage hole 50.
- the heat insulating chamber 23 adjacent to the lower side of the preheating chamber 22 is partitioned by the multilayer heat reflecting metal plate 46 on the upper side and by the multilayer heat reflecting metal plate 47 on the lower side and the side portion.
- a through-hole 57 is formed in the multilayer heat reflecting metal plate 47 covering the lower side of the heat insulating chamber 23 so that the cylinder rod 30 can be inserted.
- a storage recess 58 is formed in the multilayer heat reflecting metal plate 47.
- the storage recess 58 can store the fourth multilayer heat-reflecting metal plate 44 provided in the support 28.
- Each of the multilayer heat reflecting metal plates 41 to 44, 46, 47 has a structure in which metal plates (made of tungsten) are laminated at a predetermined interval. Also in the opening / closing member 51, a multilayer heat reflecting metal plate having the same configuration is used for a portion that closes the passage hole 50.
- any material can be used for the multilayer heat-reflecting metal plates 41 to 44, 46, 47 as long as the material has sufficient heating characteristics against the heat radiation of the mesh heater 33 and has a melting point higher than the ambient temperature.
- refractory metal materials such as tantalum, niobium, and molybdenum can be used as the multilayer heat reflecting metal plates 41 to 44, 46, and 47 in addition to the tungsten.
- carbides such as tungsten carbide, zirconium carbide, tantalum carbide, hafnium carbide, molybdenum carbide, etc. can be used as the multilayer heat reflecting metal plates 41 to 44, 46, 47.
- an infrared reflection film made of gold, tungsten carbide or the like may be further formed on the reflection surface.
- the multilayer heat-reflecting metal plates 42 to 44 provided in the support 28 have a structure in which a punch metal structure tungsten plate having a large number of small through-holes is laminated at a predetermined interval while varying the positions of the through-holes. It has become.
- the number of stacked second multilayer heat reflecting metal plates 42 provided in the uppermost layer of the support 28 is smaller than the number of stacked first multilayer heat reflecting metal plates 41 in the main heating chamber 21.
- an object to be processed (for example, a SiC substrate) is stored in an appropriate container in order to prevent contamination in the vacuum chamber 19.
- the container may be a crucible 2 described later, or may be another container.
- the object to be processed is introduced into the vacuum chamber 19 from the transport path 65 and placed on the cradle 36 in the preheating chamber 22.
- the mesh heater 33 is driven in this state, the main heating chamber 21 is heated to a predetermined temperature (for example, about 1800 ° C.) between 1,000 ° C. and 2300 ° C.
- the pressure in the vacuum chamber 19 is adjusted to 10 ⁇ 3 or less, preferably 10 ⁇ 5 or less by driving the turbo molecular pump 34.
- the number of stacked second multilayer heat reflecting metal plates 42 of the support 28 is smaller than the number of stacked first multilayer heat reflecting metal plates 41. Therefore, a part of the heat generated by the mesh heater 33 is appropriately supplied (distributed) to the preheating chamber 22 via the second multilayer heat reflecting metal plate 42, and the SiC substrate in the preheating chamber 22 is heated to 500 ° C. or more. Preheating can be performed so as to reach a predetermined temperature (for example, 800 ° C.). That is, preheating can be realized without installing a heater in the preheating chamber 22, and a simple structure of the preheating chamber 22 can be realized.
- a predetermined temperature for example, 800 ° C.
- the cylinder part 29 is driven and the support 28 is raised.
- the SiC substrate passes through the through hole 55 from the lower side and moves into the main heating chamber 21.
- the main heat treatment is immediately started, and the SiC substrate in the main heating chamber 21 can be rapidly heated to a predetermined temperature (about 1800 ° C.).
- the crucible 2 includes an upper container 2a and a lower container 2b that can be fitted to each other.
- the crucible 2 is made of tantalum metal and is configured to expose the tantalum carbide layer to the internal space.
- the crucible 2 has a TaC layer formed on the outermost layer, a Ta 2 C layer formed on the inner side of the TaC layer, and a base layer on the inner side.
- the tantalum metal as the material is arranged.
- the crucible 2 has TaC having a high carbon concentration disposed in the surface layer portion and Ta 2 C having a slightly low carbon concentration disposed inside.
- it is the structure which has arrange
- the crucible 2 When the crucible 2 is heat-treated, it is placed in the preheating chamber 22 of the high-temperature vacuum furnace 11 as shown by the chain line in FIG. 2 and preheated at an appropriate temperature (for example, about 800 ° C.). Next, the crucible 2 in the preheating chamber 22 is moved to the main heating chamber 21 that has been heated up to a preset temperature (for example, about 1800 ° C.) by driving the cylinder portion 29, and the temperature is rapidly increased.
- a preset temperature for example, about 1800 ° C.
- the atmosphere in the crucible 2 is preferably maintained at a vacuum of about 1 Pa or less during heating in the main heating chamber 21. Note that the vacuum in the crucible 2 is realized in a state where the upper container 2a is removed or by a gap between the fitting portions of the upper container 2a and the lower container 2b.
- a semiconductor wafer is manufactured from a substrate using the high-temperature vacuum furnace 11 and the crucible 2 configured as described above.
- the high temperature vacuum furnace 11 described above is used when the CVD method, heat treatment, or the like is used.
- FIG. 4 is a schematic view of a split-type semiconductor wafer.
- a semiconductor wafer is a base for a plurality of chips of a semiconductor device. Grooves or walls are formed in the semiconductor wafer so as to delimit one chip size of the semiconductor device. By dividing the semiconductor wafer by the groove or wall, the semiconductor wafer can be divided for each chip size.
- FIGS. 5 and 6 are process diagrams showing a method of manufacturing a semiconductor wafer in which a 4H—SiC single crystal layer is formed using a polycrystalline SiC substrate 70 having a structure in which a groove is formed at the boundary of a semiconductor device.
- a polycrystalline SiC substrate 70 having a plurality of groove portions 70a and convex portions 70b delimited by the groove portions 70a is prepared.
- the groove 70a is formed by appropriate means such as thermal etching or polishing, and one of the protrusions 70b has a size corresponding to one chip size of the semiconductor device.
- a carbon layer forming step for forming the carbon layer 71 on the surface of the substrate 70 is performed.
- the carbon layer forming step is performed using the high temperature vacuum furnace 11 and the crucible 2.
- the substrate 70 is accommodated in the crucible 2.
- Si on the surface of the substrate 70 is sublimated, and a carbon layer 71 is formed on the surface of the substrate 70 by the remaining C (FIG. 5). (See (b)).
- the heat treatment in the carbon layer forming step preferably includes a preheating step and a main heating step.
- the preheating step the crucible 2 containing the substrate 70 is heated at a temperature of 800 ° C. or higher in the preheating chamber.
- the main heating step the crucible 2 is moved from the preheating chamber to a main heating chamber heated in advance at a temperature of 1500 ° C. to 2300 ° C., whereby the substrate 70 is heated to a temperature of 1500 ° C. to 2300 ° C. Heat.
- the carbon layer forming step can be efficiently performed in a short time by moving the preheating chamber to the main heating chamber and performing the heat treatment by rapidly raising the temperature.
- the carbon layer 71 is configured to have a plurality of groove portions 71a and convex portions 71b.
- a through hole forming step for forming a through hole in the carbon layer 71 is performed.
- This through hole is formed using a laser device.
- an infrared laser device is used as the laser device.
- the laser device used in the through hole forming step is not limited to the infrared laser device, and other laser devices can be used as long as the output of the laser beam can be adjusted so as to remove only the carbon layer 71 without damaging the substrate 70. Can be used.
- the laser device is preferably adjustable so that the spot diameter (the diameter of the laser light when the target is irradiated with laser light) is 50 ⁇ m or less. In this step, the central portion of the plurality of convex portions 71b is irradiated with laser light.
- a feeder layer forming step for forming a feeder layer on the surface of the substrate 70 is performed.
- Si is deposited on the surface of the carbon layer 71 by the CVD method to form the Si layer 72.
- a 3C—SiC polycrystalline layer 73 is deposited by a CVD method so as to cover the Si layer 72 (see FIG. 5D).
- an epitaxial layer forming step for forming a 4H—SiC single crystal layer is performed.
- heat treatment is performed in a rare gas atmosphere in which an inert gas is introduced into a vacuum.
- the heat treatment is preferably performed in the range of 1600 ° C. or higher and 2300 ° C. or lower. Note that the aspect ratio of the epitaxial layer (4H—SiC single crystal layer) can be controlled by adjusting the heat treatment temperature (details will be described later).
- the Si layer 72 is melted inside the 3C—SiC polycrystalline layer 73, and the Si melt layer 72a is inside the 3C—SiC polycrystalline layer 73 as shown in FIG. Formed with. Since this Si melt layer 72a functions like a carbon transfer medium, the heat treatment is continued so that a seed composed of 4H—SiC single crystal is formed on the surface of the substrate 70 exposed by the through hole 71c. Crystal 74 is formed (see FIG. 6E). In addition, the microscope picture which image
- the 4H—SiC seed crystal 74 is grown in the near liquid phase epitaxial manner by the metastable solvent epitaxy method (MSE method), and the 4H—SiC single crystal layer 74a is formed (FIG. 6). (See (f)).
- the MSE method here refers to a seed layer and a feed layer having a higher free energy than the seed layer, and a Si melt layer having a small thickness interposed between both layers as a solvent, so that a vacuum high temperature It is a method of heat treatment in the environment.
- the 4H—SiC single crystal can be grown in the near-liquid phase epitaxial growth on the seed layer side using the concentration gradient (concentration gradient not based on the temperature gradient) generated in the Si melt layer based on the difference in free energy as the driving force. it can.
- the 4H—SiC single crystal layer 74a seed crystal 74
- the 3C—SiC polycrystalline layer 73 having higher free energy than the seed layer functions as a feed layer.
- a concentration gradient is generated in the Si molten layer based on the difference in free energy between the 4H—SiC single crystal layer 74a and the 3C—SiC polycrystalline layer 73, and this concentration gradient becomes a driving force.
- Si and C are eluted from the 3C—SiC polycrystalline layer 73 into the Si melt layer 72a.
- C taken into the Si melt layer 72a moves to the 4H—SiC single crystal layer 74a side, and bonds therewith, whereby the 4H—SiC single crystal layer 74a grows in a near liquid phase epitaxial manner.
- the semiconductor device can be efficiently manufactured by effectively utilizing the region of the substrate 70.
- FIGS. 10 and 11 are process diagrams showing a method for manufacturing a semiconductor wafer in which a 4H—SiC single crystal layer is formed using a polycrystalline SiC substrate having a structure in which a wall is formed at the boundary of a semiconductor device.
- the description of the process similar to the process when the groove is formed at the boundary may be simplified or omitted.
- a polycrystalline SiC substrate 80 having a plurality of wall portions 80a and recesses 80b separated by the wall portions 80a is prepared.
- the recess 80b is formed by an appropriate means such as thermal etching or polishing, and one of the recesses 80b has a size corresponding to the semiconductor device 1 chip size.
- a carbon layer forming process for forming the carbon layer 81 on the substrate 80 is performed.
- the substrate 80 is accommodated in the crucible 2 as in the first embodiment, and the inside of the crucible 2 is kept at a high temperature and in a vacuum state by the high temperature vacuum furnace 11.
- Si on the surface of the substrate 80 is sublimated, and the carbon layer 81 is formed on the surface of the substrate 80 due to the remaining C (see FIG. 10B).
- the wall portion 81a is formed on the carbon layer 81 at a position corresponding to the wall portion 80a. Therefore, the carbon layer 81 has a configuration having a plurality of wall portions 81a and concave portions 81b.
- a through hole forming step for forming a through hole in the formed carbon layer 81 is performed.
- This through hole is formed using an infrared laser device in the same manner as described above.
- laser light is irradiated to the central portions of the plurality of recesses 81b.
- part of the carbon layer 81 can be removed to form the through hole 81c (see FIG. 10C). And the surface of the board
- a feeder layer forming step for forming a feeder layer on the surface of the substrate 80 is performed.
- Si is deposited on the surface of the carbon layer 81 by a CVD method to form the Si layer 72.
- a 3C—SiC polycrystalline layer 73 is deposited by a CVD method so as to cover the Si layer 72 (see FIG. 10D).
- an epitaxial layer forming step for forming a 4H—SiC single crystal layer is performed.
- heat treatment is performed in the range of 1600 ° C. to 2300 ° C. using the high-temperature vacuum furnace 11.
- the Si layer 72 is melted inside the 3C—SiC polycrystalline layer 73, and the Si melt layer 72a is inside the 3C—SiC polycrystalline layer 73 as shown in FIG. Formed with.
- a seed crystal 74 composed of 4H—SiC single crystal is generated on the surface of the substrate 80 exposed through the through hole 81c (see FIG. 11E).
- the seed crystal 74 is epitaxially grown to form the 4H—SiC single crystal layer 74a (see FIG. 11F).
- the wall portion 81a is formed between the recesses 81b, the adjacent 4H—SiC single crystal layers 74a are prevented from interfering with each other in the epitaxial layer forming step. . Thereby, a semiconductor device can be efficiently manufactured by effectively utilizing the region of the substrate 80.
- FIG. 12 is a graph showing the relationship between the growth rate and the thickness of the Si melt at a plurality of growth temperatures.
- the vertical axis of the graph in FIG. 12 indicates the growth rate of the 4H—SiC single crystal layer, and the horizontal axis indicates the reciprocal of the thickness of the Si melt layer.
- the graph of FIG. 12 shows the relationship between the thickness of the Si melt layer and the growth rate of the 4H—SiC single crystal layer when the growth temperatures are 1500 ° C., 1700 ° C., 1800 ° C., and 1900 ° C., respectively. Show.
- This graph shows that the growth rate of the 4H—SiC single crystal layer decreases at each growth temperature as the thickness of the Si melt layer increases. This is presumably because as the thickness of the Si melt layer increases, the 3C—SiC polycrystalline layer and the 4H—SiC single crystal layer are separated from each other, so that it takes time to move C atoms.
- FIG. 13 is a graph showing the growth rate change in the a-axis direction and the c-axis direction and the change in the aspect ratio of the growth rate in the a-axis direction with respect to the c-axis direction on the Si surface of the 4H—SiC single crystal.
- FIG. 14 is a graph showing the growth rate change in the a-axis direction and the c-axis direction and the change in the aspect ratio of the growth rate in the a-axis direction with respect to the c-axis direction in the C plane of the 4H—SiC single crystal.
- the vertical axis represents the growth rate of the 4H-SiC single crystal
- the horizontal axis represents the growth temperature.
- the graphs of FIGS. 13 and 14 show the growth rate and growth temperature when the plane (Si plane or C plane) and the direction (a-axis direction or c-axis direction) of the 4H—SiC single crystal are different. Showing the relationship.
- FIG. 13 shows the relationship between the growth rate and the growth temperature on the Si surface of the 4H—SiC single crystal.
- FIG. 13A shows the relationship between the growth rate in the a-axis direction and the growth temperature
- FIG. 13B shows the relationship between the growth rate in the c-axis direction and the growth temperature. From the graph of FIG. 13A, it can be seen that the growth rate in the a-axis direction tends to increase as the growth temperature is increased.
- the graph of FIG. 13B shows that the growth rate in the c-axis direction tends to decrease as the growth temperature is increased.
- FIG. 13C is a graph showing a change in the aspect ratio of the growth rate in the a-axis direction with respect to the c-axis direction, and it can be seen that the aspect ratio increases as the growth temperature is increased.
- the 4H—SiC single crystal has the property that the growth rate ratio (growth rate in the a-axis direction / growth rate in the c-axis direction) changes according to the change in the growth temperature. Therefore, the growth rate ratio can be controlled by setting the growth temperature.
- the 4H—SiC single crystal layer 74a having a desired aspect ratio can be formed. Further, by further considering the thickness of the Si melt layer 72a shown in FIG. 12 in addition to the growth temperature, specific growth rates in the horizontal direction (a-axis direction) and the vertical direction (c-axis direction) are estimated. be able to. Thereby, the 4H—SiC single crystal layer 74a having a desired shape can be formed.
- the semiconductor wafer manufacturing method of the present embodiment includes a carbon layer forming step, a through-hole forming step, a feed layer forming step, and an epitaxial layer forming step.
- the carbon layer forming step the carbon layers 71 and 81 are formed on the surfaces of the substrates 70 and 80 having at least the surfaces made of polycrystalline SiC.
- the through hole forming step the carbon layers 71 and 81 formed on the substrates 70 and 80 are irradiated with laser light to form the through holes 71 c and 81 c in the carbon layers 71 and 81.
- the Si layer 72 is formed on the surfaces of the carbon layers 71 and 81 formed on the substrates 70 and 80, and the 3C—SiC polycrystalline layer 73 is formed on the surface of the Si layer 72.
- the epitaxial layer forming step 4H—SiC single crystal is formed on the surfaces of the substrates 70 and 80 exposed through the through holes 71c and 81c by performing heat treatment on the substrates 70 and 80 in a temperature range of 1600 ° C. to 2300 ° C.
- the seed crystal 74 is formed, and the heat treatment is continued, so that the seed crystal 74 is grown in the near liquid phase epitaxial manner to form the 4H—SiC single crystal layer 74a.
- a semiconductor wafer can be manufactured using a substrate having at least a surface made of polycrystalline SiC. Therefore, the manufacturing cost of the semiconductor wafer can be reduced, and a large-diameter semiconductor wafer can be manufactured.
- a plurality of groove portions 70a or wall portions 80a are formed on the surfaces of the substrates 70 and 80.
- a through hole is formed for each region surrounded by the groove part 70a or the wall part 80a.
- a 4H—SiC single crystal layer 74a is formed for each region.
- the semiconductor wafer on which the 4H—SiC single crystal layer 74a for a plurality of chips is formed can be manufactured with high quality in a shorter growth time than growing from the single seed crystal to the entire area of the wafer.
- Si is formed on the surface of the substrate by heating under a vacuum in a temperature range of 1500 ° C. to 2300 ° C. and 10 ⁇ 5 Torr or less.
- the carbon layers 71 and 81 are formed by sublimating atoms.
- the laser beam used in the through hole forming step is an infrared laser beam and has a spot diameter of 50 ⁇ m or less.
- the areas of the substrates 70 and 80 exposed through the through holes 71c and 81c are reduced, a single seed crystal is generated in each through hole, and a plurality of seed crystals are generated and contacted in the through holes.
- the seed crystal 74 can be appropriately generated by suppressing the growth inhibition due to the formation of crystal dislocations and the occurrence of crystal dislocation at the contact portion.
- the relationship between the epitaxial growth rate in the a-axis direction of the 4H—SiC single crystal and the temperature, and the relationship between the epitaxial growth rate in the c-axis direction of the 4H—SiC single crystal and the temperature By setting the heat treatment temperature during the epitaxial layer formation step based on the relationship, the aspect ratio of the 4H—SiC single crystal layer 74a can be set so that the dimension of the epitaxial layer in the horizontal direction (a-axis direction) is the thickness direction (c The axial dimension is adjusted to 5 to 10 times.
- the shape of the polycrystalline SiC substrate shown in FIG. 5 and FIG. 10 is an example, and can be appropriately changed according to the required one-chip size.
- the carbon layer 71 is formed on the surface of the substrate 70 (or the substrate 80) by heating in a high temperature and vacuum state with the high temperature vacuum furnace 11, but this method of forming the carbon layer It is not limited to the method.
- the carbon layer can be formed using a known technique such as a CVD method, an organic resist method, or an electron cyclotron resonance sputtering method.
- Si and 3C—SiC polycrystal are deposited on the surface of the carbon layer by the CVD method, but this is a form in which the Si substrate and the polycrystalline SiC substrate are stacked and installed. Also good.
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Abstract
Description
71,81 カーボン層
71a 溝部
71c,81c 貫通孔
81a 壁部
72 Si層
72a Si融液層
73 3C-SiC多結晶層
74 種結晶
74a 4H-SiC単結晶層
Claims (7)
- 少なくとも表面が多結晶SiCで構成される基板の表面にカーボン層を形成するカーボン層形成工程と、前記基板に形成された前記カーボン層に貫通孔を形成する貫通孔形成工程と、前記基板に形成された前記カーボン層の表面にSi層を形成するとともに、当該Si層の表面に多結晶SiCで構成されるフィード層を形成するフィード層形成工程と、前記基板に対して1600℃以上2300℃以下の温度範囲の加熱処理を行うことで、前記貫通孔を通じて露出した前記基板の表面に4H-SiC単結晶で構成される種結晶を形成し、前記加熱処理を継続することで、前記種結晶を近接液相エピタキシャル成長させて4H-SiC単結晶で構成されるエピタキシャル層を形成するエピタキシャル層形成工程と、を含むことを特徴とする半導体ウエハの製造方法。
- 請求項1に記載の半導体ウエハの製造方法であって、前記基板の表面には、複数の溝部又は壁部が形成されており、前記貫通孔形成工程では、前記溝部又は前記壁部で囲まれた領域毎に前記貫通孔を形成し、前記エピタキシャル層形成工程では、4H-SiC単結晶で構成される前記エピタキシャル層が前記領域毎に形成されることを特徴とする半導体ウエハの製造方法。
- 請求項1に記載の半導体ウエハの製造方法であって、前記カーボン層形成工程では、1500℃以上2300℃以下の温度範囲の真空下で加熱することで、前記基板の表面のSi原子を昇華させて前記カーボン層を形成することを特徴とする半導体ウエハの製造方法。
- 請求項1に記載の半導体ウエハの製造方法であって、前記カーボン層形成工程では、化学気相成長法、有機レジスト法、又は電子サイクロトロン共鳴スパッタ法によって前記カーボン層を形成することを特徴とする半導体ウエハの製造方法。
- 請求項1に記載の半導体ウエハの製造方法であって、前記貫通孔形成工程では赤外線のレーザ光を用いてカーボン層に貫通孔を形成し、赤外線のレーザ光のスポット径が100μm以下であることを特徴とする半導体ウエハの製造方法。
- 請求項1に記載の半導体ウエハの製造方法であって、前記エピタキシャル層形成工程においては、加熱処理温度の制御により、4H-SiC単結晶で構成されるエピタキシャル層の水平方向のエピタキシャル成長速度が厚み方向のエピタキシャル成長速度より5倍から10倍早く成長できることを特徴とする半導体ウエハの製造方法。
- 請求項1に記載の半導体ウエハの製造方法により製造された半導体ウエハであり、
前記種結晶を近接液相エピタキシャル成長させる加熱処理温度を制御することにより4H-SiC単結晶で構成されるエピタキシャル層の水平方向の寸度が、厚み方向の寸度に対して5倍から10倍のアスペクト比率に制御された半導体ウエハ。
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2011
- 2011-08-26 JP JP2011185181A patent/JP5875143B2/ja active Active
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2012
- 2012-08-24 KR KR1020147008007A patent/KR101910696B1/ko active IP Right Grant
- 2012-08-24 US US14/240,710 patent/US9029219B2/en active Active
- 2012-08-24 TW TW101130853A patent/TWI567867B/zh not_active IP Right Cessation
- 2012-08-24 CN CN201280041389.3A patent/CN103857835B/zh not_active Expired - Fee Related
- 2012-08-24 EP EP12828285.2A patent/EP2749675A4/en not_active Withdrawn
- 2012-08-24 WO PCT/JP2012/005301 patent/WO2013031154A1/ja active Application Filing
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Also Published As
Publication number | Publication date |
---|---|
KR101910696B1 (ko) | 2018-10-22 |
CN103857835A (zh) | 2014-06-11 |
JP2013043822A (ja) | 2013-03-04 |
TWI567867B (zh) | 2017-01-21 |
CN103857835B (zh) | 2017-02-15 |
EP2749675A4 (en) | 2015-06-03 |
US9029219B2 (en) | 2015-05-12 |
JP5875143B2 (ja) | 2016-03-02 |
US20140319539A1 (en) | 2014-10-30 |
EP2749675A1 (en) | 2014-07-02 |
KR20140069039A (ko) | 2014-06-09 |
TW201314839A (zh) | 2013-04-01 |
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