WO2013024646A1 - Transistor en couches minces, procédé de production associé, dispositif d'affichage, capteur d'images, capteur de rayons x et dispositif d'imagerie numérique par rayons x - Google Patents

Transistor en couches minces, procédé de production associé, dispositif d'affichage, capteur d'images, capteur de rayons x et dispositif d'imagerie numérique par rayons x Download PDF

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WO2013024646A1
WO2013024646A1 PCT/JP2012/067507 JP2012067507W WO2013024646A1 WO 2013024646 A1 WO2013024646 A1 WO 2013024646A1 JP 2012067507 W JP2012067507 W JP 2012067507W WO 2013024646 A1 WO2013024646 A1 WO 2013024646A1
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thin film
film transistor
gate
oxide semiconductor
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PCT/JP2012/067507
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English (en)
Japanese (ja)
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雅司 小野
真宏 高田
鈴木　真之
田中　淳
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富士フイルム株式会社
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Priority to KR1020137033689A priority Critical patent/KR101529000B1/ko
Publication of WO2013024646A1 publication Critical patent/WO2013024646A1/fr

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
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    • C23C14/08—Oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C23C14/086—Oxides of zinc, germanium, cadmium, indium, tin, thallium or bismuth
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/3464—Sputtering using more than one target
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
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    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
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    • H01L21/02381—Silicon, silicon germanium, germanium
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    • H01L21/02104—Forming layers
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    • H01L21/02439—Materials
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/02551—Group 12/16 materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention relates to a thin film transistor and a manufacturing method thereof, a display device, an image sensor, an X-ray sensor, and an X-ray digital imaging device.
  • IGZO In—Ga—Zn—O-based oxide semiconductor thin film as an active layer (channel layer)
  • An oxide semiconductor thin film can be formed at a low temperature, has higher mobility than amorphous silicon, and is transparent to visible light. Therefore, a flexible thin film transistor is formed on a substrate such as a plastic plate or a film. Is possible.
  • Table 1 shows a comparison of field effect mobility and process temperature of various transistor characteristics.
  • a thin film transistor whose active layer is polysilicon can obtain a mobility of about 100 cm 2 / Vs.
  • the process temperature is as high as 450 ° C. or higher, it can be applied only to a substrate having high heat resistance. It cannot be formed and is not suitable for low cost, large area, and flexibility.
  • the thin film transistor whose active layer is amorphous silicon can be formed at a relatively low temperature of about 300 ° C., the selectivity of the substrate is wider than that of polysilicon, but only a mobility of about 1 cm 2 / Vs can be obtained at most. Not suitable for fine display applications.
  • thin film transistors whose organic active layer is organic can be formed at 100 ° C. or lower, and therefore are expected to be applied to flexible display applications using plastic film substrates with low heat resistance.
  • the mobility is only as high as that of amorphous silicon.
  • a high mobility layer containing an oxide of IZO, ITO, GZO, or AZO is disposed on the side close to the gate electrode, and on the side far from the gate electrode.
  • a thin film transistor having an oxide layer containing Zn is disclosed.
  • Japanese Patent Laid-Open No. 2009-170905 at least a first semiconductor pattern including amorphous silicon, at least one element of Ga, In, Zn, Sn, Co, Ti, and Mg and oxygen are formed on a gate wiring.
  • a display substrate including a second semiconductor pattern including the element O is disclosed.
  • Japanese Patent Application Laid-Open No. 2010-161339 discloses a field effect transistor including at least a semiconductor layer and a gate electrode provided with respect to the semiconductor layer via a gate insulating layer, wherein the semiconductor layer includes Zn or In
  • a field effect transistor including the amorphous oxide semiconductor layer is disclosed.
  • Vg 0 V
  • amorphous silicon having a mobility about one digit lower than that of an oxide semiconductor is used for a carrier traveling layer which is a quantum well portion. Sufficient mobility cannot be obtained.
  • the off-current value may be high, which is insufficient for low power consumption.
  • HEMT heterostructure field effect transistor
  • MBE molecular beam epitaxy
  • the present invention can be manufactured even at 400 ° C. or lower, and is excellent in a thin film transistor that achieves a high field-effect mobility of 30 cm 2 / Vs or more and a low off-current that is normally off, a manufacturing method thereof, and low power consumption.
  • An object of the present invention is to provide a display device, an image sensor, an X-ray sensor, and an X-ray digital imaging device that exhibit excellent characteristics.
  • a gate electrode A gate insulating film in contact with the gate electrode; A first region represented by In (x) Zn (1-x) O (y) (0.4 ⁇ x ⁇ 0.5, y> 0) and In (a) Ga (b) Zn (c) O (d) (b / (a + b)> 0.250, c> 0, d> 0), including a second region located farther from the first region than the gate electrode
  • An oxide semiconductor layer disposed to face the gate electrode through the gate insulating film; A source electrode and a drain electrode, which are disposed apart from each other and can be conducted through the oxide semiconductor layer; Thin film transistor.
  • ⁇ 2> The thin film transistor according to ⁇ 1>, wherein the second region is represented by b / (a + b) ⁇ 0.875.
  • ⁇ 3> The thin film transistor according to ⁇ 1> or ⁇ 2>, wherein the film thickness of the second region is more than 10 nm and less than 70 nm.
  • ⁇ 4> The thin film transistor according to any one of ⁇ 1> to ⁇ 3>, wherein the oxide semiconductor layer is amorphous.
  • ⁇ 5> The thin film transistor according to any one of ⁇ 1> to ⁇ 4>, wherein the thin film transistor is a bottom gate-top contact type or a top gate-bottom contact type.
  • ⁇ 6> Forming the first region by sputtering using the first oxygen partial pressure / argon partial pressure ratio in the film formation chamber; Depositing the second region by sputtering using a second oxygen partial pressure / argon partial pressure ratio in the deposition chamber;
  • a method for producing a thin film transistor comprising producing the thin film transistor according to any one of ⁇ 1> to ⁇ 5>.
  • ⁇ 7> Forming the first region by a sputtering method; Depositing the second region by sputtering; Irradiating the surface of the film in the first region with oxygen radicals during and / or after the film formation of the first region;
  • a method for producing a thin film transistor comprising producing the thin film transistor according to any one of ⁇ 1> to ⁇ 5>.
  • ⁇ 8> A step of forming the first region by sputtering, Depositing the second region by sputtering; Irradiating the film-forming surface of the first region with ultraviolet rays in an ozone atmosphere during and / or after the film formation of the first region;
  • a method for producing a thin film transistor comprising producing the thin film transistor according to any one of ⁇ 1> to ⁇ 5>.
  • ⁇ 9> The oxide semiconductor layer according to any one of ⁇ 6> to ⁇ 8>, wherein the oxide semiconductor layer is not exposed to the atmosphere between the step of forming the first region and the step of forming the second region.
  • a method for manufacturing a thin film transistor A method for manufacturing a thin film transistor.
  • ⁇ 10> The method for manufacturing a thin film transistor according to any one of ⁇ 6> to ⁇ 9>, wherein after the first region and the second region are formed, post-annealing is performed at a temperature of 300 ° C. or higher.
  • a display device comprising the thin film transistor according to any one of ⁇ 1> to ⁇ 5>.
  • An image sensor comprising the thin film transistor according to any one of ⁇ 1> to ⁇ 5>.
  • ⁇ 13> An X-ray sensor comprising the thin film transistor according to any one of ⁇ 1> to ⁇ 5>.
  • ⁇ 14> An X-ray digital imaging apparatus comprising the X-ray sensor according to ⁇ 13>.
  • ⁇ 15> The X-ray digital imaging apparatus according to ⁇ 14>, which can capture a moving image.
  • a thin film transistor that can be manufactured at 400 ° C. or less and has both a high field-effect mobility of 30 cm 2 / Vs or more and a low off-current that is normally off, a manufacturing method thereof, and low power consumption
  • a display device, an image sensor, and an X-ray sensor that exhibit better characteristics can be provided.
  • 1 is a schematic view showing a configuration of an example (bottom gate-top contact type) of a thin film transistor according to the present invention.
  • 1 is a schematic diagram showing a configuration of an example (top gate-bottom contact type) of a thin film transistor according to the present invention.
  • It is a schematic sectional drawing which shows a part of liquid crystal display device of embodiment.
  • It is a schematic block diagram of the electrical wiring of the liquid crystal display device of FIG.
  • It is a schematic sectional drawing which shows a part of organic EL display apparatus of embodiment.
  • It is a schematic block diagram of the electrical wiring of the organic electroluminescent display apparatus of FIG.
  • It is a schematic sectional drawing which shows a part of X-ray sensor array of embodiment.
  • FIG. 1 It is a schematic block diagram of the electrical wiring of the X-ray sensor array of FIG. It is a figure which shows the change of the Vg-Id characteristic by the composition modulation of a 1st area
  • (DELTA) Vth threshold value shift
  • the thin film transistor of the present invention includes a gate electrode, a gate insulating film in contact with the gate electrode, and In (x) Zn (1-x) O (y) (0.4 ⁇ x ⁇ 0 .5, y> 0) and In (a) Ga (b) Zn (c) O (d) (b / (a + b)> 0.250, c> 0, d> 0 And an oxide semiconductor layer that includes a second region farther than the first region with respect to the gate electrode and is disposed to face the gate electrode with the gate insulating film interposed therebetween And a source electrode and a drain electrode which are arranged apart from each other and can be conducted through the oxide semiconductor layer.
  • the thin film transistor of the present invention has a function of switching a current between a source electrode and a drain electrode by applying a voltage to a gate electrode and controlling a current flowing in the oxide semiconductor layer.
  • the thin film transistor according to the present invention has high field-effect mobility (30 cm 2 / Vs or more) and can achieve normally-off (preferably an off current of 1E-9A or less). Further, in the element structure of the thin film transistor of the present invention, since the carrier traveling layer (first region) is not exposed to the outside air, the deterioration of element characteristics depending on the time and driving environment is reduced. In addition, by bonding the same oxide semiconductor system using In and Zn as the base material, the bonding interface is improved compared to a device in which different types of semiconductors are bonded, and device deterioration due to electrical stress during driving is suppressed. Is done. Even when compared with a conventional IGZO single film TFT, the driving stability is good. In addition, since the first region A1 has a binary cation as compared with the IGZO system, the composition adjustment during production is easy.
  • the TFT may be formed on the substrate, or when a component (for example, an electrode) of the TFT functions as the substrate, a separate substrate may be omitted. Further, the TFT and the substrate may be in direct contact, or an additional layer or element may be provided between the TFT and the substrate.
  • the element structure of the TFT of the present invention may be either a so-called bottom gate type (also referred to as an inverted staggered structure) or a top gate type (also referred to as a staggered structure) based on the position of the gate electrode.
  • top contact type is a form in which a gate electrode is disposed on the upper side of the gate insulating film and an active layer is formed on the lower side of the gate insulating film when the substrate on which the TFT is formed is the lowermost layer.
  • bottom gate type is a form in which a gate electrode is disposed below the gate insulating film and an active layer is formed above the gate insulating film.
  • the bottom contact type is a mode in which the source / drain electrodes are formed before the active layer and the lower surface of the active layer is in contact with the source / drain electrodes.
  • the top contact type is the type in which the active layer is the source / drain. In this embodiment, the upper surface of the active layer is in contact with the source / drain electrodes.
  • the TFT according to the present embodiment can have various configurations, and may appropriately have a configuration including a protective layer on the active layer, an insulating layer on the substrate, and the like.
  • FIGS. 1 and 2 will be specifically described as a representative example, but the present invention can also be applied to TFTs of other forms (structures).
  • FIG. 1 is a sectional view schematically showing the configuration of a thin film transistor 1 according to the first embodiment of the present invention
  • FIG. 2 is a schematic view showing the configuration of the thin film transistor 2 according to the second embodiment of the present invention.
  • the thin film transistor 1 of the first embodiment shown in FIG. 1 is a bottom gate-top contact type transistor
  • the thin film transistor 2 of the second embodiment shown in FIG. 2 is a top gate-bottom contact type transistor.
  • the arrangement of the gate electrode 16, the source electrode 13, and the drain electrode 14 with respect to the oxide semiconductor layer 12 is different, but the function of each element given the same reference numeral is the same. Similar materials can be applied.
  • the thin film transistors 1 and 2 include a gate electrode 16, a gate insulating film 15, an oxide semiconductor layer 12 (active layer), a source electrode 13, and a drain electrode 14 on a substrate 11.
  • the oxide semiconductor layer 12 includes the first region A1 and the second region A2 from the side close to the gate electrode 16 in the film thickness direction.
  • the first region A1 and the second region A2 constituting the oxide semiconductor layer 12 are continuously formed, and an insulating layer, an electrode layer, or the like is provided between the first region A1 and the second region A2.
  • Layers other than the oxide semiconductor layer are not inserted and are formed of an oxide semiconductor film.
  • each component of the TFT of the present invention including the substrate on which the TFT is formed will be described in detail.
  • the shape, structure, size, etc. of the substrate 11 for forming the thin film transistor are not particularly limited and can be appropriately selected according to the purpose.
  • the structure of the substrate 11 may be a single layer structure or a laminated structure.
  • a substrate formed of an inorganic material such as glass or YSZ (yttrium stabilized zirconium), a resin, a resin composite material, or the like can be used.
  • a substrate formed of a resin or a resin composite material is preferable from the viewpoint of light weight and flexibility.
  • a substrate formed from a composite plastic material of the aforementioned synthetic resin or the like and silicon oxide particles, or a composite plastic of the aforementioned synthetic resin or the like and metal nanoparticles, inorganic oxide nanoparticles or inorganic nitride nanoparticles, etc.
  • a substrate formed from a material, a substrate formed from a composite plastic material of the above-described synthetic resin and the like and particles having a clay mineral or mica-derived crystal structure, and between a thin glass and any of the above-described synthetic resins Laminated plastic substrate with at least one bonding interface, alternating between inorganic and organic layers (synthetic resin described above)
  • an oxidation treatment for example, a substrate formed of a composite material having a barrier performance having at least one bonding interface, a stainless steel substrate, a metal multilayer substrate in which stainless steel and a dissimilar metal are laminated, an aluminum substrate, or a surface
  • an aluminum substrate with an oxide film whose surface insulation is improved by applying an anodizing treatment for example, a substrate formed of a composite material having
  • the resin substrate is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low moisture absorption, and the like.
  • the resin substrate may include a gas barrier layer for preventing permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate and adhesion with the lower electrode, and the like.
  • the thickness of the substrate 11 is preferably 50 ⁇ m or more and 500 ⁇ m or less, assuming that a flexible substrate is used.
  • the thickness of the substrate 11 is 50 ⁇ m or more, the flatness of the substrate itself is further improved.
  • the thickness of the substrate 11 is 500 ⁇ m or less, the flexibility of the substrate itself is further improved and the use as a substrate for a flexible device becomes easier. It should be noted that since the thickness having sufficient flatness and flexibility differs depending on the material constituting the substrate 11, it is necessary to set the thickness according to the substrate material, but the range is generally in the range of 50 ⁇ m to 500 ⁇ m. is there.
  • the material of the gate electrode 16 is not particularly limited as long as it has high conductivity.
  • metal such as Al, Mo, Cr, Ta, Ti, Au, Ag, Al—Nd, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO) And metal oxide conductive films.
  • a gate electrode can be formed by forming a single layer or a stacked structure of two or more layers using the above material (eg, metal oxide).
  • the thickness is preferably 10 nm or more and 1000 nm or less in consideration of film forming property, patterning property by etching or lift-off method, conductivity, and the like. 50 nm or more and 200 nm or less is more preferable.
  • the gate insulating film 15 is a layer that separates the gate electrode 16 from the oxide semiconductor 12 and the source / drain electrodes 13 and 14, and has a high insulating property.
  • SiO 2 , SiNx, An insulating film such as SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , HfO 2, or an insulating film containing two or more of these compounds can be used.
  • the gate insulating film 15 needs to have a sufficient thickness to reduce leakage current and improve voltage resistance. On the other hand, if the thickness is too large, the drive voltage increases.
  • the thickness of the gate insulating film 15 is preferably 10 nm to 10 ⁇ m, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm.
  • the oxide semiconductor layer 12 includes a first region A1 and a second region A2 from the order close to the gate electrode 16, and is disposed to face the gate electrode 16 with the gate insulating film 15 interposed therebetween.
  • the first region A1 includes an oxide semiconductor film (IZO layer) represented by In (x) Zn (1-x) O (y) (0.4 ⁇ x ⁇ 0.5, y> 0). Has been.
  • the second region A2 is located on the side farther than the first region A1 with respect to the gate electrode 16, that is, on the opposite side to the surface in contact with the gate insulating film 15 of the first region A1, and In (a) It is composed of an oxide semiconductor film (IGZO layer) represented by Ga (b) Zn (c) O (d) (b / (a + b)> 0.250, c> 0, d> 0).
  • IGZO layer oxide semiconductor film represented by Ga (b) Zn (c) O (d) (b / (a + b)> 0.250, c> 0, d> 0).
  • field effect mobility generally increases with an increase in electron carrier concentration. That is, In (x) Zn (1-x) O (y) (0 ⁇ x ⁇ 1, y> 0) which is close to the gate electrode in the thin film transistor and becomes a current traveling layer under a state where a positive gate voltage is applied.
  • the first region (IZO layer) to be expressed is preferably an oxide semiconductor layer having a certain carrier concentration.
  • a carrier concentration sufficient for driving the transistor can be obtained, so that a thin film transistor with a field-effect mobility exceeding 30 cm 2 / Vs can be manufactured.
  • x exceeds 0.5 a field effect mobility of 30 cm 2 / Vs or more can be obtained, but at the same time, the carrier concentration becomes excessive and pinch-off becomes difficult, so that the off current increases.
  • the composition of the IZO layer that tends to be degenerate conduction is generally within a specific range as the first region near the gate electrode, that is, In (x) Zn (1-x) O (y In the first region represented by), a low off-state current can be realized while maintaining a high mobility of IZO by controlling 0.4 ⁇ x ⁇ 0.5.
  • the gate electrode is different from the first region.
  • the first region A1 and the second region A2 constituting the oxide semiconductor layer are formed of the same kind of material including In, Zn, and O.
  • the defect density at the interface is reduced as compared with the case where the first region A1 that substantially becomes the channel layer is in contact with a different material such as Si, and is excellent from the viewpoint of uniformity, stability, and reliability.
  • a thin film transistor can be provided.
  • IGZO oxide semiconductor
  • the thickness of the first region A1 is preferably 3 to 20 nm, more preferably 5 nm or more and less than 10 nm. If the thickness of the first region A1 is 5 nm or more, a highly uniform film can be obtained, so that the effect of improving the mobility can be expected, and if it is less than 10 nm, the total number of carriers is reduced and pinch-off is easy. become.
  • the second region A2 far from the gate electrode 16 includes In (a) Ga (b) Zn (c) O (d) (b / (a + b)> 0.250, c> 0. , D> 0).
  • the source electrode 13 and the drain electrode 14 are connected to the oxide semiconductor layer 12 mainly through the second region A2.
  • the second region A2 represented by In (a) Ga (b) Zn (c) O (d) (b / (a + b)> 0.250, c> 0, d> 0) is b / ( If a + b)> 0.875 (ie, Ga rich), the contact resistance between the source / drain electrodes 13 and 14 and the oxide semiconductor layer 12 tends to increase, and the field-effect mobility tends to decrease. Therefore, in order to manufacture a high mobility thin film transistor, it is preferable that the second region A2 satisfy b / (a + b) ⁇ 0.875.
  • the Fermi level and the conduction band are relatively close in the second region A2, the electron affinity is increased, and the resistance is easily reduced. It becomes a state.
  • an oxide semiconductor film (second region A2) bonded to the first region A1 is formed in this state, a conduction path is formed in the bulk of the second region A2 or in the vicinity of the surface in addition to the first region A1. This tends to cause a situation in which off-current increases. Therefore, in the second region A2 represented by In (a) Ga (b) Zn (c) O (d) (a> 0, b> 0, c> 0, d> 0), b / (a + b )> 0.250.
  • the thickness of the second region A2 is desirably more than 10 nm. Furthermore, it is desirable that the thickness of the second region A2 is less than 70 nm. When the thickness of the second region A2 exceeds 10 nm, good transistor characteristics with a small S value can be obtained. When the thickness of the second region A2 is 10 nm or less, the S value is likely to be deteriorated. In particular, when the second region is 30 nm or more, a reduction in off current can be expected. On the other hand, if the thickness of the second region A2 is 70 nm or more, a reduction in off-current can be expected, and there is no problem from the viewpoint of the S value, but the resistance between the source / drain electrodes 13 and 14 and the first region A1. Will increase, and the field-effect mobility tends to decrease. Therefore, the film thickness of the second region A2 is desirably more than 10 nm and less than 70 nm.
  • the film thickness (total film thickness) of the entire oxide semiconductor layer 12 is preferably about 10 to 200 nm, more preferably more than 15 nm and less than 80 nm, from the viewpoint of film uniformity and patternability.
  • the source electrode 13 and the drain electrode 14 are not particularly limited with respect to materials and structures as long as they have high conductivity.
  • metals such as Al, Mo, Cr, Ta, Ti, Au, and Ag, Al—Nd, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide And metal oxide conductive films such as (IZO).
  • the source / drain electrodes 13 and 14 can be formed by forming a single layer or a laminated structure of two or more layers using the above materials (for example, metal oxide).
  • the thickness is 10 nm or more and 1000 nm or less in consideration of the film forming property, the patterning property by etching or lift-off method, the conductivity, and the like. It is preferable to set it to 50 nm or more and 100 nm or less.
  • the gate electrode 16 is a material used from, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method.
  • the film may be formed according to a method appropriately selected in consideration of the suitability of For example, after the electrode film is formed, the gate electrode 16 is formed by patterning into a predetermined shape by etching or a lift-off method. At this time, it is preferable to pattern the gate electrode 16 and the gate wiring simultaneously.
  • the gate insulating film 15 is a material used from a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as a CVD or plasma CVD method.
  • the film may be formed according to a method appropriately selected in consideration of the suitability of For example, the gate insulating film 15 may be patterned into a predetermined shape by photolithography and etching.
  • a vapor deposition method such as a sputtering method, a pulse laser deposition method (PLD method), and a CVD method in order of the first region A1 and the second region A2;
  • a film is formed by a technique. Specifically, an IZO film that becomes In (x) Zn (1-x) O (y) (0.4 ⁇ x ⁇ 0.5, y> 0) is formed on the insulating film 15 as the first region A1.
  • the first region A1 is a target of In, Zn, or an oxide thereof or a composite oxide thereof.
  • Co-sputtering may be used, or a composite oxide target having a metal element composition ratio in the formed IZO film as described above may be prepared in advance and single sputtering may be performed.
  • the substrate temperature during film formation may be arbitrarily selected according to the substrate, but when a resin flexible substrate is used, the substrate temperature is preferably closer to room temperature in order to prevent deformation of the substrate.
  • the oxygen partial pressure in the film formation chamber during film formation may be relatively lowered to reduce the oxygen concentration in the film.
  • the oxygen partial pressure / argon partial pressure ratio during film formation is set to 0.005.
  • the oxygen partial pressure in the film formation chamber during film formation relatively high (for example, the oxygen partial pressure / argon partial pressure ratio during film formation is set to 0.067)?
  • the oxygen concentration in the film may be increased by irradiating oxygen radicals during or after film formation, or by irradiating the film formation surface with ultraviolet rays in an ozone atmosphere.
  • the IGZO film to be the second region A2 is formed.
  • the film formation in the second region A2 is a method of once stopping the film formation after the film formation in the first region A1, changing the oxygen partial pressure in the film formation chamber and the power applied to the target, and then restarting the film formation.
  • the oxygen partial pressure in the deposition chamber and the power applied to the target may be changed quickly or slowly without stopping the deposition.
  • the target stops supplying power to the target used for the film formation in the first region A1, and In, Ga, and Zn are used.
  • a method of additionally applying power to another target containing at least Ga may be used. May be.
  • the second region A2 In (a) Ga (b) Zn (c) O (d) (b / (a + b)> 0.250, c> 0, d> 0), b / (a + b)
  • An IGZO layer represented by 0.750 is formed to a thickness of 50 nm.
  • the substrate temperature when forming the second region A2 may be arbitrarily selected according to the substrate, but when using a resin flexible substrate, as in the first region A1 and during film formation, The substrate temperature is preferably closer to room temperature.
  • the oxygen partial pressure in the film formation chamber during film formation may be relatively lowered to reduce the oxygen concentration in the film.
  • the oxygen partial pressure / argon partial pressure ratio during film formation is set to 0.005.
  • the oxygen partial pressure in the film formation chamber during film formation relatively high (for example, the oxygen partial pressure / argon partial pressure ratio during film formation is set to 0.067)?
  • the oxygen concentration in the film may be increased by irradiating oxygen radicals during or after the film formation, or by irradiating the surface of the film formation substrate with ultraviolet rays in an ozone atmosphere.
  • the oxygen concentration in the film is increased by irradiation with oxygen radicals or ultraviolet irradiation in an ozone atmosphere, both during and after the formation of the first region A1 and the second region A2. Alternatively, it may be performed only after the film formation of the second region A2.
  • the substrate temperature at the time of oxygen radical irradiation may be arbitrarily selected according to the substrate, but when a flexible substrate is used, the substrate temperature is preferably closer to room temperature.
  • the oxide semiconductor layer 12 is preferably formed continuously without being exposed to the atmosphere.
  • the oxide semiconductor layer 12 is formed without being exposed to the air, it is possible to prevent impurities from being mixed between the regions A1 and A2, and as a result, better transistor characteristics can be obtained.
  • the manufacturing cost can also be reduced. Note that in this embodiment, when the bottom-gate thin film transistor 1 is manufactured, the oxide semiconductor layer 12 is formed in the order of the first region A1 and the second region A2, and the top-gate type thin film transistor 1 shown in FIG. When the thin film transistor 2 is manufactured, the second region A2 and the first region A1 may be formed in this order.
  • the carrier concentration of the oxide semiconductor layer 12 is controlled not only by the composition modulation of the IZO layer (first region) A1 and the IGZO layer (second region) A2, but also by oxygen partial pressure control during film formation. Can do. Specifically, the oxygen concentration in the oxide semiconductor layer 12 can be controlled by controlling the oxygen partial pressure during film formation in the first region A1 and the second region A2, respectively. For example, when the oxide semiconductor layer 12 is formed by sputtering, the first region A1 is formed with the first oxygen partial pressure / argon partial pressure ratio in the film formation chamber, and the second oxygen partial pressure / The second region A2 is formed as an argon partial pressure ratio.
  • the carrier concentration can be reduced, and a reduction in off-current can be expected accordingly.
  • the carrier concentration can be increased, and accordingly, the field effect mobility can be expected to increase.
  • the film formation surface of the first region A1 is irradiated with oxygen radicals, or the film formation surface of the first region A1 in an ozone atmosphere. It is possible to promote the oxidation of the film and to reduce the amount of oxygen vacancies in the first region by irradiating the film with ultraviolet rays.
  • the band gap of the film can be increased by doping Mg.
  • the band gap can be maintained while maintaining the band profile of the laminated film as compared with a system in which the composition ratio of only In, Ga, and Zn is controlled. Can be increased.
  • the carrier density in the first region A1 and the second region A2 can be arbitrarily controlled by cation doping.
  • a material that tends to be a cation having a relatively large valence eg, Ti, Zr, Hf, Ta, etc.
  • doping a cation with a large valence the number of constituent elements of the oxide semiconductor film increases, so that the carrier density is reduced by the oxygen concentration (oxygen deficiency) in terms of simplifying the film formation process and reducing the cost. It is preferable to control.
  • the oxide semiconductor layer 12 is preferably amorphous because it can be formed at a temperature of 300 ° C. or lower.
  • an amorphous IZO film or IGZO film can be formed at a substrate temperature of 200 ° C. or lower.
  • Whether or not the oxide semiconductor layer is amorphous can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, the oxide semiconductor layer can be determined to be amorphous.
  • an annealing process may be performed after the oxide semiconductor layer 12 is formed.
  • the atmosphere during post-annealing can be arbitrarily selected according to the film.
  • the annealing temperature may be arbitrarily selected according to the substrate 11, but when a flexible substrate is used, it is preferable to anneal at a lower temperature (for example, 200 ° C. or lower).
  • the annealing treatment may be performed at a high temperature close to 500 ° C.
  • annealing is performed at 600 ° C. or lower. Is preferred.
  • the oxide semiconductor layer 12 is formed by patterning the oxide semiconductor film in which the IZO film and the IGZO film are stacked so as to face the gate electrode 16 to be formed later with the gate insulating film 15 interposed therebetween.
  • Patterning can be performed, for example, by photolithography and etching. Specifically, a resist pattern is formed on the remaining portion by photolithography, and the pattern is formed by etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid.
  • a metal film for forming the source / drain electrodes 13 and 14 is formed on the oxide semiconductor layer 12.
  • Each of the source electrode 13 and the drain electrode 14 is, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a chemical method such as CVD or a plasma CVD method, or the like.
  • the film may be formed according to a method appropriately selected in consideration of suitability with the material to be used.
  • the metal film is patterned into a predetermined shape by etching or a lift-off method, and the source electrode 13 and the drain electrode 14 are formed. At this time, it is preferable to pattern the source / drain electrodes 13 and 14 and the wiring (not shown) connected to the source / drain electrodes 13 and 14 simultaneously. Through the above procedure, the thin film transistor 1 illustrated in FIG. 1 can be manufactured.
  • the thin film transistor of the present invention has both high mobility and low off-state current, and can be applied to various devices. Both the display device and the sensor of the present invention using the thin film transistor of the present invention exhibit good characteristics due to low power consumption.
  • the “characteristic” referred to here is a display characteristic in the case of a display device, and a sensitivity characteristic in the case of a sensor.
  • FIG. 3 shows a schematic sectional view of a part of a liquid crystal display device which is an embodiment of a display device including the thin film transistor of the present invention
  • FIG. 4 shows a schematic configuration diagram of the electric wiring.
  • the liquid crystal display device 5 of the present embodiment includes an oxide composed of the gate electrode 16, the gate insulating film 15, the first region A1, and the second region A2 shown in FIG.
  • a liquid crystal layer 57 sandwiched between the pixel lower electrode 55 and the opposed upper electrode 56 and an RGB color filter 58 for developing different colors corresponding to each pixel are provided, and on the substrate 11 side of the TFT 2 and on the color filter 58.
  • the liquid crystal display device 5 of the present embodiment includes a plurality of gate wirings 51 that are parallel to each other and data wirings 52 that are parallel to each other and intersect the gate wirings 51. Yes.
  • the gate wiring 51 and the data wiring 52 are electrically insulated.
  • the thin film transistor 2 is provided in the vicinity of the intersection between the gate line 51 and the data line 52.
  • the gate electrode 16 of the thin film transistor 2 is connected to the gate wiring 51, and the source electrode 13 of the thin film transistor 2 is connected to the data wiring 52.
  • the drain electrode 14 of the thin film transistor 2 is electrically connected to the pixel lower electrode 55 through a contact hole 19 provided in the gate insulating film 15 (a conductor is embedded in the contact hole 19).
  • the pixel lower electrode 55 constitutes a capacitor 53 together with the grounded counter upper electrode 56.
  • the top gate type thin film transistor is provided in the liquid crystal device of this embodiment shown in FIG. 3.
  • the thin film transistor used in the liquid crystal device which is the display device of the present invention is not limited to the top gate type, A bottom-gate thin film transistor may be used.
  • the thin film transistor of the present invention has high mobility, high-definition display such as high definition, high-speed response, and high contrast is possible in a liquid crystal display device, which is suitable for a large screen.
  • the oxide semiconductor layer 12 (active layer) is amorphous, variations in element characteristics can be suppressed, and an excellent display quality with a large screen and no unevenness can be realized.
  • the gate voltage can be reduced, and thus the power consumption of the display device can be reduced.
  • the first region A1 and the second region A2 constituting the oxide semiconductor layer (active layer) are amorphous films that can be formed at a low temperature (eg, 200 ° C. or lower). Therefore, a resin substrate (plastic substrate) can be used as the substrate. Therefore, according to the present invention, it is possible to provide a flexible liquid crystal display device having excellent display quality.
  • FIG. 5 shows a schematic sectional view of a part of an active matrix type organic EL display device as an embodiment of a display device including a TFT of the present invention
  • FIG. 6 shows a schematic configuration diagram of electric wiring.
  • driving methods for organic EL display devices There are two types of driving methods for organic EL display devices: a simple matrix method and an active matrix method.
  • the simple matrix method has an advantage that it can be manufactured at low cost.
  • the pixels are emitted by selecting one scanning line at a time, the number of scanning lines and the light emission time per scanning line are inversely proportional. Therefore, it is difficult to increase the definition and increase the screen size.
  • the active matrix method has a high manufacturing cost because a transistor and a capacitor are formed for each pixel.
  • it is suitable for high definition and large screen.
  • a top gate-top contact type thin film transistor is provided on the passivation layer 61a on the substrate 60 as a driving TFT 2a and a switching TFT 2b.
  • the driving TFT 2a includes a gate electrode 16a, a gate insulating film 15, a first region A1, a second region A2, a source electrode 13a, and a drain electrode 14a.
  • the switching TFT 2b includes a gate electrode 16b, a gate insulating film 15, an oxide semiconductor layer 12 including a first region A1 and a second region A2, a source electrode 13b, and a drain electrode 14b.
  • an organic EL light emitting element 65 that includes an organic light emitting layer 64 sandwiched between a lower electrode 62 and an upper electrode 63, and the upper surface of the upper electrode 63 is protected by a passivation layer 61b.
  • the organic EL display device 6 of this embodiment includes a plurality of gate wirings 66 that are parallel to each other, and data wirings 67 and driving wirings that are parallel to each other and intersect the gate wirings 66. 68.
  • the gate wiring 66, the data wiring 67, and the driving wiring 68 are electrically insulated.
  • the gate electrode 16 b of the switching thin film transistor 2 b is connected to the gate line 66, and the source electrode 13 b of the switching thin film transistor 2 b is connected to the data line 67.
  • the drain electrode 14b of the switching thin film transistor 2b is connected to the gate electrode 16a of the driving thin film transistor 2a, and the driving thin film transistor 2a is kept on by using the capacitor 69.
  • the source electrode 13 a of the driving thin film transistor 2 a is connected to the driving wiring 68, and the drain electrode 14 a is connected to the organic EL light emitting element 65.
  • the organic EL device of this embodiment shown in FIG. 5 also includes the top gate type thin film transistors 2a and 2b.
  • the thin film transistor used in the organic EL device which is the display device of the present invention is a top gate type.
  • a bottom-gate thin film transistor may be used.
  • the first region A1 and the second region A2 constituting the oxide semiconductor layer (active layer) are amorphous films that can be formed at a low temperature (eg, 200 ° C. or lower). Therefore, a resin substrate (plastic substrate) can be used as the substrate. Therefore, according to the present invention, a flexible organic EL display device having excellent display quality can be provided.
  • the top electrode 63 may be a top emission type with a transparent electrode, or the bottom electrode 62 and each of the TFTs 2a and 2b may be a transparent electrode. Good.
  • FIG. 7 shows a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention
  • FIG. 8 shows a schematic configuration diagram of its electric wiring.
  • the X-ray sensor 7 of this embodiment includes a gate electrode 16, a gate insulating film 15, an oxide semiconductor layer 12 including a first region A 1 and a second region A 2, a source electrode 13, and a drain formed on a substrate 11.
  • the thin film transistor 2 including the electrode 14 and the capacitor 70, the charge collection electrode 71 formed on the capacitor 70, the X-ray conversion layer 72, and the upper electrode 73 are configured.
  • a passivation film 75 is provided on the thin film transistor 2.
  • the capacitor 70 has a structure in which an insulating film 78 is sandwiched between a capacitor lower electrode 76 and a capacitor upper electrode 77.
  • the capacitor upper electrode 77 is connected to one of the source electrode 13 and the drain electrode 14 (the drain electrode 14 in FIG. 7) of the thin film transistor 2 through a contact hole 79 provided in the insulating film 78.
  • the charge collection electrode 71 is provided on the capacitor upper electrode 77 in the capacitor 70 and is in contact with the capacitor upper electrode 77.
  • the X-ray conversion layer 72 is a layer formed of amorphous selenium, and is provided so as to cover the thin film transistor 2 and the capacitor 70.
  • the upper electrode 73 is provided on the X-ray conversion layer 72 and is in contact with the X-ray conversion layer 72.
  • the X-ray sensor 7 of this embodiment includes a plurality of gate wirings 81 that are parallel to each other and a plurality of data wirings 82 that intersect with the gate wirings 81 and are parallel to each other.
  • the gate wiring 81 and the data wiring 82 are electrically insulated.
  • the thin film transistor 2 is provided in the vicinity of the intersection between the gate line 81 and the data line 82.
  • the gate electrode 16 of the thin film transistor 2 is connected to the gate wiring 81, and the source electrode 13 of the thin film transistor 2 is connected to the data wiring 82.
  • the drain electrode 14 of the thin film transistor 2 is connected to the charge collecting electrode 71, and the charge collecting electrode 71 constitutes a capacitor 70 together with the grounded counter electrode 76.
  • X-rays are irradiated from the top (upper electrode 73 side) in FIG.
  • the generated charges are accumulated in the capacitor 70 and read out by sequentially scanning the thin film transistor 2.
  • the X-ray sensor of the present invention includes the thin film transistor 2 having a high on-current and excellent reliability, the S / N is high and the sensitivity characteristic is excellent. A range image is obtained.
  • the X-ray digital imaging apparatus of the present invention is suitable not only for still image shooting but also for an X-ray digital imaging apparatus that can perform fluoroscopy with a moving image and still image shooting. Further, when the first region A1 and the second region A2 constituting the oxide semiconductor layer (active layer) in the thin film transistor 2 are amorphous, an image with excellent uniformity can be obtained.
  • the X-ray sensor of this embodiment shown in FIG. 7 is provided with a top gate type thin film transistor.
  • the thin film transistor used in the sensor of the present invention is not limited to the top gate type, but a bottom gate type. A thin film transistor may be used.
  • the present invention is not limited to these examples.
  • the inventors of the present invention have a high mobility and a low mobility in a specific composition range for the IZO layer and the IGZO layer, which are the first region A1 and the second region constituting the oxide semiconductor layer.
  • the following experiment proved that an off-current device could be fabricated.
  • a p-type silicon substrate manufactured by Mitsubishi Materials Corporation
  • SiO 2 oxide film thinness: 100 nm
  • the composition (x) of the IZO film was modulated as shown in Table 2 below to form the first region.
  • the oxide semiconductor layer was continuously formed between the regions without being exposed to the atmosphere.
  • Sputtering of each region includes co-sputtering using an In 2 O 3 target and a ZnO target in the first region, and In 2 O 3 target, Ga 2 O 3 target, and ZnO in the second region. This was performed using ternary co-sputtering using a target.
  • the film thickness in each region was adjusted by adjusting the film formation time.
  • the detailed sputtering conditions in the first region and the characteristics of the fabricated TFT are shown in Table 2 below.
  • the ultimate vacuum, film formation pressure, film formation temperature, and oxygen / argon partial pressure ratio in the first region are common, and are 6 ⁇ 10 ⁇ 6 Pa, 4.4 ⁇ 10 ⁇ 1 Pa, room temperature, and 0.067, respectively. is there.
  • the sputtering conditions in the second region are as follows, and are common to Examples 1 and 2 and Comparative Examples 1 to 8. Ultimate vacuum: 6 ⁇ 10 ⁇ 6 Pa Deposition pressure: 4.4 ⁇ 10 ⁇ 1 Pa Deposition temperature: room temperature oxygen partial pressure / argon partial pressure; 0.067 Input power ratio of In 2 O 3 , Ga 2 O 3 , ZnO target; 19.3: 70.0: 14.5
  • transistor characteristics (Vg-Id characteristics) and mobility ⁇ were measured using a semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies).
  • Vg-Id characteristics are measured by fixing the drain voltage (Vd) to 10V, sweeping the gate voltage (Vg) within the range of -30V to + 30V, and measuring the drain current (Id) at each gate voltage (Vg). I went to do it.
  • the mobility is linear mobility from the Vg-Id characteristic in the linear region obtained by sweeping the gate voltage (Vg) in the range of -30V to + 30V with the drain voltage (Vd) fixed at 1V. Is calculated and written.
  • the measurement results for Examples 1 and 2 and Comparative Examples 3, 4, and 7 are shown in FIG. Further, in Examples 1 and 2 and Comparative Examples 1 to 8, Table 2 below and FIG. 10 collectively show the results of mobility and off-current in addition to the composition ratio of the first region.
  • the film formation conditions in the second region are the same as the ultimate vacuum, the film formation pressure, the film formation temperature, and the oxygen / argon partial pressure, which are 6 ⁇ 10 ⁇ 6 Pa, 4.4 ⁇ 10 ⁇ 1 Pa, and room temperature, respectively.
  • the film was formed by modulating the cation composition ratio as shown in Table 3 below.
  • annealing was performed under the following conditions. (Post annealing conditions) Annealing temperature: 300 ° C Annealing time: 1 hour Annealing atmosphere: oxygen partial pressure 100% The mobility and off-current were measured and are shown in Table 3 below.
  • the off-state current is maintained while maintaining high mobility. It is possible to manufacture a TFT having a sufficiently low value.
  • the mobility exceeds 30 cm 2 / Vs and the off-current is 1 ⁇ 10 ⁇ 9 A. This achieves both high mobility and low off-current. This means that a good composition range in the second region can be applied even if the IZO composition is different.
  • the thickness of the second region is preferably more than 10 nm, preferably 30 nm or more. Further, since the mobility is slightly lowered when the film thickness of the second region is 70 nm or more, the film thickness of the second region is more preferably less than 70 nm.
  • the thickness of the second region is 50 nm, and both the high mobility and the low off-current are compatible. Therefore, the IZO composition of the first region is different. However, it can be seen that the good film thickness range is the same.
  • the driving stability of the transistor of Example 2 was evaluated by continuous application of a constant voltage.
  • a general IGZO-TFT (Comparative Example 11) was produced.
  • FIG. 11 shows the threshold shift amount ( ⁇ Vth) with respect to the stress time. Also, extrapolating using an exponential approximation from the stress time-dependent data points ⁇ Vth in FIG. 11, Table 5 shows that calculates the threshold shift amount after 108 seconds.
  • Vth in the ⁇ Vth evaluation was calculated from the intersection of the Vg ⁇ Id curve and the normalized current value W / L ⁇ 10 ⁇ 9 (A).
  • Table 5 shows the field effect mobility and ⁇ Vth of Example 2 and Comparative Example 11.
  • FIG. 11 reveals that the thin film transistor of Example 2 has extremely high stability against continuous driving as compared with the thin film transistor of Comparative Example 11. Further, from Table 5, by using the TFT of the present invention, the field effect mobility can be continuously driven while realizing at least twice that of a TFT having an oxide semiconductor layer (active layer) composed of an IGZO single film. It can be seen that the stability against is improved by more than an order of magnitude.
  • the thin film transistor of the present invention is, for example, a display device as an electro-optical device (for example, a liquid crystal display device, an organic EL (Electro-Luminescence) display device, an inorganic material) It is suitable as a drive element in an EL display device or the like.
  • a display device as an electro-optical device (for example, a liquid crystal display device, an organic EL (Electro-Luminescence) display device, an inorganic material) It is suitable as a drive element in an EL display device or the like.
  • the thin film transistor of the present invention is a device such as a flexible display that can be manufactured by a low-temperature process using a resin substrate, an image sensor such as a CCD (Charge Coupled Device), a CMOS (Complementary Metal Oxide Semiconductor), or an X-ray sensor. It is suitably used as a drive element (drive circuit) in various electronic devices such as sensors and MEMS (Micro Electro Mechanical System).
  • an image sensor such as a CCD (Charge Coupled Device), a CMOS (Complementary Metal Oxide Semiconductor), or an X-ray sensor. It is suitably used as a drive element (drive circuit) in various electronic devices such as sensors and MEMS (Micro Electro Mechanical System).
  • drive circuit drive circuit
  • the disclosure of Japanese application 2011-177234 is incorporated herein by reference in its entirety. All documents, patent applications, and technical standards mentioned in this specification are to the same extent as if each individual document, patent application, and technical standard were specifically and individually described to be incorporated

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  • Solid State Image Pick-Up Elements (AREA)
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Abstract

L'invention concerne un transistor en couches minces comprenant : une électrode de grille ; une couche isolante de grille venant en contact avec l'électrode de grille ; une couche d'oxyde semi-conductrice disposée de sorte à faire face à l'électrode de grille, avec la couche isolante de grille entre les deux, comprenant une première région représentée par In(x)Zn(1-x)O(y) (dans laquelle 0,4 ≤ x ≤ 0,5 et y > 0) et une deuxième région représentée par In(a)Ga(b)Zn(c)O(d) (dans laquelle b/(a+b) > 0,250, c > 0 et d > 0), et située plus loin de l'électrode de grille que ne l'est la première région ; ainsi qu'une électrode de source et une électrode de drain disposées à distance l'une de l'autre et pouvant être en conduction entre elles par l'intermédiaire de la couche d'oxyde semi-conductrice.
PCT/JP2012/067507 2011-08-12 2012-07-09 Transistor en couches minces, procédé de production associé, dispositif d'affichage, capteur d'images, capteur de rayons x et dispositif d'imagerie numérique par rayons x WO2013024646A1 (fr)

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KR1020137033689A KR101529000B1 (ko) 2011-08-12 2012-07-09 박막 트랜지스터 및 그 제조 방법, 표시 장치, 이미지 센서, x 선 센서 그리고 x 선 디지털 촬영 장치

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JP2011177234A JP5679933B2 (ja) 2011-08-12 2011-08-12 薄膜トランジスタ及びその製造方法、表示装置、イメージセンサー、ｘ線センサー並びにｘ線デジタル撮影装置
JP2011-177234 2011-08-12

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US10304859B2 (en) 2013-04-12 2019-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having an oxide film on an oxide semiconductor film
CN111202536A (zh) * 2018-11-21 2020-05-29 京东方科技集团股份有限公司 射线探测器及其制造方法、电子设备
US11450691B2 (en) 2016-04-13 2022-09-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device including the semiconductor device
US11869981B2 (en) 2016-03-04 2024-01-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and display device including the semiconductor device

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US9356156B2 (en) * 2013-05-24 2016-05-31 Cbrite Inc. Stable high mobility MOTFT and fabrication at low temperature
JP6345544B2 (ja) * 2013-09-05 2018-06-20 株式会社半導体エネルギー研究所 半導体装置の作製方法
US9691906B2 (en) 2013-10-24 2017-06-27 Joled Inc. Method for producing thin film transistor
TWI549265B (zh) * 2015-02-11 2016-09-11 友達光電股份有限公司 畫素結構及其製造方法
KR101878161B1 (ko) * 2015-02-12 2018-07-13 주성엔지니어링(주) 박막 트랜지스터 및 그 제조방법
CN106328661B (zh) * 2015-06-29 2019-07-16 中国科学院微电子研究所 一种x射线传感器及其制造方法
JP6747247B2 (ja) * 2016-01-29 2020-08-26 日立金属株式会社 半導体装置および半導体装置の製造方法
CN107026208B (zh) * 2016-01-29 2020-11-13 日立金属株式会社 半导体装置和半导体装置的制造方法
WO2020103583A1 (fr) * 2018-11-21 2020-05-28 京东方科技集团股份有限公司 Détecteur de rayons et son procédé de fabrication, dispositif électronique

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US10304859B2 (en) 2013-04-12 2019-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having an oxide film on an oxide semiconductor film
US11063066B2 (en) 2013-04-12 2021-07-13 Semiconductor Energy Laboratory Co., Ltd. C-axis alignment of an oxide film over an oxide semiconductor film
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US11869981B2 (en) 2016-03-04 2024-01-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method thereof, and display device including the semiconductor device
US11450691B2 (en) 2016-04-13 2022-09-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device including the semiconductor device
CN111202536A (zh) * 2018-11-21 2020-05-29 京东方科技集团股份有限公司 射线探测器及其制造方法、电子设备

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