WO2013161570A1 - Transistor à effet de champ et son procédé de fabrication, écran, capteur d'image et capteur radiographique - Google Patents

Transistor à effet de champ et son procédé de fabrication, écran, capteur d'image et capteur radiographique Download PDF

Info

Publication number
WO2013161570A1
WO2013161570A1 PCT/JP2013/060865 JP2013060865W WO2013161570A1 WO 2013161570 A1 WO2013161570 A1 WO 2013161570A1 JP 2013060865 W JP2013060865 W JP 2013060865W WO 2013161570 A1 WO2013161570 A1 WO 2013161570A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
film
field effect
effect transistor
tft
Prior art date
Application number
PCT/JP2013/060865
Other languages
English (en)
Japanese (ja)
Inventor
雅司 小野
真宏 高田
田中　淳
鈴木　真之
Original Assignee
富士フイルム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士フイルム株式会社 filed Critical 富士フイルム株式会社
Priority to KR1020147029981A priority Critical patent/KR101633621B1/ko
Publication of WO2013161570A1 publication Critical patent/WO2013161570A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention relates to a field effect transistor, a manufacturing method thereof, a display device, an image sensor, and an X-ray sensor.
  • InGaZnO oxide semiconductor thin film As an oxide semiconductor layer (channel layer), particularly a thin film transistor (Thin Film Transistor: TFT).
  • TFT Thi Film Transistor
  • An oxide semiconductor thin film can be formed at a low temperature, exhibits higher mobility than amorphous silicon, and is transparent to visible light. Therefore, a flexible TFT should be formed on a substrate such as a plastic plate or film. Is possible (eg CS Chuang et al., SID 08 DIGEST, P-13).
  • Japanese Patent Laying-Open No. 2010-21555 includes a first region containing ITO (In, Sn, and O) on the side close to the gate electrode.
  • ITO In, Sn, and O
  • a TFT using an oxide semiconductor layer having a two-layer structure in which a second region containing InGaZnO is disposed on a side far from the gate electrode is disclosed.
  • a first region containing an In—Zn—O-based (hereinafter referred to as InZnO) oxide semiconductor is disposed on the side close to the gate electrode, and the side far from the gate electrode is disclosed.
  • Japanese Laid-Open Patent Publication No. 2006-165529 discloses a TFT in which an amorphous oxide including an In—Sn—Zn—O-based (hereinafter referred to as InSnZnO) oxide semiconductor is used for an oxide semiconductor layer. Yes.
  • a blue light emitting layer used for an organic EL (Electro Luminescence) including TFT and a liquid crystal shows broad light emission having a peak of about 450 nm, but the tail of the emission spectrum of blue light of the organic EL element continues to a wavelength of 420 nm.
  • the blue color filter allows light having a wavelength of 400 nm to pass through about 70%, it is required that the characteristic deterioration with respect to light irradiation in a wavelength region smaller than the wavelength 450 nm is low. If the optical band gap of the InGaZnO film is relatively narrow and the region has optical absorption, there arises a problem that a threshold shift of the transistor occurs.
  • CS Chuang et al., SID 08 DIGEST, P-13 evaluates the deterioration of characteristics of a TFT using conventional InGaZnO as an oxide semiconductor layer against light irradiation.
  • of the threshold shift amount with respect to irradiation exceeds 1V.
  • the first region as the current path layer contains ITO, and a high mobility TFT can be realized, but the light irradiation characteristic is not mentioned.
  • the mobility of the first region as the current path layer containing InZnO is lower than 10 cmA 2 / Vs, and the light irradiation characteristics are not mentioned.
  • InZnO a combination in which Sn is included in the first region at a level equal to or higher than inevitable impurities is described, but the TFT, mobility, and light irradiation characteristics according to the example are not mentioned.
  • the present invention has been made in view of the above circumstances, and has a high mobility exceeding 20 cm 2 / Vs and a high light stability in which the absolute value
  • ⁇ 2> The field effect transistor according to ⁇ 1>, wherein the composition of the first region is represented by c / (a + b + c) ⁇ 0.200.
  • ⁇ 3> The field effect transistor according to ⁇ 1> or ⁇ 2>, wherein the composition of the first region is represented by c / (a + b + c) ⁇ 0.700.
  • ⁇ 4> The field effect transistor according to any one of ⁇ 1> to ⁇ 3>, wherein the composition of the first region is represented by c / (a + b + c) ⁇ 1/3.
  • ⁇ 5> The field effect transistor according to any one of ⁇ 1> to ⁇ 4>, wherein the composition of the first region is represented by c / (a + b + c) ⁇ 0.400.
  • ⁇ 6> The field effect transistor according to any one of ⁇ 1> to ⁇ 5>, wherein the composition of the first region is represented by a / (a + b + c) ⁇ 1/3.
  • ⁇ 7> The field effect transistor according to any one of ⁇ 1> to ⁇ 6>, wherein the film thickness of the first region is 50 nm or less.
  • ⁇ 8> The field effect transistor according to ⁇ 7>, wherein the film thickness of the first region is 16 nm or less.
  • ⁇ 9> The field effect transistor according to any one of ⁇ 1> to ⁇ 8>, wherein the film thickness of the first region is 5 nm or more.
  • ⁇ 10> The field effect transistor according to any one of ⁇ 1> to ⁇ 9>, wherein the composition of the second region is represented by f / (e + f) ⁇ 0.875.
  • ⁇ 11> The field effect transistor according to any one of ⁇ 1> to ⁇ 10>, wherein the composition of the second region is represented by f / (e + f)> 0.250.
  • ⁇ 12> The field effect transistor according to any one of ⁇ 1> to ⁇ 11>, wherein the film thickness of the second region is more than 10 nm and less than 70 nm.
  • ⁇ 13> The field effect transistor according to any one of ⁇ 1> to ⁇ 12>, wherein the oxide semiconductor layer is an amorphous film.
  • ⁇ 14> The field effect transistor according to any one of ⁇ 1> to ⁇ 13>, wherein the second region has lower electrical conductivity than the first region.
  • a method of manufacturing a field effect transistor having an oxide semiconductor layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode, wherein the oxide semiconductor layer is formed as a step of In (A) Sn (b) Zn (c) O (d) (a> 0, b> 0, c> 0, d> 0, a + b + c 1)
  • a display device comprising the field-effect transistor according to any one of ⁇ 1> to ⁇ 14>.
  • An image sensor comprising the field-effect transistor according to any one of ⁇ 1> to ⁇ 14>.
  • An X-ray sensor comprising the field effect transistor according to any one of ⁇ 1> to ⁇ 14>.
  • a field effect that achieves both high mobility exceeding 20 cm 2 / Vs and high light stability in which the absolute value
  • of the threshold shift amount is 1 V or less with respect to light irradiation with a wavelength of 420 nm.
  • Type transistor, manufacturing method thereof, display device, image sensor, and X-ray sensor can be provided.
  • FIG. 1A is a schematic diagram showing an example of a top contact type TFT having a top gate structure, which is a TFT according to an embodiment of the present invention.
  • FIG. 1B is a schematic diagram showing an example of a bottom contact type TFT with a top gate structure, which is a TFT according to an embodiment of the present invention.
  • FIG. 1C is a schematic diagram showing an example of a top contact type TFT with a bottom gate structure, which is a TFT according to an embodiment of the present invention.
  • FIG. 1D is a schematic diagram showing an example of a bottom contact type TFT with a bottom gate structure, which is a TFT according to an embodiment of the present invention.
  • FIG. 1A is a schematic diagram showing an example of a top contact type TFT having a top gate structure, which is a TFT according to an embodiment of the present invention.
  • FIG. 1B is a schematic diagram showing an example of a bottom contact type TFT with a top gate structure, which is a TFT according
  • FIG. 2 is a schematic sectional view of a part of a liquid crystal display device according to an embodiment of the electro-optical device of the invention.
  • FIG. 3 is a schematic configuration diagram of electrical wiring of the liquid crystal display device shown in FIG.
  • FIG. 4 is a schematic sectional view of a part of an active matrix organic EL display device according to an embodiment of the electro-optical device of the invention.
  • FIG. 5 is a schematic configuration diagram of the electrical wiring of the electro-optical device shown in FIG.
  • FIG. 6 is a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention.
  • FIG. 7 is a schematic configuration diagram of electrical wiring of the sensor shown in FIG. FIG.
  • FIG. 8A is a plan view of the TFTs of the example and the comparative example
  • FIG. 8B is a cross-sectional view of the TFT shown in FIG.
  • FIG. 9 is a diagram showing a ternary phase diagram focusing on the composition of the first region in Examples 1 to 10 and Comparative Examples 2 to 4.
  • FIG. 10 is a diagram showing representative Vg-Id characteristics among the measurement results of transistor characteristics (Vg-Id characteristics) for the TFTs according to Examples 1 to 10 and Comparative Examples 1 to 6.
  • FIG. 11 is a diagram illustrating the IV characteristics when the TFT according to Example 3 is irradiated with monochrome light, together with the IV characteristics before irradiation with monochrome light.
  • FIG. 10 is a diagram showing representative Vg-Id characteristics among the measurement results of transistor characteristics (Vg-Id characteristics) for the TFTs according to Examples 1 to 10 and Comparative Examples 1 to 6.
  • FIG. 11 is a diagram illustrating the IV characteristics when the TFT according to Example
  • FIG. 12 is a diagram illustrating the IV characteristics when the TFT according to Example 5 is irradiated with monochrome light, together with the IV characteristics before irradiation with monochrome light.
  • FIG. 13 is a diagram illustrating the IV characteristics when the TFT according to Example 6 is irradiated with monochrome light, together with the IV characteristics before monochrome light irradiation.
  • FIG. 14 is a diagram illustrating the IV characteristics when the TFT according to Example 7 is irradiated with monochrome light, together with the IV characteristics before irradiation with monochrome light.
  • FIG. 18 is a graph in which the relationship between the mobility and the In ratio ⁇ a / (a + b + c) ⁇ with respect to the total composition ratio of In, Sn, and Zn in the first region is plotted based on Table 3.
  • FIG. 19 is a graph plotting the relationship between the threshold shift amount ⁇ Vth and the Zn ratio ⁇ c / (a + b + c) ⁇ with respect to the sum of the composition ratios of In, Sn, and Zn in the first region based on Table 3.
  • FIG. 20 is a diagram showing the composition dependence of the carrier concentration in the InSnZnO single film.
  • a field effect transistor according to an embodiment of the present invention will be specifically described by taking a TFT as an example.
  • a TFT according to an embodiment of the present invention includes a gate electrode, a gate insulating film, an oxide semiconductor layer (active layer), a source electrode, and a drain electrode, and applies a voltage to the gate electrode to flow through the oxide semiconductor layer. It is an active element having a function of controlling current and switching current between a source electrode and a drain electrode.
  • the oxide semiconductor layer further includes a first region in the film thickness direction and a second region disposed on the side farther from the gate electrode than the first region. I have.
  • no layer other than the oxide semiconductor layer such as an electrode layer is inserted between the first region and the second region.
  • the TFT may be formed on the substrate, or when a component (for example, an electrode) of the TFT functions as the substrate, a separate substrate may be omitted. Further, the TFT and the substrate may be in direct contact, or an additional layer or element may be provided between the TFT and the substrate.
  • the element structure of the TFT may be any of a so-called reverse stagger structure (also referred to as a bottom gate structure (type)) and a stagger structure (also referred to as a top gate structure (type)) based on the position of the gate electrode. Good. Further, based on a contact portion between the oxide semiconductor layer and the source and drain electrodes (referred to as “source / drain electrodes” as appropriate), either a so-called top contact type or bottom contact type may be employed. Note that the top gate structure is a form in which a gate electrode is disposed on the upper side of the gate insulating film and an oxide semiconductor layer is formed on the lower side of the gate insulating film.
  • the gate electrode is disposed on the side, and the oxide semiconductor layer is formed on the upper side of the gate insulating film.
  • the bottom contact type is a form in which the source / drain electrodes are formed before the oxide semiconductor layer and the lower surface of the oxide semiconductor layer is in contact with the source / drain electrodes.
  • the top contact type is an oxide In this embodiment, the semiconductor layer is formed before the source / drain electrodes, and the upper surface of the oxide semiconductor layer is in contact with the source / drain electrodes.
  • FIG. 1A is a schematic diagram showing an example of a top contact type TFT having a top gate structure, which is a TFT according to an embodiment of the present invention.
  • the second region 14 ⁇ / b> B of the oxide semiconductor layer 14 and the first region 14 ⁇ / b> A of the oxide semiconductor layer 14 are sequentially stacked on one surface in the thickness direction of the substrate 12.
  • the source electrode 18 and the drain electrode 20 are spaced apart from each other on the first region 14A (surface), and the gate insulating film 22 and the gate electrode 24 are sequentially stacked on these (surface). ing.
  • FIG. 1B is a schematic view showing an example of a bottom contact type TFT having a top gate structure, which is a TFT according to an embodiment of the present invention.
  • the source electrode 18 and the drain electrode 20 are provided on one surface in the thickness direction of the substrate 12 so as to be separated from each other. Then, the second region 14B of the oxide semiconductor layer 14, the first region 14A of the oxide semiconductor layer 14, the gate insulating film 22, and the gate electrode 24 are sequentially stacked.
  • FIG. 1C is a schematic diagram showing an example of a top contact type TFT having a bottom gate structure, which is a TFT according to an embodiment of the present invention.
  • the gate electrode 24, the gate insulating film 22, the first region 14 ⁇ / b> A of the oxide semiconductor layer 14, and the second region of the oxide semiconductor layer 14 are formed on one surface in the thickness direction of the substrate 12.
  • the regions 14B are sequentially stacked.
  • the source electrode 18 and the drain electrode 20 are spaced from each other on the second region 14B (surface).
  • FIG. 1D is a schematic view showing an example of a bottom contact type TFT with a bottom gate structure, which is a TFT according to an embodiment of the present invention.
  • the gate electrode 24 and the gate insulating film 22 are sequentially stacked on one surface of the substrate 12 in the thickness direction.
  • the source electrode 18 and the drain electrode 20 are disposed on the surface of the gate insulating film 22 so as to be separated from each other, and further on the (surface) thereof, the first region 14A of the oxide semiconductor layer 14 and the oxide semiconductor
  • the second region 14B of the layer 14 is sequentially stacked.
  • the TFT according to this embodiment can have various configurations other than the above, and may have a configuration including a protective layer over an oxide semiconductor layer, an insulating layer over a substrate, and the like as appropriate. Good.
  • top contact type TFT 40 having a bottom gate structure shown in FIG. 1C is specifically described as a representative example, but the following materials, thicknesses, and the like can be similarly applied to other types of TFTs. .
  • the shape, structure, size, etc. of the substrate 12 for forming the TFT 40 are not particularly limited and can be appropriately selected depending on the purpose.
  • the structure of the substrate 12 may be a single layer structure or a laminated structure.
  • an inorganic material such as glass or YSZ (yttrium stabilized zirconium), a resin such as polyethylene terephthalate or polyethylene naphthalate, or a resin such as a composite plastic material with clay mineral or particles having a mica-derived crystal structure
  • a substrate formed of a composite material or the like can be used.
  • a substrate formed of a resin or a resin composite material is preferable from the viewpoint of light weight and flexibility.
  • the resin substrate may include a gas barrier layer for preventing permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate and adhesion to the lower electrode, and the like.
  • the gate electrode 24 is not particularly limited as long as it has high conductivity.
  • a metal such as Al, Mo, Cr, Ta, Ti, Au, and Ag, Al—Nd, tin oxide, zinc oxide, indium oxide,
  • a metal oxide conductive film such as indium tin oxide (ITO) or zinc indium oxide (InZnO) can be used as a single layer or a stacked structure of two or more layers.
  • the gate insulating film 22 is preferably one having high insulation properties, for example, an insulating film such as SiO 2 , SiNx, SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , HfO 2 , or a compound thereof. Can be made of an insulating film or the like containing at least two.
  • the first region 14A including the first region 14A and the first region 14A farther from the gate electrode 24 than the first region 14A.
  • In (e) Ga (f) Zn (g) O (h) (e ) > 0, f> 0, g> 0, h> 0, e + f + g 1, and may be abbreviated as InGaZnO film hereinafter).
  • the second region 14B is disposed on the side far from the gate electrode 24, and preferably has lower electrical conductivity than the first region 14A.
  • the carriers are electrons
  • the carrier concentration indicates the electron carrier concentration
  • the carrier mobility indicates the electron mobility.
  • the carriers are holes
  • the carrier concentration indicates the hole carrier concentration
  • the carrier mobility indicates the hole mobility.
  • the carrier concentration and carrier mobility of the substance can be obtained by Hall measurement.
  • the electric conductivity can be obtained by measuring the specific resistance of the film whose thickness is known, thereby obtaining the electric conductivity of the film.
  • composition of the first region 14A and the second region 14B is recognized by using, for example, fluorescent X-ray analysis or ICP emission analysis as a single film, and secondary ion mass spectrometry (SIMS) as a laminated film, for example. I can do it.
  • fluorescent X-ray analysis or ICP emission analysis as a single film
  • SIMS secondary ion mass spectrometry
  • the TFT 40 of the present embodiment having the above oxide semiconductor layer 14 has a high mobility exceeding 20 cm 2 / Vs and a high threshold shift amount absolute value
  • the second region 14B is a so-called “resistance layer”.
  • the first region 14A is an InSnZnO film in the TFT of this embodiment, both high light stability can be achieved as compared with the case where an InGaZnO film is used as the first region 14A, for example.
  • the composition in the vicinity of In: Sn: Zn 1.000: 1.000: 1.000 which does not require extreme compositional modulation as compared with the InGaZnO film. It is also possible to achieve higher mobility. In an InGaZnO film, it was difficult to achieve high mobility only in a composition region having an extremely high In content.
  • a high mobility and high switching performance e.g. On / Off ratio is more than 10 6
  • the TFT was constituted of only one layer of the oxide semiconductor layer 14 InSnZnO film. This is because the carrier concentration of the InSnZnO film is relatively high, so that pinch-off is difficult only with the InSnZnO film.
  • high mobility and high switching performance are realized by using a stacked structure of the first region 14A and the second region 14B.
  • the oxide semiconductor layer 14 has a two-layer structure of the first region 14A and the second region 14B, the first region 14A is an InSnZnO film, and the second region 14B is an InGaZnO film. Yes.
  • the oxide semiconductor layer 14 may be either an amorphous film or a crystalline film. However, in the case of an amorphous film, since it can be formed at a low temperature, it is preferably formed on the flexible substrate 12. In the case of an amorphous film, a crystal grain boundary does not exist and a highly uniform film can be obtained. Note that whether or not the oxide semiconductor layer 14 is an amorphous film can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, the oxide semiconductor layer 14 can be determined to be an amorphous film.
  • the film thickness (total film thickness) including the first region 14A and the second region 14B in the oxide semiconductor layer 14 is not particularly limited, but the film uniformity and the total carriers in the oxide semiconductor layer 14 are not limited. From the viewpoint of controlling the concentration, it is preferably 10 nm or more and 200 nm or less.
  • the first region 14A of the oxide semiconductor layer 14 preferably includes In, Sn, Zn, and O as main constituent elements.
  • the “main constituent element” means that the total ratio of In, Sn, Zn, and O with respect to all the constituent elements in the first region 14A is 98% or more. Therefore, the first region 14A may also contain other elements such as Mg as described later.
  • the first region 14A contains In (a) Sn (b) Zn (c) O (d) , and the composition of the first region 14A is c / (a + b + c) ⁇ 0.200. It is preferable to be represented by This is because the threshold voltage (Vth) of the TFT 40 can be suppressed from appearing significantly on the negative side. Note that the above composition does not consider other elements other than In, Sn, Zn, and O described above, but does not indicate that the first region 14A does not contain other elements. The same applies to the subsequent compositional expressions.
  • the composition of the first region 14A is more preferably represented by c / (a + b + c) ⁇ 1/3.
  • the threshold voltage of the TFT 40 can be made higher on the plus side than 0V. It is even more preferable that the composition of the first region 14A is represented by c / (a + b + c) ⁇ 0.400. This is because when c / (a + b + c) ⁇ 0.400, the threshold voltage is almost saturated, so that fluctuation of the threshold voltage with respect to the Zn composition ratio can be suppressed.
  • the composition of the first region 14A is preferably represented by c / (a + b + c) ⁇ 0.700. This is because the mobility of the TFT 40 can be more than 30 cm 2 / Vs. Furthermore, the composition of the first region 14A is more preferably 0.200 ⁇ c / (a + b + c) ⁇ 0.700. This is because the absolute value
  • the composition of the first region 14A is expressed by a / (a + b + c) ⁇ 1/3 by changing the viewpoint to the composition ratio of In. This is because the mobility of the TFT 40 can be more than 40 cm 2 / Vs.
  • the film thickness of the first region 14A is preferably 50 nm or less. This is because it is possible to suppress the threshold voltage of the TFT 40 from appearing on the minus side and to suppress the deterioration of the S value.
  • the film thickness of the first region 14A is preferably 5 nm or more. This is because the flatness of the film can be improved.
  • the film thickness of the first region 14A is preferably 16 nm or less from the following fully depleted theoretical formulas (1) to (3).
  • Table 1 shows the meanings of symbols in each theoretical formula. The parameters in Table 1 are as follows. ) ”) Is used.
  • the film thickness of 16 nm or less satisfies the condition of complete depletion. Therefore, it can be seen from the above theoretical formula that the film thickness of the first region 14A is preferably 16 nm or less in order to realize good switching characteristics and low off-state current.
  • the electric conductivity of the first region 14A is preferably 10 ⁇ 6 Scm ⁇ 1 or more and less than 10 2 Scm ⁇ 1 . More preferably, it is 10 ⁇ 4 Scm ⁇ 1 or more and less than 10 2 Scm ⁇ 1 , and further preferably 10 ⁇ 1 Scm ⁇ 1 or more and less than 10 2 Scm ⁇ 1 .
  • the second region 14B of the oxide semiconductor layer 14 contains In (e) Ga (f) Zn (g) O (h) as described above, but In, Ga, Zn, and O Is the main constituent element.
  • the “main constituent element” means that the total ratio of In, Ga, Zn, and O with respect to all the constituent elements in the second region 14B is 98% or more. Accordingly, the second region 14B may also contain other elements such as Mg as described later.
  • the composition of the second region 14B is preferably represented by f / (e + f) ⁇ 0.875. This is because high mobility is easily achieved when the composition of the second region 14B is a composition range represented by f / (e + f) ⁇ 0.875.
  • the composition of the second region 14B is e / (e + f)> 0.875, the resistance value of the second region 14B becomes relatively high, so that it is difficult to secure an ohmic contact, and high movement is caused. Getting a degree is likely to be difficult.
  • the composition of the second region 14B is preferably represented by f / (e + f)> 0.250.
  • the composition of the second region 14B is f / (e + f) ⁇ 0.250, the carrier concentration of the second region 14B is relatively high, and the second region 14B is changed to the first region 14A. Since the effect of carrier inflow increases, the hump effect may occur in the Vg-Id characteristic, or the threshold voltage may be greatly negative. Therefore, the composition of the second region 14B is preferably represented by f / (e + f)> 0.250.
  • the film thickness of the second region 14B is preferably more than 10 nm and less than 70 nm. This is because when the film thickness of the second region 14B is more than 10 nm, reduction of off-current and suppression of deterioration of the S value can be expected. Further, when the film thickness of the second region 14B is less than 70 nm, an increase in resistance between the source / drain electrodes 18 and 20 and the first region 14A is suppressed, and consequently a decrease in mobility is suppressed. Because it can be done.
  • the electric conductivity of the second region 14B can take the same range as that of the first region 14A, but is preferably lower than the first region 14A by 10 ⁇ 7 Scm ⁇ 1 or more and 10 1 Scm ⁇ 1. Is less than. More preferably, it is 10 ⁇ 7 Scm ⁇ 1 or more and less than 10 ⁇ 1 Scm ⁇ 1 .
  • the carrier concentration of the oxide semiconductor layer in other words, the electric conductivity can be controlled not only by the composition modulation of the first region 14A and the second region 14B, but also by the oxygen partial pressure control at the time of film formation. .
  • the oxygen concentration can be controlled by controlling the oxygen partial pressure during film formation in the first region 14A and the second region 14B, respectively. If the oxygen partial pressure at the time of film formation is increased, the carrier concentration can be reduced, and a reduction in off-current can be expected accordingly. On the other hand, if the oxygen partial pressure during film formation is lowered, the carrier concentration can be increased, and an increase in field effect mobility can be expected accordingly. Further, for example, by performing a treatment of irradiating oxygen radicals or ozone after forming the first region 14A, the oxidation of the film can be promoted and the amount of oxygen vacancies in the first region can be reduced.
  • the band gap of the film can be increased by doping Mg.
  • the band profile of the laminated film is compared with a system in which the composition ratio of only In, Sn (or Ga), and Zn is controlled by doping Mg in each of the first region 14A and the second region 14B.
  • the band gap can be increased while maintaining In this case, since the first region 14A is an InSnZnO film, the band gap is relatively narrower than that of the InGaZnO film in the second region 14B. Therefore, the Mg in the first region 14A than in the second region 14B. It is considered that doping with a larger amount of can expand the band gap contributing to the light irradiation stability more efficiently.
  • the blue light emitting layer used in the organic EL exhibits broad light emission having a peak at a wavelength of about 450 nm
  • the optical band gaps of the first region 14A and the second region 14B are relatively narrow, and optical absorption occurs in that region.
  • the material used for the channel layer has a larger band gap, particularly for a thin film transistor used for driving an organic EL.
  • the carrier concentration of the first region 14A and the second region 14B can be arbitrarily controlled by cation doping.
  • a material for example, Ti, Ta, etc.
  • the carrier concentration is preferably controlled by the amount).
  • TFT manufacturing method Next, a TFT manufacturing method according to an embodiment of the present invention will be briefly described using a top contact type TFT 40 having a bottom gate structure shown in FIG. 1C as a representative example. Note that the following method can be similarly applied to the manufacturing method of TFTs of other forms.
  • the substrate 12 is prepared, and the gate electrode 24 is formed on one surface of the substrate 12 in the thickness direction.
  • the method for forming the gate electrode 24 include a wet method such as a printing method and a coating method, a physical method such as a vacuum deposition method, a sputtering method, and an ion plating method, and a chemical method such as a CVD method and a plasma CVD method. It is done.
  • the sputtering method after forming an electrode film by the sputtering method, the gate electrode 24 is formed by patterning into a predetermined shape by an etching or lift-off method. At this time, it is preferable to pattern the gate electrode 24 and the gate wiring simultaneously.
  • the film is formed by controlling the degree of vacuum and the oxygen flow rate by RF magnetron sputtering deposition.
  • a complex oxide target adjusted to have a desired cation composition may be used, or ternary co-sputtering may be used.
  • the second film forming step of forming the second region 14B with the second oxygen partial pressure / argon partial pressure inside the sputter film forming chamber is sequentially performed.
  • the order of the first film forming process and the second film forming process is reversed.
  • the first oxygen partial pressure / argon partial pressure is higher than the second oxygen partial pressure / argon partial pressure.
  • the first oxygen partial pressure / argon partial pressure is higher than the second oxygen partial pressure / argon partial pressure.
  • the oxygen partial pressure of the first region 14A it is possible to reduce defects related to oxygen in the first region 14A that can be a carrier traveling layer. Because it can. Thereby, excess carriers can be suppressed and high switching characteristics can be obtained.
  • an oxide semiconductor system such as InGaZnO, it is said that a deep level due to an oxygen defect exists immediately above a valence body.
  • this deep level can degrade the light stability, if this level is suppressed by increasing the oxygen partial pressure, the effect of increasing the light stability can be expected even though the effect is not as great as the composition.
  • the effect of ionized impurity scattering (which acts as a scattering source when there are ionized oxygen defects serving as donors) can be suppressed, so that relatively high mobility is likely to be realized. .
  • the substrate 12 it is preferable not to expose the substrate 12 to the air during the film forming process of the oxide semiconductor layer 14. That is, it is preferable to perform the first film formation step and the second film formation step continuously without exposing the substrate 12 to the atmosphere. This is for preventing impurities from being mixed into the oxide semiconductor layer 14.
  • Patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed on the remaining portion by photolithography, and the pattern is formed by etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid.
  • an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid.
  • a metal film for forming the source / drain electrodes 18 and 20 is formed on the surface of the oxide semiconductor layer 14.
  • the method for forming the source / drain electrodes 18 and 20 can be the same as that for the gate electrode 24.
  • the metal film is patterned into a predetermined shape by etching or a lift-off method, and the source electrode 18 and the drain electrode 20 are formed. At this time, it is preferable to pattern the source / drain electrodes 18 and 20 and wiring (not shown) connected to these electrodes simultaneously.
  • the atmosphere during post-annealing is preferably an inert atmosphere or an oxidizing atmosphere.
  • oxygen in the oxide semiconductor layer is difficult to escape, and generation of surplus carriers and variation in electrical characteristics can be suppressed.
  • the post-annealing time it is preferable to hold it for at least 10 minutes in consideration of the time required for the film temperature to become uniform.
  • the TFT 40 of the present embodiment high mobility and high light irradiation stability can be obtained without using a protective layer or the like on the oxide semiconductor layer 14 for reducing deterioration in characteristics due to light irradiation.
  • the oxide semiconductor layer 14 may be provided with a protective layer as described above.
  • a protective layer that absorbs and reflects light in the ultraviolet region (wavelength 400 nm or less)
  • the stability against light irradiation can be further improved.
  • a top contact type TFT 40 with a bottom gate structure as shown in FIG. 1C can be manufactured.
  • the InSnZnO film in the first region 14A and the InGaZnO film in the second region 14B can be formed at a low temperature (for example, 400 ° C. or lower).
  • a flexible TFT device can be manufactured as the entire TFT 40.
  • the TFT according to this embodiment can have various configurations other than the above.
  • an insulating layer is provided on the substrate 12 or exposed from between the source electrode 18 and the drain electrode 20.
  • a single protective layer or a plurality of protective layers may be provided on the surface of the oxide semiconductor layer 14.
  • electro-optical devices for example, display devices such as liquid crystal display devices, organic EL (Electro Luminescence) display devices, inorganic EL display devices, etc.
  • a driving element in the above, particularly for a large area device.
  • the TFT of this embodiment is particularly suitable for a device that can be manufactured by a low-temperature process using a resin substrate (for example, a flexible display), and various sensors such as an X-ray sensor, MEMS (Micro Electro Mechanical System), and the like. It is suitably used as a drive element (drive circuit) in this electronic device.
  • the electro-optical device or sensor includes the above-described TFT of the present invention.
  • electro-optical devices include display devices (eg, liquid crystal display devices, organic EL display devices, inorganic EL display devices, etc.).
  • an image sensor such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor), an X-ray sensor, or the like is suitable.
  • the electro-optical device or sensor of the present embodiment exhibits good characteristics with low power consumption.
  • the characteristics referred to here indicate display characteristics in the case of an electro-optical device (display device), and sensitivity characteristics in the case of a sensor.
  • a liquid crystal display device, an organic EL display device, and an X-ray sensor will be described as representative examples of an electro-optical device or sensor including a field effect transistor manufactured according to the present invention.
  • FIG. 2 is a schematic sectional view of a part of a liquid crystal display device according to an embodiment of the electro-optical device of the present invention.
  • the liquid crystal display device 100 of this embodiment includes a substrate 12, a top contact type TFT 10 having the top gate structure shown in FIG. 1A, and a gate electrode protected by a passivation layer 102 of the TFT 10.
  • 24 includes a liquid crystal layer 108 sandwiched between the pixel lower electrode 104 and the counter upper electrode 106, and an RGB color filter 110 for developing different colors corresponding to each pixel.
  • polarizing plates 112a and 112b are provided on the color filter 110, respectively.
  • the liquid crystal display device 100 of the present embodiment includes a plurality of gate lines 112 parallel to each other and data lines 114 parallel to each other intersecting the gate lines 112.
  • the gate wiring 112 and the data wiring 114 are electrically insulated.
  • the TFT 10 is provided in the vicinity of the intersection between the gate wiring 112 and the data wiring 114.
  • the gate electrode 24 of the TFT 10 is connected to the gate wiring 112, and the source electrode 18 of the TFT 10 is connected to the data wiring 114.
  • the drain electrode 20 of the TFT 10 is connected to the pixel lower electrode 104 through a contact hole 116 provided in the gate insulating film 22 (a conductor is embedded in the contact hole 116).
  • the pixel lower electrode 104 forms a capacitor 118 together with the grounded counter upper electrode 106.
  • the TFT 10 having the top gate structure is provided in the liquid crystal device of the present embodiment shown in FIG. 2.
  • the TFT used in the liquid crystal device which is the display device of the present invention is not limited to the top gate structure.
  • a TFT having a bottom gate structure may be used.
  • the TFT 10 manufactured according to the present invention has a high mobility, a high-definition display such as high definition, high-speed response, and high contrast is possible in a liquid crystal display device, which is suitable for a large screen.
  • a high-definition display such as high definition, high-speed response, and high contrast is possible in a liquid crystal display device, which is suitable for a large screen.
  • the InGaZnO film or the InSnZnO film of the oxide semiconductor layer 14 is amorphous, variation in element characteristics can be suppressed, and excellent display quality without unevenness can be realized on a large screen.
  • the gate voltage can be reduced, and thus the power consumption of the display device can be reduced.
  • a thin film transistor can be manufactured using an amorphous InGaZnO film or an InSnZnO film that can be formed at a low temperature (for example, 200 ° C. or lower) as a semiconductor layer.
  • a plastic substrate can be used. Therefore, according to the present invention, a flexible liquid crystal display device excellent in display quality can be provided.
  • FIG. 4 is a schematic sectional view of a part of an active matrix type organic EL display device according to an embodiment of the electro-optical device of the present invention
  • FIG. 5 is a schematic configuration diagram of the electric wiring. .
  • the simple matrix method has an advantage that it can be manufactured at low cost.
  • the number of scanning lines and the light emission time per scanning line are inversely proportional. Therefore, it is difficult to increase the definition and increase the screen size.
  • the active matrix method has a high manufacturing cost because a transistor and a capacitor are formed for each pixel.
  • it is suitable for high definition and large screen.
  • the organic EL display device 200 of this embodiment includes a plurality of gate wirings 220 that are parallel to each other, and data wirings 222 and driving wirings that are parallel to each other and intersect the gate wirings 220. 224.
  • the gate wiring 220, the data wiring 222, and the drive wiring 224 are electrically insulated.
  • the gate electrode 24 of the switching TFT 206 is connected to the gate wiring 220, and the source electrode 18 of the switching TFT 206 is connected to the data wiring 222.
  • the drain electrode 20 of the switching TFT 206 is connected to the driving TFT 204 gate electrode 24, and the driving TFT 10 a is kept on by using the capacitor 226.
  • the source electrode 18 of the driving TFT 204 is connected to the driving wiring 224, and the drain electrode 20 is connected to the organic EL light emitting element 214.
  • the organic EL device of this embodiment shown in FIG. 4 includes the top-gate driving TFT 204 and the switching TF 206.
  • the TFT used in the organic EL device which is the display device of the present invention is the top.
  • the TFT is not limited to the gate structure and may be a bottom gate TFT.
  • a thin film transistor can be manufactured using an amorphous InGaZnO film or an InSnZnO film that can be formed at a low temperature (for example, 200 ° C. or less) as the oxide semiconductor layer 14.
  • a resin substrate plastic substrate
  • FIG. 6 shows a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention
  • FIG. 7 shows a schematic configuration diagram of its electric wiring.
  • FIG. 6 is a schematic cross-sectional view in which a part of the X-ray sensor array is enlarged more specifically.
  • the X-ray sensor 300 of this embodiment includes the TFT 10 and the capacitor 310 formed on the substrate 12, the charge collection electrode 302 formed on the capacitor 310, the X-ray conversion layer 304, and the upper electrode 306. Composed.
  • a passivation film 308 is provided on the TFT 10.
  • the capacitor 310 has a structure in which an insulating film 316 is sandwiched between a capacitor lower electrode 312 and a capacitor upper electrode 314.
  • the capacitor upper electrode 314 is connected to one of the source electrode 18 and the drain electrode 20 (the drain electrode 20 in FIG. 6) of the TFT 10 through a contact hole 318 provided in the insulating film 316.
  • the charge collection electrode 302 is provided on the capacitor upper electrode 314 in the capacitor 310 and is in contact with the capacitor upper electrode 314.
  • the X-ray conversion layer 304 is a layer containing amorphous selenium and is provided so as to cover the TFT 10 and the capacitor 310.
  • the upper electrode 306 is provided on the X-ray conversion layer 304 and is in contact with the X-ray conversion layer 304.
  • the X-ray sensor 300 of this embodiment includes a plurality of gate wirings 320 that are parallel to each other and a plurality of data wirings 322 that intersect with the gate wirings 320 and are parallel to each other.
  • the gate wiring 320 and the data wiring 322 are electrically insulated.
  • the TFT 10 is provided in the vicinity of the intersection between the gate wiring 320 and the data wiring 322.
  • the gate electrode 24 of the TFT 10 is connected to the gate wiring 320, and the source electrode 18 of the TFT 10 is connected to the data wiring 322.
  • the drain electrode 20 of the TFT 10 is connected to the charge collecting electrode 302, and the charge collecting electrode 302 is connected to the capacitor 310.
  • X-rays are irradiated from the upper part (upper electrode 306 side) in FIG. 6, and electron-hole pairs are generated in the X-ray conversion layer 304.
  • the generated charge is accumulated in the capacitor 310 and read out by sequentially scanning the TFT 10.
  • the X-ray sensor 300 of the present embodiment includes a TFT 10 with high mobility and on-current and excellent sensitivity characteristics, and thus has a high S / N and is suitable for a large screen. Moreover, since it has excellent sensitivity characteristics, an image with a wide dynamic range can be obtained when used in an X-ray digital imaging apparatus.
  • the X-ray digital imaging apparatus according to the present embodiment is suitable not only for still image shooting but also for an X-ray digital imaging apparatus that can perform fluoroscopy with a moving image and still image shooting. Further, when the InGaZnO film or InSnZnO film in the TFT 10 is amorphous, an image with excellent uniformity can be obtained.
  • the TFT 10 having the top gate structure is provided in the X-ray sensor 300 of the present embodiment shown in FIG. 6, the TFT 10 having the top gate structure is provided.
  • the TFT used in the sensor of the present invention is not limited to the top gate structure, but the bottom gate structure.
  • a TFT having a gate structure may be used.
  • composition modulation is performed for each of the examples and the comparative examples, so that the first region 506 of the oxide semiconductor layer has a thickness of 5 nm.
  • a sputtering film formation As shown in FIGS. 8A and 8B, a p-type Si substrate 502 with a thermal oxide film 504 (1 inch angle ⁇ 1 mm, thickness) as a substrate. : 525 ⁇ mt, thermal oxide film (SiO 2 ): 100 nmt), and a simple TFT 500 using the thermal oxide film 504 as a gate insulating film was manufactured.
  • composition modulation is performed for each of the examples and the comparative examples, so that the first
  • the film formation conditions were as follows: ultimate vacuum during film formation: 6 ⁇ 10 ⁇ 6 Pa, pressure during film formation: 4.4 ⁇ 10 ⁇ 1 Pa, film formation temperature: room temperature, oxygen partial pressure / argon partial pressure: 0.00. 067 was common to all examples and comparative examples.
  • the first region 506 is not an InSnZnO film but an InGaZnO film.
  • the second region 508 of the oxide semiconductor layer was formed by sputtering with a thickness of 50 nm and a vertical and horizontal width of 3 mm ⁇ 4 mm.
  • a pattern was formed using a metal mask, and the oxide semiconductor layer was continuously formed between the regions without being exposed to the atmosphere.
  • Sputtering of each region was performed by ternary co-sputtering using an In 2 O 3 target, a SnO 2 (or Ga 2 O 3 ) target, and a ZnO target in the first region 506 and the second region 508. .
  • the film thickness in each region was adjusted by adjusting the film formation time.
  • composition analysis is performed by fluorescent X-ray analysis on a film-formed sample formed by performing film formation under the same conditions as those of the first region 506 and the second region 508 according to Examples 1 to 10 and Comparative Examples 1 to 4. Thus, it was confirmed that each of the first region 506 and the second region 508 had the above composition. In addition, it was confirmed by X-ray diffraction measurement that each film formation sample was an amorphous film.
  • source / drain electrodes 510 and 512 were formed on the surface of the second region 508 by sputtering.
  • the source / drain electrodes 510 and 512 were formed by pattern film formation using a metal mask. After depositing 10 nm of Ti, 40 nm of Au was deposited.
  • post-annealing was performed in an atmosphere of 300 ° C. and oxygen partial pressure of 100%.
  • FIG. 9 is a diagram showing a ternary phase diagram focusing on the composition of the first region 506 in Examples 1 to 10 and Comparative Examples 2 to 4. Note that the first region 506 in Comparative Example 1 is not shown in the ternary phase diagram because part of its composition is Ga, not Sn.
  • the TFTs according to Comparative Example 5 and Comparative Example 6 have the same configuration as the TFT according to Example 1 except for the configuration of the oxide semiconductor layer.
  • the TFTs according to Examples 1 to 10 and Comparative Examples 1 to 4 were evaluated for Vg-Id characteristics and then irradiated with wavelength-variable monochrome light, so that the TFT characteristics were stable with respect to light irradiation. Evaluated.
  • each TFT was placed on a probe stage stage and dried air was allowed to flow for 2 hours or more, and then TFT characteristics were measured in the dried air atmosphere.
  • the irradiation intensity of the monochrome light source is 10 ⁇ W / cm 2
  • the wavelength ⁇ is 360 to 700 nm
  • the Vg-Id characteristics when the monochrome light is not irradiated are compared with the Vg-Id characteristics when the monochrome light is irradiated.
  • Stability ( ⁇ Vth) was evaluated.
  • the threshold shift amount ⁇ Vth for light irradiation of 420 nm was used as an indicator of TFT light stability.
  • Vg-Id characteristics among the measurement results of IV characteristics during monochrome light irradiation are shown in FIGS. 11 to 15 together with the characteristics before monochrome light irradiation.
  • the said evaluation method is common in a following example.
  • Table 3 summarizes the measurement results of the mobility, the threshold voltage Vth obtained from the IV characteristics, and the threshold shift amount ⁇ Vth obtained from the IV characteristics before and after the monochrome light irradiation.
  • Comparative Examples 5 and 6 when a film having the same composition as that of Example 5 or Example 3 was used as a single film of the oxide semiconductor layer, the threshold voltage was greatly negative, It was found that the situation does not show clear switching characteristics (indicated by “-” in Table 3). Therefore, from this example, the InSnZnO film is disposed on the side closer to the gate electrode, and the InGaZnO film is disposed on the side far from the gate electrode, thereby exhibiting high mobility, good On / Off ratio, and switching characteristics in the TFT. I understood it.
  • the threshold fluctuation amount (threshold shift amount ⁇ Vth) at the time of light irradiation is smaller than the results of Comparative Examples 1 to 4.
  • of the threshold shift amount is within 1V
  • of the threshold shift amount is a large value exceeding 1V. I understand.
  • FIG. 16 is a graph plotting the relationship between the threshold voltage and the Zn ratio ⁇ c / (a + b + c) ⁇ with respect to the total composition ratio of In, Sn, and Zn in the first region based on Table 3.
  • the dotted line in a figure is a line which connected the average value of the plot of the threshold voltage in each Zn ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
  • the threshold voltage depends on the Zn ratio ⁇ c / (a + b + c) ⁇ , and it can be seen that the threshold voltage tends to increase as the Zn ratio increases.
  • the threshold voltage is on the minus side compared to the other embodiments, and the second embodiment is also close to 0, indicating that the off-current is slightly higher. This is presumably because the carrier concentration in Examples 1 to 4 is higher than that in other Examples.
  • the carrier concentration is considered to be higher when the element content of Zn is lower than that of In or Sn elements that are likely to induce carriers. . Therefore, it can be said that the Zn content in the InSnZnO film (first region) is preferably higher to some extent from the viewpoint of threshold voltage and off-current.
  • the threshold voltage appears significantly on the negative side.
  • the threshold voltage is close to 0 or takes a positive value. Therefore, it can be seen that the composition of the first region is preferably expressed by c / (a + b + c) ⁇ 0.200 from the viewpoint of suppressing the threshold voltage of the TFT from appearing on the minus side.
  • the composition of the first region is expressed by c / (a + b + c) ⁇ 1/3 from the viewpoint that the threshold voltage of the TFT 40 can be made higher on the positive side than 0V. It can be seen that is more preferable.
  • the composition of the first region is expressed by c / (a + b + c) ⁇ 0.400. It turns out that it is even more preferable.
  • FIG. 17 is a graph plotting the relationship between the mobility and the Zn ratio ⁇ c / (a + b + c) ⁇ with respect to the total composition ratio of In, Sn, and Zn in the first region based on Table 3.
  • the dotted line in a figure is a line which connected the average value of the plot of the mobility in each Zn ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
  • the mobility depends on the Zn ratio ⁇ c / (a + b + c) ⁇ , and it can be seen that the mobility increases as the Zn ratio decreases. It was also confirmed that the Zn ratio rapidly increased as the Zn ratio decreased from 0.800 to 0.700, and that the mobility was higher than 30 cm 2 / Vs at 0.700 or less. Therefore, it can be seen that the composition of the first region is preferably expressed by c / (a + b + c) ⁇ 0.700 from the viewpoint of setting the mobility to more than 30 cm 2 / Vs.
  • FIG. 18 is a graph plotting the relationship between the mobility and the In ratio ⁇ a / (a + b + c) ⁇ with respect to the sum of the composition ratios of In, Sn, and Zn in the first region based on Table 3.
  • the dotted line in a figure is a line which connected the average value of the plot of the mobility in each In ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
  • the mobility depends on the In ratio ⁇ a / (a + b + c) ⁇ , and it can be seen that the mobility increases as the In ratio increases. It was also confirmed that the In ratio increased rapidly from 0.100 to 1/3, and that the mobility was over 40 cm 2 / Vs after 1/3. Therefore, it was found that the composition of the first region is preferably represented by a / (a + b + c) ⁇ 1/3.
  • FIG. 19 is a graph plotting the relationship between the threshold shift amount ⁇ Vth and the Zn ratio ⁇ c / (a + b + c) ⁇ with respect to the sum of the composition ratios of In, Sn, and Zn in the first region based on Table 3.
  • the dotted line in a figure is a line which connected the average value of the plot of threshold value shift amount (DELTA) Vth in each Zn ratio with respect to the sum total of the composition ratio of In, Sn, and Zn.
  • the threshold shift amount ⁇ Vth does not depend on the Zn ratio compared to the mobility and the threshold voltage.
  • the Zn ratio c is 0.1 and 0.8
  • of the threshold shift amount is 0.8 V or more and approaches 1 V as a reference, but the Zn ratio c is 0.200 ⁇ c / If it is within the range of (a + b + c) ⁇ 0.700 (hatching range shown in FIG. 9), the absolute value of the threshold shift amount
  • TFTs according to Examples 11 to 15 were produced.
  • the film thicknesses of the first regions of the TFTs according to Examples 11 to 15 were 10, 15, 30, 50, and 70 nm, respectively.
  • the thickness of the first region is preferably 50 nm or less. This is because if it is 50 nm or less, the threshold voltage of the TFT can be suppressed from appearing on the negative side, and the deterioration of the S value can be suppressed. Further, it can be seen that the threshold voltage takes a positive value when the film thickness of the first region is 30 nm or less. Therefore, it was found that the thickness of the first region is preferably 30 nm or less.
  • the disclosure of Japanese application 2012-101414 is incorporated herein by reference in its entirety. All documents, patent applications, and technical standards mentioned in this specification are to the same extent as if each individual document, patent application, and technical standard were specifically and individually described to be incorporated by reference, Incorporated herein by reference.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Thin Film Transistor (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

La présente invention a trait à un transistor à effet de champ qui inclut une couche semi-conductrice d'oxyde, une électrode de source, une électrode de drain, un film isolant de grille et une électrode de grille, laquelle couche semi-conductrice d'oxyde et dotée d'une première région incluant In(a) Sn(b) Zn(c) O(d) (où a > 0, b > 0, c > 0, d > 0, a + b + c = 1) et une seconde région incluant In(e) Ga(f) Zn(g) O(h) (où e > 0, f > 0, g > 0, h > 0, e + f + g = 1) qui est disposée sur un côté plus éloigné de l'électrode de grille que la première région.
PCT/JP2013/060865 2012-04-26 2013-04-10 Transistor à effet de champ et son procédé de fabrication, écran, capteur d'image et capteur radiographique WO2013161570A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020147029981A KR101633621B1 (ko) 2012-04-26 2013-04-10 전계 효과형 트랜지스터 및 그 제조 방법, 표시 장치, 이미지 센서 그리고 x선 센서

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012101414A JP5995504B2 (ja) 2012-04-26 2012-04-26 電界効果型トランジスタ及びその製造方法、表示装置、イメージセンサ並びにｘ線センサ
JP2012-101414 2012-04-26

Publications (1)

Publication Number Publication Date
WO2013161570A1 true WO2013161570A1 (fr) 2013-10-31

Family

ID=49482899

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/060865 WO2013161570A1 (fr) 2012-04-26 2013-04-10 Transistor à effet de champ et son procédé de fabrication, écran, capteur d'image et capteur radiographique

Country Status (3)

Country Link
JP (1) JP5995504B2 (fr)
KR (1) KR101633621B1 (fr)
WO (1) WO2013161570A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017098369A1 (fr) * 2015-12-11 2017-06-15 Semiconductor Energy Laboratory Co., Ltd. Film d'oxyde semi-conducteur, dispositif à semi-conducteur et dispositif d'affichage

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104272463B (zh) * 2012-05-09 2017-08-15 株式会社神户制钢所 薄膜晶体管和显示装置
JP6494184B2 (ja) * 2014-06-12 2019-04-03 三菱電機株式会社 薄膜トランジスタ、アクティブマトリックス基板、薄膜トランジスタの製造方法およびアクティブマトリックス基板の製造方法
US10340390B2 (en) * 2015-06-08 2019-07-02 Sharp Kabushiki Kaisha Semiconductor device and method for producing the same
WO2017099024A1 (fr) * 2015-12-09 2017-06-15 シャープ株式会社 Substrat à matrice active et panneau d'affichage à cristaux liquides muni de celui-ci
KR102454384B1 (ko) * 2015-12-31 2022-10-14 엘지디스플레이 주식회사 산화물 박막 트랜지스터와 그를 포함하는 표시 장치 및 그 제조방법
WO2017137869A1 (fr) * 2016-02-12 2017-08-17 Semiconductor Energy Laboratory Co., Ltd. Dispositif à semi-conducteur et dispositif d'affichage le comprenant
JP7063712B2 (ja) 2018-05-09 2022-05-09 株式会社神戸製鋼所 酸化物半導体層を含む薄膜トランジスタ

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010021555A (ja) * 2008-07-14 2010-01-28 Samsung Electronics Co Ltd トランジスタ
WO2010023889A1 (fr) * 2008-08-27 2010-03-04 出光興産株式会社 Transistor à effet de champ, son procédé de fabrication et cible de pulvérisation cathodique
JP2012059860A (ja) * 2010-09-08 2012-03-22 Fujifilm Corp 薄膜トランジスタおよびその製造方法、並びにその薄膜トランジスタを備えた装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5250322B2 (ja) * 2008-07-10 2013-07-31 富士フイルム株式会社 金属酸化物膜とその製造方法、及び半導体装置
CN102668028B (zh) * 2009-11-28 2015-09-02 株式会社半导体能源研究所 层叠的氧化物材料、半导体器件、以及用于制造该半导体器件的方法
JP5497417B2 (ja) * 2009-12-10 2014-05-21 富士フイルム株式会社 薄膜トランジスタおよびその製造方法、並びにその薄膜トランジスタを備えた装置
TWI615920B (zh) * 2010-08-06 2018-02-21 半導體能源研究所股份有限公司 半導體裝置及其製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010021555A (ja) * 2008-07-14 2010-01-28 Samsung Electronics Co Ltd トランジスタ
WO2010023889A1 (fr) * 2008-08-27 2010-03-04 出光興産株式会社 Transistor à effet de champ, son procédé de fabrication et cible de pulvérisation cathodique
JP2012059860A (ja) * 2010-09-08 2012-03-22 Fujifilm Corp 薄膜トランジスタおよびその製造方法、並びにその薄膜トランジスタを備えた装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017098369A1 (fr) * 2015-12-11 2017-06-15 Semiconductor Energy Laboratory Co., Ltd. Film d'oxyde semi-conducteur, dispositif à semi-conducteur et dispositif d'affichage

Also Published As

Publication number Publication date
KR20140148449A (ko) 2014-12-31
JP5995504B2 (ja) 2016-09-21
JP2013229495A (ja) 2013-11-07
KR101633621B1 (ko) 2016-06-27

Similar Documents

Publication Publication Date Title
JP4982620B1 (ja) 電界効果型トランジスタの製造方法、並びに、電界効果型トランジスタ、表示装置、イメージセンサ及びｘ線センサ
US9236454B2 (en) Method of manufacturing thin-film transistor, thin-film transistor, display apparatus, sensor, and digital X-ray image-capturing apparatus
JP5995504B2 (ja) 電界効果型トランジスタ及びその製造方法、表示装置、イメージセンサ並びにｘ線センサ
JP5052693B1 (ja) 薄膜トランジスタ及びその製造方法、表示装置、イメージセンサー、ｘ線センサー並びにｘ線デジタル撮影装置
JP5626978B2 (ja) 薄膜トランジスタおよびその製造方法、並びにその薄膜トランジスタを備えた装置
JP5795551B2 (ja) 電界効果型トランジスタの製造方法
JP5679933B2 (ja) 薄膜トランジスタ及びその製造方法、表示装置、イメージセンサー、ｘ線センサー並びにｘ線デジタル撮影装置
WO2013172237A1 (fr) Transistor à couches minces, son procédé de production, dispositif d'affichage, capteur d'images, capteur de rayons x et dispositif d'imagerie numérique à rayons x
JP5901420B2 (ja) 薄膜トランジスタの製造方法
JP5869110B2 (ja) 薄膜トランジスタ、表示装置、イメージセンサ及びｘ線センサ
JP5489429B2 (ja) 薄膜電界効果型トランジスタ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13780626

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20147029981

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13780626

Country of ref document: EP

Kind code of ref document: A1