WO2013016975A1 - 沟槽多晶硅过腐蚀台阶测试图形及其形成方法 - Google Patents

沟槽多晶硅过腐蚀台阶测试图形及其形成方法 Download PDF

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Publication number
WO2013016975A1
WO2013016975A1 PCT/CN2012/076570 CN2012076570W WO2013016975A1 WO 2013016975 A1 WO2013016975 A1 WO 2013016975A1 CN 2012076570 W CN2012076570 W CN 2012076570W WO 2013016975 A1 WO2013016975 A1 WO 2013016975A1
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Prior art keywords
trench
test pattern
groove
width
microns
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PCT/CN2012/076570
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English (en)
French (fr)
Inventor
卞铮
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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Priority to US14/236,473 priority Critical patent/US9960047B2/en
Publication of WO2013016975A1 publication Critical patent/WO2013016975A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor

Definitions

  • the present invention pertains to semiconductor manufacturing process methods, and more particularly to polysilicon etchback technology. Background technique
  • One of the ways to obtain the depth of the step is to slice. Specifically, one of a plurality of wafers is taken out, cut along a direction perpendicular to the groove, and the depth of the groove is obtained by a microscope or the like.
  • IUU05J measures 3 ⁇ 4 ⁇ shape, that is, [HI ⁇ width S ⁇ A is small, then ⁇ 1 ⁇ . ⁇ t J TO ⁇ , too wide and may be caused by the filling characteristics of polysilicon in the groove The wall is high and the middle is low and the correct result cannot be obtained. Therefore, due to the width of the test pattern, the current test pattern cannot be too wide, but at the current width it is possible that the step meter does not get the correct scan parameters. Summary of the invention
  • the present invention provides a test pattern for trench polysilicon over-etching step testing to effectively solve the above problems.
  • the test pattern is a groove formed on a substrate, the groove including a bottom surface and two side surfaces extending from the bottom surface, wherein the groove is oriented in a longitudinal direction thereof
  • the longitudinal direction of the wafer dicing groove is formed on the substrate in such a manner as to form a predetermined angle other than 90°.
  • the predetermined angle is equal to or greater than 10°. More preferably, the predetermined angle is equal to or greater than 30°
  • the width of the trench is between 0.18 micrometers and 0.36 micrometers. More preferably, the width of the trench is between 0.2 microns and 0.35 microns.
  • the depth of the trench is between 0.98 micrometers and 2.02 micrometers. More preferably, the depth of the trench is between 1 micrometer and 2 micrometers.
  • the present invention also provides a method of forming a test pattern for trench polysilicon over-etching step testing, including Forming a groove on the substrate, the groove including a bottom surface and two side surfaces extending from the bottom surface, wherein the longitudinal direction of the groove forms a non-90° predetermined length with the longitudinal direction of the wafer dicing groove
  • the trench is formed on the substrate in an angular manner.
  • the predetermined angle is equal to or greater than 10°. More preferably, the predetermined angle is equal to or greater than 30. .
  • the trench has a width between 0.18 microns and 0.36 microns. More preferably, the width of the trench is between 0.2 microns and 0.35 microns.
  • the method of forming a test pattern for trench polysilicon over-etching step testing preferably, the trench has a depth between 0.98 microns and 2.02 microns. More preferably, the depth of the trench is between 1 micrometer and 2 micrometers.
  • the step scanning apparatus can be made to obtain a longer scanning length in a case where the width of the groove can be maintained in the conventional technique, thereby obtaining the scanning parameters more accurately.
  • 1 is a schematic view of a top view of a conventional test pattern
  • Figure 2 is a schematic cross-sectional view of the test pattern shown in Figure 1 at A-A;
  • Figure 3 is a scan result of the test chart shown in Figure 1 by the step meter;
  • Figure 4 is a schematic diagram of the test pattern after the groove width is increased
  • Figure 5 is a schematic cross-sectional view of the test pattern shown in Figure 4 at A-A;
  • Figure 6 is a scan result of the test chart shown in Figure 4 by the step meter
  • Figure 7 is a schematic illustration of a top view of a test pattern in accordance with the present invention.
  • Figure 8 is a schematic cross-sectional view of the test pattern shown in Figure 7 at A-A;
  • Figure 9 is a scanning result of the test pattern shown in Figure 7 by the step meter.
  • FIG. 1 is a top plan view of a conventional test pattern.
  • the test pattern illustrated in FIG. 1 is formed in an etching manner on the test area of the silicon substrate. After the etching of the polysilicon is performed, the test pattern of the test area is scanned by the step scanner to determine the test area. depth.
  • the conventional test pattern is a concave groove, and a plurality of grooves 10 It is disposed on the silicon substrate 1.
  • Figure 2 is a schematic cross-sectional view of Figure 1 at AA. As illustrated, the trench has a width 12 and a depth 11. The stepper is swept through the trenches illustrated in Figures 1 and 2 to obtain a depth difference H1 between the polysilicon 50 and the trench 10.
  • Figure 3 shows the test results of the conventional test pattern shown by the step scanning device (such as the step meter). It can be seen that the result of this conventional test is not clear enough due to the groove width, and the reference is not large.
  • FIG. 4 is a schematic diagram of a test pattern after the groove width is increased.
  • the width of each of the plurality of grooves provided on the silicon substrate 1 shown in Fig. 4 is increased as compared with the test pattern shown in Fig. 1.
  • the groove width is increased, due to the filling characteristics of the polysilicon in the groove, it grows into side walls and is low in the middle.
  • the polysilicon 50 is grown polycrystalline silicon which grows to have a high sidewall and a low middle.
  • Figure 5 is a schematic cross-sectional view of Figure 4 at A-A. In this case, the step meter cannot obtain the correct test results.
  • Figure 6 shows the results of the test of the groove shown in Figure 4 by the step meter.
  • Figure 7 is a schematic illustration of a top view of a test pattern in accordance with the present invention.
  • Figure 8 is a cross-sectional view of the test pattern shown in Figure 7 at AA.
  • the test pattern according to the present invention that is, the trench 14 is disposed on the silicon substrate 1.
  • Each of the grooves includes a bottom surface 140 and two sides extending from the bottom surface, namely a first side 141 and a second side 142.
  • the trench in the test pattern is formed on the silicon substrate, and the longitudinal direction of the trench (the L direction shown in the figure) and the longitudinal direction of the wafer dicing trench (illustrated in the figure)
  • a predetermined angle ⁇ of not 90° is formed between the X directions).
  • the predetermined angle ⁇ is equal to or greater than 10°, preferably equal to or greater than 30°, and further preferably 30°.
  • the width 12 of the trench is between 0.18 micrometers and 0.36 micrometers, preferably between 0.2 micrometers and 0.35 micrometers; the depth 11 of the trench is preferably between 1 micrometer and 2 micrometers, but the error is ⁇ 0 ⁇ within 05 microns are possible, such as a depth of between 0.98 microns to 2.02 microns and the like.
  • the width of the trench can be kept consistent with the width of the trench in the conventional art, that is, the width of the trench in FIG. 7 is the same as the width of the trench shown in FIG.
  • the longitudinal direction has an angle ⁇ with the longitudinal direction of the wafer dicing groove, so that the step scanning device (such as the step scanner) sweeps along the longitudinal direction of the wafer dicing groove.
  • the length of the groove in the longitudinal direction of the wafer dicing groove is larger than the width of the groove, so that the conventional width of the groove is kept constant without affecting the growth shape of the polysilicon,
  • Each of the grooves in the test pattern of the present invention gives the step scanning device a longer scan length, thereby obtaining clear and accurate scan results.
  • a method of forming a test pattern for a trench step test is briefly described below, specifically including forming a test pattern as illustrated in FIG. 7 on a silicon substrate, that is, a plurality of trenches.
  • the groove includes a bottom surface 140 and extends from the bottom surface The two sides, that is, the first side 141 and the second side 142.
  • the groove is formed on the substrate in such a manner that the longitudinal direction of the groove forms a predetermined angle with the longitudinal direction of the wafer dicing groove.
  • the trench M in the test pattern is formed on the silicon substrate 1, and the step direction of the trench 14 (the L direction shown in the figure) and the longitudinal direction of the wafer dicing trench (in the figure)
  • a predetermined angle ⁇ is formed between the illustrated X directions).
  • the predetermined angle ⁇ is equal to or greater than 10°, preferably equal to or greater than 30°, and further preferably 30°.
  • the width 12 of the trench is between 0.18 micrometers and 0.36 micrometers, preferably between 0.2 micrometers and 0.35 micrometers; the depth of the trench is preferably between 1 micrometer and 2 micrometers, but the error is within ⁇ 0.05 micrometers. It is also possible, such as a depth between 0.98 microns and 2.02 microns.
  • the term “vertical” in this application includes not only vertical but also substantially vertical with an error of ⁇ 10°, preferably an error of ⁇ 5°, more preferably ⁇ 2°.
  • the term “longitudinal direction of the groove” means the direction of the groove along the length of the groove, and “the longitudinal direction of the wafer dicing groove” means the direction along the length of the wafer scribe groove.
  • the width of the groove is kept consistent with the groove width in the conventional art
  • the length direction of the groove has an angle ⁇ , so that when the step scanning device sweeps over the test pattern, the scanning length of each groove is changed from the original width 12 to the current scanning length, that is, significantly larger than the width 12
  • the length 16 makes it possible to lengthen the scanning length without changing the width of the conventional groove, so that the step scanning device can obtain the scanning parameters more accurately. It should be noted, however, that the above description illustrates the benefits of the present invention by comparing the conventional trenches shown in FIG.
  • the width of the trenches of the present invention may be different from the width of a conventional trench.
  • it may be slightly larger or smaller than it is, as long as the groove can form a predetermined angle of not 90° with the longitudinal direction of the wafer dicing groove in the longitudinal direction thereof.

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

提供一种用于沟槽多晶硅过腐蚀台阶测试的测试图形，该测试图形是被形成在衬底（1）上的沟槽（14），该沟槽（14）包括底面和从底面延伸出的两个侧面，该沟槽（14）是以使其纵长方向（L）与晶片划片槽的纵长方向（X）形成非90°的预定角度的方式形成在衬底(1）上的。通过该测试图形，可在不改变沟槽宽度的情况下，延长台阶扫描设备的扫描长度。

Description

糟名品砵忖腐^ ^ B介测 ^図形^苴 F , T^
[0001] 本发明属于半导体生产工艺方法， 尤其涉及多晶硅回刻技术。 背景技术
[0002] 在沟槽填充工艺中， 获得多晶硅 （POLY) 回刻后沟榷的台阶深度等参数， 对于比如 沟槽功率场效应管 （TRENCH POWER MOS) 等电子器件的制程监控至关重要。
[0003] 获得台阶深度的做法之一是切片。 具体来说， 就是从多个晶圆 （wafer ) 中拿出一 个， 沿与沟槽垂直的方向将其切幵， 再通过显微镜等相关仪器获得沟槽的深度。
[0004] 另一个常规做法是通过监测测试图形实现。 简单地说， 是在制造过程中相对于 ιΗ常
*il^ 5 tel M fi&iOIll lx . ^ ^"^且右^ 7^^生|1 ^ 1¾"151^日^ 1¾½1埔. ι^ ϊ^ϋιΙΐΙΐ^ίΙίΙΐΙι^Γχ 该沟槽的相关参数 （比如深度） 来获得所需要的参数。
IUU05J 测 ¾囹形， 、即 [HI罹 宽 S卯朱 A小， 则 酡尤 1史 仪犾侍止.怫 t J TO穸钗， 太宽又可能因多晶硅在凹槽内的填充特性造成侧壁高而中间低无法获取正确的结果。 因此， 受测试图形宽度的限制， 当前的测试图形无法太宽， 却又在当前宽度下有可能使台阶仪未获 得正确的扫描参数。 发明内容
[0006] 有鉴于此， 本发明提供一种用于沟槽多晶硅过腐蚀台阶测试的测试图形， 以有效解 决上述问题。 根据本发明， 所述测试图形是被形成在衬底上的沟槽， 所述沟槽包括底面和从 所述底面延伸出的两个侧面， 其中， 所述沟槽以使其纵长方向与晶片划片槽的纵长方向形成 非 90°的预定角度的方式形成在所述衬底上。
[0007] 本发明所述的测试图形， 优选地， 所述预定角度等于或大于 10°。 更优选地， 所述预 定角度等于或大于 30°
[0008] 本发明所述的测试图形， 优选地， 所述沟槽的宽度在 0.18微米到 0.36微米之间。 更 优选地， 所述沟槽的宽度在 0.2微米到 0.35微米之间。
[0009] 本发明所述的测试图形， 优选地， 所述沟槽的深度在 0.98微米到 2.02微米之间。 更 优选地， 所述沟槽的深度在 1微米到 2微米之间。
[0010] 本发明还提供一种形成用于沟槽多晶硅过腐蚀台阶测试的测试图形的方法， 包括在 衬底上形成沟槽， 所述沟槽包括底面和从底面延伸出的两个侧面， 其中， 以使所述沟槽的纵 长方向与晶片划片槽的纵长方向形成非 90°的预定角度的方式在所述衬底上形成所述沟槽。
10011] 本发明所述的形成用于沟槽多晶硅过腐蚀台阶測试的测试图形的方法， 优选地， 所述 预定角度等于或大于 10°以上。 更优选地， 所述预定角度等于或大于 30。。
[0012] 本发明所述的形成用于沟槽多晶硅过腐蚀台阶测试的测试图形的方法， 优选地， 所 述沟槽的宽度在 0.18微米到 0.36微米之间。 更优选地， 所述沟槽的宽度在 0.2微米到 0.35 微米之间。
[0013] 本发明所述的形成用于沟槽多晶硅过腐蚀台阶测试的测试图形的方法， 优选地， 所 述沟槽的深度在 0.98微米到 2.02微米之间。 更优选地， 所述沟槽的深度在 1微米到 2微米 之间。
[0014] 本发明所述的形成用于沟槽多晶硅过腐蚀台阶测试的测试图形的方法， 优选地， 在 所述硅衬底上形成多个所述沟槽。
[0015] 根据本发明， 在可以保持常规技术中沟槽的宽度不变的情况下， 使得台阶扫描设备 获得更长的扫描长度， 从而更准确地获得扫描参数。
附图说明
[0016] 图 1为常规的测试图形的俯视图的示意；
图 2为图 1所示的测试图形在 A-A处的剖视图的示意；
图 3为台阶仪对图 1所示的测试图形的扫描结果；
图 4为沟槽宽度增加后的测试图形示意；
图 5为图 4所示的测试图形在 A-A处的剖视图的示意；
图 6为台阶仪对图 4所示的测试图形的扫描结果；
图 7为根据本发明的测试图形的俯视图的示意；
图 8为图 7所示的测试图形在 A-A处的剖视图的示意； 以及
图 9为台阶仪对图 7所示的测试图形的扫描结果。
具体实施方式
[0017] 以下将结合附图进一步阐述本发明。 需要说明的是， 附图仅用于示意， 并不就此限 定所示意的部件的大小、 比例等， 且在附图中相同的标号表示相同或相似的部件。
[0018] 图 1 为常规的测试图形的俯视示意图。 图 1 所示意的测试图形以刻蚀的方式形成在 硅衬底的测试区域， 在进行了多晶硅的回刻之后， 由台阶扫描仪对该测试区域的测试图形进 行扫描， 以确定该测试区域的深度。 如图所示， 常规的测试图形为凹形沟槽， 多个沟槽 10 设置在硅衬底 1上。 图 2为图 1在 A-A处的剖视的示意图。 如图所示意， 该沟槽具有宽度 12和深度 11。 使台阶仪扫过图 1和 2中所示意的沟槽， 以获得多晶硅 50与沟槽 10之间的 深度差 Hl。 图 3 为台阶扫描设备 （如台阶仪） 对所示意的常规测试图形的测试结果， 可以 看出这种常规测试的结果因沟槽宽度的原因不够明确， 可参考性不大。
[0019] 图 4是将沟槽宽度变大后的测试图形示意。 和图 1 所示的测试图形相比， 图 4所示 的设置在硅衬底 1 上的多个沟槽中每一个沟槽 10的宽度增大。 在沟槽宽度增大的情况下， 由于多晶硅在凹槽内的填充特性， 其会生长成侧壁髙而中间低。 如图 5所示， 多晶硅 50是 生长的多晶硅， 其生长成侧壁高而中间低。 图 5是图 4在 A-A处的剖视的示意图。 这种情 况下， 台阶仪无法获取正确的测试结果。 图 6给出了台阶仪对图 4所示的沟槽的测试结果。
!0020] 图 7为根据本发明的测试图形的俯视图的示意。 图 8为图 7所示的测试图形在 A-A 处的剖视示意。 以下说明， 请同时结合图 7和图 8。 如图所示， 根据本发明的测试图形， 亦 即沟槽 14被设置在硅衬底 1 上。 每个沟槽包括底面 140， 以及从底面延伸出的两个侧面， 亦即第一侧面 141和第二侧面 142。 如图所示， 测试图形中的沟槽被形成在硅衬底上， 且沟 槽的纵长方向 （图中所示意的 L方向） 与晶片划片槽的纵长方向 （图中所示意的 X方向） 之间形成非 90°的预定角度 α。 根据本发明， 该预定角度 α等于或大于 10°， 优选等于或大 于 30°， 再优选为 30°。 根据本发明， 沟槽的宽度 12在 0.18微米到 0.36微米之间， 优选在 在 0.2微米到 0.35微米之间； 沟槽的深度 11优选在 1微米到 2微米之间， 但误差在 ± 0·05 微米内也是可以的， 比如深度在 0.98微米到 2.02微米之间等。
[0021] 如图所示， 沟槽的宽度可以保持与常规技术中沟槽的宽度一致， 亦即， 图 7 中沟槽 的宽度与图 1所示的沟槽的宽度大小相同。 但由于图 7中的沟槽， 其纵长方向与晶片划片槽 的纵长方向之间具有 α角度， 从而使得台阶扫描设备 （如台阶扫描仪） 在沿晶片划片槽的纵 长方向扫过测试图形时， 对每个沟槽的扫描长度， 由原来的扫描长度亦即宽度 12 改变为现 在的扫描长度， 即明显大于宽度 12的长度 16， 从而加长了扫描长度， 使得台阶扫描设备可 以更准确地获得扫描参数， 亦即在沟槽内所生长的多晶硅与沟槽的深度差 HI。 图 9 为台阶 仪对图 7 所示意的测试图形的扫描结果， 可以看出， 该结果清楚明了。 ώ以上描述可以看 出， 根据本发明， 沟槽在晶片划片槽的纵长方向的长度是大于沟槽宽度的， 所以在保持沟槽 常规宽度不变、 不影响多晶硅生长形状的情况下， 本发明所述的测试图形中的每个沟槽给予 台阶扫描设备更长的扫描长度， 从而获得了清楚准确的扫描结果。
[0022] 根据本发明， 以下简单描述形成用于沟槽台阶测试的测试图形的方法， 具体包括在 硅衬底上形成如图 7所示意的测试图形， 即多个沟槽。 该沟槽包括底面 140和从底面延伸出 的两个侧面， 亦即， 第一侧面 141和第二侧面 142。 以使所述沟槽的纵长方向与晶片划片槽 的纵长方向形成预定角度的方式在所述衬底上形成所述沟槽。 如图所示， 测试图形中的沟槽 M被形成在硅衬底 1上， 且沟槽 14的级长方向 （图中所示意的 L方向） 与晶片划片槽的纵 长方向 （图中所示意的 X 方向） 之间形成预定角度 α。 根据本发明， 该预定角度 α等于或 大于 10°， 优选等于或大于 30° , 再优选为 30°。 根据本发明， 沟槽的宽度 12在 0.18微米到 0.36微米之间， 优选在在 0.2微米到 0.35微米之间； 沟槽的深度优选在 1微米到 2微米之 间， 但误差在 ±0.05微米内也是可以的， 比如深度在 0.98微米到 2.02微米之间等。
[0023] 在本发明的以上各示例中， 术语 "垂直"在本申请中不仅包括垂直， 还包括误差在 ± 10°， 优选误差在 ± 5°， 更优选在 ± 2°内的基本垂直。 术语 "沟槽的纵长方向"指的是沟 槽沿沟槽长度的方向， "晶片划片槽的纵长方向"指的是沿晶片划片槽长度的方向。
[0024] 综上可见， 根据本发明， 在沟槽的宽度保持与常规技术中沟槽宽度一致的情况下， 由于改变了沟槽的布置方向， 亦即沟槽的纵长方向与晶片划片槽的级长方向之间具有 α角 度， 从而使得台阶扫描设备在扫过测试图形时， 对每个沟槽的扫描长度由原来的宽度 12 改 变为现在的扫描长度， 亦即明显大于宽度 12的长度 16 (参见图 7)， 从而可以在不改变常规 沟槽宽度的情况下加长扫描长度， 使得台阶扫描设备可以更准确地获得扫描参数。 但是需要 说明的是， 以上描述中虽是以图 1 所示的常规沟槽作为对比来阐述本发明的益处， 但实际 上， 本发明所述的沟槽的宽度可以不同于常规沟槽的宽度， 例如可比其略大或略小， 只要沟 槽可以其纵长方向与晶片划片槽的纵长方向形成非 90°的预定角度即可。
[0025] 尽管己参照上述具体实施方式对本发明进行了详细的阐述， 但本领域的普通技术人 员应当理解， 可以对本发明的具体实施方式进行修改或对部分技术特征进行等同替换， 而在 不脱离本发明的技术方案的精神下， 其均应涵盖在本发明请求保护的技术方案范围当中。

Claims

^x,
A. — rr w丁 f τ苜夕 s白庇 ' ι¾„ w「 ! ) τ¾ j ¾¾ ¾ m^wiv^ TT^ mm^ i i^— m r-y 槽， 所述沟槽包括底面和自底面延伸出的两个侧面， 其特征在于， 所述沟槽是以使其纵长方 向与晶片划片槽的纵长方向形成非 90°的预定角度的方式形成在所述衬底上的。
2. 根据权利要求 1所述的测试图形， 其特征在于， 所述预定角度等于或大于 10°
3. 根据权利要求 1或 2所述的测试图形， 其特征在于， 所述预定角度等于或大于 30°
4. 根据权利要求 3所述的测试图形， 其特征在于， 所述沟槽的宽度在 0.18微米到 0.36微米 之间。 之间。
6. 根据权利要求 4或 5所述的测试图形， 其特征在于， 所述沟槽的深度在 0.98微米到 2.02 微米之间。
7. 根据权利要求 6所述的测试图形， 其特征在于， 所述沟槽的深度在 1 微米到 2 微米之 间。
8. 一种形成用于沟槽多晶硅过腐蚀台阶测试的测试图形的方法， 包括在衬底上形成沟槽， 所述沟槽包括底面和自所述底面延伸出的两个侧面， 其特征在于， 以使所述沟槽的纵长方向 与晶片划片槽的纵长方向形成非 90°的预定角度的方式在所述衬底上形成所述沟槽。
9. 根据权利要求 8所述的方法， 其特征在于， 所述预定角度等于或大于 10°
10. 根据权利要求 8或 9所述的方法， 其特征在于， 所述预定角度等于或大于 30°
11. 根据权利要求 10所述的方法， 其特征在于， 所述沟槽的深度在 0.18微米到 0.36微米之 间。
12. 根据权利要求 11所述的方法， 其特征在于， 所述沟槽的宽度在 0.2微米到 0.35微米之 间。
13. 根据权利要求 11 或 12所述的方法， 其特征在于， 所述沟槽的深度在 0.98微米到 2.02 微米之间。
14. 根据权利要求 13所述的方法， 其特征在于， 所述沟槽的深度在 1微米到 2微米之间。
15. 根据以上权利要求 1所述的方法， 其特征在于， 在所述硅衬底上形成多个所述沟槽。
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